1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2// Copyright (C) 2023-2024 Arm Ltd. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun6i-rtc.h> 6#include <dt-bindings/clock/sun55i-a523-ccu.h> 7#include <dt-bindings/clock/sun55i-a523-r-ccu.h> 8#include <dt-bindings/reset/sun55i-a523-ccu.h> 9#include <dt-bindings/reset/sun55i-a523-r-ccu.h> 10 11/ { 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a55"; 22 device_type = "cpu"; 23 reg = <0x000>; 24 enable-method = "psci"; 25 }; 26 27 cpu1: cpu@100 { 28 compatible = "arm,cortex-a55"; 29 device_type = "cpu"; 30 reg = <0x100>; 31 enable-method = "psci"; 32 }; 33 34 cpu2: cpu@200 { 35 compatible = "arm,cortex-a55"; 36 device_type = "cpu"; 37 reg = <0x200>; 38 enable-method = "psci"; 39 }; 40 41 cpu3: cpu@300 { 42 compatible = "arm,cortex-a55"; 43 device_type = "cpu"; 44 reg = <0x300>; 45 enable-method = "psci"; 46 }; 47 48 cpu4: cpu@400 { 49 compatible = "arm,cortex-a55"; 50 device_type = "cpu"; 51 reg = <0x400>; 52 enable-method = "psci"; 53 }; 54 55 cpu5: cpu@500 { 56 compatible = "arm,cortex-a55"; 57 device_type = "cpu"; 58 reg = <0x500>; 59 enable-method = "psci"; 60 }; 61 62 cpu6: cpu@600 { 63 compatible = "arm,cortex-a55"; 64 device_type = "cpu"; 65 reg = <0x600>; 66 enable-method = "psci"; 67 }; 68 69 cpu7: cpu@700 { 70 compatible = "arm,cortex-a55"; 71 device_type = "cpu"; 72 reg = <0x700>; 73 enable-method = "psci"; 74 }; 75 }; 76 77 osc24M: osc24M-clk { 78 #clock-cells = <0>; 79 compatible = "fixed-clock"; 80 clock-frequency = <24000000>; 81 clock-output-names = "osc24M"; 82 }; 83 84 pmu { 85 compatible = "arm,cortex-a55-pmu"; 86 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 87 }; 88 89 psci { 90 compatible = "arm,psci-0.2"; 91 method = "smc"; 92 }; 93 94 timer { 95 compatible = "arm,armv8-timer"; 96 arm,no-tick-in-suspend; 97 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 99 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 100 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges = <0x0 0x0 0x0 0x40000000>; 108 109 pio: pinctrl@2000000 { 110 compatible = "allwinner,sun55i-a523-pinctrl"; 111 reg = <0x2000000 0x800>; 112 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 122 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 123 clock-names = "apb", "hosc", "losc"; 124 gpio-controller; 125 #gpio-cells = <3>; 126 interrupt-controller; 127 #interrupt-cells = <3>; 128 129 rgmii0_pins: rgmii0-pins { 130 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 131 "PH5", "PH6", "PH7", "PH9", "PH10", 132 "PH14", "PH15", "PH16", "PH17", "PH18"; 133 allwinner,pinmux = <5>; 134 function = "emac0"; 135 drive-strength = <40>; 136 bias-disable; 137 }; 138 139 mmc0_pins: mmc0-pins { 140 pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; 141 allwinner,pinmux = <2>; 142 function = "mmc0"; 143 drive-strength = <30>; 144 bias-pull-up; 145 }; 146 147 /omit-if-no-ref/ 148 mmc1_pins: mmc1-pins { 149 pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; 150 allwinner,pinmux = <2>; 151 function = "mmc1"; 152 drive-strength = <30>; 153 bias-pull-up; 154 }; 155 156 mmc2_pins: mmc2-pins { 157 pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", 158 "PC9", "PC10", "PC11", "PC13", "PC14", 159 "PC15", "PC16"; 160 allwinner,pinmux = <3>; 161 function = "mmc2"; 162 drive-strength = <30>; 163 bias-pull-up; 164 }; 165 166 uart0_pb_pins: uart0-pb-pins { 167 pins = "PB9", "PB10"; 168 allwinner,pinmux = <2>; 169 function = "uart0"; 170 }; 171 }; 172 173 ccu: clock-controller@2001000 { 174 compatible = "allwinner,sun55i-a523-ccu"; 175 reg = <0x02001000 0x1000>; 176 clocks = <&osc24M>, <&rtc CLK_OSC32K>, 177 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; 178 clock-names = "hosc", "losc", 179 "iosc", "losc-fanout"; 180 #clock-cells = <1>; 181 #reset-cells = <1>; 182 }; 183 184 mmc0: mmc@4020000 { 185 compatible = "allwinner,sun55i-a523-mmc", 186 "allwinner,sun20i-d1-mmc"; 187 reg = <0x04020000 0x1000>; 188 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 189 clock-names = "ahb", "mmc"; 190 resets = <&ccu RST_BUS_MMC0>; 191 reset-names = "ahb"; 192 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 193 pinctrl-names = "default"; 194 pinctrl-0 = <&mmc0_pins>; 195 status = "disabled"; 196 197 max-frequency = <150000000>; 198 cap-sd-highspeed; 199 cap-mmc-highspeed; 200 cap-sdio-irq; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 }; 204 205 mmc1: mmc@4021000 { 206 compatible = "allwinner,sun55i-a523-mmc", 207 "allwinner,sun20i-d1-mmc"; 208 reg = <0x04021000 0x1000>; 209 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 210 clock-names = "ahb", "mmc"; 211 resets = <&ccu RST_BUS_MMC1>; 212 reset-names = "ahb"; 213 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&mmc1_pins>; 216 status = "disabled"; 217 218 max-frequency = <150000000>; 219 cap-sd-highspeed; 220 cap-mmc-highspeed; 221 cap-sdio-irq; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 }; 225 226 mmc2: mmc@4022000 { 227 compatible = "allwinner,sun55i-a523-mmc", 228 "allwinner,sun20i-d1-mmc"; 229 reg = <0x04022000 0x1000>; 230 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 231 clock-names = "ahb", "mmc"; 232 resets = <&ccu RST_BUS_MMC2>; 233 reset-names = "ahb"; 234 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&mmc2_pins>; 237 status = "disabled"; 238 239 max-frequency = <150000000>; 240 cap-sd-highspeed; 241 cap-mmc-highspeed; 242 cap-sdio-irq; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 }; 246 247 wdt: watchdog@2050000 { 248 compatible = "allwinner,sun55i-a523-wdt"; 249 reg = <0x2050000 0x20>; 250 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 252 clock-names = "hosc", "losc"; 253 status = "okay"; 254 }; 255 256 uart0: serial@2500000 { 257 compatible = "snps,dw-apb-uart"; 258 reg = <0x02500000 0x400>; 259 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 260 reg-shift = <2>; 261 reg-io-width = <4>; 262 clocks = <&ccu CLK_BUS_UART0>; 263 resets = <&ccu RST_BUS_UART0>; 264 status = "disabled"; 265 }; 266 267 uart1: serial@2500400 { 268 compatible = "snps,dw-apb-uart"; 269 reg = <0x02500400 0x400>; 270 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 271 reg-shift = <2>; 272 reg-io-width = <4>; 273 clocks = <&ccu CLK_BUS_UART1>; 274 resets = <&ccu RST_BUS_UART1>; 275 status = "disabled"; 276 }; 277 278 uart2: serial@2500800 { 279 compatible = "snps,dw-apb-uart"; 280 reg = <0x02500800 0x400>; 281 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 282 reg-shift = <2>; 283 reg-io-width = <4>; 284 clocks = <&ccu CLK_BUS_UART2>; 285 resets = <&ccu RST_BUS_UART2>; 286 status = "disabled"; 287 }; 288 289 uart3: serial@2500c00 { 290 compatible = "snps,dw-apb-uart"; 291 reg = <0x02500c00 0x400>; 292 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 293 reg-shift = <2>; 294 reg-io-width = <4>; 295 clocks = <&ccu CLK_BUS_UART3>; 296 resets = <&ccu RST_BUS_UART3>; 297 status = "disabled"; 298 }; 299 300 uart4: serial@2501000 { 301 compatible = "snps,dw-apb-uart"; 302 reg = <0x02501000 0x400>; 303 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 304 reg-shift = <2>; 305 reg-io-width = <4>; 306 clocks = <&ccu CLK_BUS_UART4>; 307 resets = <&ccu RST_BUS_UART4>; 308 status = "disabled"; 309 }; 310 311 uart5: serial@2501400 { 312 compatible = "snps,dw-apb-uart"; 313 reg = <0x02501400 0x400>; 314 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 315 reg-shift = <2>; 316 reg-io-width = <4>; 317 clocks = <&ccu CLK_BUS_UART5>; 318 resets = <&ccu RST_BUS_UART5>; 319 status = "disabled"; 320 }; 321 322 uart6: serial@2501800 { 323 compatible = "snps,dw-apb-uart"; 324 reg = <0x02501800 0x400>; 325 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 326 reg-shift = <2>; 327 reg-io-width = <4>; 328 clocks = <&ccu CLK_BUS_UART6>; 329 resets = <&ccu RST_BUS_UART6>; 330 status = "disabled"; 331 }; 332 333 uart7: serial@2501c00 { 334 compatible = "snps,dw-apb-uart"; 335 reg = <0x02501c00 0x400>; 336 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 337 reg-shift = <2>; 338 reg-io-width = <4>; 339 clocks = <&ccu CLK_BUS_UART7>; 340 resets = <&ccu RST_BUS_UART7>; 341 status = "disabled"; 342 }; 343 344 i2c0: i2c@2502000 { 345 compatible = "allwinner,sun55i-a523-i2c", 346 "allwinner,sun8i-v536-i2c", 347 "allwinner,sun6i-a31-i2c"; 348 reg = <0x2502000 0x400>; 349 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&ccu CLK_BUS_I2C0>; 351 resets = <&ccu RST_BUS_I2C0>; 352 status = "disabled"; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 }; 356 357 i2c1: i2c@2502400 { 358 compatible = "allwinner,sun55i-a523-i2c", 359 "allwinner,sun8i-v536-i2c", 360 "allwinner,sun6i-a31-i2c"; 361 reg = <0x2502400 0x400>; 362 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&ccu CLK_BUS_I2C1>; 364 resets = <&ccu RST_BUS_I2C1>; 365 status = "disabled"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 }; 369 370 i2c2: i2c@2502800 { 371 compatible = "allwinner,sun55i-a523-i2c", 372 "allwinner,sun8i-v536-i2c", 373 "allwinner,sun6i-a31-i2c"; 374 reg = <0x2502800 0x400>; 375 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&ccu CLK_BUS_I2C2>; 377 resets = <&ccu RST_BUS_I2C2>; 378 status = "disabled"; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 }; 382 383 i2c3: i2c@2502c00 { 384 compatible = "allwinner,sun55i-a523-i2c", 385 "allwinner,sun8i-v536-i2c", 386 "allwinner,sun6i-a31-i2c"; 387 reg = <0x2502c00 0x400>; 388 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&ccu CLK_BUS_I2C3>; 390 resets = <&ccu RST_BUS_I2C3>; 391 status = "disabled"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 }; 395 396 i2c4: i2c@2503000 { 397 compatible = "allwinner,sun55i-a523-i2c", 398 "allwinner,sun8i-v536-i2c", 399 "allwinner,sun6i-a31-i2c"; 400 reg = <0x2503000 0x400>; 401 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&ccu CLK_BUS_I2C4>; 403 resets = <&ccu RST_BUS_I2C4>; 404 status = "disabled"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 }; 408 409 i2c5: i2c@2503400 { 410 compatible = "allwinner,sun55i-a523-i2c", 411 "allwinner,sun8i-v536-i2c", 412 "allwinner,sun6i-a31-i2c"; 413 reg = <0x2503400 0x400>; 414 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&ccu CLK_BUS_I2C5>; 416 resets = <&ccu RST_BUS_I2C5>; 417 status = "disabled"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 }; 421 422 syscon: syscon@3000000 { 423 compatible = "allwinner,sun55i-a523-system-control", 424 "allwinner,sun50i-a64-system-control"; 425 reg = <0x03000000 0x1000>; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 ranges; 429 }; 430 431 gic: interrupt-controller@3400000 { 432 compatible = "arm,gic-v3"; 433 #address-cells = <1>; 434 #interrupt-cells = <3>; 435 #size-cells = <1>; 436 ranges; 437 interrupt-controller; 438 reg = <0x3400000 0x10000>, 439 <0x3460000 0x100000>; 440 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 441 dma-noncoherent; 442 443 its: msi-controller@3440000 { 444 compatible = "arm,gic-v3-its"; 445 reg = <0x3440000 0x20000>; 446 msi-controller; 447 #msi-cells = <1>; 448 dma-noncoherent; 449 }; 450 }; 451 452 usb_otg: usb@4100000 { 453 compatible = "allwinner,sun55i-a523-musb", 454 "allwinner,sun8i-a33-musb"; 455 reg = <0x4100000 0x400>; 456 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 457 interrupt-names = "mc"; 458 clocks = <&ccu CLK_BUS_OTG>; 459 resets = <&ccu RST_BUS_OTG>; 460 extcon = <&usbphy 0>; 461 phys = <&usbphy 0>; 462 phy-names = "usb"; 463 status = "disabled"; 464 }; 465 466 usbphy: phy@4100400 { 467 compatible = "allwinner,sun55i-a523-usb-phy", 468 "allwinner,sun20i-d1-usb-phy"; 469 reg = <0x4100400 0x100>, 470 <0x4101800 0x100>, 471 <0x4200800 0x100>; 472 reg-names = "phy_ctrl", 473 "pmu0", 474 "pmu1"; 475 clocks = <&osc24M>, 476 <&osc24M>; 477 clock-names = "usb0_phy", 478 "usb1_phy"; 479 resets = <&ccu RST_USB_PHY0>, 480 <&ccu RST_USB_PHY1>; 481 reset-names = "usb0_reset", 482 "usb1_reset"; 483 status = "disabled"; 484 #phy-cells = <1>; 485 }; 486 487 ehci0: usb@4101000 { 488 compatible = "allwinner,sun55i-a523-ehci", 489 "generic-ehci"; 490 reg = <0x4101000 0x100>; 491 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_OHCI0>, 493 <&ccu CLK_BUS_EHCI0>, 494 <&ccu CLK_USB_OHCI0>; 495 resets = <&ccu RST_BUS_OHCI0>, 496 <&ccu RST_BUS_EHCI0>; 497 phys = <&usbphy 0>; 498 phy-names = "usb"; 499 status = "disabled"; 500 }; 501 502 ohci0: usb@4101400 { 503 compatible = "allwinner,sun55i-a523-ohci", 504 "generic-ohci"; 505 reg = <0x4101400 0x100>; 506 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&ccu CLK_BUS_OHCI0>, 508 <&ccu CLK_USB_OHCI0>; 509 resets = <&ccu RST_BUS_OHCI0>; 510 phys = <&usbphy 0>; 511 phy-names = "usb"; 512 status = "disabled"; 513 }; 514 515 ehci1: usb@4200000 { 516 compatible = "allwinner,sun55i-a523-ehci", 517 "generic-ehci"; 518 reg = <0x4200000 0x100>; 519 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&ccu CLK_BUS_OHCI1>, 521 <&ccu CLK_BUS_EHCI1>, 522 <&ccu CLK_USB_OHCI1>; 523 resets = <&ccu RST_BUS_OHCI1>, 524 <&ccu RST_BUS_EHCI1>; 525 phys = <&usbphy 1>; 526 phy-names = "usb"; 527 status = "disabled"; 528 }; 529 530 ohci1: usb@4200400 { 531 compatible = "allwinner,sun55i-a523-ohci", 532 "generic-ohci"; 533 reg = <0x4200400 0x100>; 534 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 535 clocks = <&ccu CLK_BUS_OHCI1>, 536 <&ccu CLK_USB_OHCI1>; 537 resets = <&ccu RST_BUS_OHCI1>; 538 phys = <&usbphy 1>; 539 phy-names = "usb"; 540 status = "disabled"; 541 }; 542 543 emac0: ethernet@4500000 { 544 compatible = "allwinner,sun55i-a523-emac0", 545 "allwinner,sun50i-a64-emac"; 546 reg = <0x04500000 0x10000>; 547 clocks = <&ccu CLK_BUS_EMAC0>; 548 clock-names = "stmmaceth"; 549 resets = <&ccu RST_BUS_EMAC0>; 550 reset-names = "stmmaceth"; 551 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 552 interrupt-names = "macirq"; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&rgmii0_pins>; 555 syscon = <&syscon>; 556 status = "disabled"; 557 558 mdio0: mdio { 559 compatible = "snps,dwmac-mdio"; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 }; 563 }; 564 565 r_ccu: clock-controller@7010000 { 566 compatible = "allwinner,sun55i-a523-r-ccu"; 567 reg = <0x7010000 0x250>; 568 clocks = <&osc24M>, 569 <&rtc CLK_OSC32K>, 570 <&rtc CLK_IOSC>, 571 <&ccu CLK_PLL_PERIPH0_200M>, 572 <&ccu CLK_PLL_AUDIO0_4X>; 573 clock-names = "hosc", 574 "losc", 575 "iosc", 576 "pll-periph", 577 "pll-audio"; 578 #clock-cells = <1>; 579 #reset-cells = <1>; 580 }; 581 582 nmi_intc: interrupt-controller@7010320 { 583 compatible = "allwinner,sun55i-a523-nmi"; 584 reg = <0x07010320 0xc>; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 588 }; 589 590 r_pio: pinctrl@7022000 { 591 compatible = "allwinner,sun55i-a523-r-pinctrl"; 592 reg = <0x7022000 0x800>; 593 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&r_ccu CLK_R_APB0>, 596 <&osc24M>, 597 <&rtc CLK_OSC32K>; 598 clock-names = "apb", "hosc", "losc"; 599 gpio-controller; 600 #gpio-cells = <3>; 601 interrupt-controller; 602 #interrupt-cells = <3>; 603 604 r_i2c_pins: r-i2c-pins { 605 pins = "PL0" ,"PL1"; 606 allwinner,pinmux = <2>; 607 function = "r_i2c0"; 608 }; 609 }; 610 611 r_i2c0: i2c@7081400 { 612 compatible = "allwinner,sun55i-a523-i2c", 613 "allwinner,sun8i-v536-i2c", 614 "allwinner,sun6i-a31-i2c"; 615 reg = <0x07081400 0x400>; 616 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 617 clocks = <&r_ccu CLK_BUS_R_I2C0>; 618 resets = <&r_ccu RST_BUS_R_I2C0>; 619 pinctrl-names = "default"; 620 pinctrl-0 = <&r_i2c_pins>; 621 status = "disabled"; 622 623 #address-cells = <1>; 624 #size-cells = <0>; 625 }; 626 627 rtc: rtc@7090000 { 628 compatible = "allwinner,sun55i-a523-rtc", 629 "allwinner,sun50i-r329-rtc"; 630 reg = <0x7090000 0x400>; 631 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&r_ccu CLK_BUS_R_RTC>, 633 <&osc24M>, 634 <&r_ccu CLK_R_AHB>; 635 clock-names = "bus", "hosc", "ahb"; 636 #clock-cells = <1>; 637 }; 638 }; 639}; 640