1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2// Copyright (C) 2023-2024 Arm Ltd. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun6i-rtc.h> 6#include <dt-bindings/clock/sun55i-a523-ccu.h> 7#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h> 8#include <dt-bindings/clock/sun55i-a523-r-ccu.h> 9#include <dt-bindings/reset/sun55i-a523-ccu.h> 10#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h> 11#include <dt-bindings/reset/sun55i-a523-r-ccu.h> 12#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> 13#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a55"; 26 device_type = "cpu"; 27 reg = <0x000>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@100 { 32 compatible = "arm,cortex-a55"; 33 device_type = "cpu"; 34 reg = <0x100>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@200 { 39 compatible = "arm,cortex-a55"; 40 device_type = "cpu"; 41 reg = <0x200>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 device_type = "cpu"; 48 reg = <0x300>; 49 enable-method = "psci"; 50 }; 51 52 cpu4: cpu@400 { 53 compatible = "arm,cortex-a55"; 54 device_type = "cpu"; 55 reg = <0x400>; 56 enable-method = "psci"; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a55"; 61 device_type = "cpu"; 62 reg = <0x500>; 63 enable-method = "psci"; 64 }; 65 66 cpu6: cpu@600 { 67 compatible = "arm,cortex-a55"; 68 device_type = "cpu"; 69 reg = <0x600>; 70 enable-method = "psci"; 71 }; 72 73 cpu7: cpu@700 { 74 compatible = "arm,cortex-a55"; 75 device_type = "cpu"; 76 reg = <0x700>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 osc24M: osc24M-clk { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 clock-output-names = "osc24M"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 91 }; 92 93 psci { 94 compatible = "arm,psci-0.2"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 arm,no-tick-in-suspend; 101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0x0 0x0 0x0 0x40000000>; 112 113 gpu: gpu@1800000 { 114 compatible = "allwinner,sun55i-a523-mali", 115 "arm,mali-valhall-jm"; 116 reg = <0x1800000 0x10000>; 117 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 120 interrupt-names = "job", "mmu", "gpu"; 121 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 122 clock-names = "core", "bus"; 123 power-domains = <&pck600 PD_GPU>; 124 resets = <&ccu RST_BUS_GPU>; 125 status = "disabled"; 126 }; 127 128 pio: pinctrl@2000000 { 129 compatible = "allwinner,sun55i-a523-pinctrl"; 130 reg = <0x2000000 0x800>; 131 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 142 clock-names = "apb", "hosc", "losc"; 143 gpio-controller; 144 #gpio-cells = <3>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 148 mmc0_pins: mmc0-pins { 149 pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; 150 allwinner,pinmux = <2>; 151 function = "mmc0"; 152 drive-strength = <30>; 153 bias-pull-up; 154 }; 155 156 /omit-if-no-ref/ 157 mmc1_pins: mmc1-pins { 158 pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; 159 allwinner,pinmux = <2>; 160 function = "mmc1"; 161 drive-strength = <30>; 162 bias-pull-up; 163 }; 164 165 mmc2_pins: mmc2-pins { 166 pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", 167 "PC9", "PC10", "PC11", "PC13", "PC14", 168 "PC15", "PC16"; 169 allwinner,pinmux = <3>; 170 function = "mmc2"; 171 drive-strength = <30>; 172 bias-pull-up; 173 }; 174 175 rgmii0_pins: rgmii0-pins { 176 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 177 "PH5", "PH6", "PH7", "PH9", "PH10", 178 "PH14", "PH15", "PH16", "PH17", "PH18"; 179 allwinner,pinmux = <5>; 180 function = "gmac0"; 181 drive-strength = <40>; 182 bias-disable; 183 }; 184 185 uart0_pb_pins: uart0-pb-pins { 186 pins = "PB9", "PB10"; 187 allwinner,pinmux = <2>; 188 function = "uart0"; 189 }; 190 191 /omit-if-no-ref/ 192 uart1_pins: uart1-pins { 193 pins = "PG6", "PG7"; 194 function = "uart1"; 195 allwinner,pinmux = <2>; 196 }; 197 198 /omit-if-no-ref/ 199 uart1_rts_cts_pins: uart1-rts-cts-pins { 200 pins = "PG8", "PG9"; 201 function = "uart1"; 202 allwinner,pinmux = <2>; 203 }; 204 }; 205 206 ccu: clock-controller@2001000 { 207 compatible = "allwinner,sun55i-a523-ccu"; 208 reg = <0x02001000 0x1000>; 209 clocks = <&osc24M>, <&rtc CLK_OSC32K>, 210 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; 211 clock-names = "hosc", "losc", 212 "iosc", "losc-fanout"; 213 #clock-cells = <1>; 214 #reset-cells = <1>; 215 }; 216 217 wdt: watchdog@2050000 { 218 compatible = "allwinner,sun55i-a523-wdt"; 219 reg = <0x2050000 0x20>; 220 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 222 clock-names = "hosc", "losc"; 223 status = "okay"; 224 }; 225 226 uart0: serial@2500000 { 227 compatible = "snps,dw-apb-uart"; 228 reg = <0x02500000 0x400>; 229 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 230 reg-shift = <2>; 231 reg-io-width = <4>; 232 clocks = <&ccu CLK_BUS_UART0>; 233 resets = <&ccu RST_BUS_UART0>; 234 status = "disabled"; 235 }; 236 237 uart1: serial@2500400 { 238 compatible = "snps,dw-apb-uart"; 239 reg = <0x02500400 0x400>; 240 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 241 reg-shift = <2>; 242 reg-io-width = <4>; 243 clocks = <&ccu CLK_BUS_UART1>; 244 resets = <&ccu RST_BUS_UART1>; 245 status = "disabled"; 246 }; 247 248 uart2: serial@2500800 { 249 compatible = "snps,dw-apb-uart"; 250 reg = <0x02500800 0x400>; 251 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 252 reg-shift = <2>; 253 reg-io-width = <4>; 254 clocks = <&ccu CLK_BUS_UART2>; 255 resets = <&ccu RST_BUS_UART2>; 256 status = "disabled"; 257 }; 258 259 uart3: serial@2500c00 { 260 compatible = "snps,dw-apb-uart"; 261 reg = <0x02500c00 0x400>; 262 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 263 reg-shift = <2>; 264 reg-io-width = <4>; 265 clocks = <&ccu CLK_BUS_UART3>; 266 resets = <&ccu RST_BUS_UART3>; 267 status = "disabled"; 268 }; 269 270 uart4: serial@2501000 { 271 compatible = "snps,dw-apb-uart"; 272 reg = <0x02501000 0x400>; 273 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 274 reg-shift = <2>; 275 reg-io-width = <4>; 276 clocks = <&ccu CLK_BUS_UART4>; 277 resets = <&ccu RST_BUS_UART4>; 278 status = "disabled"; 279 }; 280 281 uart5: serial@2501400 { 282 compatible = "snps,dw-apb-uart"; 283 reg = <0x02501400 0x400>; 284 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 285 reg-shift = <2>; 286 reg-io-width = <4>; 287 clocks = <&ccu CLK_BUS_UART5>; 288 resets = <&ccu RST_BUS_UART5>; 289 status = "disabled"; 290 }; 291 292 uart6: serial@2501800 { 293 compatible = "snps,dw-apb-uart"; 294 reg = <0x02501800 0x400>; 295 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 296 reg-shift = <2>; 297 reg-io-width = <4>; 298 clocks = <&ccu CLK_BUS_UART6>; 299 resets = <&ccu RST_BUS_UART6>; 300 status = "disabled"; 301 }; 302 303 uart7: serial@2501c00 { 304 compatible = "snps,dw-apb-uart"; 305 reg = <0x02501c00 0x400>; 306 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 307 reg-shift = <2>; 308 reg-io-width = <4>; 309 clocks = <&ccu CLK_BUS_UART7>; 310 resets = <&ccu RST_BUS_UART7>; 311 status = "disabled"; 312 }; 313 314 i2c0: i2c@2502000 { 315 compatible = "allwinner,sun55i-a523-i2c", 316 "allwinner,sun8i-v536-i2c", 317 "allwinner,sun6i-a31-i2c"; 318 reg = <0x2502000 0x400>; 319 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 320 clocks = <&ccu CLK_BUS_I2C0>; 321 resets = <&ccu RST_BUS_I2C0>; 322 status = "disabled"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 }; 326 327 i2c1: i2c@2502400 { 328 compatible = "allwinner,sun55i-a523-i2c", 329 "allwinner,sun8i-v536-i2c", 330 "allwinner,sun6i-a31-i2c"; 331 reg = <0x2502400 0x400>; 332 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_I2C1>; 334 resets = <&ccu RST_BUS_I2C1>; 335 status = "disabled"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 }; 339 340 i2c2: i2c@2502800 { 341 compatible = "allwinner,sun55i-a523-i2c", 342 "allwinner,sun8i-v536-i2c", 343 "allwinner,sun6i-a31-i2c"; 344 reg = <0x2502800 0x400>; 345 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&ccu CLK_BUS_I2C2>; 347 resets = <&ccu RST_BUS_I2C2>; 348 status = "disabled"; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 }; 352 353 i2c3: i2c@2502c00 { 354 compatible = "allwinner,sun55i-a523-i2c", 355 "allwinner,sun8i-v536-i2c", 356 "allwinner,sun6i-a31-i2c"; 357 reg = <0x2502c00 0x400>; 358 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&ccu CLK_BUS_I2C3>; 360 resets = <&ccu RST_BUS_I2C3>; 361 status = "disabled"; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 }; 365 366 i2c4: i2c@2503000 { 367 compatible = "allwinner,sun55i-a523-i2c", 368 "allwinner,sun8i-v536-i2c", 369 "allwinner,sun6i-a31-i2c"; 370 reg = <0x2503000 0x400>; 371 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&ccu CLK_BUS_I2C4>; 373 resets = <&ccu RST_BUS_I2C4>; 374 status = "disabled"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 }; 378 379 i2c5: i2c@2503400 { 380 compatible = "allwinner,sun55i-a523-i2c", 381 "allwinner,sun8i-v536-i2c", 382 "allwinner,sun6i-a31-i2c"; 383 reg = <0x2503400 0x400>; 384 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&ccu CLK_BUS_I2C5>; 386 resets = <&ccu RST_BUS_I2C5>; 387 status = "disabled"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 }; 391 392 syscon: syscon@3000000 { 393 compatible = "allwinner,sun55i-a523-system-control", 394 "allwinner,sun50i-a64-system-control"; 395 reg = <0x03000000 0x1000>; 396 #address-cells = <1>; 397 #size-cells = <1>; 398 ranges; 399 }; 400 401 sid: efuse@3006000 { 402 compatible = "allwinner,sun55i-a523-sid", 403 "allwinner,sun50i-a64-sid"; 404 reg = <0x03006000 0x1000>; 405 #address-cells = <1>; 406 #size-cells = <1>; 407 }; 408 409 gic: interrupt-controller@3400000 { 410 compatible = "arm,gic-v3"; 411 #address-cells = <1>; 412 #interrupt-cells = <3>; 413 #size-cells = <1>; 414 ranges; 415 interrupt-controller; 416 reg = <0x3400000 0x10000>, 417 <0x3460000 0x100000>; 418 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 419 dma-noncoherent; 420 421 its: msi-controller@3440000 { 422 compatible = "arm,gic-v3-its"; 423 reg = <0x3440000 0x20000>; 424 msi-controller; 425 #msi-cells = <1>; 426 dma-noncoherent; 427 }; 428 }; 429 430 mmc0: mmc@4020000 { 431 compatible = "allwinner,sun55i-a523-mmc", 432 "allwinner,sun20i-d1-mmc"; 433 reg = <0x04020000 0x1000>; 434 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 435 clock-names = "ahb", "mmc"; 436 resets = <&ccu RST_BUS_MMC0>; 437 reset-names = "ahb"; 438 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&mmc0_pins>; 441 status = "disabled"; 442 443 max-frequency = <150000000>; 444 cap-sd-highspeed; 445 cap-mmc-highspeed; 446 cap-sdio-irq; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 }; 450 451 mmc1: mmc@4021000 { 452 compatible = "allwinner,sun55i-a523-mmc", 453 "allwinner,sun20i-d1-mmc"; 454 reg = <0x04021000 0x1000>; 455 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 456 clock-names = "ahb", "mmc"; 457 resets = <&ccu RST_BUS_MMC1>; 458 reset-names = "ahb"; 459 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&mmc1_pins>; 462 status = "disabled"; 463 464 max-frequency = <150000000>; 465 cap-sd-highspeed; 466 cap-mmc-highspeed; 467 cap-sdio-irq; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 }; 471 472 mmc2: mmc@4022000 { 473 compatible = "allwinner,sun55i-a523-mmc", 474 "allwinner,sun20i-d1-mmc"; 475 reg = <0x04022000 0x1000>; 476 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 477 clock-names = "ahb", "mmc"; 478 resets = <&ccu RST_BUS_MMC2>; 479 reset-names = "ahb"; 480 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 481 pinctrl-names = "default"; 482 pinctrl-0 = <&mmc2_pins>; 483 status = "disabled"; 484 485 max-frequency = <150000000>; 486 cap-sd-highspeed; 487 cap-mmc-highspeed; 488 cap-sdio-irq; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 }; 492 493 usb_otg: usb@4100000 { 494 compatible = "allwinner,sun55i-a523-musb", 495 "allwinner,sun8i-a33-musb"; 496 reg = <0x4100000 0x400>; 497 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "mc"; 499 clocks = <&ccu CLK_BUS_OTG>; 500 resets = <&ccu RST_BUS_OTG>; 501 extcon = <&usbphy 0>; 502 phys = <&usbphy 0>; 503 phy-names = "usb"; 504 status = "disabled"; 505 }; 506 507 usbphy: phy@4100400 { 508 compatible = "allwinner,sun55i-a523-usb-phy", 509 "allwinner,sun20i-d1-usb-phy"; 510 reg = <0x4100400 0x100>, 511 <0x4101800 0x100>, 512 <0x4200800 0x100>; 513 reg-names = "phy_ctrl", 514 "pmu0", 515 "pmu1"; 516 clocks = <&osc24M>, 517 <&osc24M>; 518 clock-names = "usb0_phy", 519 "usb1_phy"; 520 resets = <&ccu RST_USB_PHY0>, 521 <&ccu RST_USB_PHY1>; 522 reset-names = "usb0_reset", 523 "usb1_reset"; 524 status = "disabled"; 525 #phy-cells = <1>; 526 }; 527 528 ehci0: usb@4101000 { 529 compatible = "allwinner,sun55i-a523-ehci", 530 "generic-ehci"; 531 reg = <0x4101000 0x100>; 532 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&ccu CLK_BUS_OHCI0>, 534 <&ccu CLK_BUS_EHCI0>, 535 <&ccu CLK_USB_OHCI0>; 536 resets = <&ccu RST_BUS_OHCI0>, 537 <&ccu RST_BUS_EHCI0>; 538 phys = <&usbphy 0>; 539 phy-names = "usb"; 540 status = "disabled"; 541 }; 542 543 ohci0: usb@4101400 { 544 compatible = "allwinner,sun55i-a523-ohci", 545 "generic-ohci"; 546 reg = <0x4101400 0x100>; 547 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&ccu CLK_BUS_OHCI0>, 549 <&ccu CLK_USB_OHCI0>; 550 resets = <&ccu RST_BUS_OHCI0>; 551 phys = <&usbphy 0>; 552 phy-names = "usb"; 553 status = "disabled"; 554 }; 555 556 ehci1: usb@4200000 { 557 compatible = "allwinner,sun55i-a523-ehci", 558 "generic-ehci"; 559 reg = <0x4200000 0x100>; 560 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&ccu CLK_BUS_OHCI1>, 562 <&ccu CLK_BUS_EHCI1>, 563 <&ccu CLK_USB_OHCI1>; 564 resets = <&ccu RST_BUS_OHCI1>, 565 <&ccu RST_BUS_EHCI1>; 566 phys = <&usbphy 1>; 567 phy-names = "usb"; 568 status = "disabled"; 569 }; 570 571 ohci1: usb@4200400 { 572 compatible = "allwinner,sun55i-a523-ohci", 573 "generic-ohci"; 574 reg = <0x4200400 0x100>; 575 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&ccu CLK_BUS_OHCI1>, 577 <&ccu CLK_USB_OHCI1>; 578 resets = <&ccu RST_BUS_OHCI1>; 579 phys = <&usbphy 1>; 580 phy-names = "usb"; 581 status = "disabled"; 582 }; 583 584 gmac0: ethernet@4500000 { 585 compatible = "allwinner,sun55i-a523-gmac0", 586 "allwinner,sun50i-a64-emac"; 587 reg = <0x04500000 0x10000>; 588 clocks = <&ccu CLK_BUS_EMAC0>; 589 clock-names = "stmmaceth"; 590 resets = <&ccu RST_BUS_EMAC0>; 591 reset-names = "stmmaceth"; 592 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 593 interrupt-names = "macirq"; 594 pinctrl-names = "default"; 595 pinctrl-0 = <&rgmii0_pins>; 596 syscon = <&syscon>; 597 status = "disabled"; 598 599 mdio0: mdio { 600 compatible = "snps,dwmac-mdio"; 601 #address-cells = <1>; 602 #size-cells = <0>; 603 }; 604 }; 605 606 ppu: power-controller@7001400 { 607 compatible = "allwinner,sun55i-a523-ppu"; 608 reg = <0x07001400 0x400>; 609 clocks = <&r_ccu CLK_BUS_R_PPU1>; 610 resets = <&r_ccu RST_BUS_R_PPU1>; 611 #power-domain-cells = <1>; 612 }; 613 614 r_ccu: clock-controller@7010000 { 615 compatible = "allwinner,sun55i-a523-r-ccu"; 616 reg = <0x7010000 0x250>; 617 clocks = <&osc24M>, 618 <&rtc CLK_OSC32K>, 619 <&rtc CLK_IOSC>, 620 <&ccu CLK_PLL_PERIPH0_200M>, 621 <&ccu CLK_PLL_AUDIO0_4X>; 622 clock-names = "hosc", 623 "losc", 624 "iosc", 625 "pll-periph", 626 "pll-audio"; 627 #clock-cells = <1>; 628 #reset-cells = <1>; 629 assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; 630 assigned-clock-rates = <200000000>, <100000000>; 631 }; 632 633 nmi_intc: interrupt-controller@7010320 { 634 compatible = "allwinner,sun55i-a523-nmi"; 635 reg = <0x07010320 0xc>; 636 interrupt-controller; 637 #interrupt-cells = <2>; 638 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 639 }; 640 641 r_pio: pinctrl@7022000 { 642 compatible = "allwinner,sun55i-a523-r-pinctrl"; 643 reg = <0x7022000 0x800>; 644 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&r_ccu CLK_R_APB0>, 647 <&osc24M>, 648 <&rtc CLK_OSC32K>; 649 clock-names = "apb", "hosc", "losc"; 650 gpio-controller; 651 #gpio-cells = <3>; 652 interrupt-controller; 653 #interrupt-cells = <3>; 654 655 r_i2c_pins: r-i2c-pins { 656 pins = "PL0" ,"PL1"; 657 allwinner,pinmux = <2>; 658 function = "r_i2c0"; 659 }; 660 }; 661 662 pck600: power-controller@7060000 { 663 compatible = "allwinner,sun55i-a523-pck-600"; 664 reg = <0x07060000 0x8000>; 665 clocks = <&r_ccu CLK_BUS_R_PPU0>; 666 resets = <&r_ccu RST_BUS_R_PPU0>; 667 #power-domain-cells = <1>; 668 }; 669 670 r_i2c0: i2c@7081400 { 671 compatible = "allwinner,sun55i-a523-i2c", 672 "allwinner,sun8i-v536-i2c", 673 "allwinner,sun6i-a31-i2c"; 674 reg = <0x07081400 0x400>; 675 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&r_ccu CLK_BUS_R_I2C0>; 677 resets = <&r_ccu RST_BUS_R_I2C0>; 678 pinctrl-names = "default"; 679 pinctrl-0 = <&r_i2c_pins>; 680 status = "disabled"; 681 682 #address-cells = <1>; 683 #size-cells = <0>; 684 }; 685 686 rtc: rtc@7090000 { 687 compatible = "allwinner,sun55i-a523-rtc", 688 "allwinner,sun50i-r329-rtc"; 689 reg = <0x7090000 0x400>; 690 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&r_ccu CLK_BUS_R_RTC>, 692 <&osc24M>, 693 <&r_ccu CLK_R_AHB>; 694 clock-names = "bus", "hosc", "ahb"; 695 #clock-cells = <1>; 696 }; 697 698 mcu_ccu: clock-controller@7102000 { 699 compatible = "allwinner,sun55i-a523-mcu-ccu"; 700 reg = <0x7102000 0x200>; 701 clocks = <&osc24M>, 702 <&rtc CLK_OSC32K>, 703 <&rtc CLK_IOSC>, 704 <&ccu CLK_PLL_AUDIO0_4X>, 705 <&ccu CLK_PLL_PERIPH0_300M>, 706 <&ccu CLK_DSP>, 707 <&ccu CLK_MBUS>, 708 <&r_ccu CLK_R_AHB>, 709 <&r_ccu CLK_R_APB0>; 710 clock-names = "hosc", 711 "losc", 712 "iosc", 713 "pll-audio0-4x", 714 "pll-periph0-300m", 715 "dsp", 716 "mbus", 717 "r-ahb", 718 "r-apb0"; 719 #clock-cells = <1>; 720 #reset-cells = <1>; 721 }; 722 723 npu: npu@7122000 { 724 compatible = "vivante,gc"; 725 reg = <0x07122000 0x1000>; 726 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, 728 <&ccu CLK_NPU>, 729 <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; 730 clock-names = "bus", "core", "reg"; 731 resets = <&mcu_ccu RST_BUS_MCU_NPU>; 732 power-domains = <&ppu PD_NPU>; 733 }; 734 }; 735}; 736