1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-tcon-top.h> 10#include <dt-bindings/reset/sun50i-h6-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 clocks = <&ccu CLK_CPUX>; 30 clock-latency-ns = <244144>; /* 8 32k periods */ 31 #cooling-cells = <2>; 32 }; 33 34 cpu1: cpu@1 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 reg = <1>; 38 enable-method = "psci"; 39 clocks = <&ccu CLK_CPUX>; 40 clock-latency-ns = <244144>; /* 8 32k periods */ 41 #cooling-cells = <2>; 42 }; 43 44 cpu2: cpu@2 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 reg = <2>; 48 enable-method = "psci"; 49 clocks = <&ccu CLK_CPUX>; 50 clock-latency-ns = <244144>; /* 8 32k periods */ 51 #cooling-cells = <2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 reg = <3>; 58 enable-method = "psci"; 59 clocks = <&ccu CLK_CPUX>; 60 clock-latency-ns = <244144>; /* 8 32k periods */ 61 #cooling-cells = <2>; 62 }; 63 }; 64 65 de: display-engine { 66 compatible = "allwinner,sun50i-h6-display-engine"; 67 allwinner,pipelines = <&mixer0>; 68 status = "disabled"; 69 }; 70 71 osc24M: osc24M_clk { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <24000000>; 75 clock-output-names = "osc24M"; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 arm,no-tick-in-suspend; 95 interrupts = <GIC_PPI 13 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 14 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 10 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 bus@1000000 { 112 compatible = "allwinner,sun50i-h6-de3", 113 "allwinner,sun50i-a64-de2"; 114 reg = <0x1000000 0x400000>; 115 allwinner,sram = <&de2_sram 1>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x1000000 0x400000>; 119 120 display_clocks: clock@0 { 121 compatible = "allwinner,sun50i-h6-de3-clk"; 122 reg = <0x0 0x10000>; 123 clocks = <&ccu CLK_BUS_DE>, 124 <&ccu CLK_DE>; 125 clock-names = "bus", 126 "mod"; 127 resets = <&ccu RST_BUS_DE>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 mixer0: mixer@100000 { 133 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 134 reg = <0x100000 0x100000>; 135 clocks = <&display_clocks CLK_BUS_MIXER0>, 136 <&display_clocks CLK_MIXER0>; 137 clock-names = "bus", 138 "mod"; 139 resets = <&display_clocks RST_MIXER0>; 140 iommus = <&iommu 0>; 141 142 ports { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 mixer0_out: port@1 { 147 reg = <1>; 148 149 mixer0_out_tcon_top_mixer0: endpoint { 150 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 151 }; 152 }; 153 }; 154 }; 155 }; 156 157 video-codec-g2@1c00000 { 158 compatible = "allwinner,sun50i-h6-vpu-g2"; 159 reg = <0x01c00000 0x1000>; 160 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; 162 clock-names = "bus", "mod"; 163 resets = <&ccu RST_BUS_VP9>; 164 iommus = <&iommu 5>; 165 }; 166 167 video-codec@1c0e000 { 168 compatible = "allwinner,sun50i-h6-video-engine"; 169 reg = <0x01c0e000 0x2000>; 170 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 171 <&ccu CLK_MBUS_VE>; 172 clock-names = "ahb", "mod", "ram"; 173 resets = <&ccu RST_BUS_VE>; 174 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 175 allwinner,sram = <&ve_sram 1>; 176 iommus = <&iommu 3>; 177 }; 178 179 gpu: gpu@1800000 { 180 compatible = "allwinner,sun50i-h6-mali", 181 "arm,mali-t720"; 182 reg = <0x01800000 0x4000>; 183 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "job", "mmu", "gpu"; 187 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 188 clock-names = "core", "bus"; 189 resets = <&ccu RST_BUS_GPU>; 190 #cooling-cells = <2>; 191 status = "disabled"; 192 }; 193 194 crypto: crypto@1904000 { 195 compatible = "allwinner,sun50i-h6-crypto"; 196 reg = <0x01904000 0x1000>; 197 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 199 clock-names = "bus", "mod", "ram"; 200 resets = <&ccu RST_BUS_CE>; 201 }; 202 203 syscon: syscon@3000000 { 204 compatible = "allwinner,sun50i-h6-system-control", 205 "allwinner,sun50i-a64-system-control"; 206 reg = <0x03000000 0x1000>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 ranges; 210 211 sram_c: sram@28000 { 212 compatible = "mmio-sram"; 213 reg = <0x00028000 0x1e000>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges = <0 0x00028000 0x1e000>; 217 218 de2_sram: sram-section@0 { 219 compatible = "allwinner,sun50i-h6-sram-c", 220 "allwinner,sun50i-a64-sram-c"; 221 reg = <0x0000 0x1e000>; 222 }; 223 }; 224 225 sram_c1: sram@1a00000 { 226 compatible = "mmio-sram"; 227 reg = <0x01a00000 0x200000>; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 ranges = <0 0x01a00000 0x200000>; 231 232 ve_sram: sram-section@0 { 233 compatible = "allwinner,sun50i-h6-sram-c1", 234 "allwinner,sun4i-a10-sram-c1"; 235 reg = <0x000000 0x200000>; 236 }; 237 }; 238 }; 239 240 ccu: clock@3001000 { 241 compatible = "allwinner,sun50i-h6-ccu"; 242 reg = <0x03001000 0x1000>; 243 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 244 clock-names = "hosc", "losc", "iosc"; 245 #clock-cells = <1>; 246 #reset-cells = <1>; 247 }; 248 249 dma: dma-controller@3002000 { 250 compatible = "allwinner,sun50i-h6-dma"; 251 reg = <0x03002000 0x1000>; 252 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 254 clock-names = "bus", "mbus"; 255 dma-channels = <16>; 256 dma-requests = <46>; 257 resets = <&ccu RST_BUS_DMA>; 258 #dma-cells = <1>; 259 }; 260 261 msgbox: mailbox@3003000 { 262 compatible = "allwinner,sun50i-h6-msgbox", 263 "allwinner,sun6i-a31-msgbox"; 264 reg = <0x03003000 0x1000>; 265 clocks = <&ccu CLK_BUS_MSGBOX>; 266 resets = <&ccu RST_BUS_MSGBOX>; 267 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 268 #mbox-cells = <1>; 269 }; 270 271 sid: efuse@3006000 { 272 compatible = "allwinner,sun50i-h6-sid"; 273 reg = <0x03006000 0x400>; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 277 ths_calibration: thermal-sensor-calibration@14 { 278 reg = <0x14 0x8>; 279 }; 280 281 cpu_speed_grade: cpu-speed-grade@1c { 282 reg = <0x1c 0x4>; 283 }; 284 }; 285 286 timer@3009000 { 287 compatible = "allwinner,sun50i-h6-timer", 288 "allwinner,sun8i-a23-timer"; 289 reg = <0x03009000 0xa0>; 290 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&osc24M>; 293 }; 294 295 watchdog: watchdog@30090a0 { 296 compatible = "allwinner,sun50i-h6-wdt", 297 "allwinner,sun6i-a31-wdt"; 298 reg = <0x030090a0 0x20>; 299 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&osc24M>; 301 /* Broken on some H6 boards */ 302 status = "disabled"; 303 }; 304 305 pwm: pwm@300a000 { 306 compatible = "allwinner,sun50i-h6-pwm"; 307 reg = <0x0300a000 0x400>; 308 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 309 clock-names = "mod", "bus"; 310 resets = <&ccu RST_BUS_PWM>; 311 #pwm-cells = <3>; 312 status = "disabled"; 313 }; 314 315 pio: pinctrl@300b000 { 316 compatible = "allwinner,sun50i-h6-pinctrl"; 317 reg = <0x0300b000 0x400>; 318 interrupt-parent = <&r_intc>; 319 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 324 clock-names = "apb", "hosc", "losc"; 325 gpio-controller; 326 #gpio-cells = <3>; 327 interrupt-controller; 328 #interrupt-cells = <3>; 329 330 ext_rgmii_pins: rgmii-pins { 331 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 332 "PD5", "PD7", "PD8", "PD9", "PD10", 333 "PD11", "PD12", "PD13", "PD19", "PD20"; 334 function = "emac"; 335 drive-strength = <40>; 336 }; 337 338 hdmi_pins: hdmi-pins { 339 pins = "PH8", "PH9", "PH10"; 340 function = "hdmi"; 341 }; 342 343 i2c0_pins: i2c0-pins { 344 pins = "PD25", "PD26"; 345 function = "i2c0"; 346 }; 347 348 i2c1_pins: i2c1-pins { 349 pins = "PH5", "PH6"; 350 function = "i2c1"; 351 }; 352 353 i2c2_pins: i2c2-pins { 354 pins = "PD23", "PD24"; 355 function = "i2c2"; 356 }; 357 358 mmc0_pins: mmc0-pins { 359 pins = "PF0", "PF1", "PF2", "PF3", 360 "PF4", "PF5"; 361 function = "mmc0"; 362 drive-strength = <30>; 363 bias-pull-up; 364 }; 365 366 /omit-if-no-ref/ 367 mmc1_pins: mmc1-pins { 368 pins = "PG0", "PG1", "PG2", "PG3", 369 "PG4", "PG5"; 370 function = "mmc1"; 371 drive-strength = <30>; 372 bias-pull-up; 373 }; 374 375 mmc2_pins: mmc2-pins { 376 pins = "PC1", "PC4", "PC5", "PC6", 377 "PC7", "PC8", "PC9", "PC10", 378 "PC11", "PC12", "PC13", "PC14"; 379 function = "mmc2"; 380 drive-strength = <30>; 381 bias-pull-up; 382 }; 383 384 /omit-if-no-ref/ 385 spi0_pins: spi0-pins { 386 pins = "PC0", "PC2", "PC3"; 387 function = "spi0"; 388 }; 389 390 /* pin shared with MMC2-CMD (eMMC) */ 391 /omit-if-no-ref/ 392 spi0_cs_pin: spi0-cs-pin { 393 pins = "PC5"; 394 function = "spi0"; 395 }; 396 397 /omit-if-no-ref/ 398 spi1_pins: spi1-pins { 399 pins = "PH4", "PH5", "PH6"; 400 function = "spi1"; 401 }; 402 403 /omit-if-no-ref/ 404 spi1_cs_pin: spi1-cs-pin { 405 pins = "PH3"; 406 function = "spi1"; 407 }; 408 409 spdif_tx_pin: spdif-tx-pin { 410 pins = "PH7"; 411 function = "spdif"; 412 }; 413 414 uart0_ph_pins: uart0-ph-pins { 415 pins = "PH0", "PH1"; 416 function = "uart0"; 417 }; 418 419 uart1_pins: uart1-pins { 420 pins = "PG6", "PG7"; 421 function = "uart1"; 422 }; 423 424 uart1_rts_cts_pins: uart1-rts-cts-pins { 425 pins = "PG8", "PG9"; 426 function = "uart1"; 427 }; 428 }; 429 430 gic: interrupt-controller@3021000 { 431 compatible = "arm,gic-400"; 432 reg = <0x03021000 0x1000>, 433 <0x03022000 0x2000>, 434 <0x03024000 0x2000>, 435 <0x03026000 0x2000>; 436 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 437 interrupt-controller; 438 #interrupt-cells = <3>; 439 }; 440 441 iommu: iommu@30f0000 { 442 compatible = "allwinner,sun50i-h6-iommu"; 443 reg = <0x030f0000 0x10000>; 444 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&ccu CLK_BUS_IOMMU>; 446 resets = <&ccu RST_BUS_IOMMU>; 447 #iommu-cells = <1>; 448 }; 449 450 mmc0: mmc@4020000 { 451 compatible = "allwinner,sun50i-h6-mmc", 452 "allwinner,sun50i-a64-mmc"; 453 reg = <0x04020000 0x1000>; 454 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 455 clock-names = "ahb", "mmc"; 456 resets = <&ccu RST_BUS_MMC0>; 457 reset-names = "ahb"; 458 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 459 pinctrl-names = "default"; 460 pinctrl-0 = <&mmc0_pins>; 461 max-frequency = <150000000>; 462 status = "disabled"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 467 mmc1: mmc@4021000 { 468 compatible = "allwinner,sun50i-h6-mmc", 469 "allwinner,sun50i-a64-mmc"; 470 reg = <0x04021000 0x1000>; 471 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 472 clock-names = "ahb", "mmc"; 473 resets = <&ccu RST_BUS_MMC1>; 474 reset-names = "ahb"; 475 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&mmc1_pins>; 478 max-frequency = <150000000>; 479 status = "disabled"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 }; 483 484 mmc2: mmc@4022000 { 485 compatible = "allwinner,sun50i-h6-emmc", 486 "allwinner,sun50i-a64-emmc"; 487 reg = <0x04022000 0x1000>; 488 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 489 clock-names = "ahb", "mmc"; 490 resets = <&ccu RST_BUS_MMC2>; 491 reset-names = "ahb"; 492 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&mmc2_pins>; 495 max-frequency = <150000000>; 496 status = "disabled"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 }; 500 501 uart0: serial@5000000 { 502 compatible = "snps,dw-apb-uart"; 503 reg = <0x05000000 0x400>; 504 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 505 reg-shift = <2>; 506 reg-io-width = <4>; 507 clocks = <&ccu CLK_BUS_UART0>; 508 resets = <&ccu RST_BUS_UART0>; 509 status = "disabled"; 510 }; 511 512 uart1: serial@5000400 { 513 compatible = "snps,dw-apb-uart"; 514 reg = <0x05000400 0x400>; 515 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 516 reg-shift = <2>; 517 reg-io-width = <4>; 518 clocks = <&ccu CLK_BUS_UART1>; 519 resets = <&ccu RST_BUS_UART1>; 520 status = "disabled"; 521 }; 522 523 uart2: serial@5000800 { 524 compatible = "snps,dw-apb-uart"; 525 reg = <0x05000800 0x400>; 526 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 527 reg-shift = <2>; 528 reg-io-width = <4>; 529 clocks = <&ccu CLK_BUS_UART2>; 530 resets = <&ccu RST_BUS_UART2>; 531 status = "disabled"; 532 }; 533 534 uart3: serial@5000c00 { 535 compatible = "snps,dw-apb-uart"; 536 reg = <0x05000c00 0x400>; 537 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 538 reg-shift = <2>; 539 reg-io-width = <4>; 540 clocks = <&ccu CLK_BUS_UART3>; 541 resets = <&ccu RST_BUS_UART3>; 542 status = "disabled"; 543 }; 544 545 i2c0: i2c@5002000 { 546 compatible = "allwinner,sun50i-h6-i2c", 547 "allwinner,sun6i-a31-i2c"; 548 reg = <0x05002000 0x400>; 549 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&ccu CLK_BUS_I2C0>; 551 resets = <&ccu RST_BUS_I2C0>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c0_pins>; 554 status = "disabled"; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 }; 558 559 i2c1: i2c@5002400 { 560 compatible = "allwinner,sun50i-h6-i2c", 561 "allwinner,sun6i-a31-i2c"; 562 reg = <0x05002400 0x400>; 563 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&ccu CLK_BUS_I2C1>; 565 resets = <&ccu RST_BUS_I2C1>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&i2c1_pins>; 568 status = "disabled"; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 }; 572 573 i2c2: i2c@5002800 { 574 compatible = "allwinner,sun50i-h6-i2c", 575 "allwinner,sun6i-a31-i2c"; 576 reg = <0x05002800 0x400>; 577 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&ccu CLK_BUS_I2C2>; 579 resets = <&ccu RST_BUS_I2C2>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&i2c2_pins>; 582 status = "disabled"; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 }; 586 587 spi0: spi@5010000 { 588 compatible = "allwinner,sun50i-h6-spi", 589 "allwinner,sun8i-h3-spi"; 590 reg = <0x05010000 0x1000>; 591 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 593 clock-names = "ahb", "mod"; 594 dmas = <&dma 22>, <&dma 22>; 595 dma-names = "rx", "tx"; 596 resets = <&ccu RST_BUS_SPI0>; 597 status = "disabled"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 }; 601 602 spi1: spi@5011000 { 603 compatible = "allwinner,sun50i-h6-spi", 604 "allwinner,sun8i-h3-spi"; 605 reg = <0x05011000 0x1000>; 606 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 608 clock-names = "ahb", "mod"; 609 dmas = <&dma 23>, <&dma 23>; 610 dma-names = "rx", "tx"; 611 resets = <&ccu RST_BUS_SPI1>; 612 status = "disabled"; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 }; 616 617 emac: ethernet@5020000 { 618 compatible = "allwinner,sun50i-h6-emac", 619 "allwinner,sun50i-a64-emac"; 620 syscon = <&syscon>; 621 reg = <0x05020000 0x10000>; 622 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "macirq"; 624 resets = <&ccu RST_BUS_EMAC>; 625 reset-names = "stmmaceth"; 626 clocks = <&ccu CLK_BUS_EMAC>; 627 clock-names = "stmmaceth"; 628 status = "disabled"; 629 630 mdio: mdio { 631 compatible = "snps,dwmac-mdio"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 }; 635 }; 636 637 i2s1: i2s@5091000 { 638 #sound-dai-cells = <0>; 639 compatible = "allwinner,sun50i-h6-i2s"; 640 reg = <0x05091000 0x1000>; 641 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 643 clock-names = "apb", "mod"; 644 dmas = <&dma 4>, <&dma 4>; 645 resets = <&ccu RST_BUS_I2S1>; 646 dma-names = "rx", "tx"; 647 status = "disabled"; 648 }; 649 650 spdif: spdif@5093000 { 651 #sound-dai-cells = <0>; 652 compatible = "allwinner,sun50i-h6-spdif"; 653 reg = <0x05093000 0x400>; 654 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 655 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 656 clock-names = "apb", "spdif"; 657 resets = <&ccu RST_BUS_SPDIF>; 658 dmas = <&dma 2>; 659 dma-names = "tx"; 660 pinctrl-names = "default"; 661 pinctrl-0 = <&spdif_tx_pin>; 662 status = "disabled"; 663 }; 664 665 usb2otg: usb@5100000 { 666 compatible = "allwinner,sun50i-h6-musb", 667 "allwinner,sun8i-a33-musb"; 668 reg = <0x05100000 0x0400>; 669 clocks = <&ccu CLK_BUS_OTG>; 670 resets = <&ccu RST_BUS_OTG>; 671 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 672 interrupt-names = "mc"; 673 phys = <&usb2phy 0>; 674 phy-names = "usb"; 675 extcon = <&usb2phy 0>; 676 status = "disabled"; 677 }; 678 679 usb2phy: phy@5100400 { 680 compatible = "allwinner,sun50i-h6-usb-phy"; 681 reg = <0x05100400 0x24>, 682 <0x05101800 0x4>, 683 <0x05311800 0x4>; 684 reg-names = "phy_ctrl", 685 "pmu0", 686 "pmu3"; 687 clocks = <&ccu CLK_USB_PHY0>, 688 <&ccu CLK_USB_PHY3>; 689 clock-names = "usb0_phy", 690 "usb3_phy"; 691 resets = <&ccu RST_USB_PHY0>, 692 <&ccu RST_USB_PHY3>; 693 reset-names = "usb0_reset", 694 "usb3_reset"; 695 status = "disabled"; 696 #phy-cells = <1>; 697 }; 698 699 ehci0: usb@5101000 { 700 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 701 reg = <0x05101000 0x100>; 702 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&ccu CLK_BUS_OHCI0>, 704 <&ccu CLK_BUS_EHCI0>, 705 <&ccu CLK_USB_OHCI0>; 706 resets = <&ccu RST_BUS_OHCI0>, 707 <&ccu RST_BUS_EHCI0>; 708 phys = <&usb2phy 0>; 709 phy-names = "usb"; 710 status = "disabled"; 711 }; 712 713 ohci0: usb@5101400 { 714 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 715 reg = <0x05101400 0x100>; 716 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&ccu CLK_BUS_OHCI0>, 718 <&ccu CLK_USB_OHCI0>; 719 resets = <&ccu RST_BUS_OHCI0>; 720 phys = <&usb2phy 0>; 721 phy-names = "usb"; 722 status = "disabled"; 723 }; 724 725 dwc3: usb@5200000 { 726 compatible = "snps,dwc3"; 727 reg = <0x05200000 0x10000>; 728 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_BUS_XHCI>, 730 <&ccu CLK_BUS_XHCI>, 731 <&rtc CLK_OSC32K>; 732 clock-names = "ref", "bus_early", "suspend"; 733 resets = <&ccu RST_BUS_XHCI>; 734 /* 735 * The datasheet of the chip doesn't declare the 736 * peripheral function, and there's no boards known 737 * to have a USB Type-B port routed to the port. 738 * In addition, no one has tested the peripheral 739 * function yet. 740 * So set the dr_mode to "host" in the DTSI file. 741 */ 742 dr_mode = "host"; 743 phys = <&usb3phy>; 744 phy-names = "usb3-phy"; 745 status = "disabled"; 746 }; 747 748 usb3phy: phy@5210000 { 749 compatible = "allwinner,sun50i-h6-usb3-phy"; 750 reg = <0x5210000 0x10000>; 751 clocks = <&ccu CLK_USB_PHY1>; 752 resets = <&ccu RST_USB_PHY1>; 753 #phy-cells = <0>; 754 status = "disabled"; 755 }; 756 757 ehci3: usb@5311000 { 758 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 759 reg = <0x05311000 0x100>; 760 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&ccu CLK_BUS_OHCI3>, 762 <&ccu CLK_BUS_EHCI3>, 763 <&ccu CLK_USB_OHCI3>; 764 resets = <&ccu RST_BUS_OHCI3>, 765 <&ccu RST_BUS_EHCI3>; 766 phys = <&usb2phy 3>; 767 phy-names = "usb"; 768 status = "disabled"; 769 }; 770 771 ohci3: usb@5311400 { 772 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 773 reg = <0x05311400 0x100>; 774 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&ccu CLK_BUS_OHCI3>, 776 <&ccu CLK_USB_OHCI3>; 777 resets = <&ccu RST_BUS_OHCI3>; 778 phys = <&usb2phy 3>; 779 phy-names = "usb"; 780 status = "disabled"; 781 }; 782 783 hdmi: hdmi@6000000 { 784 compatible = "allwinner,sun50i-h6-dw-hdmi"; 785 reg = <0x06000000 0x10000>; 786 reg-io-width = <1>; 787 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 789 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 790 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 791 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 792 "hdcp-bus"; 793 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 794 reset-names = "ctrl", "hdcp"; 795 phys = <&hdmi_phy>; 796 phy-names = "phy"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&hdmi_pins>; 799 status = "disabled"; 800 801 ports { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 805 hdmi_in: port@0 { 806 reg = <0>; 807 808 hdmi_in_tcon_top: endpoint { 809 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 810 }; 811 }; 812 813 hdmi_out: port@1 { 814 reg = <1>; 815 }; 816 }; 817 }; 818 819 hdmi_phy: hdmi-phy@6010000 { 820 compatible = "allwinner,sun50i-h6-hdmi-phy"; 821 reg = <0x06010000 0x10000>; 822 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 823 clock-names = "bus", "mod"; 824 resets = <&ccu RST_BUS_HDMI>; 825 reset-names = "phy"; 826 #phy-cells = <0>; 827 }; 828 829 tcon_top: tcon-top@6510000 { 830 compatible = "allwinner,sun50i-h6-tcon-top"; 831 reg = <0x06510000 0x1000>; 832 clocks = <&ccu CLK_BUS_TCON_TOP>, 833 <&ccu CLK_TCON_TV0>; 834 clock-names = "bus", 835 "tcon-tv0"; 836 clock-output-names = "tcon-top-tv0"; 837 resets = <&ccu RST_BUS_TCON_TOP>; 838 #clock-cells = <1>; 839 840 ports { 841 #address-cells = <1>; 842 #size-cells = <0>; 843 844 tcon_top_mixer0_in: port@0 { 845 #address-cells = <1>; 846 #size-cells = <0>; 847 reg = <0>; 848 849 tcon_top_mixer0_in_mixer0: endpoint@0 { 850 reg = <0>; 851 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 852 }; 853 }; 854 855 tcon_top_mixer0_out: port@1 { 856 #address-cells = <1>; 857 #size-cells = <0>; 858 reg = <1>; 859 860 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 861 reg = <2>; 862 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 863 }; 864 }; 865 866 tcon_top_hdmi_in: port@4 { 867 #address-cells = <1>; 868 #size-cells = <0>; 869 reg = <4>; 870 871 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 872 reg = <0>; 873 remote-endpoint = <&tcon_tv_out_tcon_top>; 874 }; 875 }; 876 877 tcon_top_hdmi_out: port@5 { 878 reg = <5>; 879 880 tcon_top_hdmi_out_hdmi: endpoint { 881 remote-endpoint = <&hdmi_in_tcon_top>; 882 }; 883 }; 884 }; 885 }; 886 887 tcon_tv: lcd-controller@6515000 { 888 compatible = "allwinner,sun50i-h6-tcon-tv", 889 "allwinner,sun8i-r40-tcon-tv"; 890 reg = <0x06515000 0x1000>; 891 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&ccu CLK_BUS_TCON_TV0>, 893 <&tcon_top CLK_TCON_TOP_TV0>; 894 clock-names = "ahb", 895 "tcon-ch1"; 896 resets = <&ccu RST_BUS_TCON_TV0>; 897 reset-names = "lcd"; 898 899 ports { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 tcon_tv_in: port@0 { 904 reg = <0>; 905 906 tcon_tv_in_tcon_top_mixer0: endpoint { 907 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 908 }; 909 }; 910 911 tcon_tv_out: port@1 { 912 #address-cells = <1>; 913 #size-cells = <0>; 914 reg = <1>; 915 916 tcon_tv_out_tcon_top: endpoint@1 { 917 reg = <1>; 918 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 919 }; 920 }; 921 }; 922 }; 923 924 rtc: rtc@7000000 { 925 compatible = "allwinner,sun50i-h6-rtc"; 926 reg = <0x07000000 0x400>; 927 interrupt-parent = <&r_intc>; 928 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 930 clock-output-names = "osc32k", "osc32k-out", "iosc"; 931 #clock-cells = <1>; 932 }; 933 934 r_ccu: clock@7010000 { 935 compatible = "allwinner,sun50i-h6-r-ccu"; 936 reg = <0x07010000 0x400>; 937 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 938 <&ccu CLK_PLL_PERIPH0>; 939 clock-names = "hosc", "losc", "iosc", "pll-periph"; 940 #clock-cells = <1>; 941 #reset-cells = <1>; 942 }; 943 944 r_watchdog: watchdog@7020400 { 945 compatible = "allwinner,sun50i-h6-wdt", 946 "allwinner,sun6i-a31-wdt"; 947 reg = <0x07020400 0x20>; 948 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 949 clocks = <&osc24M>; 950 }; 951 952 r_intc: interrupt-controller@7021000 { 953 compatible = "allwinner,sun50i-h6-r-intc"; 954 interrupt-controller; 955 #interrupt-cells = <3>; 956 reg = <0x07021000 0x400>; 957 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 958 }; 959 960 r_pio: pinctrl@7022000 { 961 compatible = "allwinner,sun50i-h6-r-pinctrl"; 962 reg = <0x07022000 0x400>; 963 interrupt-parent = <&r_intc>; 964 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 967 <&rtc CLK_OSC32K>; 968 clock-names = "apb", "hosc", "losc"; 969 gpio-controller; 970 #gpio-cells = <3>; 971 interrupt-controller; 972 #interrupt-cells = <3>; 973 974 r_i2c_pins: r-i2c-pins { 975 pins = "PL0", "PL1"; 976 function = "s_i2c"; 977 }; 978 979 r_ir_rx_pin: r-ir-rx-pin { 980 pins = "PL9"; 981 function = "s_cir_rx"; 982 }; 983 984 r_rsb_pins: r-rsb-pins { 985 pins = "PL0", "PL1"; 986 function = "s_rsb"; 987 }; 988 }; 989 990 r_ir: ir@7040000 { 991 compatible = "allwinner,sun50i-h6-ir", 992 "allwinner,sun6i-a31-ir"; 993 reg = <0x07040000 0x400>; 994 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&r_ccu CLK_R_APB1_IR>, 996 <&r_ccu CLK_IR>; 997 clock-names = "apb", "ir"; 998 resets = <&r_ccu RST_R_APB1_IR>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&r_ir_rx_pin>; 1001 status = "disabled"; 1002 }; 1003 1004 r_i2c: i2c@7081400 { 1005 compatible = "allwinner,sun50i-h6-i2c", 1006 "allwinner,sun6i-a31-i2c"; 1007 reg = <0x07081400 0x400>; 1008 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&r_ccu CLK_R_APB2_I2C>; 1010 resets = <&r_ccu RST_R_APB2_I2C>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&r_i2c_pins>; 1013 status = "disabled"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 }; 1017 1018 r_rsb: rsb@7083000 { 1019 compatible = "allwinner,sun8i-a23-rsb"; 1020 reg = <0x07083000 0x400>; 1021 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&r_ccu CLK_R_APB2_RSB>; 1023 clock-frequency = <3000000>; 1024 resets = <&r_ccu RST_R_APB2_RSB>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&r_rsb_pins>; 1027 status = "disabled"; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 }; 1031 1032 ths: thermal-sensor@5070400 { 1033 compatible = "allwinner,sun50i-h6-ths"; 1034 reg = <0x05070400 0x100>; 1035 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&ccu CLK_BUS_THS>; 1037 clock-names = "bus"; 1038 resets = <&ccu RST_BUS_THS>; 1039 nvmem-cells = <&ths_calibration>; 1040 nvmem-cell-names = "calibration"; 1041 #thermal-sensor-cells = <1>; 1042 }; 1043 }; 1044 1045 thermal-zones { 1046 cpu-thermal { 1047 polling-delay-passive = <0>; 1048 polling-delay = <0>; 1049 thermal-sensors = <&ths 0>; 1050 1051 trips { 1052 cpu_alert: cpu-alert { 1053 temperature = <85000>; 1054 hysteresis = <2000>; 1055 type = "passive"; 1056 }; 1057 1058 cpu-crit { 1059 temperature = <100000>; 1060 hysteresis = <0>; 1061 type = "critical"; 1062 }; 1063 }; 1064 1065 cooling-maps { 1066 map0 { 1067 trip = <&cpu_alert>; 1068 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1069 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1070 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1071 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1072 }; 1073 }; 1074 }; 1075 1076 gpu-thermal { 1077 polling-delay-passive = <1000>; 1078 polling-delay = <2000>; 1079 thermal-sensors = <&ths 1>; 1080 1081 trips { 1082 gpu_alert0: gpu-alert-0 { 1083 temperature = <95000>; 1084 hysteresis = <2000>; 1085 type = "passive"; 1086 }; 1087 1088 gpu_alert1: gpu-alert-1 { 1089 temperature = <100000>; 1090 hysteresis = <2000>; 1091 type = "passive"; 1092 }; 1093 1094 gpu_alert2: gpu-alert-2 { 1095 temperature = <105000>; 1096 hysteresis = <2000>; 1097 type = "passive"; 1098 }; 1099 1100 gpu-crit { 1101 temperature = <115000>; 1102 hysteresis = <0>; 1103 type = "critical"; 1104 }; 1105 }; 1106 1107 cooling-maps { 1108 // Forbid the GPU to go over 756MHz 1109 map0 { 1110 trip = <&gpu_alert0>; 1111 cooling-device = <&gpu 1 THERMAL_NO_LIMIT>; 1112 }; 1113 1114 // Forbid the GPU to go over 624MHz 1115 map1 { 1116 trip = <&gpu_alert1>; 1117 cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; 1118 }; 1119 1120 // Forbid the GPU to go over 576MHz 1121 map2 { 1122 trip = <&gpu_alert2>; 1123 cooling-device = <&gpu 3 THERMAL_NO_LIMIT>; 1124 }; 1125 }; 1126 }; 1127 }; 1128}; 1129