1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 clock-latency-ns = <244144>; /* 8 32k periods */ 30 #cooling-cells = <2>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 reg = <1>; 37 enable-method = "psci"; 38 clocks = <&ccu CLK_CPUX>; 39 clock-latency-ns = <244144>; /* 8 32k periods */ 40 #cooling-cells = <2>; 41 }; 42 43 cpu2: cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <2>; 47 enable-method = "psci"; 48 clocks = <&ccu CLK_CPUX>; 49 clock-latency-ns = <244144>; /* 8 32k periods */ 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 reg = <3>; 57 enable-method = "psci"; 58 clocks = <&ccu CLK_CPUX>; 59 clock-latency-ns = <244144>; /* 8 32k periods */ 60 #cooling-cells = <2>; 61 }; 62 }; 63 64 de: display-engine { 65 compatible = "allwinner,sun50i-h6-display-engine"; 66 allwinner,pipelines = <&mixer0>; 67 status = "disabled"; 68 }; 69 70 osc24M: osc24M_clk { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "osc24M"; 75 }; 76 77 pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-0.2"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <GIC_PPI 13 94 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 14 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 11 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 10 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 ranges; 108 109 bus@1000000 { 110 compatible = "allwinner,sun50i-h6-de3", 111 "allwinner,sun50i-a64-de2"; 112 reg = <0x1000000 0x400000>; 113 allwinner,sram = <&de2_sram 1>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges = <0 0x1000000 0x400000>; 117 118 display_clocks: clock@0 { 119 compatible = "allwinner,sun50i-h6-de3-clk"; 120 reg = <0x0 0x10000>; 121 clocks = <&ccu CLK_DE>, 122 <&ccu CLK_BUS_DE>; 123 clock-names = "mod", 124 "bus"; 125 resets = <&ccu RST_BUS_DE>; 126 #clock-cells = <1>; 127 #reset-cells = <1>; 128 }; 129 130 mixer0: mixer@100000 { 131 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 132 reg = <0x100000 0x100000>; 133 clocks = <&display_clocks CLK_BUS_MIXER0>, 134 <&display_clocks CLK_MIXER0>; 135 clock-names = "bus", 136 "mod"; 137 resets = <&display_clocks RST_MIXER0>; 138 iommus = <&iommu 0>; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 mixer0_out: port@1 { 145 reg = <1>; 146 147 mixer0_out_tcon_top_mixer0: endpoint { 148 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 149 }; 150 }; 151 }; 152 }; 153 }; 154 155 video-codec@1c0e000 { 156 compatible = "allwinner,sun50i-h6-video-engine"; 157 reg = <0x01c0e000 0x2000>; 158 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 159 <&ccu CLK_MBUS_VE>; 160 clock-names = "ahb", "mod", "ram"; 161 resets = <&ccu RST_BUS_VE>; 162 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 163 allwinner,sram = <&ve_sram 1>; 164 iommus = <&iommu 3>; 165 }; 166 167 gpu: gpu@1800000 { 168 compatible = "allwinner,sun50i-h6-mali", 169 "arm,mali-t720"; 170 reg = <0x01800000 0x4000>; 171 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 172 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 174 interrupt-names = "job", "mmu", "gpu"; 175 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 176 clock-names = "core", "bus"; 177 resets = <&ccu RST_BUS_GPU>; 178 status = "disabled"; 179 }; 180 181 crypto: crypto@1904000 { 182 compatible = "allwinner,sun50i-h6-crypto"; 183 reg = <0x01904000 0x1000>; 184 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 186 clock-names = "bus", "mod", "ram"; 187 resets = <&ccu RST_BUS_CE>; 188 }; 189 190 syscon: syscon@3000000 { 191 compatible = "allwinner,sun50i-h6-system-control", 192 "allwinner,sun50i-a64-system-control"; 193 reg = <0x03000000 0x1000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 ranges; 197 198 sram_c: sram@28000 { 199 compatible = "mmio-sram"; 200 reg = <0x00028000 0x1e000>; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges = <0 0x00028000 0x1e000>; 204 205 de2_sram: sram-section@0 { 206 compatible = "allwinner,sun50i-h6-sram-c", 207 "allwinner,sun50i-a64-sram-c"; 208 reg = <0x0000 0x1e000>; 209 }; 210 }; 211 212 sram_c1: sram@1a00000 { 213 compatible = "mmio-sram"; 214 reg = <0x01a00000 0x200000>; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges = <0 0x01a00000 0x200000>; 218 219 ve_sram: sram-section@0 { 220 compatible = "allwinner,sun50i-h6-sram-c1", 221 "allwinner,sun4i-a10-sram-c1"; 222 reg = <0x000000 0x200000>; 223 }; 224 }; 225 }; 226 227 ccu: clock@3001000 { 228 compatible = "allwinner,sun50i-h6-ccu"; 229 reg = <0x03001000 0x1000>; 230 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 231 clock-names = "hosc", "losc", "iosc"; 232 #clock-cells = <1>; 233 #reset-cells = <1>; 234 }; 235 236 dma: dma-controller@3002000 { 237 compatible = "allwinner,sun50i-h6-dma"; 238 reg = <0x03002000 0x1000>; 239 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 240 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 241 clock-names = "bus", "mbus"; 242 dma-channels = <16>; 243 dma-requests = <46>; 244 resets = <&ccu RST_BUS_DMA>; 245 #dma-cells = <1>; 246 }; 247 248 msgbox: mailbox@3003000 { 249 compatible = "allwinner,sun50i-h6-msgbox", 250 "allwinner,sun6i-a31-msgbox"; 251 reg = <0x03003000 0x1000>; 252 clocks = <&ccu CLK_BUS_MSGBOX>; 253 resets = <&ccu RST_BUS_MSGBOX>; 254 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 255 #mbox-cells = <1>; 256 }; 257 258 sid: efuse@3006000 { 259 compatible = "allwinner,sun50i-h6-sid"; 260 reg = <0x03006000 0x400>; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 264 ths_calibration: thermal-sensor-calibration@14 { 265 reg = <0x14 0x8>; 266 }; 267 268 cpu_speed_grade: cpu-speed-grade@1c { 269 reg = <0x1c 0x4>; 270 }; 271 }; 272 273 watchdog: watchdog@30090a0 { 274 compatible = "allwinner,sun50i-h6-wdt", 275 "allwinner,sun6i-a31-wdt"; 276 reg = <0x030090a0 0x20>; 277 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&osc24M>; 279 /* Broken on some H6 boards */ 280 status = "disabled"; 281 }; 282 283 pwm: pwm@300a000 { 284 compatible = "allwinner,sun50i-h6-pwm"; 285 reg = <0x0300a000 0x400>; 286 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 287 clock-names = "mod", "bus"; 288 resets = <&ccu RST_BUS_PWM>; 289 #pwm-cells = <3>; 290 status = "disabled"; 291 }; 292 293 pio: pinctrl@300b000 { 294 compatible = "allwinner,sun50i-h6-pinctrl"; 295 reg = <0x0300b000 0x400>; 296 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 300 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 301 clock-names = "apb", "hosc", "losc"; 302 gpio-controller; 303 #gpio-cells = <3>; 304 interrupt-controller; 305 #interrupt-cells = <3>; 306 307 ext_rgmii_pins: rgmii-pins { 308 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 309 "PD5", "PD7", "PD8", "PD9", "PD10", 310 "PD11", "PD12", "PD13", "PD19", "PD20"; 311 function = "emac"; 312 drive-strength = <40>; 313 }; 314 315 hdmi_pins: hdmi-pins { 316 pins = "PH8", "PH9", "PH10"; 317 function = "hdmi"; 318 }; 319 320 i2c0_pins: i2c0-pins { 321 pins = "PD25", "PD26"; 322 function = "i2c0"; 323 }; 324 325 i2c1_pins: i2c1-pins { 326 pins = "PH5", "PH6"; 327 function = "i2c1"; 328 }; 329 330 i2c2_pins: i2c2-pins { 331 pins = "PD23", "PD24"; 332 function = "i2c2"; 333 }; 334 335 mmc0_pins: mmc0-pins { 336 pins = "PF0", "PF1", "PF2", "PF3", 337 "PF4", "PF5"; 338 function = "mmc0"; 339 drive-strength = <30>; 340 bias-pull-up; 341 }; 342 343 /omit-if-no-ref/ 344 mmc1_pins: mmc1-pins { 345 pins = "PG0", "PG1", "PG2", "PG3", 346 "PG4", "PG5"; 347 function = "mmc1"; 348 drive-strength = <30>; 349 bias-pull-up; 350 }; 351 352 mmc2_pins: mmc2-pins { 353 pins = "PC1", "PC4", "PC5", "PC6", 354 "PC7", "PC8", "PC9", "PC10", 355 "PC11", "PC12", "PC13", "PC14"; 356 function = "mmc2"; 357 drive-strength = <30>; 358 bias-pull-up; 359 }; 360 361 /omit-if-no-ref/ 362 spi0_pins: spi0-pins { 363 pins = "PC0", "PC2", "PC3"; 364 function = "spi0"; 365 }; 366 367 /* pin shared with MMC2-CMD (eMMC) */ 368 /omit-if-no-ref/ 369 spi0_cs_pin: spi0-cs-pin { 370 pins = "PC5"; 371 function = "spi0"; 372 }; 373 374 /omit-if-no-ref/ 375 spi1_pins: spi1-pins { 376 pins = "PH4", "PH5", "PH6"; 377 function = "spi1"; 378 }; 379 380 /omit-if-no-ref/ 381 spi1_cs_pin: spi1-cs-pin { 382 pins = "PH3"; 383 function = "spi1"; 384 }; 385 386 spdif_tx_pin: spdif-tx-pin { 387 pins = "PH7"; 388 function = "spdif"; 389 }; 390 391 uart0_ph_pins: uart0-ph-pins { 392 pins = "PH0", "PH1"; 393 function = "uart0"; 394 }; 395 396 uart1_pins: uart1-pins { 397 pins = "PG6", "PG7"; 398 function = "uart1"; 399 }; 400 401 uart1_rts_cts_pins: uart1-rts-cts-pins { 402 pins = "PG8", "PG9"; 403 function = "uart1"; 404 }; 405 }; 406 407 gic: interrupt-controller@3021000 { 408 compatible = "arm,gic-400"; 409 reg = <0x03021000 0x1000>, 410 <0x03022000 0x2000>, 411 <0x03024000 0x2000>, 412 <0x03026000 0x2000>; 413 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 414 interrupt-controller; 415 #interrupt-cells = <3>; 416 }; 417 418 iommu: iommu@30f0000 { 419 compatible = "allwinner,sun50i-h6-iommu"; 420 reg = <0x030f0000 0x10000>; 421 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&ccu CLK_BUS_IOMMU>; 423 resets = <&ccu RST_BUS_IOMMU>; 424 #iommu-cells = <1>; 425 }; 426 427 mmc0: mmc@4020000 { 428 compatible = "allwinner,sun50i-h6-mmc", 429 "allwinner,sun50i-a64-mmc"; 430 reg = <0x04020000 0x1000>; 431 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 432 clock-names = "ahb", "mmc"; 433 resets = <&ccu RST_BUS_MMC0>; 434 reset-names = "ahb"; 435 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&mmc0_pins>; 438 status = "disabled"; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 }; 442 443 mmc1: mmc@4021000 { 444 compatible = "allwinner,sun50i-h6-mmc", 445 "allwinner,sun50i-a64-mmc"; 446 reg = <0x04021000 0x1000>; 447 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 448 clock-names = "ahb", "mmc"; 449 resets = <&ccu RST_BUS_MMC1>; 450 reset-names = "ahb"; 451 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&mmc1_pins>; 454 status = "disabled"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 }; 458 459 mmc2: mmc@4022000 { 460 compatible = "allwinner,sun50i-h6-emmc", 461 "allwinner,sun50i-a64-emmc"; 462 reg = <0x04022000 0x1000>; 463 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 464 clock-names = "ahb", "mmc"; 465 resets = <&ccu RST_BUS_MMC2>; 466 reset-names = "ahb"; 467 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 468 pinctrl-names = "default"; 469 pinctrl-0 = <&mmc2_pins>; 470 status = "disabled"; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 }; 474 475 uart0: serial@5000000 { 476 compatible = "snps,dw-apb-uart"; 477 reg = <0x05000000 0x400>; 478 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 479 reg-shift = <2>; 480 reg-io-width = <4>; 481 clocks = <&ccu CLK_BUS_UART0>; 482 resets = <&ccu RST_BUS_UART0>; 483 status = "disabled"; 484 }; 485 486 uart1: serial@5000400 { 487 compatible = "snps,dw-apb-uart"; 488 reg = <0x05000400 0x400>; 489 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 490 reg-shift = <2>; 491 reg-io-width = <4>; 492 clocks = <&ccu CLK_BUS_UART1>; 493 resets = <&ccu RST_BUS_UART1>; 494 status = "disabled"; 495 }; 496 497 uart2: serial@5000800 { 498 compatible = "snps,dw-apb-uart"; 499 reg = <0x05000800 0x400>; 500 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 501 reg-shift = <2>; 502 reg-io-width = <4>; 503 clocks = <&ccu CLK_BUS_UART2>; 504 resets = <&ccu RST_BUS_UART2>; 505 status = "disabled"; 506 }; 507 508 uart3: serial@5000c00 { 509 compatible = "snps,dw-apb-uart"; 510 reg = <0x05000c00 0x400>; 511 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 512 reg-shift = <2>; 513 reg-io-width = <4>; 514 clocks = <&ccu CLK_BUS_UART3>; 515 resets = <&ccu RST_BUS_UART3>; 516 status = "disabled"; 517 }; 518 519 i2c0: i2c@5002000 { 520 compatible = "allwinner,sun50i-h6-i2c", 521 "allwinner,sun6i-a31-i2c"; 522 reg = <0x05002000 0x400>; 523 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&ccu CLK_BUS_I2C0>; 525 resets = <&ccu RST_BUS_I2C0>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c0_pins>; 528 status = "disabled"; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 }; 532 533 i2c1: i2c@5002400 { 534 compatible = "allwinner,sun50i-h6-i2c", 535 "allwinner,sun6i-a31-i2c"; 536 reg = <0x05002400 0x400>; 537 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&ccu CLK_BUS_I2C1>; 539 resets = <&ccu RST_BUS_I2C1>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&i2c1_pins>; 542 status = "disabled"; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 }; 546 547 i2c2: i2c@5002800 { 548 compatible = "allwinner,sun50i-h6-i2c", 549 "allwinner,sun6i-a31-i2c"; 550 reg = <0x05002800 0x400>; 551 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&ccu CLK_BUS_I2C2>; 553 resets = <&ccu RST_BUS_I2C2>; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&i2c2_pins>; 556 status = "disabled"; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 }; 560 561 spi0: spi@5010000 { 562 compatible = "allwinner,sun50i-h6-spi", 563 "allwinner,sun8i-h3-spi"; 564 reg = <0x05010000 0x1000>; 565 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 567 clock-names = "ahb", "mod"; 568 dmas = <&dma 22>, <&dma 22>; 569 dma-names = "rx", "tx"; 570 resets = <&ccu RST_BUS_SPI0>; 571 status = "disabled"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 }; 575 576 spi1: spi@5011000 { 577 compatible = "allwinner,sun50i-h6-spi", 578 "allwinner,sun8i-h3-spi"; 579 reg = <0x05011000 0x1000>; 580 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 582 clock-names = "ahb", "mod"; 583 dmas = <&dma 23>, <&dma 23>; 584 dma-names = "rx", "tx"; 585 resets = <&ccu RST_BUS_SPI1>; 586 status = "disabled"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 }; 590 591 emac: ethernet@5020000 { 592 compatible = "allwinner,sun50i-h6-emac", 593 "allwinner,sun50i-a64-emac"; 594 syscon = <&syscon>; 595 reg = <0x05020000 0x10000>; 596 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 597 interrupt-names = "macirq"; 598 resets = <&ccu RST_BUS_EMAC>; 599 reset-names = "stmmaceth"; 600 clocks = <&ccu CLK_BUS_EMAC>; 601 clock-names = "stmmaceth"; 602 status = "disabled"; 603 604 mdio: mdio { 605 compatible = "snps,dwmac-mdio"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 }; 609 }; 610 611 spdif: spdif@5093000 { 612 #sound-dai-cells = <0>; 613 compatible = "allwinner,sun50i-h6-spdif"; 614 reg = <0x05093000 0x400>; 615 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 617 clock-names = "apb", "spdif"; 618 resets = <&ccu RST_BUS_SPDIF>; 619 dmas = <&dma 2>; 620 dma-names = "tx"; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&spdif_tx_pin>; 623 status = "disabled"; 624 }; 625 626 usb2otg: usb@5100000 { 627 compatible = "allwinner,sun50i-h6-musb", 628 "allwinner,sun8i-a33-musb"; 629 reg = <0x05100000 0x0400>; 630 clocks = <&ccu CLK_BUS_OTG>; 631 resets = <&ccu RST_BUS_OTG>; 632 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 633 interrupt-names = "mc"; 634 phys = <&usb2phy 0>; 635 phy-names = "usb"; 636 extcon = <&usb2phy 0>; 637 status = "disabled"; 638 }; 639 640 usb2phy: phy@5100400 { 641 compatible = "allwinner,sun50i-h6-usb-phy"; 642 reg = <0x05100400 0x24>, 643 <0x05101800 0x4>, 644 <0x05311800 0x4>; 645 reg-names = "phy_ctrl", 646 "pmu0", 647 "pmu3"; 648 clocks = <&ccu CLK_USB_PHY0>, 649 <&ccu CLK_USB_PHY3>; 650 clock-names = "usb0_phy", 651 "usb3_phy"; 652 resets = <&ccu RST_USB_PHY0>, 653 <&ccu RST_USB_PHY3>; 654 reset-names = "usb0_reset", 655 "usb3_reset"; 656 status = "disabled"; 657 #phy-cells = <1>; 658 }; 659 660 ehci0: usb@5101000 { 661 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 662 reg = <0x05101000 0x100>; 663 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&ccu CLK_BUS_OHCI0>, 665 <&ccu CLK_BUS_EHCI0>, 666 <&ccu CLK_USB_OHCI0>; 667 resets = <&ccu RST_BUS_OHCI0>, 668 <&ccu RST_BUS_EHCI0>; 669 status = "disabled"; 670 }; 671 672 ohci0: usb@5101400 { 673 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 674 reg = <0x05101400 0x100>; 675 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&ccu CLK_BUS_OHCI0>, 677 <&ccu CLK_USB_OHCI0>; 678 resets = <&ccu RST_BUS_OHCI0>; 679 status = "disabled"; 680 }; 681 682 dwc3: dwc3@5200000 { 683 compatible = "snps,dwc3"; 684 reg = <0x05200000 0x10000>; 685 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&ccu CLK_BUS_XHCI>, 687 <&ccu CLK_BUS_XHCI>, 688 <&rtc 0>; 689 clock-names = "ref", "bus_early", "suspend"; 690 resets = <&ccu RST_BUS_XHCI>; 691 /* 692 * The datasheet of the chip doesn't declare the 693 * peripheral function, and there's no boards known 694 * to have a USB Type-B port routed to the port. 695 * In addition, no one has tested the peripheral 696 * function yet. 697 * So set the dr_mode to "host" in the DTSI file. 698 */ 699 dr_mode = "host"; 700 phys = <&usb3phy>; 701 phy-names = "usb3-phy"; 702 status = "disabled"; 703 }; 704 705 usb3phy: phy@5210000 { 706 compatible = "allwinner,sun50i-h6-usb3-phy"; 707 reg = <0x5210000 0x10000>; 708 clocks = <&ccu CLK_USB_PHY1>; 709 resets = <&ccu RST_USB_PHY1>; 710 #phy-cells = <0>; 711 status = "disabled"; 712 }; 713 714 ehci3: usb@5311000 { 715 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 716 reg = <0x05311000 0x100>; 717 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&ccu CLK_BUS_OHCI3>, 719 <&ccu CLK_BUS_EHCI3>, 720 <&ccu CLK_USB_OHCI3>; 721 resets = <&ccu RST_BUS_OHCI3>, 722 <&ccu RST_BUS_EHCI3>; 723 phys = <&usb2phy 3>; 724 phy-names = "usb"; 725 status = "disabled"; 726 }; 727 728 ohci3: usb@5311400 { 729 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 730 reg = <0x05311400 0x100>; 731 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 732 clocks = <&ccu CLK_BUS_OHCI3>, 733 <&ccu CLK_USB_OHCI3>; 734 resets = <&ccu RST_BUS_OHCI3>; 735 phys = <&usb2phy 3>; 736 phy-names = "usb"; 737 status = "disabled"; 738 }; 739 740 hdmi: hdmi@6000000 { 741 compatible = "allwinner,sun50i-h6-dw-hdmi"; 742 reg = <0x06000000 0x10000>; 743 reg-io-width = <1>; 744 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 745 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 746 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 747 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 748 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 749 "hdcp-bus"; 750 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 751 reset-names = "ctrl", "hdcp"; 752 phys = <&hdmi_phy>; 753 phy-names = "phy"; 754 pinctrl-names = "default"; 755 pinctrl-0 = <&hdmi_pins>; 756 status = "disabled"; 757 758 ports { 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 hdmi_in: port@0 { 763 reg = <0>; 764 765 hdmi_in_tcon_top: endpoint { 766 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 767 }; 768 }; 769 770 hdmi_out: port@1 { 771 reg = <1>; 772 }; 773 }; 774 }; 775 776 hdmi_phy: hdmi-phy@6010000 { 777 compatible = "allwinner,sun50i-h6-hdmi-phy"; 778 reg = <0x06010000 0x10000>; 779 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 780 clock-names = "bus", "mod"; 781 resets = <&ccu RST_BUS_HDMI>; 782 reset-names = "phy"; 783 #phy-cells = <0>; 784 }; 785 786 tcon_top: tcon-top@6510000 { 787 compatible = "allwinner,sun50i-h6-tcon-top"; 788 reg = <0x06510000 0x1000>; 789 clocks = <&ccu CLK_BUS_TCON_TOP>, 790 <&ccu CLK_TCON_TV0>; 791 clock-names = "bus", 792 "tcon-tv0"; 793 clock-output-names = "tcon-top-tv0"; 794 resets = <&ccu RST_BUS_TCON_TOP>; 795 #clock-cells = <1>; 796 797 ports { 798 #address-cells = <1>; 799 #size-cells = <0>; 800 801 tcon_top_mixer0_in: port@0 { 802 #address-cells = <1>; 803 #size-cells = <0>; 804 reg = <0>; 805 806 tcon_top_mixer0_in_mixer0: endpoint@0 { 807 reg = <0>; 808 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 809 }; 810 }; 811 812 tcon_top_mixer0_out: port@1 { 813 #address-cells = <1>; 814 #size-cells = <0>; 815 reg = <1>; 816 817 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 818 reg = <2>; 819 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 820 }; 821 }; 822 823 tcon_top_hdmi_in: port@4 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <4>; 827 828 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 829 reg = <0>; 830 remote-endpoint = <&tcon_tv_out_tcon_top>; 831 }; 832 }; 833 834 tcon_top_hdmi_out: port@5 { 835 reg = <5>; 836 837 tcon_top_hdmi_out_hdmi: endpoint { 838 remote-endpoint = <&hdmi_in_tcon_top>; 839 }; 840 }; 841 }; 842 }; 843 844 tcon_tv: lcd-controller@6515000 { 845 compatible = "allwinner,sun50i-h6-tcon-tv", 846 "allwinner,sun8i-r40-tcon-tv"; 847 reg = <0x06515000 0x1000>; 848 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&ccu CLK_BUS_TCON_TV0>, 850 <&tcon_top CLK_TCON_TOP_TV0>; 851 clock-names = "ahb", 852 "tcon-ch1"; 853 resets = <&ccu RST_BUS_TCON_TV0>; 854 reset-names = "lcd"; 855 856 ports { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 860 tcon_tv_in: port@0 { 861 reg = <0>; 862 863 tcon_tv_in_tcon_top_mixer0: endpoint { 864 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 865 }; 866 }; 867 868 tcon_tv_out: port@1 { 869 #address-cells = <1>; 870 #size-cells = <0>; 871 reg = <1>; 872 873 tcon_tv_out_tcon_top: endpoint@1 { 874 reg = <1>; 875 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 876 }; 877 }; 878 }; 879 }; 880 881 rtc: rtc@7000000 { 882 compatible = "allwinner,sun50i-h6-rtc"; 883 reg = <0x07000000 0x400>; 884 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 886 clock-output-names = "osc32k", "osc32k-out", "iosc"; 887 #clock-cells = <1>; 888 }; 889 890 r_ccu: clock@7010000 { 891 compatible = "allwinner,sun50i-h6-r-ccu"; 892 reg = <0x07010000 0x400>; 893 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 894 <&ccu CLK_PLL_PERIPH0>; 895 clock-names = "hosc", "losc", "iosc", "pll-periph"; 896 #clock-cells = <1>; 897 #reset-cells = <1>; 898 }; 899 900 r_watchdog: watchdog@7020400 { 901 compatible = "allwinner,sun50i-h6-wdt", 902 "allwinner,sun6i-a31-wdt"; 903 reg = <0x07020400 0x20>; 904 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&osc24M>; 906 }; 907 908 r_intc: interrupt-controller@7021000 { 909 compatible = "allwinner,sun50i-h6-r-intc", 910 "allwinner,sun6i-a31-r-intc"; 911 interrupt-controller; 912 #interrupt-cells = <2>; 913 reg = <0x07021000 0x400>; 914 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 915 }; 916 917 r_pio: pinctrl@7022000 { 918 compatible = "allwinner,sun50i-h6-r-pinctrl"; 919 reg = <0x07022000 0x400>; 920 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 923 clock-names = "apb", "hosc", "losc"; 924 gpio-controller; 925 #gpio-cells = <3>; 926 interrupt-controller; 927 #interrupt-cells = <3>; 928 929 r_i2c_pins: r-i2c-pins { 930 pins = "PL0", "PL1"; 931 function = "s_i2c"; 932 }; 933 934 r_ir_rx_pin: r-ir-rx-pin { 935 pins = "PL9"; 936 function = "s_cir_rx"; 937 }; 938 }; 939 940 r_ir: ir@7040000 { 941 compatible = "allwinner,sun50i-h6-ir", 942 "allwinner,sun6i-a31-ir"; 943 reg = <0x07040000 0x400>; 944 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&r_ccu CLK_R_APB1_IR>, 946 <&r_ccu CLK_IR>; 947 clock-names = "apb", "ir"; 948 resets = <&r_ccu RST_R_APB1_IR>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&r_ir_rx_pin>; 951 status = "disabled"; 952 }; 953 954 r_i2c: i2c@7081400 { 955 compatible = "allwinner,sun50i-h6-i2c", 956 "allwinner,sun6i-a31-i2c"; 957 reg = <0x07081400 0x400>; 958 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&r_ccu CLK_R_APB2_I2C>; 960 resets = <&r_ccu RST_R_APB2_I2C>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&r_i2c_pins>; 963 status = "disabled"; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 }; 967 968 ths: thermal-sensor@5070400 { 969 compatible = "allwinner,sun50i-h6-ths"; 970 reg = <0x05070400 0x100>; 971 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&ccu CLK_BUS_THS>; 973 clock-names = "bus"; 974 resets = <&ccu RST_BUS_THS>; 975 nvmem-cells = <&ths_calibration>; 976 nvmem-cell-names = "calibration"; 977 #thermal-sensor-cells = <1>; 978 }; 979 }; 980 981 thermal-zones { 982 cpu-thermal { 983 polling-delay-passive = <0>; 984 polling-delay = <0>; 985 thermal-sensors = <&ths 0>; 986 987 trips { 988 cpu_alert: cpu-alert { 989 temperature = <85000>; 990 hysteresis = <2000>; 991 type = "passive"; 992 }; 993 994 cpu-crit { 995 temperature = <100000>; 996 hysteresis = <0>; 997 type = "critical"; 998 }; 999 }; 1000 1001 cooling-maps { 1002 map0 { 1003 trip = <&cpu_alert>; 1004 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1005 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1006 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1007 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1008 }; 1009 }; 1010 }; 1011 1012 gpu-thermal { 1013 polling-delay-passive = <0>; 1014 polling-delay = <0>; 1015 thermal-sensors = <&ths 1>; 1016 }; 1017 }; 1018}; 1019