1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_HAVE_TRACE_MMIO_ACCESS 52 select ARCH_INLINE_READ_LOCK if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_KEEP_MEMBLOCK 79 select ARCH_USE_CMPXCHG_LOCKREF 80 select ARCH_USE_GNU_PROPERTY 81 select ARCH_USE_MEMTEST 82 select ARCH_USE_QUEUED_RWLOCKS 83 select ARCH_USE_QUEUED_SPINLOCKS 84 select ARCH_USE_SYM_ANNOTATIONS 85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 86 select ARCH_SUPPORTS_HUGETLBFS 87 select ARCH_SUPPORTS_MEMORY_FAILURE 88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 90 select ARCH_SUPPORTS_LTO_CLANG_THIN 91 select ARCH_SUPPORTS_CFI_CLANG 92 select ARCH_SUPPORTS_ATOMIC_RMW 93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 94 select ARCH_SUPPORTS_NUMA_BALANCING 95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 97 select ARCH_WANT_DEFAULT_BPF_JIT 98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 99 select ARCH_WANT_FRAME_POINTERS 100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP 102 select ARCH_WANT_LD_ORPHAN_WARN 103 select ARCH_WANTS_NO_INSTR 104 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 105 select ARCH_HAS_UBSAN_SANITIZE_ALL 106 select ARM_AMBA 107 select ARM_ARCH_TIMER 108 select ARM_GIC 109 select AUDIT_ARCH_COMPAT_GENERIC 110 select ARM_GIC_V2M if PCI 111 select ARM_GIC_V3 112 select ARM_GIC_V3_ITS if PCI 113 select ARM_PSCI_FW 114 select BUILDTIME_TABLE_SORT 115 select CLONE_BACKWARDS 116 select COMMON_CLK 117 select CPU_PM if (SUSPEND || CPU_IDLE) 118 select CRC32 119 select DCACHE_WORD_ACCESS 120 select DMA_DIRECT_REMAP 121 select EDAC_SUPPORT 122 select FRAME_POINTER 123 select GENERIC_ALLOCATOR 124 select GENERIC_ARCH_TOPOLOGY 125 select GENERIC_CLOCKEVENTS_BROADCAST 126 select GENERIC_CPU_AUTOPROBE 127 select GENERIC_CPU_VULNERABILITIES 128 select GENERIC_EARLY_IOREMAP 129 select GENERIC_IDLE_POLL_SETUP 130 select GENERIC_IOREMAP 131 select GENERIC_IRQ_IPI 132 select GENERIC_IRQ_PROBE 133 select GENERIC_IRQ_SHOW 134 select GENERIC_IRQ_SHOW_LEVEL 135 select GENERIC_LIB_DEVMEM_IS_ALLOWED 136 select GENERIC_PCI_IOMAP 137 select GENERIC_PTDUMP 138 select GENERIC_SCHED_CLOCK 139 select GENERIC_SMP_IDLE_THREAD 140 select GENERIC_TIME_VSYSCALL 141 select GENERIC_GETTIMEOFDAY 142 select GENERIC_VDSO_TIME_NS 143 select HARDIRQS_SW_RESEND 144 select HAVE_MOVE_PMD 145 select HAVE_MOVE_PUD 146 select HAVE_PCI 147 select HAVE_ACPI_APEI if (ACPI && EFI) 148 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 149 select HAVE_ARCH_AUDITSYSCALL 150 select HAVE_ARCH_BITREVERSE 151 select HAVE_ARCH_COMPILER_H 152 select HAVE_ARCH_HUGE_VMAP 153 select HAVE_ARCH_JUMP_LABEL 154 select HAVE_ARCH_JUMP_LABEL_RELATIVE 155 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 156 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 157 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 158 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 159 # Some instrumentation may be unsound, hence EXPERT 160 select HAVE_ARCH_KCSAN if EXPERT 161 select HAVE_ARCH_KFENCE 162 select HAVE_ARCH_KGDB 163 select HAVE_ARCH_MMAP_RND_BITS 164 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 165 select HAVE_ARCH_PREL32_RELOCATIONS 166 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 167 select HAVE_ARCH_SECCOMP_FILTER 168 select HAVE_ARCH_STACKLEAK 169 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 170 select HAVE_ARCH_TRACEHOOK 171 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 172 select HAVE_ARCH_VMAP_STACK 173 select HAVE_ARM_SMCCC 174 select HAVE_ASM_MODVERSIONS 175 select HAVE_EBPF_JIT 176 select HAVE_C_RECORDMCOUNT 177 select HAVE_CMPXCHG_DOUBLE 178 select HAVE_CMPXCHG_LOCAL 179 select HAVE_CONTEXT_TRACKING_USER 180 select HAVE_DEBUG_KMEMLEAK 181 select HAVE_DMA_CONTIGUOUS 182 select HAVE_DYNAMIC_FTRACE 183 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 184 if DYNAMIC_FTRACE_WITH_REGS 185 select HAVE_EFFICIENT_UNALIGNED_ACCESS 186 select HAVE_FAST_GUP 187 select HAVE_FTRACE_MCOUNT_RECORD 188 select HAVE_FUNCTION_TRACER 189 select HAVE_FUNCTION_ERROR_INJECTION 190 select HAVE_FUNCTION_GRAPH_TRACER 191 select HAVE_GCC_PLUGINS 192 select HAVE_HW_BREAKPOINT if PERF_EVENTS 193 select HAVE_IOREMAP_PROT 194 select HAVE_IRQ_TIME_ACCOUNTING 195 select HAVE_KVM 196 select HAVE_NMI 197 select HAVE_PATA_PLATFORM 198 select HAVE_PERF_EVENTS 199 select HAVE_PERF_REGS 200 select HAVE_PERF_USER_STACK_DUMP 201 select HAVE_PREEMPT_DYNAMIC_KEY 202 select HAVE_REGS_AND_STACK_ACCESS_API 203 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 204 select HAVE_FUNCTION_ARG_ACCESS_API 205 select MMU_GATHER_RCU_TABLE_FREE 206 select HAVE_RSEQ 207 select HAVE_STACKPROTECTOR 208 select HAVE_SYSCALL_TRACEPOINTS 209 select HAVE_KPROBES 210 select HAVE_KRETPROBES 211 select HAVE_GENERIC_VDSO 212 select IOMMU_DMA if IOMMU_SUPPORT 213 select IRQ_DOMAIN 214 select IRQ_FORCED_THREADING 215 select KASAN_VMALLOC if KASAN 216 select MODULES_USE_ELF_RELA 217 select NEED_DMA_MAP_STATE 218 select NEED_SG_DMA_LENGTH 219 select OF 220 select OF_EARLY_FLATTREE 221 select PCI_DOMAINS_GENERIC if PCI 222 select PCI_ECAM if (ACPI && PCI) 223 select PCI_SYSCALL if PCI 224 select POWER_RESET 225 select POWER_SUPPLY 226 select SPARSE_IRQ 227 select SWIOTLB 228 select SYSCTL_EXCEPTION_TRACE 229 select THREAD_INFO_IN_TASK 230 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 231 select TRACE_IRQFLAGS_SUPPORT 232 select TRACE_IRQFLAGS_NMI_SUPPORT 233 help 234 ARM 64-bit (AArch64) Linux support. 235 236config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 237 def_bool CC_IS_CLANG 238 # https://github.com/ClangBuiltLinux/linux/issues/1507 239 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 240 select HAVE_DYNAMIC_FTRACE_WITH_REGS 241 242config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 243 def_bool CC_IS_GCC 244 depends on $(cc-option,-fpatchable-function-entry=2) 245 select HAVE_DYNAMIC_FTRACE_WITH_REGS 246 247config 64BIT 248 def_bool y 249 250config MMU 251 def_bool y 252 253config ARM64_PAGE_SHIFT 254 int 255 default 16 if ARM64_64K_PAGES 256 default 14 if ARM64_16K_PAGES 257 default 12 258 259config ARM64_CONT_PTE_SHIFT 260 int 261 default 5 if ARM64_64K_PAGES 262 default 7 if ARM64_16K_PAGES 263 default 4 264 265config ARM64_CONT_PMD_SHIFT 266 int 267 default 5 if ARM64_64K_PAGES 268 default 5 if ARM64_16K_PAGES 269 default 4 270 271config ARCH_MMAP_RND_BITS_MIN 272 default 14 if ARM64_64K_PAGES 273 default 16 if ARM64_16K_PAGES 274 default 18 275 276# max bits determined by the following formula: 277# VA_BITS - PAGE_SHIFT - 3 278config ARCH_MMAP_RND_BITS_MAX 279 default 19 if ARM64_VA_BITS=36 280 default 24 if ARM64_VA_BITS=39 281 default 27 if ARM64_VA_BITS=42 282 default 30 if ARM64_VA_BITS=47 283 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 284 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 285 default 33 if ARM64_VA_BITS=48 286 default 14 if ARM64_64K_PAGES 287 default 16 if ARM64_16K_PAGES 288 default 18 289 290config ARCH_MMAP_RND_COMPAT_BITS_MIN 291 default 7 if ARM64_64K_PAGES 292 default 9 if ARM64_16K_PAGES 293 default 11 294 295config ARCH_MMAP_RND_COMPAT_BITS_MAX 296 default 16 297 298config NO_IOPORT_MAP 299 def_bool y if !PCI 300 301config STACKTRACE_SUPPORT 302 def_bool y 303 304config ILLEGAL_POINTER_VALUE 305 hex 306 default 0xdead000000000000 307 308config LOCKDEP_SUPPORT 309 def_bool y 310 311config GENERIC_BUG 312 def_bool y 313 depends on BUG 314 315config GENERIC_BUG_RELATIVE_POINTERS 316 def_bool y 317 depends on GENERIC_BUG 318 319config GENERIC_HWEIGHT 320 def_bool y 321 322config GENERIC_CSUM 323 def_bool y 324 325config GENERIC_CALIBRATE_DELAY 326 def_bool y 327 328config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 329 def_bool y 330 331config SMP 332 def_bool y 333 334config KERNEL_MODE_NEON 335 def_bool y 336 337config FIX_EARLYCON_MEM 338 def_bool y 339 340config PGTABLE_LEVELS 341 int 342 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 343 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 344 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 345 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 346 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 347 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 348 349config ARCH_SUPPORTS_UPROBES 350 def_bool y 351 352config ARCH_PROC_KCORE_TEXT 353 def_bool y 354 355config BROKEN_GAS_INST 356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 357 358config KASAN_SHADOW_OFFSET 359 hex 360 depends on KASAN_GENERIC || KASAN_SW_TAGS 361 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 362 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 363 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 364 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 365 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 366 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 367 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 368 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 369 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 370 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 371 default 0xffffffffffffffff 372 373source "arch/arm64/Kconfig.platforms" 374 375menu "Kernel Features" 376 377menu "ARM errata workarounds via the alternatives framework" 378 379config ARM64_WORKAROUND_CLEAN_CACHE 380 bool 381 382config ARM64_ERRATUM_826319 383 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 384 default y 385 select ARM64_WORKAROUND_CLEAN_CACHE 386 help 387 This option adds an alternative code sequence to work around ARM 388 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 389 AXI master interface and an L2 cache. 390 391 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 392 and is unable to accept a certain write via this interface, it will 393 not progress on read data presented on the read data channel and the 394 system can deadlock. 395 396 The workaround promotes data cache clean instructions to 397 data cache clean-and-invalidate. 398 Please note that this does not necessarily enable the workaround, 399 as it depends on the alternative framework, which will only patch 400 the kernel if an affected CPU is detected. 401 402 If unsure, say Y. 403 404config ARM64_ERRATUM_827319 405 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 406 default y 407 select ARM64_WORKAROUND_CLEAN_CACHE 408 help 409 This option adds an alternative code sequence to work around ARM 410 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 411 master interface and an L2 cache. 412 413 Under certain conditions this erratum can cause a clean line eviction 414 to occur at the same time as another transaction to the same address 415 on the AMBA 5 CHI interface, which can cause data corruption if the 416 interconnect reorders the two transactions. 417 418 The workaround promotes data cache clean instructions to 419 data cache clean-and-invalidate. 420 Please note that this does not necessarily enable the workaround, 421 as it depends on the alternative framework, which will only patch 422 the kernel if an affected CPU is detected. 423 424 If unsure, say Y. 425 426config ARM64_ERRATUM_824069 427 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 428 default y 429 select ARM64_WORKAROUND_CLEAN_CACHE 430 help 431 This option adds an alternative code sequence to work around ARM 432 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 433 to a coherent interconnect. 434 435 If a Cortex-A53 processor is executing a store or prefetch for 436 write instruction at the same time as a processor in another 437 cluster is executing a cache maintenance operation to the same 438 address, then this erratum might cause a clean cache line to be 439 incorrectly marked as dirty. 440 441 The workaround promotes data cache clean instructions to 442 data cache clean-and-invalidate. 443 Please note that this option does not necessarily enable the 444 workaround, as it depends on the alternative framework, which will 445 only patch the kernel if an affected CPU is detected. 446 447 If unsure, say Y. 448 449config ARM64_ERRATUM_819472 450 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 451 default y 452 select ARM64_WORKAROUND_CLEAN_CACHE 453 help 454 This option adds an alternative code sequence to work around ARM 455 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 456 present when it is connected to a coherent interconnect. 457 458 If the processor is executing a load and store exclusive sequence at 459 the same time as a processor in another cluster is executing a cache 460 maintenance operation to the same address, then this erratum might 461 cause data corruption. 462 463 The workaround promotes data cache clean instructions to 464 data cache clean-and-invalidate. 465 Please note that this does not necessarily enable the workaround, 466 as it depends on the alternative framework, which will only patch 467 the kernel if an affected CPU is detected. 468 469 If unsure, say Y. 470 471config ARM64_ERRATUM_832075 472 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 473 default y 474 help 475 This option adds an alternative code sequence to work around ARM 476 erratum 832075 on Cortex-A57 parts up to r1p2. 477 478 Affected Cortex-A57 parts might deadlock when exclusive load/store 479 instructions to Write-Back memory are mixed with Device loads. 480 481 The workaround is to promote device loads to use Load-Acquire 482 semantics. 483 Please note that this does not necessarily enable the workaround, 484 as it depends on the alternative framework, which will only patch 485 the kernel if an affected CPU is detected. 486 487 If unsure, say Y. 488 489config ARM64_ERRATUM_834220 490 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 491 depends on KVM 492 default y 493 help 494 This option adds an alternative code sequence to work around ARM 495 erratum 834220 on Cortex-A57 parts up to r1p2. 496 497 Affected Cortex-A57 parts might report a Stage 2 translation 498 fault as the result of a Stage 1 fault for load crossing a 499 page boundary when there is a permission or device memory 500 alignment fault at Stage 1 and a translation fault at Stage 2. 501 502 The workaround is to verify that the Stage 1 translation 503 doesn't generate a fault before handling the Stage 2 fault. 504 Please note that this does not necessarily enable the workaround, 505 as it depends on the alternative framework, which will only patch 506 the kernel if an affected CPU is detected. 507 508 If unsure, say Y. 509 510config ARM64_ERRATUM_1742098 511 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 512 depends on COMPAT 513 default y 514 help 515 This option removes the AES hwcap for aarch32 user-space to 516 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 517 518 Affected parts may corrupt the AES state if an interrupt is 519 taken between a pair of AES instructions. These instructions 520 are only present if the cryptography extensions are present. 521 All software should have a fallback implementation for CPUs 522 that don't implement the cryptography extensions. 523 524 If unsure, say Y. 525 526config ARM64_ERRATUM_845719 527 bool "Cortex-A53: 845719: a load might read incorrect data" 528 depends on COMPAT 529 default y 530 help 531 This option adds an alternative code sequence to work around ARM 532 erratum 845719 on Cortex-A53 parts up to r0p4. 533 534 When running a compat (AArch32) userspace on an affected Cortex-A53 535 part, a load at EL0 from a virtual address that matches the bottom 32 536 bits of the virtual address used by a recent load at (AArch64) EL1 537 might return incorrect data. 538 539 The workaround is to write the contextidr_el1 register on exception 540 return to a 32-bit task. 541 Please note that this does not necessarily enable the workaround, 542 as it depends on the alternative framework, which will only patch 543 the kernel if an affected CPU is detected. 544 545 If unsure, say Y. 546 547config ARM64_ERRATUM_843419 548 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 549 default y 550 select ARM64_MODULE_PLTS if MODULES 551 help 552 This option links the kernel with '--fix-cortex-a53-843419' and 553 enables PLT support to replace certain ADRP instructions, which can 554 cause subsequent memory accesses to use an incorrect address on 555 Cortex-A53 parts up to r0p4. 556 557 If unsure, say Y. 558 559config ARM64_LD_HAS_FIX_ERRATUM_843419 560 def_bool $(ld-option,--fix-cortex-a53-843419) 561 562config ARM64_ERRATUM_1024718 563 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 564 default y 565 help 566 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 567 568 Affected Cortex-A55 cores (all revisions) could cause incorrect 569 update of the hardware dirty bit when the DBM/AP bits are updated 570 without a break-before-make. The workaround is to disable the usage 571 of hardware DBM locally on the affected cores. CPUs not affected by 572 this erratum will continue to use the feature. 573 574 If unsure, say Y. 575 576config ARM64_ERRATUM_1418040 577 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 578 default y 579 depends on COMPAT 580 help 581 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 582 errata 1188873 and 1418040. 583 584 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 585 cause register corruption when accessing the timer registers 586 from AArch32 userspace. 587 588 If unsure, say Y. 589 590config ARM64_WORKAROUND_SPECULATIVE_AT 591 bool 592 593config ARM64_ERRATUM_1165522 594 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 595 default y 596 select ARM64_WORKAROUND_SPECULATIVE_AT 597 help 598 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 599 600 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 601 corrupted TLBs by speculating an AT instruction during a guest 602 context switch. 603 604 If unsure, say Y. 605 606config ARM64_ERRATUM_1319367 607 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 608 default y 609 select ARM64_WORKAROUND_SPECULATIVE_AT 610 help 611 This option adds work arounds for ARM Cortex-A57 erratum 1319537 612 and A72 erratum 1319367 613 614 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 615 speculating an AT instruction during a guest context switch. 616 617 If unsure, say Y. 618 619config ARM64_ERRATUM_1530923 620 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 621 default y 622 select ARM64_WORKAROUND_SPECULATIVE_AT 623 help 624 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 625 626 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 627 corrupted TLBs by speculating an AT instruction during a guest 628 context switch. 629 630 If unsure, say Y. 631 632config ARM64_WORKAROUND_REPEAT_TLBI 633 bool 634 635config ARM64_ERRATUM_1286807 636 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 637 default y 638 select ARM64_WORKAROUND_REPEAT_TLBI 639 help 640 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 641 642 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 643 address for a cacheable mapping of a location is being 644 accessed by a core while another core is remapping the virtual 645 address to a new physical page using the recommended 646 break-before-make sequence, then under very rare circumstances 647 TLBI+DSB completes before a read using the translation being 648 invalidated has been observed by other observers. The 649 workaround repeats the TLBI+DSB operation. 650 651config ARM64_ERRATUM_1463225 652 bool "Cortex-A76: Software Step might prevent interrupt recognition" 653 default y 654 help 655 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 656 657 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 658 of a system call instruction (SVC) can prevent recognition of 659 subsequent interrupts when software stepping is disabled in the 660 exception handler of the system call and either kernel debugging 661 is enabled or VHE is in use. 662 663 Work around the erratum by triggering a dummy step exception 664 when handling a system call from a task that is being stepped 665 in a VHE configuration of the kernel. 666 667 If unsure, say Y. 668 669config ARM64_ERRATUM_1542419 670 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 671 default y 672 help 673 This option adds a workaround for ARM Neoverse-N1 erratum 674 1542419. 675 676 Affected Neoverse-N1 cores could execute a stale instruction when 677 modified by another CPU. The workaround depends on a firmware 678 counterpart. 679 680 Workaround the issue by hiding the DIC feature from EL0. This 681 forces user-space to perform cache maintenance. 682 683 If unsure, say Y. 684 685config ARM64_ERRATUM_1508412 686 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 687 default y 688 help 689 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 690 691 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 692 of a store-exclusive or read of PAR_EL1 and a load with device or 693 non-cacheable memory attributes. The workaround depends on a firmware 694 counterpart. 695 696 KVM guests must also have the workaround implemented or they can 697 deadlock the system. 698 699 Work around the issue by inserting DMB SY barriers around PAR_EL1 700 register reads and warning KVM users. The DMB barrier is sufficient 701 to prevent a speculative PAR_EL1 read. 702 703 If unsure, say Y. 704 705config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 706 bool 707 708config ARM64_ERRATUM_2051678 709 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 710 default y 711 help 712 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 713 Affected Cortex-A510 might not respect the ordering rules for 714 hardware update of the page table's dirty bit. The workaround 715 is to not enable the feature on affected CPUs. 716 717 If unsure, say Y. 718 719config ARM64_ERRATUM_2077057 720 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 721 default y 722 help 723 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 724 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 725 expected, but a Pointer Authentication trap is taken instead. The 726 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 727 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 728 729 This can only happen when EL2 is stepping EL1. 730 731 When these conditions occur, the SPSR_EL2 value is unchanged from the 732 previous guest entry, and can be restored from the in-memory copy. 733 734 If unsure, say Y. 735 736config ARM64_ERRATUM_2119858 737 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 738 default y 739 depends on CORESIGHT_TRBE 740 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 741 help 742 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 743 744 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 745 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 746 the event of a WRAP event. 747 748 Work around the issue by always making sure we move the TRBPTR_EL1 by 749 256 bytes before enabling the buffer and filling the first 256 bytes of 750 the buffer with ETM ignore packets upon disabling. 751 752 If unsure, say Y. 753 754config ARM64_ERRATUM_2139208 755 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 756 default y 757 depends on CORESIGHT_TRBE 758 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 759 help 760 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 761 762 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 763 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 764 the event of a WRAP event. 765 766 Work around the issue by always making sure we move the TRBPTR_EL1 by 767 256 bytes before enabling the buffer and filling the first 256 bytes of 768 the buffer with ETM ignore packets upon disabling. 769 770 If unsure, say Y. 771 772config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 773 bool 774 775config ARM64_ERRATUM_2054223 776 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 777 default y 778 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 779 help 780 Enable workaround for ARM Cortex-A710 erratum 2054223 781 782 Affected cores may fail to flush the trace data on a TSB instruction, when 783 the PE is in trace prohibited state. This will cause losing a few bytes 784 of the trace cached. 785 786 Workaround is to issue two TSB consecutively on affected cores. 787 788 If unsure, say Y. 789 790config ARM64_ERRATUM_2067961 791 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 792 default y 793 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 794 help 795 Enable workaround for ARM Neoverse-N2 erratum 2067961 796 797 Affected cores may fail to flush the trace data on a TSB instruction, when 798 the PE is in trace prohibited state. This will cause losing a few bytes 799 of the trace cached. 800 801 Workaround is to issue two TSB consecutively on affected cores. 802 803 If unsure, say Y. 804 805config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 806 bool 807 808config ARM64_ERRATUM_2253138 809 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 810 depends on CORESIGHT_TRBE 811 default y 812 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 813 help 814 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 815 816 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 817 for TRBE. Under some conditions, the TRBE might generate a write to the next 818 virtually addressed page following the last page of the TRBE address space 819 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 820 821 Work around this in the driver by always making sure that there is a 822 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 823 824 If unsure, say Y. 825 826config ARM64_ERRATUM_2224489 827 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 828 depends on CORESIGHT_TRBE 829 default y 830 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 831 help 832 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 833 834 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 835 for TRBE. Under some conditions, the TRBE might generate a write to the next 836 virtually addressed page following the last page of the TRBE address space 837 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 838 839 Work around this in the driver by always making sure that there is a 840 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 841 842 If unsure, say Y. 843 844config ARM64_ERRATUM_2441009 845 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 846 default y 847 select ARM64_WORKAROUND_REPEAT_TLBI 848 help 849 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 850 851 Under very rare circumstances, affected Cortex-A510 CPUs 852 may not handle a race between a break-before-make sequence on one 853 CPU, and another CPU accessing the same page. This could allow a 854 store to a page that has been unmapped. 855 856 Work around this by adding the affected CPUs to the list that needs 857 TLB sequences to be done twice. 858 859 If unsure, say Y. 860 861config ARM64_ERRATUM_2064142 862 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 863 depends on CORESIGHT_TRBE 864 default y 865 help 866 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 867 868 Affected Cortex-A510 core might fail to write into system registers after the 869 TRBE has been disabled. Under some conditions after the TRBE has been disabled 870 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 871 and TRBTRG_EL1 will be ignored and will not be effected. 872 873 Work around this in the driver by executing TSB CSYNC and DSB after collection 874 is stopped and before performing a system register write to one of the affected 875 registers. 876 877 If unsure, say Y. 878 879config ARM64_ERRATUM_2038923 880 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 881 depends on CORESIGHT_TRBE 882 default y 883 help 884 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 885 886 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 887 prohibited within the CPU. As a result, the trace buffer or trace buffer state 888 might be corrupted. This happens after TRBE buffer has been enabled by setting 889 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 890 execution changes from a context, in which trace is prohibited to one where it 891 isn't, or vice versa. In these mentioned conditions, the view of whether trace 892 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 893 the trace buffer state might be corrupted. 894 895 Work around this in the driver by preventing an inconsistent view of whether the 896 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 897 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 898 two ISB instructions if no ERET is to take place. 899 900 If unsure, say Y. 901 902config ARM64_ERRATUM_1902691 903 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 904 depends on CORESIGHT_TRBE 905 default y 906 help 907 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 908 909 Affected Cortex-A510 core might cause trace data corruption, when being written 910 into the memory. Effectively TRBE is broken and hence cannot be used to capture 911 trace data. 912 913 Work around this problem in the driver by just preventing TRBE initialization on 914 affected cpus. The firmware must have disabled the access to TRBE for the kernel 915 on such implementations. This will cover the kernel for any firmware that doesn't 916 do this already. 917 918 If unsure, say Y. 919 920config ARM64_ERRATUM_2457168 921 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 922 depends on ARM64_AMU_EXTN 923 default y 924 help 925 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 926 927 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 928 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 929 incorrectly giving a significantly higher output value. 930 931 Work around this problem by returning 0 when reading the affected counter in 932 key locations that results in disabling all users of this counter. This effect 933 is the same to firmware disabling affected counters. 934 935 If unsure, say Y. 936 937config CAVIUM_ERRATUM_22375 938 bool "Cavium erratum 22375, 24313" 939 default y 940 help 941 Enable workaround for errata 22375 and 24313. 942 943 This implements two gicv3-its errata workarounds for ThunderX. Both 944 with a small impact affecting only ITS table allocation. 945 946 erratum 22375: only alloc 8MB table size 947 erratum 24313: ignore memory access type 948 949 The fixes are in ITS initialization and basically ignore memory access 950 type and table size provided by the TYPER and BASER registers. 951 952 If unsure, say Y. 953 954config CAVIUM_ERRATUM_23144 955 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 956 depends on NUMA 957 default y 958 help 959 ITS SYNC command hang for cross node io and collections/cpu mapping. 960 961 If unsure, say Y. 962 963config CAVIUM_ERRATUM_23154 964 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 965 default y 966 help 967 The ThunderX GICv3 implementation requires a modified version for 968 reading the IAR status to ensure data synchronization 969 (access to icc_iar1_el1 is not sync'ed before and after). 970 971 It also suffers from erratum 38545 (also present on Marvell's 972 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 973 spuriously presented to the CPU interface. 974 975 If unsure, say Y. 976 977config CAVIUM_ERRATUM_27456 978 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 979 default y 980 help 981 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 982 instructions may cause the icache to become corrupted if it 983 contains data for a non-current ASID. The fix is to 984 invalidate the icache when changing the mm context. 985 986 If unsure, say Y. 987 988config CAVIUM_ERRATUM_30115 989 bool "Cavium erratum 30115: Guest may disable interrupts in host" 990 default y 991 help 992 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 993 1.2, and T83 Pass 1.0, KVM guest execution may disable 994 interrupts in host. Trapping both GICv3 group-0 and group-1 995 accesses sidesteps the issue. 996 997 If unsure, say Y. 998 999config CAVIUM_TX2_ERRATUM_219 1000 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1001 default y 1002 help 1003 On Cavium ThunderX2, a load, store or prefetch instruction between a 1004 TTBR update and the corresponding context synchronizing operation can 1005 cause a spurious Data Abort to be delivered to any hardware thread in 1006 the CPU core. 1007 1008 Work around the issue by avoiding the problematic code sequence and 1009 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1010 trap handler performs the corresponding register access, skips the 1011 instruction and ensures context synchronization by virtue of the 1012 exception return. 1013 1014 If unsure, say Y. 1015 1016config FUJITSU_ERRATUM_010001 1017 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1018 default y 1019 help 1020 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1021 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1022 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1023 This fault occurs under a specific hardware condition when a 1024 load/store instruction performs an address translation using: 1025 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1026 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1027 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1028 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1029 1030 The workaround is to ensure these bits are clear in TCR_ELx. 1031 The workaround only affects the Fujitsu-A64FX. 1032 1033 If unsure, say Y. 1034 1035config HISILICON_ERRATUM_161600802 1036 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1037 default y 1038 help 1039 The HiSilicon Hip07 SoC uses the wrong redistributor base 1040 when issued ITS commands such as VMOVP and VMAPP, and requires 1041 a 128kB offset to be applied to the target address in this commands. 1042 1043 If unsure, say Y. 1044 1045config QCOM_FALKOR_ERRATUM_1003 1046 bool "Falkor E1003: Incorrect translation due to ASID change" 1047 default y 1048 help 1049 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1050 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1051 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1052 then only for entries in the walk cache, since the leaf translation 1053 is unchanged. Work around the erratum by invalidating the walk cache 1054 entries for the trampoline before entering the kernel proper. 1055 1056config QCOM_FALKOR_ERRATUM_1009 1057 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1058 default y 1059 select ARM64_WORKAROUND_REPEAT_TLBI 1060 help 1061 On Falkor v1, the CPU may prematurely complete a DSB following a 1062 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1063 one more time to fix the issue. 1064 1065 If unsure, say Y. 1066 1067config QCOM_QDF2400_ERRATUM_0065 1068 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1069 default y 1070 help 1071 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1072 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1073 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1074 1075 If unsure, say Y. 1076 1077config QCOM_FALKOR_ERRATUM_E1041 1078 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1079 default y 1080 help 1081 Falkor CPU may speculatively fetch instructions from an improper 1082 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1083 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1084 1085 If unsure, say Y. 1086 1087config NVIDIA_CARMEL_CNP_ERRATUM 1088 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1089 default y 1090 help 1091 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1092 invalidate shared TLB entries installed by a different core, as it would 1093 on standard ARM cores. 1094 1095 If unsure, say Y. 1096 1097config SOCIONEXT_SYNQUACER_PREITS 1098 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1099 default y 1100 help 1101 Socionext Synquacer SoCs implement a separate h/w block to generate 1102 MSI doorbell writes with non-zero values for the device ID. 1103 1104 If unsure, say Y. 1105 1106endmenu # "ARM errata workarounds via the alternatives framework" 1107 1108choice 1109 prompt "Page size" 1110 default ARM64_4K_PAGES 1111 help 1112 Page size (translation granule) configuration. 1113 1114config ARM64_4K_PAGES 1115 bool "4KB" 1116 help 1117 This feature enables 4KB pages support. 1118 1119config ARM64_16K_PAGES 1120 bool "16KB" 1121 help 1122 The system will use 16KB pages support. AArch32 emulation 1123 requires applications compiled with 16K (or a multiple of 16K) 1124 aligned segments. 1125 1126config ARM64_64K_PAGES 1127 bool "64KB" 1128 help 1129 This feature enables 64KB pages support (4KB by default) 1130 allowing only two levels of page tables and faster TLB 1131 look-up. AArch32 emulation requires applications compiled 1132 with 64K aligned segments. 1133 1134endchoice 1135 1136choice 1137 prompt "Virtual address space size" 1138 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1139 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1140 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1141 help 1142 Allows choosing one of multiple possible virtual address 1143 space sizes. The level of translation table is determined by 1144 a combination of page size and virtual address space size. 1145 1146config ARM64_VA_BITS_36 1147 bool "36-bit" if EXPERT 1148 depends on ARM64_16K_PAGES 1149 1150config ARM64_VA_BITS_39 1151 bool "39-bit" 1152 depends on ARM64_4K_PAGES 1153 1154config ARM64_VA_BITS_42 1155 bool "42-bit" 1156 depends on ARM64_64K_PAGES 1157 1158config ARM64_VA_BITS_47 1159 bool "47-bit" 1160 depends on ARM64_16K_PAGES 1161 1162config ARM64_VA_BITS_48 1163 bool "48-bit" 1164 1165config ARM64_VA_BITS_52 1166 bool "52-bit" 1167 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1168 help 1169 Enable 52-bit virtual addressing for userspace when explicitly 1170 requested via a hint to mmap(). The kernel will also use 52-bit 1171 virtual addresses for its own mappings (provided HW support for 1172 this feature is available, otherwise it reverts to 48-bit). 1173 1174 NOTE: Enabling 52-bit virtual addressing in conjunction with 1175 ARMv8.3 Pointer Authentication will result in the PAC being 1176 reduced from 7 bits to 3 bits, which may have a significant 1177 impact on its susceptibility to brute-force attacks. 1178 1179 If unsure, select 48-bit virtual addressing instead. 1180 1181endchoice 1182 1183config ARM64_FORCE_52BIT 1184 bool "Force 52-bit virtual addresses for userspace" 1185 depends on ARM64_VA_BITS_52 && EXPERT 1186 help 1187 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1188 to maintain compatibility with older software by providing 48-bit VAs 1189 unless a hint is supplied to mmap. 1190 1191 This configuration option disables the 48-bit compatibility logic, and 1192 forces all userspace addresses to be 52-bit on HW that supports it. One 1193 should only enable this configuration option for stress testing userspace 1194 memory management code. If unsure say N here. 1195 1196config ARM64_VA_BITS 1197 int 1198 default 36 if ARM64_VA_BITS_36 1199 default 39 if ARM64_VA_BITS_39 1200 default 42 if ARM64_VA_BITS_42 1201 default 47 if ARM64_VA_BITS_47 1202 default 48 if ARM64_VA_BITS_48 1203 default 52 if ARM64_VA_BITS_52 1204 1205choice 1206 prompt "Physical address space size" 1207 default ARM64_PA_BITS_48 1208 help 1209 Choose the maximum physical address range that the kernel will 1210 support. 1211 1212config ARM64_PA_BITS_48 1213 bool "48-bit" 1214 1215config ARM64_PA_BITS_52 1216 bool "52-bit (ARMv8.2)" 1217 depends on ARM64_64K_PAGES 1218 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1219 help 1220 Enable support for a 52-bit physical address space, introduced as 1221 part of the ARMv8.2-LPA extension. 1222 1223 With this enabled, the kernel will also continue to work on CPUs that 1224 do not support ARMv8.2-LPA, but with some added memory overhead (and 1225 minor performance overhead). 1226 1227endchoice 1228 1229config ARM64_PA_BITS 1230 int 1231 default 48 if ARM64_PA_BITS_48 1232 default 52 if ARM64_PA_BITS_52 1233 1234choice 1235 prompt "Endianness" 1236 default CPU_LITTLE_ENDIAN 1237 help 1238 Select the endianness of data accesses performed by the CPU. Userspace 1239 applications will need to be compiled and linked for the endianness 1240 that is selected here. 1241 1242config CPU_BIG_ENDIAN 1243 bool "Build big-endian kernel" 1244 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1245 help 1246 Say Y if you plan on running a kernel with a big-endian userspace. 1247 1248config CPU_LITTLE_ENDIAN 1249 bool "Build little-endian kernel" 1250 help 1251 Say Y if you plan on running a kernel with a little-endian userspace. 1252 This is usually the case for distributions targeting arm64. 1253 1254endchoice 1255 1256config SCHED_MC 1257 bool "Multi-core scheduler support" 1258 help 1259 Multi-core scheduler support improves the CPU scheduler's decision 1260 making when dealing with multi-core CPU chips at a cost of slightly 1261 increased overhead in some places. If unsure say N here. 1262 1263config SCHED_CLUSTER 1264 bool "Cluster scheduler support" 1265 help 1266 Cluster scheduler support improves the CPU scheduler's decision 1267 making when dealing with machines that have clusters of CPUs. 1268 Cluster usually means a couple of CPUs which are placed closely 1269 by sharing mid-level caches, last-level cache tags or internal 1270 busses. 1271 1272config SCHED_SMT 1273 bool "SMT scheduler support" 1274 help 1275 Improves the CPU scheduler's decision making when dealing with 1276 MultiThreading at a cost of slightly increased overhead in some 1277 places. If unsure say N here. 1278 1279config NR_CPUS 1280 int "Maximum number of CPUs (2-4096)" 1281 range 2 4096 1282 default "256" 1283 1284config HOTPLUG_CPU 1285 bool "Support for hot-pluggable CPUs" 1286 select GENERIC_IRQ_MIGRATION 1287 help 1288 Say Y here to experiment with turning CPUs off and on. CPUs 1289 can be controlled through /sys/devices/system/cpu. 1290 1291# Common NUMA Features 1292config NUMA 1293 bool "NUMA Memory Allocation and Scheduler Support" 1294 select GENERIC_ARCH_NUMA 1295 select ACPI_NUMA if ACPI 1296 select OF_NUMA 1297 select HAVE_SETUP_PER_CPU_AREA 1298 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1299 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1300 select USE_PERCPU_NUMA_NODE_ID 1301 help 1302 Enable NUMA (Non-Uniform Memory Access) support. 1303 1304 The kernel will try to allocate memory used by a CPU on the 1305 local memory of the CPU and add some more 1306 NUMA awareness to the kernel. 1307 1308config NODES_SHIFT 1309 int "Maximum NUMA Nodes (as a power of 2)" 1310 range 1 10 1311 default "4" 1312 depends on NUMA 1313 help 1314 Specify the maximum number of NUMA Nodes available on the target 1315 system. Increases memory reserved to accommodate various tables. 1316 1317source "kernel/Kconfig.hz" 1318 1319config ARCH_SPARSEMEM_ENABLE 1320 def_bool y 1321 select SPARSEMEM_VMEMMAP_ENABLE 1322 select SPARSEMEM_VMEMMAP 1323 1324config HW_PERF_EVENTS 1325 def_bool y 1326 depends on ARM_PMU 1327 1328# Supported by clang >= 7.0 or GCC >= 12.0.0 1329config CC_HAVE_SHADOW_CALL_STACK 1330 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1331 1332config PARAVIRT 1333 bool "Enable paravirtualization code" 1334 help 1335 This changes the kernel so it can modify itself when it is run 1336 under a hypervisor, potentially improving performance significantly 1337 over full virtualization. 1338 1339config PARAVIRT_TIME_ACCOUNTING 1340 bool "Paravirtual steal time accounting" 1341 select PARAVIRT 1342 help 1343 Select this option to enable fine granularity task steal time 1344 accounting. Time spent executing other tasks in parallel with 1345 the current vCPU is discounted from the vCPU power. To account for 1346 that, there can be a small performance impact. 1347 1348 If in doubt, say N here. 1349 1350config KEXEC 1351 depends on PM_SLEEP_SMP 1352 select KEXEC_CORE 1353 bool "kexec system call" 1354 help 1355 kexec is a system call that implements the ability to shutdown your 1356 current kernel, and to start another kernel. It is like a reboot 1357 but it is independent of the system firmware. And like a reboot 1358 you can start any kernel with it, not just Linux. 1359 1360config KEXEC_FILE 1361 bool "kexec file based system call" 1362 select KEXEC_CORE 1363 select HAVE_IMA_KEXEC if IMA 1364 help 1365 This is new version of kexec system call. This system call is 1366 file based and takes file descriptors as system call argument 1367 for kernel and initramfs as opposed to list of segments as 1368 accepted by previous system call. 1369 1370config KEXEC_SIG 1371 bool "Verify kernel signature during kexec_file_load() syscall" 1372 depends on KEXEC_FILE 1373 help 1374 Select this option to verify a signature with loaded kernel 1375 image. If configured, any attempt of loading a image without 1376 valid signature will fail. 1377 1378 In addition to that option, you need to enable signature 1379 verification for the corresponding kernel image type being 1380 loaded in order for this to work. 1381 1382config KEXEC_IMAGE_VERIFY_SIG 1383 bool "Enable Image signature verification support" 1384 default y 1385 depends on KEXEC_SIG 1386 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1387 help 1388 Enable Image signature verification support. 1389 1390comment "Support for PE file signature verification disabled" 1391 depends on KEXEC_SIG 1392 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1393 1394config CRASH_DUMP 1395 bool "Build kdump crash kernel" 1396 help 1397 Generate crash dump after being started by kexec. This should 1398 be normally only set in special crash dump kernels which are 1399 loaded in the main kernel with kexec-tools into a specially 1400 reserved region and then later executed after a crash by 1401 kdump/kexec. 1402 1403 For more details see Documentation/admin-guide/kdump/kdump.rst 1404 1405config TRANS_TABLE 1406 def_bool y 1407 depends on HIBERNATION || KEXEC_CORE 1408 1409config XEN_DOM0 1410 def_bool y 1411 depends on XEN 1412 1413config XEN 1414 bool "Xen guest support on ARM64" 1415 depends on ARM64 && OF 1416 select SWIOTLB_XEN 1417 select PARAVIRT 1418 help 1419 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1420 1421config FORCE_MAX_ZONEORDER 1422 int 1423 default "14" if ARM64_64K_PAGES 1424 default "12" if ARM64_16K_PAGES 1425 default "11" 1426 help 1427 The kernel memory allocator divides physically contiguous memory 1428 blocks into "zones", where each zone is a power of two number of 1429 pages. This option selects the largest power of two that the kernel 1430 keeps in the memory allocator. If you need to allocate very large 1431 blocks of physically contiguous memory, then you may need to 1432 increase this value. 1433 1434 This config option is actually maximum order plus one. For example, 1435 a value of 11 means that the largest free memory block is 2^10 pages. 1436 1437 We make sure that we can allocate upto a HugePage size for each configuration. 1438 Hence we have : 1439 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1440 1441 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1442 4M allocations matching the default size used by generic code. 1443 1444config UNMAP_KERNEL_AT_EL0 1445 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1446 default y 1447 help 1448 Speculation attacks against some high-performance processors can 1449 be used to bypass MMU permission checks and leak kernel data to 1450 userspace. This can be defended against by unmapping the kernel 1451 when running in userspace, mapping it back in on exception entry 1452 via a trampoline page in the vector table. 1453 1454 If unsure, say Y. 1455 1456config MITIGATE_SPECTRE_BRANCH_HISTORY 1457 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1458 default y 1459 help 1460 Speculation attacks against some high-performance processors can 1461 make use of branch history to influence future speculation. 1462 When taking an exception from user-space, a sequence of branches 1463 or a firmware call overwrites the branch history. 1464 1465config RODATA_FULL_DEFAULT_ENABLED 1466 bool "Apply r/o permissions of VM areas also to their linear aliases" 1467 default y 1468 help 1469 Apply read-only attributes of VM areas to the linear alias of 1470 the backing pages as well. This prevents code or read-only data 1471 from being modified (inadvertently or intentionally) via another 1472 mapping of the same memory page. This additional enhancement can 1473 be turned off at runtime by passing rodata=[off|on] (and turned on 1474 with rodata=full if this option is set to 'n') 1475 1476 This requires the linear region to be mapped down to pages, 1477 which may adversely affect performance in some cases. 1478 1479config ARM64_SW_TTBR0_PAN 1480 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1481 help 1482 Enabling this option prevents the kernel from accessing 1483 user-space memory directly by pointing TTBR0_EL1 to a reserved 1484 zeroed area and reserved ASID. The user access routines 1485 restore the valid TTBR0_EL1 temporarily. 1486 1487config ARM64_TAGGED_ADDR_ABI 1488 bool "Enable the tagged user addresses syscall ABI" 1489 default y 1490 help 1491 When this option is enabled, user applications can opt in to a 1492 relaxed ABI via prctl() allowing tagged addresses to be passed 1493 to system calls as pointer arguments. For details, see 1494 Documentation/arm64/tagged-address-abi.rst. 1495 1496menuconfig COMPAT 1497 bool "Kernel support for 32-bit EL0" 1498 depends on ARM64_4K_PAGES || EXPERT 1499 select HAVE_UID16 1500 select OLD_SIGSUSPEND3 1501 select COMPAT_OLD_SIGACTION 1502 help 1503 This option enables support for a 32-bit EL0 running under a 64-bit 1504 kernel at EL1. AArch32-specific components such as system calls, 1505 the user helper functions, VFP support and the ptrace interface are 1506 handled appropriately by the kernel. 1507 1508 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1509 that you will only be able to execute AArch32 binaries that were compiled 1510 with page size aligned segments. 1511 1512 If you want to execute 32-bit userspace applications, say Y. 1513 1514if COMPAT 1515 1516config KUSER_HELPERS 1517 bool "Enable kuser helpers page for 32-bit applications" 1518 default y 1519 help 1520 Warning: disabling this option may break 32-bit user programs. 1521 1522 Provide kuser helpers to compat tasks. The kernel provides 1523 helper code to userspace in read only form at a fixed location 1524 to allow userspace to be independent of the CPU type fitted to 1525 the system. This permits binaries to be run on ARMv4 through 1526 to ARMv8 without modification. 1527 1528 See Documentation/arm/kernel_user_helpers.rst for details. 1529 1530 However, the fixed address nature of these helpers can be used 1531 by ROP (return orientated programming) authors when creating 1532 exploits. 1533 1534 If all of the binaries and libraries which run on your platform 1535 are built specifically for your platform, and make no use of 1536 these helpers, then you can turn this option off to hinder 1537 such exploits. However, in that case, if a binary or library 1538 relying on those helpers is run, it will not function correctly. 1539 1540 Say N here only if you are absolutely certain that you do not 1541 need these helpers; otherwise, the safe option is to say Y. 1542 1543config COMPAT_VDSO 1544 bool "Enable vDSO for 32-bit applications" 1545 depends on !CPU_BIG_ENDIAN 1546 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1547 select GENERIC_COMPAT_VDSO 1548 default y 1549 help 1550 Place in the process address space of 32-bit applications an 1551 ELF shared object providing fast implementations of gettimeofday 1552 and clock_gettime. 1553 1554 You must have a 32-bit build of glibc 2.22 or later for programs 1555 to seamlessly take advantage of this. 1556 1557config THUMB2_COMPAT_VDSO 1558 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1559 depends on COMPAT_VDSO 1560 default y 1561 help 1562 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1563 otherwise with '-marm'. 1564 1565menuconfig ARMV8_DEPRECATED 1566 bool "Emulate deprecated/obsolete ARMv8 instructions" 1567 depends on SYSCTL 1568 help 1569 Legacy software support may require certain instructions 1570 that have been deprecated or obsoleted in the architecture. 1571 1572 Enable this config to enable selective emulation of these 1573 features. 1574 1575 If unsure, say Y 1576 1577if ARMV8_DEPRECATED 1578 1579config SWP_EMULATION 1580 bool "Emulate SWP/SWPB instructions" 1581 help 1582 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1583 they are always undefined. Say Y here to enable software 1584 emulation of these instructions for userspace using LDXR/STXR. 1585 This feature can be controlled at runtime with the abi.swp 1586 sysctl which is disabled by default. 1587 1588 In some older versions of glibc [<=2.8] SWP is used during futex 1589 trylock() operations with the assumption that the code will not 1590 be preempted. This invalid assumption may be more likely to fail 1591 with SWP emulation enabled, leading to deadlock of the user 1592 application. 1593 1594 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1595 on an external transaction monitoring block called a global 1596 monitor to maintain update atomicity. If your system does not 1597 implement a global monitor, this option can cause programs that 1598 perform SWP operations to uncached memory to deadlock. 1599 1600 If unsure, say Y 1601 1602config CP15_BARRIER_EMULATION 1603 bool "Emulate CP15 Barrier instructions" 1604 help 1605 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1606 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1607 strongly recommended to use the ISB, DSB, and DMB 1608 instructions instead. 1609 1610 Say Y here to enable software emulation of these 1611 instructions for AArch32 userspace code. When this option is 1612 enabled, CP15 barrier usage is traced which can help 1613 identify software that needs updating. This feature can be 1614 controlled at runtime with the abi.cp15_barrier sysctl. 1615 1616 If unsure, say Y 1617 1618config SETEND_EMULATION 1619 bool "Emulate SETEND instruction" 1620 help 1621 The SETEND instruction alters the data-endianness of the 1622 AArch32 EL0, and is deprecated in ARMv8. 1623 1624 Say Y here to enable software emulation of the instruction 1625 for AArch32 userspace code. This feature can be controlled 1626 at runtime with the abi.setend sysctl. 1627 1628 Note: All the cpus on the system must have mixed endian support at EL0 1629 for this feature to be enabled. If a new CPU - which doesn't support mixed 1630 endian - is hotplugged in after this feature has been enabled, there could 1631 be unexpected results in the applications. 1632 1633 If unsure, say Y 1634endif # ARMV8_DEPRECATED 1635 1636endif # COMPAT 1637 1638menu "ARMv8.1 architectural features" 1639 1640config ARM64_HW_AFDBM 1641 bool "Support for hardware updates of the Access and Dirty page flags" 1642 default y 1643 help 1644 The ARMv8.1 architecture extensions introduce support for 1645 hardware updates of the access and dirty information in page 1646 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1647 capable processors, accesses to pages with PTE_AF cleared will 1648 set this bit instead of raising an access flag fault. 1649 Similarly, writes to read-only pages with the DBM bit set will 1650 clear the read-only bit (AP[2]) instead of raising a 1651 permission fault. 1652 1653 Kernels built with this configuration option enabled continue 1654 to work on pre-ARMv8.1 hardware and the performance impact is 1655 minimal. If unsure, say Y. 1656 1657config ARM64_PAN 1658 bool "Enable support for Privileged Access Never (PAN)" 1659 default y 1660 help 1661 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1662 prevents the kernel or hypervisor from accessing user-space (EL0) 1663 memory directly. 1664 1665 Choosing this option will cause any unprotected (not using 1666 copy_to_user et al) memory access to fail with a permission fault. 1667 1668 The feature is detected at runtime, and will remain as a 'nop' 1669 instruction if the cpu does not implement the feature. 1670 1671config AS_HAS_LDAPR 1672 def_bool $(as-instr,.arch_extension rcpc) 1673 1674config AS_HAS_LSE_ATOMICS 1675 def_bool $(as-instr,.arch_extension lse) 1676 1677config ARM64_LSE_ATOMICS 1678 bool 1679 default ARM64_USE_LSE_ATOMICS 1680 depends on AS_HAS_LSE_ATOMICS 1681 1682config ARM64_USE_LSE_ATOMICS 1683 bool "Atomic instructions" 1684 depends on JUMP_LABEL 1685 default y 1686 help 1687 As part of the Large System Extensions, ARMv8.1 introduces new 1688 atomic instructions that are designed specifically to scale in 1689 very large systems. 1690 1691 Say Y here to make use of these instructions for the in-kernel 1692 atomic routines. This incurs a small overhead on CPUs that do 1693 not support these instructions and requires the kernel to be 1694 built with binutils >= 2.25 in order for the new instructions 1695 to be used. 1696 1697endmenu # "ARMv8.1 architectural features" 1698 1699menu "ARMv8.2 architectural features" 1700 1701config AS_HAS_ARMV8_2 1702 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1703 1704config AS_HAS_SHA3 1705 def_bool $(as-instr,.arch armv8.2-a+sha3) 1706 1707config ARM64_PMEM 1708 bool "Enable support for persistent memory" 1709 select ARCH_HAS_PMEM_API 1710 select ARCH_HAS_UACCESS_FLUSHCACHE 1711 help 1712 Say Y to enable support for the persistent memory API based on the 1713 ARMv8.2 DCPoP feature. 1714 1715 The feature is detected at runtime, and the kernel will use DC CVAC 1716 operations if DC CVAP is not supported (following the behaviour of 1717 DC CVAP itself if the system does not define a point of persistence). 1718 1719config ARM64_RAS_EXTN 1720 bool "Enable support for RAS CPU Extensions" 1721 default y 1722 help 1723 CPUs that support the Reliability, Availability and Serviceability 1724 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1725 errors, classify them and report them to software. 1726 1727 On CPUs with these extensions system software can use additional 1728 barriers to determine if faults are pending and read the 1729 classification from a new set of registers. 1730 1731 Selecting this feature will allow the kernel to use these barriers 1732 and access the new registers if the system supports the extension. 1733 Platform RAS features may additionally depend on firmware support. 1734 1735config ARM64_CNP 1736 bool "Enable support for Common Not Private (CNP) translations" 1737 default y 1738 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1739 help 1740 Common Not Private (CNP) allows translation table entries to 1741 be shared between different PEs in the same inner shareable 1742 domain, so the hardware can use this fact to optimise the 1743 caching of such entries in the TLB. 1744 1745 Selecting this option allows the CNP feature to be detected 1746 at runtime, and does not affect PEs that do not implement 1747 this feature. 1748 1749endmenu # "ARMv8.2 architectural features" 1750 1751menu "ARMv8.3 architectural features" 1752 1753config ARM64_PTR_AUTH 1754 bool "Enable support for pointer authentication" 1755 default y 1756 help 1757 Pointer authentication (part of the ARMv8.3 Extensions) provides 1758 instructions for signing and authenticating pointers against secret 1759 keys, which can be used to mitigate Return Oriented Programming (ROP) 1760 and other attacks. 1761 1762 This option enables these instructions at EL0 (i.e. for userspace). 1763 Choosing this option will cause the kernel to initialise secret keys 1764 for each process at exec() time, with these keys being 1765 context-switched along with the process. 1766 1767 The feature is detected at runtime. If the feature is not present in 1768 hardware it will not be advertised to userspace/KVM guest nor will it 1769 be enabled. 1770 1771 If the feature is present on the boot CPU but not on a late CPU, then 1772 the late CPU will be parked. Also, if the boot CPU does not have 1773 address auth and the late CPU has then the late CPU will still boot 1774 but with the feature disabled. On such a system, this option should 1775 not be selected. 1776 1777config ARM64_PTR_AUTH_KERNEL 1778 bool "Use pointer authentication for kernel" 1779 default y 1780 depends on ARM64_PTR_AUTH 1781 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1782 # Modern compilers insert a .note.gnu.property section note for PAC 1783 # which is only understood by binutils starting with version 2.33.1. 1784 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1785 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1786 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1787 help 1788 If the compiler supports the -mbranch-protection or 1789 -msign-return-address flag (e.g. GCC 7 or later), then this option 1790 will cause the kernel itself to be compiled with return address 1791 protection. In this case, and if the target hardware is known to 1792 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1793 disabled with minimal loss of protection. 1794 1795 This feature works with FUNCTION_GRAPH_TRACER option only if 1796 DYNAMIC_FTRACE_WITH_REGS is enabled. 1797 1798config CC_HAS_BRANCH_PROT_PAC_RET 1799 # GCC 9 or later, clang 8 or later 1800 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1801 1802config CC_HAS_SIGN_RETURN_ADDRESS 1803 # GCC 7, 8 1804 def_bool $(cc-option,-msign-return-address=all) 1805 1806config AS_HAS_PAC 1807 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1808 1809config AS_HAS_CFI_NEGATE_RA_STATE 1810 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1811 1812endmenu # "ARMv8.3 architectural features" 1813 1814menu "ARMv8.4 architectural features" 1815 1816config ARM64_AMU_EXTN 1817 bool "Enable support for the Activity Monitors Unit CPU extension" 1818 default y 1819 help 1820 The activity monitors extension is an optional extension introduced 1821 by the ARMv8.4 CPU architecture. This enables support for version 1 1822 of the activity monitors architecture, AMUv1. 1823 1824 To enable the use of this extension on CPUs that implement it, say Y. 1825 1826 Note that for architectural reasons, firmware _must_ implement AMU 1827 support when running on CPUs that present the activity monitors 1828 extension. The required support is present in: 1829 * Version 1.5 and later of the ARM Trusted Firmware 1830 1831 For kernels that have this configuration enabled but boot with broken 1832 firmware, you may need to say N here until the firmware is fixed. 1833 Otherwise you may experience firmware panics or lockups when 1834 accessing the counter registers. Even if you are not observing these 1835 symptoms, the values returned by the register reads might not 1836 correctly reflect reality. Most commonly, the value read will be 0, 1837 indicating that the counter is not enabled. 1838 1839config AS_HAS_ARMV8_4 1840 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1841 1842config ARM64_TLB_RANGE 1843 bool "Enable support for tlbi range feature" 1844 default y 1845 depends on AS_HAS_ARMV8_4 1846 help 1847 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1848 range of input addresses. 1849 1850 The feature introduces new assembly instructions, and they were 1851 support when binutils >= 2.30. 1852 1853endmenu # "ARMv8.4 architectural features" 1854 1855menu "ARMv8.5 architectural features" 1856 1857config AS_HAS_ARMV8_5 1858 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1859 1860config ARM64_BTI 1861 bool "Branch Target Identification support" 1862 default y 1863 help 1864 Branch Target Identification (part of the ARMv8.5 Extensions) 1865 provides a mechanism to limit the set of locations to which computed 1866 branch instructions such as BR or BLR can jump. 1867 1868 To make use of BTI on CPUs that support it, say Y. 1869 1870 BTI is intended to provide complementary protection to other control 1871 flow integrity protection mechanisms, such as the Pointer 1872 authentication mechanism provided as part of the ARMv8.3 Extensions. 1873 For this reason, it does not make sense to enable this option without 1874 also enabling support for pointer authentication. Thus, when 1875 enabling this option you should also select ARM64_PTR_AUTH=y. 1876 1877 Userspace binaries must also be specifically compiled to make use of 1878 this mechanism. If you say N here or the hardware does not support 1879 BTI, such binaries can still run, but you get no additional 1880 enforcement of branch destinations. 1881 1882config ARM64_BTI_KERNEL 1883 bool "Use Branch Target Identification for kernel" 1884 default y 1885 depends on ARM64_BTI 1886 depends on ARM64_PTR_AUTH_KERNEL 1887 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1888 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1889 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1890 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 1891 depends on !CC_IS_GCC 1892 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1893 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1894 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1895 help 1896 Build the kernel with Branch Target Identification annotations 1897 and enable enforcement of this for kernel code. When this option 1898 is enabled and the system supports BTI all kernel code including 1899 modular code must have BTI enabled. 1900 1901config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1902 # GCC 9 or later, clang 8 or later 1903 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1904 1905config ARM64_E0PD 1906 bool "Enable support for E0PD" 1907 default y 1908 help 1909 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1910 that EL0 accesses made via TTBR1 always fault in constant time, 1911 providing similar benefits to KASLR as those provided by KPTI, but 1912 with lower overhead and without disrupting legitimate access to 1913 kernel memory such as SPE. 1914 1915 This option enables E0PD for TTBR1 where available. 1916 1917config ARM64_AS_HAS_MTE 1918 # Initial support for MTE went in binutils 2.32.0, checked with 1919 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1920 # as a late addition to the final architecture spec (LDGM/STGM) 1921 # is only supported in the newer 2.32.x and 2.33 binutils 1922 # versions, hence the extra "stgm" instruction check below. 1923 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1924 1925config ARM64_MTE 1926 bool "Memory Tagging Extension support" 1927 default y 1928 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1929 depends on AS_HAS_ARMV8_5 1930 depends on AS_HAS_LSE_ATOMICS 1931 # Required for tag checking in the uaccess routines 1932 depends on ARM64_PAN 1933 select ARCH_HAS_SUBPAGE_FAULTS 1934 select ARCH_USES_HIGH_VMA_FLAGS 1935 help 1936 Memory Tagging (part of the ARMv8.5 Extensions) provides 1937 architectural support for run-time, always-on detection of 1938 various classes of memory error to aid with software debugging 1939 to eliminate vulnerabilities arising from memory-unsafe 1940 languages. 1941 1942 This option enables the support for the Memory Tagging 1943 Extension at EL0 (i.e. for userspace). 1944 1945 Selecting this option allows the feature to be detected at 1946 runtime. Any secondary CPU not implementing this feature will 1947 not be allowed a late bring-up. 1948 1949 Userspace binaries that want to use this feature must 1950 explicitly opt in. The mechanism for the userspace is 1951 described in: 1952 1953 Documentation/arm64/memory-tagging-extension.rst. 1954 1955endmenu # "ARMv8.5 architectural features" 1956 1957menu "ARMv8.7 architectural features" 1958 1959config ARM64_EPAN 1960 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1961 default y 1962 depends on ARM64_PAN 1963 help 1964 Enhanced Privileged Access Never (EPAN) allows Privileged 1965 Access Never to be used with Execute-only mappings. 1966 1967 The feature is detected at runtime, and will remain disabled 1968 if the cpu does not implement the feature. 1969endmenu # "ARMv8.7 architectural features" 1970 1971config ARM64_SVE 1972 bool "ARM Scalable Vector Extension support" 1973 default y 1974 help 1975 The Scalable Vector Extension (SVE) is an extension to the AArch64 1976 execution state which complements and extends the SIMD functionality 1977 of the base architecture to support much larger vectors and to enable 1978 additional vectorisation opportunities. 1979 1980 To enable use of this extension on CPUs that implement it, say Y. 1981 1982 On CPUs that support the SVE2 extensions, this option will enable 1983 those too. 1984 1985 Note that for architectural reasons, firmware _must_ implement SVE 1986 support when running on SVE capable hardware. The required support 1987 is present in: 1988 1989 * version 1.5 and later of the ARM Trusted Firmware 1990 * the AArch64 boot wrapper since commit 5e1261e08abf 1991 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1992 1993 For other firmware implementations, consult the firmware documentation 1994 or vendor. 1995 1996 If you need the kernel to boot on SVE-capable hardware with broken 1997 firmware, you may need to say N here until you get your firmware 1998 fixed. Otherwise, you may experience firmware panics or lockups when 1999 booting the kernel. If unsure and you are not observing these 2000 symptoms, you should assume that it is safe to say Y. 2001 2002config ARM64_SME 2003 bool "ARM Scalable Matrix Extension support" 2004 default y 2005 depends on ARM64_SVE 2006 help 2007 The Scalable Matrix Extension (SME) is an extension to the AArch64 2008 execution state which utilises a substantial subset of the SVE 2009 instruction set, together with the addition of new architectural 2010 register state capable of holding two dimensional matrix tiles to 2011 enable various matrix operations. 2012 2013config ARM64_MODULE_PLTS 2014 bool "Use PLTs to allow module memory to spill over into vmalloc area" 2015 depends on MODULES 2016 select HAVE_MOD_ARCH_SPECIFIC 2017 help 2018 Allocate PLTs when loading modules so that jumps and calls whose 2019 targets are too far away for their relative offsets to be encoded 2020 in the instructions themselves can be bounced via veneers in the 2021 module's PLT. This allows modules to be allocated in the generic 2022 vmalloc area after the dedicated module memory area has been 2023 exhausted. 2024 2025 When running with address space randomization (KASLR), the module 2026 region itself may be too far away for ordinary relative jumps and 2027 calls, and so in that case, module PLTs are required and cannot be 2028 disabled. 2029 2030 Specific errata workaround(s) might also force module PLTs to be 2031 enabled (ARM64_ERRATUM_843419). 2032 2033config ARM64_PSEUDO_NMI 2034 bool "Support for NMI-like interrupts" 2035 select ARM_GIC_V3 2036 help 2037 Adds support for mimicking Non-Maskable Interrupts through the use of 2038 GIC interrupt priority. This support requires version 3 or later of 2039 ARM GIC. 2040 2041 This high priority configuration for interrupts needs to be 2042 explicitly enabled by setting the kernel parameter 2043 "irqchip.gicv3_pseudo_nmi" to 1. 2044 2045 If unsure, say N 2046 2047if ARM64_PSEUDO_NMI 2048config ARM64_DEBUG_PRIORITY_MASKING 2049 bool "Debug interrupt priority masking" 2050 help 2051 This adds runtime checks to functions enabling/disabling 2052 interrupts when using priority masking. The additional checks verify 2053 the validity of ICC_PMR_EL1 when calling concerned functions. 2054 2055 If unsure, say N 2056endif # ARM64_PSEUDO_NMI 2057 2058config RELOCATABLE 2059 bool "Build a relocatable kernel image" if EXPERT 2060 select ARCH_HAS_RELR 2061 default y 2062 help 2063 This builds the kernel as a Position Independent Executable (PIE), 2064 which retains all relocation metadata required to relocate the 2065 kernel binary at runtime to a different virtual address than the 2066 address it was linked at. 2067 Since AArch64 uses the RELA relocation format, this requires a 2068 relocation pass at runtime even if the kernel is loaded at the 2069 same address it was linked at. 2070 2071config RANDOMIZE_BASE 2072 bool "Randomize the address of the kernel image" 2073 select ARM64_MODULE_PLTS if MODULES 2074 select RELOCATABLE 2075 help 2076 Randomizes the virtual address at which the kernel image is 2077 loaded, as a security feature that deters exploit attempts 2078 relying on knowledge of the location of kernel internals. 2079 2080 It is the bootloader's job to provide entropy, by passing a 2081 random u64 value in /chosen/kaslr-seed at kernel entry. 2082 2083 When booting via the UEFI stub, it will invoke the firmware's 2084 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2085 to the kernel proper. In addition, it will randomise the physical 2086 location of the kernel Image as well. 2087 2088 If unsure, say N. 2089 2090config RANDOMIZE_MODULE_REGION_FULL 2091 bool "Randomize the module region over a 2 GB range" 2092 depends on RANDOMIZE_BASE 2093 default y 2094 help 2095 Randomizes the location of the module region inside a 2 GB window 2096 covering the core kernel. This way, it is less likely for modules 2097 to leak information about the location of core kernel data structures 2098 but it does imply that function calls between modules and the core 2099 kernel will need to be resolved via veneers in the module PLT. 2100 2101 When this option is not set, the module region will be randomized over 2102 a limited range that contains the [_stext, _etext] interval of the 2103 core kernel, so branch relocations are almost always in range unless 2104 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2105 particular case of region exhaustion, modules might be able to fall 2106 back to a larger 2GB area. 2107 2108config CC_HAVE_STACKPROTECTOR_SYSREG 2109 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2110 2111config STACKPROTECTOR_PER_TASK 2112 def_bool y 2113 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2114 2115# The GPIO number here must be sorted by descending number. In case of 2116# a multiplatform kernel, we just want the highest value required by the 2117# selected platforms. 2118config ARCH_NR_GPIO 2119 int 2120 default 2048 if ARCH_APPLE 2121 default 0 2122 help 2123 Maximum number of GPIOs in the system. 2124 2125 If unsure, leave the default value. 2126 2127endmenu # "Kernel Features" 2128 2129menu "Boot options" 2130 2131config ARM64_ACPI_PARKING_PROTOCOL 2132 bool "Enable support for the ARM64 ACPI parking protocol" 2133 depends on ACPI 2134 help 2135 Enable support for the ARM64 ACPI parking protocol. If disabled 2136 the kernel will not allow booting through the ARM64 ACPI parking 2137 protocol even if the corresponding data is present in the ACPI 2138 MADT table. 2139 2140config CMDLINE 2141 string "Default kernel command string" 2142 default "" 2143 help 2144 Provide a set of default command-line options at build time by 2145 entering them here. As a minimum, you should specify the the 2146 root device (e.g. root=/dev/nfs). 2147 2148choice 2149 prompt "Kernel command line type" if CMDLINE != "" 2150 default CMDLINE_FROM_BOOTLOADER 2151 help 2152 Choose how the kernel will handle the provided default kernel 2153 command line string. 2154 2155config CMDLINE_FROM_BOOTLOADER 2156 bool "Use bootloader kernel arguments if available" 2157 help 2158 Uses the command-line options passed by the boot loader. If 2159 the boot loader doesn't provide any, the default kernel command 2160 string provided in CMDLINE will be used. 2161 2162config CMDLINE_FORCE 2163 bool "Always use the default kernel command string" 2164 help 2165 Always use the default kernel command string, even if the boot 2166 loader passes other arguments to the kernel. 2167 This is useful if you cannot or don't want to change the 2168 command-line options your boot loader passes to the kernel. 2169 2170endchoice 2171 2172config EFI_STUB 2173 bool 2174 2175config EFI 2176 bool "UEFI runtime support" 2177 depends on OF && !CPU_BIG_ENDIAN 2178 depends on KERNEL_MODE_NEON 2179 select ARCH_SUPPORTS_ACPI 2180 select LIBFDT 2181 select UCS2_STRING 2182 select EFI_PARAMS_FROM_FDT 2183 select EFI_RUNTIME_WRAPPERS 2184 select EFI_STUB 2185 select EFI_GENERIC_STUB 2186 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2187 default y 2188 help 2189 This option provides support for runtime services provided 2190 by UEFI firmware (such as non-volatile variables, realtime 2191 clock, and platform reset). A UEFI stub is also provided to 2192 allow the kernel to be booted as an EFI application. This 2193 is only useful on systems that have UEFI firmware. 2194 2195config DMI 2196 bool "Enable support for SMBIOS (DMI) tables" 2197 depends on EFI 2198 default y 2199 help 2200 This enables SMBIOS/DMI feature for systems. 2201 2202 This option is only useful on systems that have UEFI firmware. 2203 However, even with this option, the resultant kernel should 2204 continue to boot on existing non-UEFI platforms. 2205 2206endmenu # "Boot options" 2207 2208menu "Power management options" 2209 2210source "kernel/power/Kconfig" 2211 2212config ARCH_HIBERNATION_POSSIBLE 2213 def_bool y 2214 depends on CPU_PM 2215 2216config ARCH_HIBERNATION_HEADER 2217 def_bool y 2218 depends on HIBERNATION 2219 2220config ARCH_SUSPEND_POSSIBLE 2221 def_bool y 2222 2223endmenu # "Power management options" 2224 2225menu "CPU Power Management" 2226 2227source "drivers/cpuidle/Kconfig" 2228 2229source "drivers/cpufreq/Kconfig" 2230 2231endmenu # "CPU Power Management" 2232 2233source "drivers/acpi/Kconfig" 2234 2235source "arch/arm64/kvm/Kconfig" 2236 2237if CRYPTO 2238source "arch/arm64/crypto/Kconfig" 2239endif # CRYPTO 2240