1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 41 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 42 select ARCH_HAS_PTE_DEVMAP 43 select ARCH_HAS_PTE_SPECIAL 44 select ARCH_HAS_HW_PTE_YOUNG 45 select ARCH_HAS_SETUP_DMA_OPS 46 select ARCH_HAS_SET_DIRECT_MAP 47 select ARCH_HAS_SET_MEMORY 48 select ARCH_HAS_MEM_ENCRYPT 49 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 50 select ARCH_STACKWALK 51 select ARCH_HAS_STRICT_KERNEL_RWX 52 select ARCH_HAS_STRICT_MODULE_RWX 53 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 54 select ARCH_HAS_SYNC_DMA_FOR_CPU 55 select ARCH_HAS_SYSCALL_WRAPPER 56 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 57 select ARCH_HAS_ZONE_DMA_SET if EXPERT 58 select ARCH_HAVE_ELF_PROT 59 select ARCH_HAVE_NMI_SAFE_CMPXCHG 60 select ARCH_HAVE_TRACE_MMIO_ACCESS 61 select ARCH_INLINE_READ_LOCK if !PREEMPTION 62 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 63 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 65 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 66 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 69 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 70 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 73 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 74 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 77 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 78 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 79 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 83 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 84 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 87 select ARCH_KEEP_MEMBLOCK 88 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 89 select ARCH_USE_CMPXCHG_LOCKREF 90 select ARCH_USE_GNU_PROPERTY 91 select ARCH_USE_MEMTEST 92 select ARCH_USE_QUEUED_RWLOCKS 93 select ARCH_USE_QUEUED_SPINLOCKS 94 select ARCH_USE_SYM_ANNOTATIONS 95 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 96 select ARCH_SUPPORTS_HUGETLBFS 97 select ARCH_SUPPORTS_MEMORY_FAILURE 98 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 99 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 100 select ARCH_SUPPORTS_LTO_CLANG_THIN 101 select ARCH_SUPPORTS_CFI_CLANG 102 select ARCH_SUPPORTS_ATOMIC_RMW 103 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 104 select ARCH_SUPPORTS_NUMA_BALANCING 105 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 106 select ARCH_SUPPORTS_PER_VMA_LOCK 107 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 108 select ARCH_SUPPORTS_RT 109 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 110 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 111 select ARCH_WANT_DEFAULT_BPF_JIT 112 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 113 select ARCH_WANT_FRAME_POINTERS 114 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 115 select ARCH_WANT_LD_ORPHAN_WARN 116 select ARCH_WANTS_EXECMEM_LATE 117 select ARCH_WANTS_NO_INSTR 118 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 119 select ARCH_HAS_UBSAN 120 select ARM_AMBA 121 select ARM_ARCH_TIMER 122 select ARM_GIC 123 select AUDIT_ARCH_COMPAT_GENERIC 124 select ARM_GIC_V2M if PCI 125 select ARM_GIC_V3 126 select ARM_GIC_V3_ITS if PCI 127 select ARM_PSCI_FW 128 select BUILDTIME_TABLE_SORT 129 select CLONE_BACKWARDS 130 select COMMON_CLK 131 select CPU_PM if (SUSPEND || CPU_IDLE) 132 select CPUMASK_OFFSTACK if NR_CPUS > 256 133 select CRC32 134 select DCACHE_WORD_ACCESS 135 select DYNAMIC_FTRACE if FUNCTION_TRACER 136 select DMA_BOUNCE_UNALIGNED_KMALLOC 137 select DMA_DIRECT_REMAP 138 select EDAC_SUPPORT 139 select FRAME_POINTER 140 select FUNCTION_ALIGNMENT_4B 141 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 142 select GENERIC_ALLOCATOR 143 select GENERIC_ARCH_TOPOLOGY 144 select GENERIC_CLOCKEVENTS_BROADCAST 145 select GENERIC_CPU_AUTOPROBE 146 select GENERIC_CPU_DEVICES 147 select GENERIC_CPU_VULNERABILITIES 148 select GENERIC_EARLY_IOREMAP 149 select GENERIC_IDLE_POLL_SETUP 150 select GENERIC_IOREMAP 151 select GENERIC_IRQ_IPI 152 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 153 select GENERIC_IRQ_PROBE 154 select GENERIC_IRQ_SHOW 155 select GENERIC_IRQ_SHOW_LEVEL 156 select GENERIC_LIB_DEVMEM_IS_ALLOWED 157 select GENERIC_PCI_IOMAP 158 select GENERIC_PTDUMP 159 select GENERIC_SCHED_CLOCK 160 select GENERIC_SMP_IDLE_THREAD 161 select GENERIC_TIME_VSYSCALL 162 select GENERIC_GETTIMEOFDAY 163 select GENERIC_VDSO_TIME_NS 164 select HARDIRQS_SW_RESEND 165 select HAS_IOPORT 166 select HAVE_MOVE_PMD 167 select HAVE_MOVE_PUD 168 select HAVE_PCI 169 select HAVE_ACPI_APEI if (ACPI && EFI) 170 select HAVE_ALIGNED_STRUCT_PAGE 171 select HAVE_ARCH_AUDITSYSCALL 172 select HAVE_ARCH_BITREVERSE 173 select HAVE_ARCH_COMPILER_H 174 select HAVE_ARCH_HUGE_VMALLOC 175 select HAVE_ARCH_HUGE_VMAP 176 select HAVE_ARCH_JUMP_LABEL 177 select HAVE_ARCH_JUMP_LABEL_RELATIVE 178 select HAVE_ARCH_KASAN 179 select HAVE_ARCH_KASAN_VMALLOC 180 select HAVE_ARCH_KASAN_SW_TAGS 181 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 182 # Some instrumentation may be unsound, hence EXPERT 183 select HAVE_ARCH_KCSAN if EXPERT 184 select HAVE_ARCH_KFENCE 185 select HAVE_ARCH_KGDB 186 select HAVE_ARCH_MMAP_RND_BITS 187 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 188 select HAVE_ARCH_PREL32_RELOCATIONS 189 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 190 select HAVE_ARCH_SECCOMP_FILTER 191 select HAVE_ARCH_STACKLEAK 192 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 193 select HAVE_ARCH_TRACEHOOK 194 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 195 select HAVE_ARCH_VMAP_STACK 196 select HAVE_ARM_SMCCC 197 select HAVE_ASM_MODVERSIONS 198 select HAVE_EBPF_JIT 199 select HAVE_C_RECORDMCOUNT 200 select HAVE_CMPXCHG_DOUBLE 201 select HAVE_CMPXCHG_LOCAL 202 select HAVE_CONTEXT_TRACKING_USER 203 select HAVE_DEBUG_KMEMLEAK 204 select HAVE_DMA_CONTIGUOUS 205 select HAVE_DYNAMIC_FTRACE 206 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 207 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 208 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 209 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 210 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 211 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 212 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 213 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 214 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 215 if DYNAMIC_FTRACE_WITH_ARGS 216 select HAVE_SAMPLE_FTRACE_DIRECT 217 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 218 select HAVE_EFFICIENT_UNALIGNED_ACCESS 219 select HAVE_GUP_FAST 220 select HAVE_FTRACE_GRAPH_FUNC 221 select HAVE_FTRACE_MCOUNT_RECORD 222 select HAVE_FUNCTION_TRACER 223 select HAVE_FUNCTION_ERROR_INJECTION 224 select HAVE_FUNCTION_GRAPH_FREGS 225 select HAVE_FUNCTION_GRAPH_TRACER 226 select HAVE_FUNCTION_GRAPH_RETVAL 227 select HAVE_GCC_PLUGINS 228 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 229 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 230 select HAVE_HW_BREAKPOINT if PERF_EVENTS 231 select HAVE_IOREMAP_PROT 232 select HAVE_IRQ_TIME_ACCOUNTING 233 select HAVE_MOD_ARCH_SPECIFIC 234 select HAVE_NMI 235 select HAVE_PERF_EVENTS 236 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 237 select HAVE_PERF_REGS 238 select HAVE_PERF_USER_STACK_DUMP 239 select HAVE_PREEMPT_DYNAMIC_KEY 240 select HAVE_REGS_AND_STACK_ACCESS_API 241 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 242 select HAVE_FUNCTION_ARG_ACCESS_API 243 select MMU_GATHER_RCU_TABLE_FREE 244 select HAVE_RSEQ 245 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 246 select HAVE_STACKPROTECTOR 247 select HAVE_SYSCALL_TRACEPOINTS 248 select HAVE_KPROBES 249 select HAVE_KRETPROBES 250 select HAVE_GENERIC_VDSO 251 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 252 select IRQ_DOMAIN 253 select IRQ_FORCED_THREADING 254 select KASAN_VMALLOC if KASAN 255 select LOCK_MM_AND_FIND_VMA 256 select MODULES_USE_ELF_RELA 257 select NEED_DMA_MAP_STATE 258 select NEED_SG_DMA_LENGTH 259 select OF 260 select OF_EARLY_FLATTREE 261 select PCI_DOMAINS_GENERIC if PCI 262 select PCI_ECAM if (ACPI && PCI) 263 select PCI_SYSCALL if PCI 264 select POWER_RESET 265 select POWER_SUPPLY 266 select SPARSE_IRQ 267 select SWIOTLB 268 select SYSCTL_EXCEPTION_TRACE 269 select THREAD_INFO_IN_TASK 270 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 271 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 272 select TRACE_IRQFLAGS_SUPPORT 273 select TRACE_IRQFLAGS_NMI_SUPPORT 274 select HAVE_SOFTIRQ_ON_OWN_STACK 275 select USER_STACKTRACE_SUPPORT 276 select VDSO_GETRANDOM 277 help 278 ARM 64-bit (AArch64) Linux support. 279 280config RUSTC_SUPPORTS_ARM64 281 def_bool y 282 depends on CPU_LITTLE_ENDIAN 283 # Shadow call stack is only supported on certain rustc versions. 284 # 285 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 286 # required due to use of the -Zfixed-x18 flag. 287 # 288 # Otherwise, rustc version 1.82+ is required due to use of the 289 # -Zsanitizer=shadow-call-stack flag. 290 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 291 292config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 293 def_bool CC_IS_CLANG 294 # https://github.com/ClangBuiltLinux/linux/issues/1507 295 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 296 297config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 298 def_bool CC_IS_GCC 299 depends on $(cc-option,-fpatchable-function-entry=2) 300 301config 64BIT 302 def_bool y 303 304config MMU 305 def_bool y 306 307config ARM64_CONT_PTE_SHIFT 308 int 309 default 5 if PAGE_SIZE_64KB 310 default 7 if PAGE_SIZE_16KB 311 default 4 312 313config ARM64_CONT_PMD_SHIFT 314 int 315 default 5 if PAGE_SIZE_64KB 316 default 5 if PAGE_SIZE_16KB 317 default 4 318 319config ARCH_MMAP_RND_BITS_MIN 320 default 14 if PAGE_SIZE_64KB 321 default 16 if PAGE_SIZE_16KB 322 default 18 323 324# max bits determined by the following formula: 325# VA_BITS - PAGE_SHIFT - 3 326config ARCH_MMAP_RND_BITS_MAX 327 default 19 if ARM64_VA_BITS=36 328 default 24 if ARM64_VA_BITS=39 329 default 27 if ARM64_VA_BITS=42 330 default 30 if ARM64_VA_BITS=47 331 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 332 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 333 default 33 if ARM64_VA_BITS=48 334 default 14 if ARM64_64K_PAGES 335 default 16 if ARM64_16K_PAGES 336 default 18 337 338config ARCH_MMAP_RND_COMPAT_BITS_MIN 339 default 7 if ARM64_64K_PAGES 340 default 9 if ARM64_16K_PAGES 341 default 11 342 343config ARCH_MMAP_RND_COMPAT_BITS_MAX 344 default 16 345 346config NO_IOPORT_MAP 347 def_bool y if !PCI 348 349config STACKTRACE_SUPPORT 350 def_bool y 351 352config ILLEGAL_POINTER_VALUE 353 hex 354 default 0xdead000000000000 355 356config LOCKDEP_SUPPORT 357 def_bool y 358 359config GENERIC_BUG 360 def_bool y 361 depends on BUG 362 363config GENERIC_BUG_RELATIVE_POINTERS 364 def_bool y 365 depends on GENERIC_BUG 366 367config GENERIC_HWEIGHT 368 def_bool y 369 370config GENERIC_CSUM 371 def_bool y 372 373config GENERIC_CALIBRATE_DELAY 374 def_bool y 375 376config SMP 377 def_bool y 378 379config KERNEL_MODE_NEON 380 def_bool y 381 382config FIX_EARLYCON_MEM 383 def_bool y 384 385config PGTABLE_LEVELS 386 int 387 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 388 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 389 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 390 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 391 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 392 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 393 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 394 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 395 396config ARCH_SUPPORTS_UPROBES 397 def_bool y 398 399config ARCH_PROC_KCORE_TEXT 400 def_bool y 401 402config BROKEN_GAS_INST 403 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 404 405config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 406 bool 407 # Clang's __builtin_return_address() strips the PAC since 12.0.0 408 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 409 default y if CC_IS_CLANG 410 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 411 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 412 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 413 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 414 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 415 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 416 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 417 default n 418 419config KASAN_SHADOW_OFFSET 420 hex 421 depends on KASAN_GENERIC || KASAN_SW_TAGS 422 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 423 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 424 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 425 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 426 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 427 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 428 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 429 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 430 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 431 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 432 default 0xffffffffffffffff 433 434config UNWIND_TABLES 435 bool 436 437source "arch/arm64/Kconfig.platforms" 438 439menu "Kernel Features" 440 441menu "ARM errata workarounds via the alternatives framework" 442 443config AMPERE_ERRATUM_AC03_CPU_38 444 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 445 default y 446 help 447 This option adds an alternative code sequence to work around Ampere 448 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 449 450 The affected design reports FEAT_HAFDBS as not implemented in 451 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 452 as required by the architecture. The unadvertised HAFDBS 453 implementation suffers from an additional erratum where hardware 454 A/D updates can occur after a PTE has been marked invalid. 455 456 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 457 which avoids enabling unadvertised hardware Access Flag management 458 at stage-2. 459 460 If unsure, say Y. 461 462config ARM64_WORKAROUND_CLEAN_CACHE 463 bool 464 465config ARM64_ERRATUM_826319 466 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 467 default y 468 select ARM64_WORKAROUND_CLEAN_CACHE 469 help 470 This option adds an alternative code sequence to work around ARM 471 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 472 AXI master interface and an L2 cache. 473 474 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 475 and is unable to accept a certain write via this interface, it will 476 not progress on read data presented on the read data channel and the 477 system can deadlock. 478 479 The workaround promotes data cache clean instructions to 480 data cache clean-and-invalidate. 481 Please note that this does not necessarily enable the workaround, 482 as it depends on the alternative framework, which will only patch 483 the kernel if an affected CPU is detected. 484 485 If unsure, say Y. 486 487config ARM64_ERRATUM_827319 488 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 489 default y 490 select ARM64_WORKAROUND_CLEAN_CACHE 491 help 492 This option adds an alternative code sequence to work around ARM 493 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 494 master interface and an L2 cache. 495 496 Under certain conditions this erratum can cause a clean line eviction 497 to occur at the same time as another transaction to the same address 498 on the AMBA 5 CHI interface, which can cause data corruption if the 499 interconnect reorders the two transactions. 500 501 The workaround promotes data cache clean instructions to 502 data cache clean-and-invalidate. 503 Please note that this does not necessarily enable the workaround, 504 as it depends on the alternative framework, which will only patch 505 the kernel if an affected CPU is detected. 506 507 If unsure, say Y. 508 509config ARM64_ERRATUM_824069 510 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 511 default y 512 select ARM64_WORKAROUND_CLEAN_CACHE 513 help 514 This option adds an alternative code sequence to work around ARM 515 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 516 to a coherent interconnect. 517 518 If a Cortex-A53 processor is executing a store or prefetch for 519 write instruction at the same time as a processor in another 520 cluster is executing a cache maintenance operation to the same 521 address, then this erratum might cause a clean cache line to be 522 incorrectly marked as dirty. 523 524 The workaround promotes data cache clean instructions to 525 data cache clean-and-invalidate. 526 Please note that this option does not necessarily enable the 527 workaround, as it depends on the alternative framework, which will 528 only patch the kernel if an affected CPU is detected. 529 530 If unsure, say Y. 531 532config ARM64_ERRATUM_819472 533 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 534 default y 535 select ARM64_WORKAROUND_CLEAN_CACHE 536 help 537 This option adds an alternative code sequence to work around ARM 538 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 539 present when it is connected to a coherent interconnect. 540 541 If the processor is executing a load and store exclusive sequence at 542 the same time as a processor in another cluster is executing a cache 543 maintenance operation to the same address, then this erratum might 544 cause data corruption. 545 546 The workaround promotes data cache clean instructions to 547 data cache clean-and-invalidate. 548 Please note that this does not necessarily enable the workaround, 549 as it depends on the alternative framework, which will only patch 550 the kernel if an affected CPU is detected. 551 552 If unsure, say Y. 553 554config ARM64_ERRATUM_832075 555 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 556 default y 557 help 558 This option adds an alternative code sequence to work around ARM 559 erratum 832075 on Cortex-A57 parts up to r1p2. 560 561 Affected Cortex-A57 parts might deadlock when exclusive load/store 562 instructions to Write-Back memory are mixed with Device loads. 563 564 The workaround is to promote device loads to use Load-Acquire 565 semantics. 566 Please note that this does not necessarily enable the workaround, 567 as it depends on the alternative framework, which will only patch 568 the kernel if an affected CPU is detected. 569 570 If unsure, say Y. 571 572config ARM64_ERRATUM_834220 573 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 574 depends on KVM 575 help 576 This option adds an alternative code sequence to work around ARM 577 erratum 834220 on Cortex-A57 parts up to r1p2. 578 579 Affected Cortex-A57 parts might report a Stage 2 translation 580 fault as the result of a Stage 1 fault for load crossing a 581 page boundary when there is a permission or device memory 582 alignment fault at Stage 1 and a translation fault at Stage 2. 583 584 The workaround is to verify that the Stage 1 translation 585 doesn't generate a fault before handling the Stage 2 fault. 586 Please note that this does not necessarily enable the workaround, 587 as it depends on the alternative framework, which will only patch 588 the kernel if an affected CPU is detected. 589 590 If unsure, say N. 591 592config ARM64_ERRATUM_1742098 593 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 594 depends on COMPAT 595 default y 596 help 597 This option removes the AES hwcap for aarch32 user-space to 598 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 599 600 Affected parts may corrupt the AES state if an interrupt is 601 taken between a pair of AES instructions. These instructions 602 are only present if the cryptography extensions are present. 603 All software should have a fallback implementation for CPUs 604 that don't implement the cryptography extensions. 605 606 If unsure, say Y. 607 608config ARM64_ERRATUM_845719 609 bool "Cortex-A53: 845719: a load might read incorrect data" 610 depends on COMPAT 611 default y 612 help 613 This option adds an alternative code sequence to work around ARM 614 erratum 845719 on Cortex-A53 parts up to r0p4. 615 616 When running a compat (AArch32) userspace on an affected Cortex-A53 617 part, a load at EL0 from a virtual address that matches the bottom 32 618 bits of the virtual address used by a recent load at (AArch64) EL1 619 might return incorrect data. 620 621 The workaround is to write the contextidr_el1 register on exception 622 return to a 32-bit task. 623 Please note that this does not necessarily enable the workaround, 624 as it depends on the alternative framework, which will only patch 625 the kernel if an affected CPU is detected. 626 627 If unsure, say Y. 628 629config ARM64_ERRATUM_843419 630 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 631 default y 632 help 633 This option links the kernel with '--fix-cortex-a53-843419' and 634 enables PLT support to replace certain ADRP instructions, which can 635 cause subsequent memory accesses to use an incorrect address on 636 Cortex-A53 parts up to r0p4. 637 638 If unsure, say Y. 639 640config ARM64_LD_HAS_FIX_ERRATUM_843419 641 def_bool $(ld-option,--fix-cortex-a53-843419) 642 643config ARM64_ERRATUM_1024718 644 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 645 default y 646 help 647 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 648 649 Affected Cortex-A55 cores (all revisions) could cause incorrect 650 update of the hardware dirty bit when the DBM/AP bits are updated 651 without a break-before-make. The workaround is to disable the usage 652 of hardware DBM locally on the affected cores. CPUs not affected by 653 this erratum will continue to use the feature. 654 655 If unsure, say Y. 656 657config ARM64_ERRATUM_1418040 658 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 659 default y 660 depends on COMPAT 661 help 662 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 663 errata 1188873 and 1418040. 664 665 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 666 cause register corruption when accessing the timer registers 667 from AArch32 userspace. 668 669 If unsure, say Y. 670 671config ARM64_WORKAROUND_SPECULATIVE_AT 672 bool 673 674config ARM64_ERRATUM_1165522 675 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 676 default y 677 select ARM64_WORKAROUND_SPECULATIVE_AT 678 help 679 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 680 681 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 682 corrupted TLBs by speculating an AT instruction during a guest 683 context switch. 684 685 If unsure, say Y. 686 687config ARM64_ERRATUM_1319367 688 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 689 default y 690 select ARM64_WORKAROUND_SPECULATIVE_AT 691 help 692 This option adds work arounds for ARM Cortex-A57 erratum 1319537 693 and A72 erratum 1319367 694 695 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 696 speculating an AT instruction during a guest context switch. 697 698 If unsure, say Y. 699 700config ARM64_ERRATUM_1530923 701 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 702 default y 703 select ARM64_WORKAROUND_SPECULATIVE_AT 704 help 705 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 706 707 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 708 corrupted TLBs by speculating an AT instruction during a guest 709 context switch. 710 711 If unsure, say Y. 712 713config ARM64_WORKAROUND_REPEAT_TLBI 714 bool 715 716config ARM64_ERRATUM_2441007 717 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 718 select ARM64_WORKAROUND_REPEAT_TLBI 719 help 720 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 721 722 Under very rare circumstances, affected Cortex-A55 CPUs 723 may not handle a race between a break-before-make sequence on one 724 CPU, and another CPU accessing the same page. This could allow a 725 store to a page that has been unmapped. 726 727 Work around this by adding the affected CPUs to the list that needs 728 TLB sequences to be done twice. 729 730 If unsure, say N. 731 732config ARM64_ERRATUM_1286807 733 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 734 select ARM64_WORKAROUND_REPEAT_TLBI 735 help 736 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 737 738 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 739 address for a cacheable mapping of a location is being 740 accessed by a core while another core is remapping the virtual 741 address to a new physical page using the recommended 742 break-before-make sequence, then under very rare circumstances 743 TLBI+DSB completes before a read using the translation being 744 invalidated has been observed by other observers. The 745 workaround repeats the TLBI+DSB operation. 746 747 If unsure, say N. 748 749config ARM64_ERRATUM_1463225 750 bool "Cortex-A76: Software Step might prevent interrupt recognition" 751 default y 752 help 753 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 754 755 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 756 of a system call instruction (SVC) can prevent recognition of 757 subsequent interrupts when software stepping is disabled in the 758 exception handler of the system call and either kernel debugging 759 is enabled or VHE is in use. 760 761 Work around the erratum by triggering a dummy step exception 762 when handling a system call from a task that is being stepped 763 in a VHE configuration of the kernel. 764 765 If unsure, say Y. 766 767config ARM64_ERRATUM_1542419 768 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 769 help 770 This option adds a workaround for ARM Neoverse-N1 erratum 771 1542419. 772 773 Affected Neoverse-N1 cores could execute a stale instruction when 774 modified by another CPU. The workaround depends on a firmware 775 counterpart. 776 777 Workaround the issue by hiding the DIC feature from EL0. This 778 forces user-space to perform cache maintenance. 779 780 If unsure, say N. 781 782config ARM64_ERRATUM_1508412 783 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 784 default y 785 help 786 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 787 788 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 789 of a store-exclusive or read of PAR_EL1 and a load with device or 790 non-cacheable memory attributes. The workaround depends on a firmware 791 counterpart. 792 793 KVM guests must also have the workaround implemented or they can 794 deadlock the system. 795 796 Work around the issue by inserting DMB SY barriers around PAR_EL1 797 register reads and warning KVM users. The DMB barrier is sufficient 798 to prevent a speculative PAR_EL1 read. 799 800 If unsure, say Y. 801 802config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 803 bool 804 805config ARM64_ERRATUM_2051678 806 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 807 default y 808 help 809 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 810 Affected Cortex-A510 might not respect the ordering rules for 811 hardware update of the page table's dirty bit. The workaround 812 is to not enable the feature on affected CPUs. 813 814 If unsure, say Y. 815 816config ARM64_ERRATUM_2077057 817 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 818 default y 819 help 820 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 821 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 822 expected, but a Pointer Authentication trap is taken instead. The 823 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 824 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 825 826 This can only happen when EL2 is stepping EL1. 827 828 When these conditions occur, the SPSR_EL2 value is unchanged from the 829 previous guest entry, and can be restored from the in-memory copy. 830 831 If unsure, say Y. 832 833config ARM64_ERRATUM_2658417 834 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 835 default y 836 help 837 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 838 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 839 BFMMLA or VMMLA instructions in rare circumstances when a pair of 840 A510 CPUs are using shared neon hardware. As the sharing is not 841 discoverable by the kernel, hide the BF16 HWCAP to indicate that 842 user-space should not be using these instructions. 843 844 If unsure, say Y. 845 846config ARM64_ERRATUM_2119858 847 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 848 default y 849 depends on CORESIGHT_TRBE 850 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 851 help 852 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 853 854 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 855 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 856 the event of a WRAP event. 857 858 Work around the issue by always making sure we move the TRBPTR_EL1 by 859 256 bytes before enabling the buffer and filling the first 256 bytes of 860 the buffer with ETM ignore packets upon disabling. 861 862 If unsure, say Y. 863 864config ARM64_ERRATUM_2139208 865 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 866 default y 867 depends on CORESIGHT_TRBE 868 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 869 help 870 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 871 872 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 873 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 874 the event of a WRAP event. 875 876 Work around the issue by always making sure we move the TRBPTR_EL1 by 877 256 bytes before enabling the buffer and filling the first 256 bytes of 878 the buffer with ETM ignore packets upon disabling. 879 880 If unsure, say Y. 881 882config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 883 bool 884 885config ARM64_ERRATUM_2054223 886 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 887 default y 888 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 889 help 890 Enable workaround for ARM Cortex-A710 erratum 2054223 891 892 Affected cores may fail to flush the trace data on a TSB instruction, when 893 the PE is in trace prohibited state. This will cause losing a few bytes 894 of the trace cached. 895 896 Workaround is to issue two TSB consecutively on affected cores. 897 898 If unsure, say Y. 899 900config ARM64_ERRATUM_2067961 901 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 902 default y 903 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 904 help 905 Enable workaround for ARM Neoverse-N2 erratum 2067961 906 907 Affected cores may fail to flush the trace data on a TSB instruction, when 908 the PE is in trace prohibited state. This will cause losing a few bytes 909 of the trace cached. 910 911 Workaround is to issue two TSB consecutively on affected cores. 912 913 If unsure, say Y. 914 915config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 916 bool 917 918config ARM64_ERRATUM_2253138 919 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 920 depends on CORESIGHT_TRBE 921 default y 922 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 923 help 924 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 925 926 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 927 for TRBE. Under some conditions, the TRBE might generate a write to the next 928 virtually addressed page following the last page of the TRBE address space 929 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 930 931 Work around this in the driver by always making sure that there is a 932 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 933 934 If unsure, say Y. 935 936config ARM64_ERRATUM_2224489 937 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 938 depends on CORESIGHT_TRBE 939 default y 940 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 941 help 942 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 943 944 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 945 for TRBE. Under some conditions, the TRBE might generate a write to the next 946 virtually addressed page following the last page of the TRBE address space 947 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 948 949 Work around this in the driver by always making sure that there is a 950 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 951 952 If unsure, say Y. 953 954config ARM64_ERRATUM_2441009 955 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 956 select ARM64_WORKAROUND_REPEAT_TLBI 957 help 958 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 959 960 Under very rare circumstances, affected Cortex-A510 CPUs 961 may not handle a race between a break-before-make sequence on one 962 CPU, and another CPU accessing the same page. This could allow a 963 store to a page that has been unmapped. 964 965 Work around this by adding the affected CPUs to the list that needs 966 TLB sequences to be done twice. 967 968 If unsure, say N. 969 970config ARM64_ERRATUM_2064142 971 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 972 depends on CORESIGHT_TRBE 973 default y 974 help 975 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 976 977 Affected Cortex-A510 core might fail to write into system registers after the 978 TRBE has been disabled. Under some conditions after the TRBE has been disabled 979 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 980 and TRBTRG_EL1 will be ignored and will not be effected. 981 982 Work around this in the driver by executing TSB CSYNC and DSB after collection 983 is stopped and before performing a system register write to one of the affected 984 registers. 985 986 If unsure, say Y. 987 988config ARM64_ERRATUM_2038923 989 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 990 depends on CORESIGHT_TRBE 991 default y 992 help 993 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 994 995 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 996 prohibited within the CPU. As a result, the trace buffer or trace buffer state 997 might be corrupted. This happens after TRBE buffer has been enabled by setting 998 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 999 execution changes from a context, in which trace is prohibited to one where it 1000 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1001 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1002 the trace buffer state might be corrupted. 1003 1004 Work around this in the driver by preventing an inconsistent view of whether the 1005 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1006 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1007 two ISB instructions if no ERET is to take place. 1008 1009 If unsure, say Y. 1010 1011config ARM64_ERRATUM_1902691 1012 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1013 depends on CORESIGHT_TRBE 1014 default y 1015 help 1016 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1017 1018 Affected Cortex-A510 core might cause trace data corruption, when being written 1019 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1020 trace data. 1021 1022 Work around this problem in the driver by just preventing TRBE initialization on 1023 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1024 on such implementations. This will cover the kernel for any firmware that doesn't 1025 do this already. 1026 1027 If unsure, say Y. 1028 1029config ARM64_ERRATUM_2457168 1030 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1031 depends on ARM64_AMU_EXTN 1032 default y 1033 help 1034 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1035 1036 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1037 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1038 incorrectly giving a significantly higher output value. 1039 1040 Work around this problem by returning 0 when reading the affected counter in 1041 key locations that results in disabling all users of this counter. This effect 1042 is the same to firmware disabling affected counters. 1043 1044 If unsure, say Y. 1045 1046config ARM64_ERRATUM_2645198 1047 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1048 default y 1049 help 1050 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1051 1052 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1053 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1054 next instruction abort caused by permission fault. 1055 1056 Only user-space does executable to non-executable permission transition via 1057 mprotect() system call. Workaround the problem by doing a break-before-make 1058 TLB invalidation, for all changes to executable user space mappings. 1059 1060 If unsure, say Y. 1061 1062config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1063 bool 1064 1065config ARM64_ERRATUM_2966298 1066 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1067 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1068 default y 1069 help 1070 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1071 1072 On an affected Cortex-A520 core, a speculatively executed unprivileged 1073 load might leak data from a privileged level via a cache side channel. 1074 1075 Work around this problem by executing a TLBI before returning to EL0. 1076 1077 If unsure, say Y. 1078 1079config ARM64_ERRATUM_3117295 1080 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1081 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1082 default y 1083 help 1084 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1085 1086 On an affected Cortex-A510 core, a speculatively executed unprivileged 1087 load might leak data from a privileged level via a cache side channel. 1088 1089 Work around this problem by executing a TLBI before returning to EL0. 1090 1091 If unsure, say Y. 1092 1093config ARM64_ERRATUM_3194386 1094 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1095 default y 1096 help 1097 This option adds the workaround for the following errata: 1098 1099 * ARM Cortex-A76 erratum 3324349 1100 * ARM Cortex-A77 erratum 3324348 1101 * ARM Cortex-A78 erratum 3324344 1102 * ARM Cortex-A78C erratum 3324346 1103 * ARM Cortex-A78C erratum 3324347 1104 * ARM Cortex-A710 erratam 3324338 1105 * ARM Cortex-A715 errartum 3456084 1106 * ARM Cortex-A720 erratum 3456091 1107 * ARM Cortex-A725 erratum 3456106 1108 * ARM Cortex-X1 erratum 3324344 1109 * ARM Cortex-X1C erratum 3324346 1110 * ARM Cortex-X2 erratum 3324338 1111 * ARM Cortex-X3 erratum 3324335 1112 * ARM Cortex-X4 erratum 3194386 1113 * ARM Cortex-X925 erratum 3324334 1114 * ARM Neoverse-N1 erratum 3324349 1115 * ARM Neoverse N2 erratum 3324339 1116 * ARM Neoverse-N3 erratum 3456111 1117 * ARM Neoverse-V1 erratum 3324341 1118 * ARM Neoverse V2 erratum 3324336 1119 * ARM Neoverse-V3 erratum 3312417 1120 1121 On affected cores "MSR SSBS, #0" instructions may not affect 1122 subsequent speculative instructions, which may permit unexepected 1123 speculative store bypassing. 1124 1125 Work around this problem by placing a Speculation Barrier (SB) or 1126 Instruction Synchronization Barrier (ISB) after kernel changes to 1127 SSBS. The presence of the SSBS special-purpose register is hidden 1128 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1129 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1130 1131 If unsure, say Y. 1132 1133config CAVIUM_ERRATUM_22375 1134 bool "Cavium erratum 22375, 24313" 1135 default y 1136 help 1137 Enable workaround for errata 22375 and 24313. 1138 1139 This implements two gicv3-its errata workarounds for ThunderX. Both 1140 with a small impact affecting only ITS table allocation. 1141 1142 erratum 22375: only alloc 8MB table size 1143 erratum 24313: ignore memory access type 1144 1145 The fixes are in ITS initialization and basically ignore memory access 1146 type and table size provided by the TYPER and BASER registers. 1147 1148 If unsure, say Y. 1149 1150config CAVIUM_ERRATUM_23144 1151 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1152 depends on NUMA 1153 default y 1154 help 1155 ITS SYNC command hang for cross node io and collections/cpu mapping. 1156 1157 If unsure, say Y. 1158 1159config CAVIUM_ERRATUM_23154 1160 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1161 default y 1162 help 1163 The ThunderX GICv3 implementation requires a modified version for 1164 reading the IAR status to ensure data synchronization 1165 (access to icc_iar1_el1 is not sync'ed before and after). 1166 1167 It also suffers from erratum 38545 (also present on Marvell's 1168 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1169 spuriously presented to the CPU interface. 1170 1171 If unsure, say Y. 1172 1173config CAVIUM_ERRATUM_27456 1174 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1175 default y 1176 help 1177 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1178 instructions may cause the icache to become corrupted if it 1179 contains data for a non-current ASID. The fix is to 1180 invalidate the icache when changing the mm context. 1181 1182 If unsure, say Y. 1183 1184config CAVIUM_ERRATUM_30115 1185 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1186 default y 1187 help 1188 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1189 1.2, and T83 Pass 1.0, KVM guest execution may disable 1190 interrupts in host. Trapping both GICv3 group-0 and group-1 1191 accesses sidesteps the issue. 1192 1193 If unsure, say Y. 1194 1195config CAVIUM_TX2_ERRATUM_219 1196 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1197 default y 1198 help 1199 On Cavium ThunderX2, a load, store or prefetch instruction between a 1200 TTBR update and the corresponding context synchronizing operation can 1201 cause a spurious Data Abort to be delivered to any hardware thread in 1202 the CPU core. 1203 1204 Work around the issue by avoiding the problematic code sequence and 1205 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1206 trap handler performs the corresponding register access, skips the 1207 instruction and ensures context synchronization by virtue of the 1208 exception return. 1209 1210 If unsure, say Y. 1211 1212config FUJITSU_ERRATUM_010001 1213 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1214 default y 1215 help 1216 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1217 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1218 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1219 This fault occurs under a specific hardware condition when a 1220 load/store instruction performs an address translation using: 1221 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1222 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1223 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1224 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1225 1226 The workaround is to ensure these bits are clear in TCR_ELx. 1227 The workaround only affects the Fujitsu-A64FX. 1228 1229 If unsure, say Y. 1230 1231config HISILICON_ERRATUM_161600802 1232 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1233 default y 1234 help 1235 The HiSilicon Hip07 SoC uses the wrong redistributor base 1236 when issued ITS commands such as VMOVP and VMAPP, and requires 1237 a 128kB offset to be applied to the target address in this commands. 1238 1239 If unsure, say Y. 1240 1241config HISILICON_ERRATUM_162100801 1242 bool "Hip09 162100801 erratum support" 1243 default y 1244 help 1245 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1246 during unmapping operation, which will cause some vSGIs lost. 1247 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1248 after VMOVP. 1249 1250 If unsure, say Y. 1251 1252config QCOM_FALKOR_ERRATUM_1003 1253 bool "Falkor E1003: Incorrect translation due to ASID change" 1254 default y 1255 help 1256 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1257 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1258 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1259 then only for entries in the walk cache, since the leaf translation 1260 is unchanged. Work around the erratum by invalidating the walk cache 1261 entries for the trampoline before entering the kernel proper. 1262 1263config QCOM_FALKOR_ERRATUM_1009 1264 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1265 default y 1266 select ARM64_WORKAROUND_REPEAT_TLBI 1267 help 1268 On Falkor v1, the CPU may prematurely complete a DSB following a 1269 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1270 one more time to fix the issue. 1271 1272 If unsure, say Y. 1273 1274config QCOM_QDF2400_ERRATUM_0065 1275 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1276 default y 1277 help 1278 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1279 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1280 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1281 1282 If unsure, say Y. 1283 1284config QCOM_FALKOR_ERRATUM_E1041 1285 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1286 default y 1287 help 1288 Falkor CPU may speculatively fetch instructions from an improper 1289 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1290 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1291 1292 If unsure, say Y. 1293 1294config NVIDIA_CARMEL_CNP_ERRATUM 1295 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1296 default y 1297 help 1298 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1299 invalidate shared TLB entries installed by a different core, as it would 1300 on standard ARM cores. 1301 1302 If unsure, say Y. 1303 1304config ROCKCHIP_ERRATUM_3588001 1305 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1306 default y 1307 help 1308 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1309 This means, that its sharability feature may not be used, even though it 1310 is supported by the IP itself. 1311 1312 If unsure, say Y. 1313 1314config SOCIONEXT_SYNQUACER_PREITS 1315 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1316 default y 1317 help 1318 Socionext Synquacer SoCs implement a separate h/w block to generate 1319 MSI doorbell writes with non-zero values for the device ID. 1320 1321 If unsure, say Y. 1322 1323endmenu # "ARM errata workarounds via the alternatives framework" 1324 1325choice 1326 prompt "Page size" 1327 default ARM64_4K_PAGES 1328 help 1329 Page size (translation granule) configuration. 1330 1331config ARM64_4K_PAGES 1332 bool "4KB" 1333 select HAVE_PAGE_SIZE_4KB 1334 help 1335 This feature enables 4KB pages support. 1336 1337config ARM64_16K_PAGES 1338 bool "16KB" 1339 select HAVE_PAGE_SIZE_16KB 1340 help 1341 The system will use 16KB pages support. AArch32 emulation 1342 requires applications compiled with 16K (or a multiple of 16K) 1343 aligned segments. 1344 1345config ARM64_64K_PAGES 1346 bool "64KB" 1347 select HAVE_PAGE_SIZE_64KB 1348 help 1349 This feature enables 64KB pages support (4KB by default) 1350 allowing only two levels of page tables and faster TLB 1351 look-up. AArch32 emulation requires applications compiled 1352 with 64K aligned segments. 1353 1354endchoice 1355 1356choice 1357 prompt "Virtual address space size" 1358 default ARM64_VA_BITS_52 1359 help 1360 Allows choosing one of multiple possible virtual address 1361 space sizes. The level of translation table is determined by 1362 a combination of page size and virtual address space size. 1363 1364config ARM64_VA_BITS_36 1365 bool "36-bit" if EXPERT 1366 depends on PAGE_SIZE_16KB 1367 1368config ARM64_VA_BITS_39 1369 bool "39-bit" 1370 depends on PAGE_SIZE_4KB 1371 1372config ARM64_VA_BITS_42 1373 bool "42-bit" 1374 depends on PAGE_SIZE_64KB 1375 1376config ARM64_VA_BITS_47 1377 bool "47-bit" 1378 depends on PAGE_SIZE_16KB 1379 1380config ARM64_VA_BITS_48 1381 bool "48-bit" 1382 1383config ARM64_VA_BITS_52 1384 bool "52-bit" 1385 help 1386 Enable 52-bit virtual addressing for userspace when explicitly 1387 requested via a hint to mmap(). The kernel will also use 52-bit 1388 virtual addresses for its own mappings (provided HW support for 1389 this feature is available, otherwise it reverts to 48-bit). 1390 1391 NOTE: Enabling 52-bit virtual addressing in conjunction with 1392 ARMv8.3 Pointer Authentication will result in the PAC being 1393 reduced from 7 bits to 3 bits, which may have a significant 1394 impact on its susceptibility to brute-force attacks. 1395 1396 If unsure, select 48-bit virtual addressing instead. 1397 1398endchoice 1399 1400config ARM64_FORCE_52BIT 1401 bool "Force 52-bit virtual addresses for userspace" 1402 depends on ARM64_VA_BITS_52 && EXPERT 1403 help 1404 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1405 to maintain compatibility with older software by providing 48-bit VAs 1406 unless a hint is supplied to mmap. 1407 1408 This configuration option disables the 48-bit compatibility logic, and 1409 forces all userspace addresses to be 52-bit on HW that supports it. One 1410 should only enable this configuration option for stress testing userspace 1411 memory management code. If unsure say N here. 1412 1413config ARM64_VA_BITS 1414 int 1415 default 36 if ARM64_VA_BITS_36 1416 default 39 if ARM64_VA_BITS_39 1417 default 42 if ARM64_VA_BITS_42 1418 default 47 if ARM64_VA_BITS_47 1419 default 48 if ARM64_VA_BITS_48 1420 default 52 if ARM64_VA_BITS_52 1421 1422choice 1423 prompt "Physical address space size" 1424 default ARM64_PA_BITS_48 1425 help 1426 Choose the maximum physical address range that the kernel will 1427 support. 1428 1429config ARM64_PA_BITS_48 1430 bool "48-bit" 1431 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1432 1433config ARM64_PA_BITS_52 1434 bool "52-bit" 1435 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1436 help 1437 Enable support for a 52-bit physical address space, introduced as 1438 part of the ARMv8.2-LPA extension. 1439 1440 With this enabled, the kernel will also continue to work on CPUs that 1441 do not support ARMv8.2-LPA, but with some added memory overhead (and 1442 minor performance overhead). 1443 1444endchoice 1445 1446config ARM64_PA_BITS 1447 int 1448 default 48 if ARM64_PA_BITS_48 1449 default 52 if ARM64_PA_BITS_52 1450 1451config ARM64_LPA2 1452 def_bool y 1453 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1454 1455choice 1456 prompt "Endianness" 1457 default CPU_LITTLE_ENDIAN 1458 help 1459 Select the endianness of data accesses performed by the CPU. Userspace 1460 applications will need to be compiled and linked for the endianness 1461 that is selected here. 1462 1463config CPU_BIG_ENDIAN 1464 bool "Build big-endian kernel" 1465 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1466 depends on AS_IS_GNU || AS_VERSION >= 150000 1467 help 1468 Say Y if you plan on running a kernel with a big-endian userspace. 1469 1470config CPU_LITTLE_ENDIAN 1471 bool "Build little-endian kernel" 1472 help 1473 Say Y if you plan on running a kernel with a little-endian userspace. 1474 This is usually the case for distributions targeting arm64. 1475 1476endchoice 1477 1478config SCHED_MC 1479 bool "Multi-core scheduler support" 1480 help 1481 Multi-core scheduler support improves the CPU scheduler's decision 1482 making when dealing with multi-core CPU chips at a cost of slightly 1483 increased overhead in some places. If unsure say N here. 1484 1485config SCHED_CLUSTER 1486 bool "Cluster scheduler support" 1487 help 1488 Cluster scheduler support improves the CPU scheduler's decision 1489 making when dealing with machines that have clusters of CPUs. 1490 Cluster usually means a couple of CPUs which are placed closely 1491 by sharing mid-level caches, last-level cache tags or internal 1492 busses. 1493 1494config SCHED_SMT 1495 bool "SMT scheduler support" 1496 help 1497 Improves the CPU scheduler's decision making when dealing with 1498 MultiThreading at a cost of slightly increased overhead in some 1499 places. If unsure say N here. 1500 1501config NR_CPUS 1502 int "Maximum number of CPUs (2-4096)" 1503 range 2 4096 1504 default "512" 1505 1506config HOTPLUG_CPU 1507 bool "Support for hot-pluggable CPUs" 1508 select GENERIC_IRQ_MIGRATION 1509 help 1510 Say Y here to experiment with turning CPUs off and on. CPUs 1511 can be controlled through /sys/devices/system/cpu. 1512 1513# Common NUMA Features 1514config NUMA 1515 bool "NUMA Memory Allocation and Scheduler Support" 1516 select GENERIC_ARCH_NUMA 1517 select OF_NUMA 1518 select HAVE_SETUP_PER_CPU_AREA 1519 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1520 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1521 select USE_PERCPU_NUMA_NODE_ID 1522 help 1523 Enable NUMA (Non-Uniform Memory Access) support. 1524 1525 The kernel will try to allocate memory used by a CPU on the 1526 local memory of the CPU and add some more 1527 NUMA awareness to the kernel. 1528 1529config NODES_SHIFT 1530 int "Maximum NUMA Nodes (as a power of 2)" 1531 range 1 10 1532 default "4" 1533 depends on NUMA 1534 help 1535 Specify the maximum number of NUMA Nodes available on the target 1536 system. Increases memory reserved to accommodate various tables. 1537 1538source "kernel/Kconfig.hz" 1539 1540config ARCH_SPARSEMEM_ENABLE 1541 def_bool y 1542 select SPARSEMEM_VMEMMAP_ENABLE 1543 select SPARSEMEM_VMEMMAP 1544 1545config HW_PERF_EVENTS 1546 def_bool y 1547 depends on ARM_PMU 1548 1549# Supported by clang >= 7.0 or GCC >= 12.0.0 1550config CC_HAVE_SHADOW_CALL_STACK 1551 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1552 1553config PARAVIRT 1554 bool "Enable paravirtualization code" 1555 help 1556 This changes the kernel so it can modify itself when it is run 1557 under a hypervisor, potentially improving performance significantly 1558 over full virtualization. 1559 1560config PARAVIRT_TIME_ACCOUNTING 1561 bool "Paravirtual steal time accounting" 1562 select PARAVIRT 1563 help 1564 Select this option to enable fine granularity task steal time 1565 accounting. Time spent executing other tasks in parallel with 1566 the current vCPU is discounted from the vCPU power. To account for 1567 that, there can be a small performance impact. 1568 1569 If in doubt, say N here. 1570 1571config ARCH_SUPPORTS_KEXEC 1572 def_bool PM_SLEEP_SMP 1573 1574config ARCH_SUPPORTS_KEXEC_FILE 1575 def_bool y 1576 1577config ARCH_SELECTS_KEXEC_FILE 1578 def_bool y 1579 depends on KEXEC_FILE 1580 select HAVE_IMA_KEXEC if IMA 1581 1582config ARCH_SUPPORTS_KEXEC_SIG 1583 def_bool y 1584 1585config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1586 def_bool y 1587 1588config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1589 def_bool y 1590 1591config ARCH_SUPPORTS_CRASH_DUMP 1592 def_bool y 1593 1594config ARCH_DEFAULT_CRASH_DUMP 1595 def_bool y 1596 1597config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1598 def_bool CRASH_RESERVE 1599 1600config TRANS_TABLE 1601 def_bool y 1602 depends on HIBERNATION || KEXEC_CORE 1603 1604config XEN_DOM0 1605 def_bool y 1606 depends on XEN 1607 1608config XEN 1609 bool "Xen guest support on ARM64" 1610 depends on ARM64 && OF 1611 select SWIOTLB_XEN 1612 select PARAVIRT 1613 help 1614 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1615 1616# include/linux/mmzone.h requires the following to be true: 1617# 1618# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1619# 1620# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1621# 1622# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1623# ----+-------------------+--------------+----------------------+-------------------------+ 1624# 4K | 27 | 12 | 15 | 10 | 1625# 16K | 27 | 14 | 13 | 11 | 1626# 64K | 29 | 16 | 13 | 13 | 1627config ARCH_FORCE_MAX_ORDER 1628 int 1629 default "13" if ARM64_64K_PAGES 1630 default "11" if ARM64_16K_PAGES 1631 default "10" 1632 help 1633 The kernel page allocator limits the size of maximal physically 1634 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1635 defines the maximal power of two of number of pages that can be 1636 allocated as a single contiguous block. This option allows 1637 overriding the default setting when ability to allocate very 1638 large blocks of physically contiguous memory is required. 1639 1640 The maximal size of allocation cannot exceed the size of the 1641 section, so the value of MAX_PAGE_ORDER should satisfy 1642 1643 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1644 1645 Don't change if unsure. 1646 1647config UNMAP_KERNEL_AT_EL0 1648 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1649 default y 1650 help 1651 Speculation attacks against some high-performance processors can 1652 be used to bypass MMU permission checks and leak kernel data to 1653 userspace. This can be defended against by unmapping the kernel 1654 when running in userspace, mapping it back in on exception entry 1655 via a trampoline page in the vector table. 1656 1657 If unsure, say Y. 1658 1659config MITIGATE_SPECTRE_BRANCH_HISTORY 1660 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1661 default y 1662 help 1663 Speculation attacks against some high-performance processors can 1664 make use of branch history to influence future speculation. 1665 When taking an exception from user-space, a sequence of branches 1666 or a firmware call overwrites the branch history. 1667 1668config RODATA_FULL_DEFAULT_ENABLED 1669 bool "Apply r/o permissions of VM areas also to their linear aliases" 1670 default y 1671 help 1672 Apply read-only attributes of VM areas to the linear alias of 1673 the backing pages as well. This prevents code or read-only data 1674 from being modified (inadvertently or intentionally) via another 1675 mapping of the same memory page. This additional enhancement can 1676 be turned off at runtime by passing rodata=[off|on] (and turned on 1677 with rodata=full if this option is set to 'n') 1678 1679 This requires the linear region to be mapped down to pages, 1680 which may adversely affect performance in some cases. 1681 1682config ARM64_SW_TTBR0_PAN 1683 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1684 depends on !KCSAN 1685 select ARM64_PAN 1686 help 1687 Enabling this option prevents the kernel from accessing 1688 user-space memory directly by pointing TTBR0_EL1 to a reserved 1689 zeroed area and reserved ASID. The user access routines 1690 restore the valid TTBR0_EL1 temporarily. 1691 1692config ARM64_TAGGED_ADDR_ABI 1693 bool "Enable the tagged user addresses syscall ABI" 1694 default y 1695 help 1696 When this option is enabled, user applications can opt in to a 1697 relaxed ABI via prctl() allowing tagged addresses to be passed 1698 to system calls as pointer arguments. For details, see 1699 Documentation/arch/arm64/tagged-address-abi.rst. 1700 1701menuconfig COMPAT 1702 bool "Kernel support for 32-bit EL0" 1703 depends on ARM64_4K_PAGES || EXPERT 1704 select HAVE_UID16 1705 select OLD_SIGSUSPEND3 1706 select COMPAT_OLD_SIGACTION 1707 help 1708 This option enables support for a 32-bit EL0 running under a 64-bit 1709 kernel at EL1. AArch32-specific components such as system calls, 1710 the user helper functions, VFP support and the ptrace interface are 1711 handled appropriately by the kernel. 1712 1713 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1714 that you will only be able to execute AArch32 binaries that were compiled 1715 with page size aligned segments. 1716 1717 If you want to execute 32-bit userspace applications, say Y. 1718 1719if COMPAT 1720 1721config KUSER_HELPERS 1722 bool "Enable kuser helpers page for 32-bit applications" 1723 default y 1724 help 1725 Warning: disabling this option may break 32-bit user programs. 1726 1727 Provide kuser helpers to compat tasks. The kernel provides 1728 helper code to userspace in read only form at a fixed location 1729 to allow userspace to be independent of the CPU type fitted to 1730 the system. This permits binaries to be run on ARMv4 through 1731 to ARMv8 without modification. 1732 1733 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1734 1735 However, the fixed address nature of these helpers can be used 1736 by ROP (return orientated programming) authors when creating 1737 exploits. 1738 1739 If all of the binaries and libraries which run on your platform 1740 are built specifically for your platform, and make no use of 1741 these helpers, then you can turn this option off to hinder 1742 such exploits. However, in that case, if a binary or library 1743 relying on those helpers is run, it will not function correctly. 1744 1745 Say N here only if you are absolutely certain that you do not 1746 need these helpers; otherwise, the safe option is to say Y. 1747 1748config COMPAT_VDSO 1749 bool "Enable vDSO for 32-bit applications" 1750 depends on !CPU_BIG_ENDIAN 1751 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1752 select GENERIC_COMPAT_VDSO 1753 default y 1754 help 1755 Place in the process address space of 32-bit applications an 1756 ELF shared object providing fast implementations of gettimeofday 1757 and clock_gettime. 1758 1759 You must have a 32-bit build of glibc 2.22 or later for programs 1760 to seamlessly take advantage of this. 1761 1762config THUMB2_COMPAT_VDSO 1763 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1764 depends on COMPAT_VDSO 1765 default y 1766 help 1767 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1768 otherwise with '-marm'. 1769 1770config COMPAT_ALIGNMENT_FIXUPS 1771 bool "Fix up misaligned multi-word loads and stores in user space" 1772 1773menuconfig ARMV8_DEPRECATED 1774 bool "Emulate deprecated/obsolete ARMv8 instructions" 1775 depends on SYSCTL 1776 help 1777 Legacy software support may require certain instructions 1778 that have been deprecated or obsoleted in the architecture. 1779 1780 Enable this config to enable selective emulation of these 1781 features. 1782 1783 If unsure, say Y 1784 1785if ARMV8_DEPRECATED 1786 1787config SWP_EMULATION 1788 bool "Emulate SWP/SWPB instructions" 1789 help 1790 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1791 they are always undefined. Say Y here to enable software 1792 emulation of these instructions for userspace using LDXR/STXR. 1793 This feature can be controlled at runtime with the abi.swp 1794 sysctl which is disabled by default. 1795 1796 In some older versions of glibc [<=2.8] SWP is used during futex 1797 trylock() operations with the assumption that the code will not 1798 be preempted. This invalid assumption may be more likely to fail 1799 with SWP emulation enabled, leading to deadlock of the user 1800 application. 1801 1802 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1803 on an external transaction monitoring block called a global 1804 monitor to maintain update atomicity. If your system does not 1805 implement a global monitor, this option can cause programs that 1806 perform SWP operations to uncached memory to deadlock. 1807 1808 If unsure, say Y 1809 1810config CP15_BARRIER_EMULATION 1811 bool "Emulate CP15 Barrier instructions" 1812 help 1813 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1814 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1815 strongly recommended to use the ISB, DSB, and DMB 1816 instructions instead. 1817 1818 Say Y here to enable software emulation of these 1819 instructions for AArch32 userspace code. When this option is 1820 enabled, CP15 barrier usage is traced which can help 1821 identify software that needs updating. This feature can be 1822 controlled at runtime with the abi.cp15_barrier sysctl. 1823 1824 If unsure, say Y 1825 1826config SETEND_EMULATION 1827 bool "Emulate SETEND instruction" 1828 help 1829 The SETEND instruction alters the data-endianness of the 1830 AArch32 EL0, and is deprecated in ARMv8. 1831 1832 Say Y here to enable software emulation of the instruction 1833 for AArch32 userspace code. This feature can be controlled 1834 at runtime with the abi.setend sysctl. 1835 1836 Note: All the cpus on the system must have mixed endian support at EL0 1837 for this feature to be enabled. If a new CPU - which doesn't support mixed 1838 endian - is hotplugged in after this feature has been enabled, there could 1839 be unexpected results in the applications. 1840 1841 If unsure, say Y 1842endif # ARMV8_DEPRECATED 1843 1844endif # COMPAT 1845 1846menu "ARMv8.1 architectural features" 1847 1848config ARM64_HW_AFDBM 1849 bool "Support for hardware updates of the Access and Dirty page flags" 1850 default y 1851 help 1852 The ARMv8.1 architecture extensions introduce support for 1853 hardware updates of the access and dirty information in page 1854 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1855 capable processors, accesses to pages with PTE_AF cleared will 1856 set this bit instead of raising an access flag fault. 1857 Similarly, writes to read-only pages with the DBM bit set will 1858 clear the read-only bit (AP[2]) instead of raising a 1859 permission fault. 1860 1861 Kernels built with this configuration option enabled continue 1862 to work on pre-ARMv8.1 hardware and the performance impact is 1863 minimal. If unsure, say Y. 1864 1865config ARM64_PAN 1866 bool "Enable support for Privileged Access Never (PAN)" 1867 default y 1868 help 1869 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1870 prevents the kernel or hypervisor from accessing user-space (EL0) 1871 memory directly. 1872 1873 Choosing this option will cause any unprotected (not using 1874 copy_to_user et al) memory access to fail with a permission fault. 1875 1876 The feature is detected at runtime, and will remain as a 'nop' 1877 instruction if the cpu does not implement the feature. 1878 1879config AS_HAS_LSE_ATOMICS 1880 def_bool $(as-instr,.arch_extension lse) 1881 1882config ARM64_LSE_ATOMICS 1883 bool 1884 default ARM64_USE_LSE_ATOMICS 1885 depends on AS_HAS_LSE_ATOMICS 1886 1887config ARM64_USE_LSE_ATOMICS 1888 bool "Atomic instructions" 1889 default y 1890 help 1891 As part of the Large System Extensions, ARMv8.1 introduces new 1892 atomic instructions that are designed specifically to scale in 1893 very large systems. 1894 1895 Say Y here to make use of these instructions for the in-kernel 1896 atomic routines. This incurs a small overhead on CPUs that do 1897 not support these instructions and requires the kernel to be 1898 built with binutils >= 2.25 in order for the new instructions 1899 to be used. 1900 1901endmenu # "ARMv8.1 architectural features" 1902 1903menu "ARMv8.2 architectural features" 1904 1905config AS_HAS_ARMV8_2 1906 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1907 1908config AS_HAS_SHA3 1909 def_bool $(as-instr,.arch armv8.2-a+sha3) 1910 1911config ARM64_PMEM 1912 bool "Enable support for persistent memory" 1913 select ARCH_HAS_PMEM_API 1914 select ARCH_HAS_UACCESS_FLUSHCACHE 1915 help 1916 Say Y to enable support for the persistent memory API based on the 1917 ARMv8.2 DCPoP feature. 1918 1919 The feature is detected at runtime, and the kernel will use DC CVAC 1920 operations if DC CVAP is not supported (following the behaviour of 1921 DC CVAP itself if the system does not define a point of persistence). 1922 1923config ARM64_RAS_EXTN 1924 bool "Enable support for RAS CPU Extensions" 1925 default y 1926 help 1927 CPUs that support the Reliability, Availability and Serviceability 1928 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1929 errors, classify them and report them to software. 1930 1931 On CPUs with these extensions system software can use additional 1932 barriers to determine if faults are pending and read the 1933 classification from a new set of registers. 1934 1935 Selecting this feature will allow the kernel to use these barriers 1936 and access the new registers if the system supports the extension. 1937 Platform RAS features may additionally depend on firmware support. 1938 1939config ARM64_CNP 1940 bool "Enable support for Common Not Private (CNP) translations" 1941 default y 1942 help 1943 Common Not Private (CNP) allows translation table entries to 1944 be shared between different PEs in the same inner shareable 1945 domain, so the hardware can use this fact to optimise the 1946 caching of such entries in the TLB. 1947 1948 Selecting this option allows the CNP feature to be detected 1949 at runtime, and does not affect PEs that do not implement 1950 this feature. 1951 1952endmenu # "ARMv8.2 architectural features" 1953 1954menu "ARMv8.3 architectural features" 1955 1956config ARM64_PTR_AUTH 1957 bool "Enable support for pointer authentication" 1958 default y 1959 help 1960 Pointer authentication (part of the ARMv8.3 Extensions) provides 1961 instructions for signing and authenticating pointers against secret 1962 keys, which can be used to mitigate Return Oriented Programming (ROP) 1963 and other attacks. 1964 1965 This option enables these instructions at EL0 (i.e. for userspace). 1966 Choosing this option will cause the kernel to initialise secret keys 1967 for each process at exec() time, with these keys being 1968 context-switched along with the process. 1969 1970 The feature is detected at runtime. If the feature is not present in 1971 hardware it will not be advertised to userspace/KVM guest nor will it 1972 be enabled. 1973 1974 If the feature is present on the boot CPU but not on a late CPU, then 1975 the late CPU will be parked. Also, if the boot CPU does not have 1976 address auth and the late CPU has then the late CPU will still boot 1977 but with the feature disabled. On such a system, this option should 1978 not be selected. 1979 1980config ARM64_PTR_AUTH_KERNEL 1981 bool "Use pointer authentication for kernel" 1982 default y 1983 depends on ARM64_PTR_AUTH 1984 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1985 # Modern compilers insert a .note.gnu.property section note for PAC 1986 # which is only understood by binutils starting with version 2.33.1. 1987 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1988 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1989 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1990 help 1991 If the compiler supports the -mbranch-protection or 1992 -msign-return-address flag (e.g. GCC 7 or later), then this option 1993 will cause the kernel itself to be compiled with return address 1994 protection. In this case, and if the target hardware is known to 1995 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1996 disabled with minimal loss of protection. 1997 1998 This feature works with FUNCTION_GRAPH_TRACER option only if 1999 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2000 2001config CC_HAS_BRANCH_PROT_PAC_RET 2002 # GCC 9 or later, clang 8 or later 2003 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2004 2005config CC_HAS_SIGN_RETURN_ADDRESS 2006 # GCC 7, 8 2007 def_bool $(cc-option,-msign-return-address=all) 2008 2009config AS_HAS_ARMV8_3 2010 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 2011 2012config AS_HAS_CFI_NEGATE_RA_STATE 2013 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2014 2015config AS_HAS_LDAPR 2016 def_bool $(as-instr,.arch_extension rcpc) 2017 2018endmenu # "ARMv8.3 architectural features" 2019 2020menu "ARMv8.4 architectural features" 2021 2022config ARM64_AMU_EXTN 2023 bool "Enable support for the Activity Monitors Unit CPU extension" 2024 default y 2025 help 2026 The activity monitors extension is an optional extension introduced 2027 by the ARMv8.4 CPU architecture. This enables support for version 1 2028 of the activity monitors architecture, AMUv1. 2029 2030 To enable the use of this extension on CPUs that implement it, say Y. 2031 2032 Note that for architectural reasons, firmware _must_ implement AMU 2033 support when running on CPUs that present the activity monitors 2034 extension. The required support is present in: 2035 * Version 1.5 and later of the ARM Trusted Firmware 2036 2037 For kernels that have this configuration enabled but boot with broken 2038 firmware, you may need to say N here until the firmware is fixed. 2039 Otherwise you may experience firmware panics or lockups when 2040 accessing the counter registers. Even if you are not observing these 2041 symptoms, the values returned by the register reads might not 2042 correctly reflect reality. Most commonly, the value read will be 0, 2043 indicating that the counter is not enabled. 2044 2045config AS_HAS_ARMV8_4 2046 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2047 2048config ARM64_TLB_RANGE 2049 bool "Enable support for tlbi range feature" 2050 default y 2051 depends on AS_HAS_ARMV8_4 2052 help 2053 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2054 range of input addresses. 2055 2056 The feature introduces new assembly instructions, and they were 2057 support when binutils >= 2.30. 2058 2059endmenu # "ARMv8.4 architectural features" 2060 2061menu "ARMv8.5 architectural features" 2062 2063config AS_HAS_ARMV8_5 2064 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2065 2066config ARM64_BTI 2067 bool "Branch Target Identification support" 2068 default y 2069 help 2070 Branch Target Identification (part of the ARMv8.5 Extensions) 2071 provides a mechanism to limit the set of locations to which computed 2072 branch instructions such as BR or BLR can jump. 2073 2074 To make use of BTI on CPUs that support it, say Y. 2075 2076 BTI is intended to provide complementary protection to other control 2077 flow integrity protection mechanisms, such as the Pointer 2078 authentication mechanism provided as part of the ARMv8.3 Extensions. 2079 For this reason, it does not make sense to enable this option without 2080 also enabling support for pointer authentication. Thus, when 2081 enabling this option you should also select ARM64_PTR_AUTH=y. 2082 2083 Userspace binaries must also be specifically compiled to make use of 2084 this mechanism. If you say N here or the hardware does not support 2085 BTI, such binaries can still run, but you get no additional 2086 enforcement of branch destinations. 2087 2088config ARM64_BTI_KERNEL 2089 bool "Use Branch Target Identification for kernel" 2090 default y 2091 depends on ARM64_BTI 2092 depends on ARM64_PTR_AUTH_KERNEL 2093 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2094 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2095 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2096 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2097 depends on !CC_IS_GCC 2098 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2099 help 2100 Build the kernel with Branch Target Identification annotations 2101 and enable enforcement of this for kernel code. When this option 2102 is enabled and the system supports BTI all kernel code including 2103 modular code must have BTI enabled. 2104 2105config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2106 # GCC 9 or later, clang 8 or later 2107 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2108 2109config ARM64_E0PD 2110 bool "Enable support for E0PD" 2111 default y 2112 help 2113 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2114 that EL0 accesses made via TTBR1 always fault in constant time, 2115 providing similar benefits to KASLR as those provided by KPTI, but 2116 with lower overhead and without disrupting legitimate access to 2117 kernel memory such as SPE. 2118 2119 This option enables E0PD for TTBR1 where available. 2120 2121config ARM64_AS_HAS_MTE 2122 # Initial support for MTE went in binutils 2.32.0, checked with 2123 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2124 # as a late addition to the final architecture spec (LDGM/STGM) 2125 # is only supported in the newer 2.32.x and 2.33 binutils 2126 # versions, hence the extra "stgm" instruction check below. 2127 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2128 2129config ARM64_MTE 2130 bool "Memory Tagging Extension support" 2131 default y 2132 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2133 depends on AS_HAS_ARMV8_5 2134 depends on AS_HAS_LSE_ATOMICS 2135 # Required for tag checking in the uaccess routines 2136 select ARM64_PAN 2137 select ARCH_HAS_SUBPAGE_FAULTS 2138 select ARCH_USES_HIGH_VMA_FLAGS 2139 select ARCH_USES_PG_ARCH_2 2140 select ARCH_USES_PG_ARCH_3 2141 help 2142 Memory Tagging (part of the ARMv8.5 Extensions) provides 2143 architectural support for run-time, always-on detection of 2144 various classes of memory error to aid with software debugging 2145 to eliminate vulnerabilities arising from memory-unsafe 2146 languages. 2147 2148 This option enables the support for the Memory Tagging 2149 Extension at EL0 (i.e. for userspace). 2150 2151 Selecting this option allows the feature to be detected at 2152 runtime. Any secondary CPU not implementing this feature will 2153 not be allowed a late bring-up. 2154 2155 Userspace binaries that want to use this feature must 2156 explicitly opt in. The mechanism for the userspace is 2157 described in: 2158 2159 Documentation/arch/arm64/memory-tagging-extension.rst. 2160 2161endmenu # "ARMv8.5 architectural features" 2162 2163menu "ARMv8.7 architectural features" 2164 2165config ARM64_EPAN 2166 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2167 default y 2168 depends on ARM64_PAN 2169 help 2170 Enhanced Privileged Access Never (EPAN) allows Privileged 2171 Access Never to be used with Execute-only mappings. 2172 2173 The feature is detected at runtime, and will remain disabled 2174 if the cpu does not implement the feature. 2175endmenu # "ARMv8.7 architectural features" 2176 2177config AS_HAS_MOPS 2178 def_bool $(as-instr,.arch_extension mops) 2179 2180menu "ARMv8.9 architectural features" 2181 2182config ARM64_POE 2183 prompt "Permission Overlay Extension" 2184 def_bool y 2185 select ARCH_USES_HIGH_VMA_FLAGS 2186 select ARCH_HAS_PKEYS 2187 help 2188 The Permission Overlay Extension is used to implement Memory 2189 Protection Keys. Memory Protection Keys provides a mechanism for 2190 enforcing page-based protections, but without requiring modification 2191 of the page tables when an application changes protection domains. 2192 2193 For details, see Documentation/core-api/protection-keys.rst 2194 2195 If unsure, say y. 2196 2197config ARCH_PKEY_BITS 2198 int 2199 default 3 2200 2201config ARM64_HAFT 2202 bool "Support for Hardware managed Access Flag for Table Descriptors" 2203 depends on ARM64_HW_AFDBM 2204 default y 2205 help 2206 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2207 Flag for Table descriptors. When enabled an architectural executed 2208 memory access will update the Access Flag in each Table descriptor 2209 which is accessed during the translation table walk and for which 2210 the Access Flag is 0. The Access Flag of the Table descriptor use 2211 the same bit of PTE_AF. 2212 2213 The feature will only be enabled if all the CPUs in the system 2214 support this feature. If unsure, say Y. 2215 2216endmenu # "ARMv8.9 architectural features" 2217 2218menu "v9.4 architectural features" 2219 2220config ARM64_GCS 2221 bool "Enable support for Guarded Control Stack (GCS)" 2222 default y 2223 select ARCH_HAS_USER_SHADOW_STACK 2224 select ARCH_USES_HIGH_VMA_FLAGS 2225 depends on !UPROBES 2226 help 2227 Guarded Control Stack (GCS) provides support for a separate 2228 stack with restricted access which contains only return 2229 addresses. This can be used to harden against some attacks 2230 by comparing return address used by the program with what is 2231 stored in the GCS, and may also be used to efficiently obtain 2232 the call stack for applications such as profiling. 2233 2234 The feature is detected at runtime, and will remain disabled 2235 if the system does not implement the feature. 2236 2237endmenu # "v9.4 architectural features" 2238 2239config ARM64_SVE 2240 bool "ARM Scalable Vector Extension support" 2241 default y 2242 help 2243 The Scalable Vector Extension (SVE) is an extension to the AArch64 2244 execution state which complements and extends the SIMD functionality 2245 of the base architecture to support much larger vectors and to enable 2246 additional vectorisation opportunities. 2247 2248 To enable use of this extension on CPUs that implement it, say Y. 2249 2250 On CPUs that support the SVE2 extensions, this option will enable 2251 those too. 2252 2253 Note that for architectural reasons, firmware _must_ implement SVE 2254 support when running on SVE capable hardware. The required support 2255 is present in: 2256 2257 * version 1.5 and later of the ARM Trusted Firmware 2258 * the AArch64 boot wrapper since commit 5e1261e08abf 2259 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2260 2261 For other firmware implementations, consult the firmware documentation 2262 or vendor. 2263 2264 If you need the kernel to boot on SVE-capable hardware with broken 2265 firmware, you may need to say N here until you get your firmware 2266 fixed. Otherwise, you may experience firmware panics or lockups when 2267 booting the kernel. If unsure and you are not observing these 2268 symptoms, you should assume that it is safe to say Y. 2269 2270config ARM64_SME 2271 bool "ARM Scalable Matrix Extension support" 2272 default y 2273 depends on ARM64_SVE 2274 depends on BROKEN 2275 help 2276 The Scalable Matrix Extension (SME) is an extension to the AArch64 2277 execution state which utilises a substantial subset of the SVE 2278 instruction set, together with the addition of new architectural 2279 register state capable of holding two dimensional matrix tiles to 2280 enable various matrix operations. 2281 2282config ARM64_PSEUDO_NMI 2283 bool "Support for NMI-like interrupts" 2284 select ARM_GIC_V3 2285 help 2286 Adds support for mimicking Non-Maskable Interrupts through the use of 2287 GIC interrupt priority. This support requires version 3 or later of 2288 ARM GIC. 2289 2290 This high priority configuration for interrupts needs to be 2291 explicitly enabled by setting the kernel parameter 2292 "irqchip.gicv3_pseudo_nmi" to 1. 2293 2294 If unsure, say N 2295 2296if ARM64_PSEUDO_NMI 2297config ARM64_DEBUG_PRIORITY_MASKING 2298 bool "Debug interrupt priority masking" 2299 help 2300 This adds runtime checks to functions enabling/disabling 2301 interrupts when using priority masking. The additional checks verify 2302 the validity of ICC_PMR_EL1 when calling concerned functions. 2303 2304 If unsure, say N 2305endif # ARM64_PSEUDO_NMI 2306 2307config RELOCATABLE 2308 bool "Build a relocatable kernel image" if EXPERT 2309 select ARCH_HAS_RELR 2310 default y 2311 help 2312 This builds the kernel as a Position Independent Executable (PIE), 2313 which retains all relocation metadata required to relocate the 2314 kernel binary at runtime to a different virtual address than the 2315 address it was linked at. 2316 Since AArch64 uses the RELA relocation format, this requires a 2317 relocation pass at runtime even if the kernel is loaded at the 2318 same address it was linked at. 2319 2320config RANDOMIZE_BASE 2321 bool "Randomize the address of the kernel image" 2322 select RELOCATABLE 2323 help 2324 Randomizes the virtual address at which the kernel image is 2325 loaded, as a security feature that deters exploit attempts 2326 relying on knowledge of the location of kernel internals. 2327 2328 It is the bootloader's job to provide entropy, by passing a 2329 random u64 value in /chosen/kaslr-seed at kernel entry. 2330 2331 When booting via the UEFI stub, it will invoke the firmware's 2332 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2333 to the kernel proper. In addition, it will randomise the physical 2334 location of the kernel Image as well. 2335 2336 If unsure, say N. 2337 2338config RANDOMIZE_MODULE_REGION_FULL 2339 bool "Randomize the module region over a 2 GB range" 2340 depends on RANDOMIZE_BASE 2341 default y 2342 help 2343 Randomizes the location of the module region inside a 2 GB window 2344 covering the core kernel. This way, it is less likely for modules 2345 to leak information about the location of core kernel data structures 2346 but it does imply that function calls between modules and the core 2347 kernel will need to be resolved via veneers in the module PLT. 2348 2349 When this option is not set, the module region will be randomized over 2350 a limited range that contains the [_stext, _etext] interval of the 2351 core kernel, so branch relocations are almost always in range unless 2352 the region is exhausted. In this particular case of region 2353 exhaustion, modules might be able to fall back to a larger 2GB area. 2354 2355config CC_HAVE_STACKPROTECTOR_SYSREG 2356 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2357 2358config STACKPROTECTOR_PER_TASK 2359 def_bool y 2360 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2361 2362config UNWIND_PATCH_PAC_INTO_SCS 2363 bool "Enable shadow call stack dynamically using code patching" 2364 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2365 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2366 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2367 depends on SHADOW_CALL_STACK 2368 select UNWIND_TABLES 2369 select DYNAMIC_SCS 2370 2371config ARM64_CONTPTE 2372 bool "Contiguous PTE mappings for user memory" if EXPERT 2373 depends on TRANSPARENT_HUGEPAGE 2374 default y 2375 help 2376 When enabled, user mappings are configured using the PTE contiguous 2377 bit, for any mappings that meet the size and alignment requirements. 2378 This reduces TLB pressure and improves performance. 2379 2380endmenu # "Kernel Features" 2381 2382menu "Boot options" 2383 2384config ARM64_ACPI_PARKING_PROTOCOL 2385 bool "Enable support for the ARM64 ACPI parking protocol" 2386 depends on ACPI 2387 help 2388 Enable support for the ARM64 ACPI parking protocol. If disabled 2389 the kernel will not allow booting through the ARM64 ACPI parking 2390 protocol even if the corresponding data is present in the ACPI 2391 MADT table. 2392 2393config CMDLINE 2394 string "Default kernel command string" 2395 default "" 2396 help 2397 Provide a set of default command-line options at build time by 2398 entering them here. As a minimum, you should specify the the 2399 root device (e.g. root=/dev/nfs). 2400 2401choice 2402 prompt "Kernel command line type" 2403 depends on CMDLINE != "" 2404 default CMDLINE_FROM_BOOTLOADER 2405 help 2406 Choose how the kernel will handle the provided default kernel 2407 command line string. 2408 2409config CMDLINE_FROM_BOOTLOADER 2410 bool "Use bootloader kernel arguments if available" 2411 help 2412 Uses the command-line options passed by the boot loader. If 2413 the boot loader doesn't provide any, the default kernel command 2414 string provided in CMDLINE will be used. 2415 2416config CMDLINE_FORCE 2417 bool "Always use the default kernel command string" 2418 help 2419 Always use the default kernel command string, even if the boot 2420 loader passes other arguments to the kernel. 2421 This is useful if you cannot or don't want to change the 2422 command-line options your boot loader passes to the kernel. 2423 2424endchoice 2425 2426config EFI_STUB 2427 bool 2428 2429config EFI 2430 bool "UEFI runtime support" 2431 depends on OF && !CPU_BIG_ENDIAN 2432 depends on KERNEL_MODE_NEON 2433 select ARCH_SUPPORTS_ACPI 2434 select LIBFDT 2435 select UCS2_STRING 2436 select EFI_PARAMS_FROM_FDT 2437 select EFI_RUNTIME_WRAPPERS 2438 select EFI_STUB 2439 select EFI_GENERIC_STUB 2440 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2441 default y 2442 help 2443 This option provides support for runtime services provided 2444 by UEFI firmware (such as non-volatile variables, realtime 2445 clock, and platform reset). A UEFI stub is also provided to 2446 allow the kernel to be booted as an EFI application. This 2447 is only useful on systems that have UEFI firmware. 2448 2449config COMPRESSED_INSTALL 2450 bool "Install compressed image by default" 2451 help 2452 This makes the regular "make install" install the compressed 2453 image we built, not the legacy uncompressed one. 2454 2455 You can check that a compressed image works for you by doing 2456 "make zinstall" first, and verifying that everything is fine 2457 in your environment before making "make install" do this for 2458 you. 2459 2460config DMI 2461 bool "Enable support for SMBIOS (DMI) tables" 2462 depends on EFI 2463 default y 2464 help 2465 This enables SMBIOS/DMI feature for systems. 2466 2467 This option is only useful on systems that have UEFI firmware. 2468 However, even with this option, the resultant kernel should 2469 continue to boot on existing non-UEFI platforms. 2470 2471endmenu # "Boot options" 2472 2473menu "Power management options" 2474 2475source "kernel/power/Kconfig" 2476 2477config ARCH_HIBERNATION_POSSIBLE 2478 def_bool y 2479 depends on CPU_PM 2480 2481config ARCH_HIBERNATION_HEADER 2482 def_bool y 2483 depends on HIBERNATION 2484 2485config ARCH_SUSPEND_POSSIBLE 2486 def_bool y 2487 2488endmenu # "Power management options" 2489 2490menu "CPU Power Management" 2491 2492source "drivers/cpuidle/Kconfig" 2493 2494source "drivers/cpufreq/Kconfig" 2495 2496endmenu # "CPU Power Management" 2497 2498source "drivers/acpi/Kconfig" 2499 2500source "arch/arm64/kvm/Kconfig" 2501 2502