1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 41 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 42 select ARCH_HAS_PTE_DEVMAP 43 select ARCH_HAS_PTE_SPECIAL 44 select ARCH_HAS_HW_PTE_YOUNG 45 select ARCH_HAS_SETUP_DMA_OPS 46 select ARCH_HAS_SET_DIRECT_MAP 47 select ARCH_HAS_SET_MEMORY 48 select ARCH_HAS_MEM_ENCRYPT 49 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 50 select ARCH_STACKWALK 51 select ARCH_HAS_STRICT_KERNEL_RWX 52 select ARCH_HAS_STRICT_MODULE_RWX 53 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 54 select ARCH_HAS_SYNC_DMA_FOR_CPU 55 select ARCH_HAS_SYSCALL_WRAPPER 56 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 57 select ARCH_HAS_ZONE_DMA_SET if EXPERT 58 select ARCH_HAVE_ELF_PROT 59 select ARCH_HAVE_NMI_SAFE_CMPXCHG 60 select ARCH_HAVE_TRACE_MMIO_ACCESS 61 select ARCH_INLINE_READ_LOCK if !PREEMPTION 62 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 63 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 65 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 66 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 69 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 70 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 73 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 74 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 77 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 78 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 79 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 83 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 84 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 87 select ARCH_KEEP_MEMBLOCK 88 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 89 select ARCH_USE_CMPXCHG_LOCKREF 90 select ARCH_USE_GNU_PROPERTY 91 select ARCH_USE_MEMTEST 92 select ARCH_USE_QUEUED_RWLOCKS 93 select ARCH_USE_QUEUED_SPINLOCKS 94 select ARCH_USE_SYM_ANNOTATIONS 95 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 96 select ARCH_SUPPORTS_HUGETLBFS 97 select ARCH_SUPPORTS_MEMORY_FAILURE 98 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 99 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 100 select ARCH_SUPPORTS_LTO_CLANG_THIN 101 select ARCH_SUPPORTS_CFI_CLANG 102 select ARCH_SUPPORTS_ATOMIC_RMW 103 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 104 select ARCH_SUPPORTS_NUMA_BALANCING 105 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 106 select ARCH_SUPPORTS_PER_VMA_LOCK 107 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 108 select ARCH_SUPPORTS_RT 109 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 110 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 111 select ARCH_WANT_DEFAULT_BPF_JIT 112 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 113 select ARCH_WANT_FRAME_POINTERS 114 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 115 select ARCH_WANT_LD_ORPHAN_WARN 116 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 117 select ARCH_WANTS_NO_INSTR 118 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 119 select ARCH_HAS_UBSAN 120 select ARM_AMBA 121 select ARM_ARCH_TIMER 122 select ARM_GIC 123 select AUDIT_ARCH_COMPAT_GENERIC 124 select ARM_GIC_V2M if PCI 125 select ARM_GIC_V3 126 select ARM_GIC_V3_ITS if PCI 127 select ARM_PSCI_FW 128 select BUILDTIME_TABLE_SORT 129 select CLONE_BACKWARDS 130 select COMMON_CLK 131 select CPU_PM if (SUSPEND || CPU_IDLE) 132 select CPUMASK_OFFSTACK if NR_CPUS > 256 133 select CRC32 134 select DCACHE_WORD_ACCESS 135 select DYNAMIC_FTRACE if FUNCTION_TRACER 136 select DMA_BOUNCE_UNALIGNED_KMALLOC 137 select DMA_DIRECT_REMAP 138 select EDAC_SUPPORT 139 select FRAME_POINTER 140 select FUNCTION_ALIGNMENT_4B 141 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 142 select GENERIC_ALLOCATOR 143 select GENERIC_ARCH_TOPOLOGY 144 select GENERIC_CLOCKEVENTS_BROADCAST 145 select GENERIC_CPU_AUTOPROBE 146 select GENERIC_CPU_DEVICES 147 select GENERIC_CPU_VULNERABILITIES 148 select GENERIC_EARLY_IOREMAP 149 select GENERIC_IDLE_POLL_SETUP 150 select GENERIC_IOREMAP 151 select GENERIC_IRQ_IPI 152 select GENERIC_IRQ_PROBE 153 select GENERIC_IRQ_SHOW 154 select GENERIC_IRQ_SHOW_LEVEL 155 select GENERIC_LIB_DEVMEM_IS_ALLOWED 156 select GENERIC_PCI_IOMAP 157 select GENERIC_PTDUMP 158 select GENERIC_SCHED_CLOCK 159 select GENERIC_SMP_IDLE_THREAD 160 select GENERIC_TIME_VSYSCALL 161 select GENERIC_GETTIMEOFDAY 162 select GENERIC_VDSO_TIME_NS 163 select HARDIRQS_SW_RESEND 164 select HAS_IOPORT 165 select HAVE_MOVE_PMD 166 select HAVE_MOVE_PUD 167 select HAVE_PCI 168 select HAVE_ACPI_APEI if (ACPI && EFI) 169 select HAVE_ALIGNED_STRUCT_PAGE 170 select HAVE_ARCH_AUDITSYSCALL 171 select HAVE_ARCH_BITREVERSE 172 select HAVE_ARCH_COMPILER_H 173 select HAVE_ARCH_HUGE_VMALLOC 174 select HAVE_ARCH_HUGE_VMAP 175 select HAVE_ARCH_JUMP_LABEL 176 select HAVE_ARCH_JUMP_LABEL_RELATIVE 177 select HAVE_ARCH_KASAN 178 select HAVE_ARCH_KASAN_VMALLOC 179 select HAVE_ARCH_KASAN_SW_TAGS 180 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 181 # Some instrumentation may be unsound, hence EXPERT 182 select HAVE_ARCH_KCSAN if EXPERT 183 select HAVE_ARCH_KFENCE 184 select HAVE_ARCH_KGDB 185 select HAVE_ARCH_MMAP_RND_BITS 186 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 187 select HAVE_ARCH_PREL32_RELOCATIONS 188 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 189 select HAVE_ARCH_SECCOMP_FILTER 190 select HAVE_ARCH_STACKLEAK 191 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 192 select HAVE_ARCH_TRACEHOOK 193 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 194 select HAVE_ARCH_VMAP_STACK 195 select HAVE_ARM_SMCCC 196 select HAVE_ASM_MODVERSIONS 197 select HAVE_EBPF_JIT 198 select HAVE_C_RECORDMCOUNT 199 select HAVE_CMPXCHG_DOUBLE 200 select HAVE_CMPXCHG_LOCAL 201 select HAVE_CONTEXT_TRACKING_USER 202 select HAVE_DEBUG_KMEMLEAK 203 select HAVE_DMA_CONTIGUOUS 204 select HAVE_DYNAMIC_FTRACE 205 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 206 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 207 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 208 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 209 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 210 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 211 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 212 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 213 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 214 if DYNAMIC_FTRACE_WITH_ARGS 215 select HAVE_SAMPLE_FTRACE_DIRECT 216 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 217 select HAVE_EFFICIENT_UNALIGNED_ACCESS 218 select HAVE_GUP_FAST 219 select HAVE_FTRACE_MCOUNT_RECORD 220 select HAVE_FUNCTION_TRACER 221 select HAVE_FUNCTION_ERROR_INJECTION 222 select HAVE_FUNCTION_GRAPH_TRACER 223 select HAVE_FUNCTION_GRAPH_RETVAL 224 select HAVE_GCC_PLUGINS 225 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 226 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 227 select HAVE_HW_BREAKPOINT if PERF_EVENTS 228 select HAVE_IOREMAP_PROT 229 select HAVE_IRQ_TIME_ACCOUNTING 230 select HAVE_MOD_ARCH_SPECIFIC 231 select HAVE_NMI 232 select HAVE_PERF_EVENTS 233 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 234 select HAVE_PERF_REGS 235 select HAVE_PERF_USER_STACK_DUMP 236 select HAVE_PREEMPT_DYNAMIC_KEY 237 select HAVE_REGS_AND_STACK_ACCESS_API 238 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 239 select HAVE_FUNCTION_ARG_ACCESS_API 240 select MMU_GATHER_RCU_TABLE_FREE 241 select HAVE_RSEQ 242 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 243 select HAVE_STACKPROTECTOR 244 select HAVE_SYSCALL_TRACEPOINTS 245 select HAVE_KPROBES 246 select HAVE_KRETPROBES 247 select HAVE_GENERIC_VDSO 248 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 249 select IRQ_DOMAIN 250 select IRQ_FORCED_THREADING 251 select KASAN_VMALLOC if KASAN 252 select LOCK_MM_AND_FIND_VMA 253 select MODULES_USE_ELF_RELA 254 select NEED_DMA_MAP_STATE 255 select NEED_SG_DMA_LENGTH 256 select OF 257 select OF_EARLY_FLATTREE 258 select PCI_DOMAINS_GENERIC if PCI 259 select PCI_ECAM if (ACPI && PCI) 260 select PCI_SYSCALL if PCI 261 select POWER_RESET 262 select POWER_SUPPLY 263 select SPARSE_IRQ 264 select SWIOTLB 265 select SYSCTL_EXCEPTION_TRACE 266 select THREAD_INFO_IN_TASK 267 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 268 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 269 select TRACE_IRQFLAGS_SUPPORT 270 select TRACE_IRQFLAGS_NMI_SUPPORT 271 select HAVE_SOFTIRQ_ON_OWN_STACK 272 select USER_STACKTRACE_SUPPORT 273 select VDSO_GETRANDOM 274 help 275 ARM 64-bit (AArch64) Linux support. 276 277config RUSTC_SUPPORTS_ARM64 278 def_bool y 279 depends on CPU_LITTLE_ENDIAN 280 # Shadow call stack is only supported on certain rustc versions. 281 # 282 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 283 # required due to use of the -Zfixed-x18 flag. 284 # 285 # Otherwise, rustc version 1.82+ is required due to use of the 286 # -Zsanitizer=shadow-call-stack flag. 287 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 288 289config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 290 def_bool CC_IS_CLANG 291 # https://github.com/ClangBuiltLinux/linux/issues/1507 292 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 293 294config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 295 def_bool CC_IS_GCC 296 depends on $(cc-option,-fpatchable-function-entry=2) 297 298config 64BIT 299 def_bool y 300 301config MMU 302 def_bool y 303 304config ARM64_CONT_PTE_SHIFT 305 int 306 default 5 if PAGE_SIZE_64KB 307 default 7 if PAGE_SIZE_16KB 308 default 4 309 310config ARM64_CONT_PMD_SHIFT 311 int 312 default 5 if PAGE_SIZE_64KB 313 default 5 if PAGE_SIZE_16KB 314 default 4 315 316config ARCH_MMAP_RND_BITS_MIN 317 default 14 if PAGE_SIZE_64KB 318 default 16 if PAGE_SIZE_16KB 319 default 18 320 321# max bits determined by the following formula: 322# VA_BITS - PAGE_SHIFT - 3 323config ARCH_MMAP_RND_BITS_MAX 324 default 19 if ARM64_VA_BITS=36 325 default 24 if ARM64_VA_BITS=39 326 default 27 if ARM64_VA_BITS=42 327 default 30 if ARM64_VA_BITS=47 328 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 329 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 330 default 33 if ARM64_VA_BITS=48 331 default 14 if ARM64_64K_PAGES 332 default 16 if ARM64_16K_PAGES 333 default 18 334 335config ARCH_MMAP_RND_COMPAT_BITS_MIN 336 default 7 if ARM64_64K_PAGES 337 default 9 if ARM64_16K_PAGES 338 default 11 339 340config ARCH_MMAP_RND_COMPAT_BITS_MAX 341 default 16 342 343config NO_IOPORT_MAP 344 def_bool y if !PCI 345 346config STACKTRACE_SUPPORT 347 def_bool y 348 349config ILLEGAL_POINTER_VALUE 350 hex 351 default 0xdead000000000000 352 353config LOCKDEP_SUPPORT 354 def_bool y 355 356config GENERIC_BUG 357 def_bool y 358 depends on BUG 359 360config GENERIC_BUG_RELATIVE_POINTERS 361 def_bool y 362 depends on GENERIC_BUG 363 364config GENERIC_HWEIGHT 365 def_bool y 366 367config GENERIC_CSUM 368 def_bool y 369 370config GENERIC_CALIBRATE_DELAY 371 def_bool y 372 373config SMP 374 def_bool y 375 376config KERNEL_MODE_NEON 377 def_bool y 378 379config FIX_EARLYCON_MEM 380 def_bool y 381 382config PGTABLE_LEVELS 383 int 384 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 385 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 386 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 387 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 388 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 389 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 390 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 391 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 392 393config ARCH_SUPPORTS_UPROBES 394 def_bool y 395 396config ARCH_PROC_KCORE_TEXT 397 def_bool y 398 399config BROKEN_GAS_INST 400 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 401 402config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 403 bool 404 # Clang's __builtin_return_address() strips the PAC since 12.0.0 405 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 406 default y if CC_IS_CLANG 407 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 408 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 409 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 410 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 411 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 412 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 413 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 414 default n 415 416config KASAN_SHADOW_OFFSET 417 hex 418 depends on KASAN_GENERIC || KASAN_SW_TAGS 419 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 420 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 421 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 422 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 423 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 424 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 425 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 426 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 427 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 428 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 429 default 0xffffffffffffffff 430 431config UNWIND_TABLES 432 bool 433 434source "arch/arm64/Kconfig.platforms" 435 436menu "Kernel Features" 437 438menu "ARM errata workarounds via the alternatives framework" 439 440config AMPERE_ERRATUM_AC03_CPU_38 441 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 442 default y 443 help 444 This option adds an alternative code sequence to work around Ampere 445 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 446 447 The affected design reports FEAT_HAFDBS as not implemented in 448 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 449 as required by the architecture. The unadvertised HAFDBS 450 implementation suffers from an additional erratum where hardware 451 A/D updates can occur after a PTE has been marked invalid. 452 453 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 454 which avoids enabling unadvertised hardware Access Flag management 455 at stage-2. 456 457 If unsure, say Y. 458 459config ARM64_WORKAROUND_CLEAN_CACHE 460 bool 461 462config ARM64_ERRATUM_826319 463 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 464 default y 465 select ARM64_WORKAROUND_CLEAN_CACHE 466 help 467 This option adds an alternative code sequence to work around ARM 468 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 469 AXI master interface and an L2 cache. 470 471 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 472 and is unable to accept a certain write via this interface, it will 473 not progress on read data presented on the read data channel and the 474 system can deadlock. 475 476 The workaround promotes data cache clean instructions to 477 data cache clean-and-invalidate. 478 Please note that this does not necessarily enable the workaround, 479 as it depends on the alternative framework, which will only patch 480 the kernel if an affected CPU is detected. 481 482 If unsure, say Y. 483 484config ARM64_ERRATUM_827319 485 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 486 default y 487 select ARM64_WORKAROUND_CLEAN_CACHE 488 help 489 This option adds an alternative code sequence to work around ARM 490 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 491 master interface and an L2 cache. 492 493 Under certain conditions this erratum can cause a clean line eviction 494 to occur at the same time as another transaction to the same address 495 on the AMBA 5 CHI interface, which can cause data corruption if the 496 interconnect reorders the two transactions. 497 498 The workaround promotes data cache clean instructions to 499 data cache clean-and-invalidate. 500 Please note that this does not necessarily enable the workaround, 501 as it depends on the alternative framework, which will only patch 502 the kernel if an affected CPU is detected. 503 504 If unsure, say Y. 505 506config ARM64_ERRATUM_824069 507 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 508 default y 509 select ARM64_WORKAROUND_CLEAN_CACHE 510 help 511 This option adds an alternative code sequence to work around ARM 512 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 513 to a coherent interconnect. 514 515 If a Cortex-A53 processor is executing a store or prefetch for 516 write instruction at the same time as a processor in another 517 cluster is executing a cache maintenance operation to the same 518 address, then this erratum might cause a clean cache line to be 519 incorrectly marked as dirty. 520 521 The workaround promotes data cache clean instructions to 522 data cache clean-and-invalidate. 523 Please note that this option does not necessarily enable the 524 workaround, as it depends on the alternative framework, which will 525 only patch the kernel if an affected CPU is detected. 526 527 If unsure, say Y. 528 529config ARM64_ERRATUM_819472 530 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 531 default y 532 select ARM64_WORKAROUND_CLEAN_CACHE 533 help 534 This option adds an alternative code sequence to work around ARM 535 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 536 present when it is connected to a coherent interconnect. 537 538 If the processor is executing a load and store exclusive sequence at 539 the same time as a processor in another cluster is executing a cache 540 maintenance operation to the same address, then this erratum might 541 cause data corruption. 542 543 The workaround promotes data cache clean instructions to 544 data cache clean-and-invalidate. 545 Please note that this does not necessarily enable the workaround, 546 as it depends on the alternative framework, which will only patch 547 the kernel if an affected CPU is detected. 548 549 If unsure, say Y. 550 551config ARM64_ERRATUM_832075 552 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 553 default y 554 help 555 This option adds an alternative code sequence to work around ARM 556 erratum 832075 on Cortex-A57 parts up to r1p2. 557 558 Affected Cortex-A57 parts might deadlock when exclusive load/store 559 instructions to Write-Back memory are mixed with Device loads. 560 561 The workaround is to promote device loads to use Load-Acquire 562 semantics. 563 Please note that this does not necessarily enable the workaround, 564 as it depends on the alternative framework, which will only patch 565 the kernel if an affected CPU is detected. 566 567 If unsure, say Y. 568 569config ARM64_ERRATUM_834220 570 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 571 depends on KVM 572 help 573 This option adds an alternative code sequence to work around ARM 574 erratum 834220 on Cortex-A57 parts up to r1p2. 575 576 Affected Cortex-A57 parts might report a Stage 2 translation 577 fault as the result of a Stage 1 fault for load crossing a 578 page boundary when there is a permission or device memory 579 alignment fault at Stage 1 and a translation fault at Stage 2. 580 581 The workaround is to verify that the Stage 1 translation 582 doesn't generate a fault before handling the Stage 2 fault. 583 Please note that this does not necessarily enable the workaround, 584 as it depends on the alternative framework, which will only patch 585 the kernel if an affected CPU is detected. 586 587 If unsure, say N. 588 589config ARM64_ERRATUM_1742098 590 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 591 depends on COMPAT 592 default y 593 help 594 This option removes the AES hwcap for aarch32 user-space to 595 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 596 597 Affected parts may corrupt the AES state if an interrupt is 598 taken between a pair of AES instructions. These instructions 599 are only present if the cryptography extensions are present. 600 All software should have a fallback implementation for CPUs 601 that don't implement the cryptography extensions. 602 603 If unsure, say Y. 604 605config ARM64_ERRATUM_845719 606 bool "Cortex-A53: 845719: a load might read incorrect data" 607 depends on COMPAT 608 default y 609 help 610 This option adds an alternative code sequence to work around ARM 611 erratum 845719 on Cortex-A53 parts up to r0p4. 612 613 When running a compat (AArch32) userspace on an affected Cortex-A53 614 part, a load at EL0 from a virtual address that matches the bottom 32 615 bits of the virtual address used by a recent load at (AArch64) EL1 616 might return incorrect data. 617 618 The workaround is to write the contextidr_el1 register on exception 619 return to a 32-bit task. 620 Please note that this does not necessarily enable the workaround, 621 as it depends on the alternative framework, which will only patch 622 the kernel if an affected CPU is detected. 623 624 If unsure, say Y. 625 626config ARM64_ERRATUM_843419 627 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 628 default y 629 help 630 This option links the kernel with '--fix-cortex-a53-843419' and 631 enables PLT support to replace certain ADRP instructions, which can 632 cause subsequent memory accesses to use an incorrect address on 633 Cortex-A53 parts up to r0p4. 634 635 If unsure, say Y. 636 637config ARM64_LD_HAS_FIX_ERRATUM_843419 638 def_bool $(ld-option,--fix-cortex-a53-843419) 639 640config ARM64_ERRATUM_1024718 641 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 642 default y 643 help 644 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 645 646 Affected Cortex-A55 cores (all revisions) could cause incorrect 647 update of the hardware dirty bit when the DBM/AP bits are updated 648 without a break-before-make. The workaround is to disable the usage 649 of hardware DBM locally on the affected cores. CPUs not affected by 650 this erratum will continue to use the feature. 651 652 If unsure, say Y. 653 654config ARM64_ERRATUM_1418040 655 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 656 default y 657 depends on COMPAT 658 help 659 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 660 errata 1188873 and 1418040. 661 662 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 663 cause register corruption when accessing the timer registers 664 from AArch32 userspace. 665 666 If unsure, say Y. 667 668config ARM64_WORKAROUND_SPECULATIVE_AT 669 bool 670 671config ARM64_ERRATUM_1165522 672 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 673 default y 674 select ARM64_WORKAROUND_SPECULATIVE_AT 675 help 676 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 677 678 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 679 corrupted TLBs by speculating an AT instruction during a guest 680 context switch. 681 682 If unsure, say Y. 683 684config ARM64_ERRATUM_1319367 685 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 686 default y 687 select ARM64_WORKAROUND_SPECULATIVE_AT 688 help 689 This option adds work arounds for ARM Cortex-A57 erratum 1319537 690 and A72 erratum 1319367 691 692 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 693 speculating an AT instruction during a guest context switch. 694 695 If unsure, say Y. 696 697config ARM64_ERRATUM_1530923 698 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 699 default y 700 select ARM64_WORKAROUND_SPECULATIVE_AT 701 help 702 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 703 704 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 705 corrupted TLBs by speculating an AT instruction during a guest 706 context switch. 707 708 If unsure, say Y. 709 710config ARM64_WORKAROUND_REPEAT_TLBI 711 bool 712 713config ARM64_ERRATUM_2441007 714 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 715 select ARM64_WORKAROUND_REPEAT_TLBI 716 help 717 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 718 719 Under very rare circumstances, affected Cortex-A55 CPUs 720 may not handle a race between a break-before-make sequence on one 721 CPU, and another CPU accessing the same page. This could allow a 722 store to a page that has been unmapped. 723 724 Work around this by adding the affected CPUs to the list that needs 725 TLB sequences to be done twice. 726 727 If unsure, say N. 728 729config ARM64_ERRATUM_1286807 730 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 731 select ARM64_WORKAROUND_REPEAT_TLBI 732 help 733 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 734 735 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 736 address for a cacheable mapping of a location is being 737 accessed by a core while another core is remapping the virtual 738 address to a new physical page using the recommended 739 break-before-make sequence, then under very rare circumstances 740 TLBI+DSB completes before a read using the translation being 741 invalidated has been observed by other observers. The 742 workaround repeats the TLBI+DSB operation. 743 744 If unsure, say N. 745 746config ARM64_ERRATUM_1463225 747 bool "Cortex-A76: Software Step might prevent interrupt recognition" 748 default y 749 help 750 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 751 752 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 753 of a system call instruction (SVC) can prevent recognition of 754 subsequent interrupts when software stepping is disabled in the 755 exception handler of the system call and either kernel debugging 756 is enabled or VHE is in use. 757 758 Work around the erratum by triggering a dummy step exception 759 when handling a system call from a task that is being stepped 760 in a VHE configuration of the kernel. 761 762 If unsure, say Y. 763 764config ARM64_ERRATUM_1542419 765 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 766 help 767 This option adds a workaround for ARM Neoverse-N1 erratum 768 1542419. 769 770 Affected Neoverse-N1 cores could execute a stale instruction when 771 modified by another CPU. The workaround depends on a firmware 772 counterpart. 773 774 Workaround the issue by hiding the DIC feature from EL0. This 775 forces user-space to perform cache maintenance. 776 777 If unsure, say N. 778 779config ARM64_ERRATUM_1508412 780 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 781 default y 782 help 783 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 784 785 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 786 of a store-exclusive or read of PAR_EL1 and a load with device or 787 non-cacheable memory attributes. The workaround depends on a firmware 788 counterpart. 789 790 KVM guests must also have the workaround implemented or they can 791 deadlock the system. 792 793 Work around the issue by inserting DMB SY barriers around PAR_EL1 794 register reads and warning KVM users. The DMB barrier is sufficient 795 to prevent a speculative PAR_EL1 read. 796 797 If unsure, say Y. 798 799config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 800 bool 801 802config ARM64_ERRATUM_2051678 803 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 804 default y 805 help 806 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 807 Affected Cortex-A510 might not respect the ordering rules for 808 hardware update of the page table's dirty bit. The workaround 809 is to not enable the feature on affected CPUs. 810 811 If unsure, say Y. 812 813config ARM64_ERRATUM_2077057 814 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 815 default y 816 help 817 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 818 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 819 expected, but a Pointer Authentication trap is taken instead. The 820 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 821 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 822 823 This can only happen when EL2 is stepping EL1. 824 825 When these conditions occur, the SPSR_EL2 value is unchanged from the 826 previous guest entry, and can be restored from the in-memory copy. 827 828 If unsure, say Y. 829 830config ARM64_ERRATUM_2658417 831 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 832 default y 833 help 834 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 835 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 836 BFMMLA or VMMLA instructions in rare circumstances when a pair of 837 A510 CPUs are using shared neon hardware. As the sharing is not 838 discoverable by the kernel, hide the BF16 HWCAP to indicate that 839 user-space should not be using these instructions. 840 841 If unsure, say Y. 842 843config ARM64_ERRATUM_2119858 844 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 845 default y 846 depends on CORESIGHT_TRBE 847 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 848 help 849 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 850 851 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 852 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 853 the event of a WRAP event. 854 855 Work around the issue by always making sure we move the TRBPTR_EL1 by 856 256 bytes before enabling the buffer and filling the first 256 bytes of 857 the buffer with ETM ignore packets upon disabling. 858 859 If unsure, say Y. 860 861config ARM64_ERRATUM_2139208 862 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 863 default y 864 depends on CORESIGHT_TRBE 865 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 866 help 867 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 868 869 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 870 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 871 the event of a WRAP event. 872 873 Work around the issue by always making sure we move the TRBPTR_EL1 by 874 256 bytes before enabling the buffer and filling the first 256 bytes of 875 the buffer with ETM ignore packets upon disabling. 876 877 If unsure, say Y. 878 879config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 880 bool 881 882config ARM64_ERRATUM_2054223 883 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 884 default y 885 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 886 help 887 Enable workaround for ARM Cortex-A710 erratum 2054223 888 889 Affected cores may fail to flush the trace data on a TSB instruction, when 890 the PE is in trace prohibited state. This will cause losing a few bytes 891 of the trace cached. 892 893 Workaround is to issue two TSB consecutively on affected cores. 894 895 If unsure, say Y. 896 897config ARM64_ERRATUM_2067961 898 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 899 default y 900 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 901 help 902 Enable workaround for ARM Neoverse-N2 erratum 2067961 903 904 Affected cores may fail to flush the trace data on a TSB instruction, when 905 the PE is in trace prohibited state. This will cause losing a few bytes 906 of the trace cached. 907 908 Workaround is to issue two TSB consecutively on affected cores. 909 910 If unsure, say Y. 911 912config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 913 bool 914 915config ARM64_ERRATUM_2253138 916 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 917 depends on CORESIGHT_TRBE 918 default y 919 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 920 help 921 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 922 923 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 924 for TRBE. Under some conditions, the TRBE might generate a write to the next 925 virtually addressed page following the last page of the TRBE address space 926 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 927 928 Work around this in the driver by always making sure that there is a 929 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 930 931 If unsure, say Y. 932 933config ARM64_ERRATUM_2224489 934 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 935 depends on CORESIGHT_TRBE 936 default y 937 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 938 help 939 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 940 941 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 942 for TRBE. Under some conditions, the TRBE might generate a write to the next 943 virtually addressed page following the last page of the TRBE address space 944 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 945 946 Work around this in the driver by always making sure that there is a 947 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 948 949 If unsure, say Y. 950 951config ARM64_ERRATUM_2441009 952 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 953 select ARM64_WORKAROUND_REPEAT_TLBI 954 help 955 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 956 957 Under very rare circumstances, affected Cortex-A510 CPUs 958 may not handle a race between a break-before-make sequence on one 959 CPU, and another CPU accessing the same page. This could allow a 960 store to a page that has been unmapped. 961 962 Work around this by adding the affected CPUs to the list that needs 963 TLB sequences to be done twice. 964 965 If unsure, say N. 966 967config ARM64_ERRATUM_2064142 968 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 969 depends on CORESIGHT_TRBE 970 default y 971 help 972 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 973 974 Affected Cortex-A510 core might fail to write into system registers after the 975 TRBE has been disabled. Under some conditions after the TRBE has been disabled 976 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 977 and TRBTRG_EL1 will be ignored and will not be effected. 978 979 Work around this in the driver by executing TSB CSYNC and DSB after collection 980 is stopped and before performing a system register write to one of the affected 981 registers. 982 983 If unsure, say Y. 984 985config ARM64_ERRATUM_2038923 986 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 987 depends on CORESIGHT_TRBE 988 default y 989 help 990 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 991 992 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 993 prohibited within the CPU. As a result, the trace buffer or trace buffer state 994 might be corrupted. This happens after TRBE buffer has been enabled by setting 995 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 996 execution changes from a context, in which trace is prohibited to one where it 997 isn't, or vice versa. In these mentioned conditions, the view of whether trace 998 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 999 the trace buffer state might be corrupted. 1000 1001 Work around this in the driver by preventing an inconsistent view of whether the 1002 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1003 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1004 two ISB instructions if no ERET is to take place. 1005 1006 If unsure, say Y. 1007 1008config ARM64_ERRATUM_1902691 1009 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1010 depends on CORESIGHT_TRBE 1011 default y 1012 help 1013 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1014 1015 Affected Cortex-A510 core might cause trace data corruption, when being written 1016 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1017 trace data. 1018 1019 Work around this problem in the driver by just preventing TRBE initialization on 1020 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1021 on such implementations. This will cover the kernel for any firmware that doesn't 1022 do this already. 1023 1024 If unsure, say Y. 1025 1026config ARM64_ERRATUM_2457168 1027 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1028 depends on ARM64_AMU_EXTN 1029 default y 1030 help 1031 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1032 1033 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1034 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1035 incorrectly giving a significantly higher output value. 1036 1037 Work around this problem by returning 0 when reading the affected counter in 1038 key locations that results in disabling all users of this counter. This effect 1039 is the same to firmware disabling affected counters. 1040 1041 If unsure, say Y. 1042 1043config ARM64_ERRATUM_2645198 1044 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1045 default y 1046 help 1047 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1048 1049 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1050 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1051 next instruction abort caused by permission fault. 1052 1053 Only user-space does executable to non-executable permission transition via 1054 mprotect() system call. Workaround the problem by doing a break-before-make 1055 TLB invalidation, for all changes to executable user space mappings. 1056 1057 If unsure, say Y. 1058 1059config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1060 bool 1061 1062config ARM64_ERRATUM_2966298 1063 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1064 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1065 default y 1066 help 1067 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1068 1069 On an affected Cortex-A520 core, a speculatively executed unprivileged 1070 load might leak data from a privileged level via a cache side channel. 1071 1072 Work around this problem by executing a TLBI before returning to EL0. 1073 1074 If unsure, say Y. 1075 1076config ARM64_ERRATUM_3117295 1077 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1078 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1079 default y 1080 help 1081 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1082 1083 On an affected Cortex-A510 core, a speculatively executed unprivileged 1084 load might leak data from a privileged level via a cache side channel. 1085 1086 Work around this problem by executing a TLBI before returning to EL0. 1087 1088 If unsure, say Y. 1089 1090config ARM64_ERRATUM_3194386 1091 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1092 default y 1093 help 1094 This option adds the workaround for the following errata: 1095 1096 * ARM Cortex-A76 erratum 3324349 1097 * ARM Cortex-A77 erratum 3324348 1098 * ARM Cortex-A78 erratum 3324344 1099 * ARM Cortex-A78C erratum 3324346 1100 * ARM Cortex-A78C erratum 3324347 1101 * ARM Cortex-A710 erratam 3324338 1102 * ARM Cortex-A715 errartum 3456084 1103 * ARM Cortex-A720 erratum 3456091 1104 * ARM Cortex-A725 erratum 3456106 1105 * ARM Cortex-X1 erratum 3324344 1106 * ARM Cortex-X1C erratum 3324346 1107 * ARM Cortex-X2 erratum 3324338 1108 * ARM Cortex-X3 erratum 3324335 1109 * ARM Cortex-X4 erratum 3194386 1110 * ARM Cortex-X925 erratum 3324334 1111 * ARM Neoverse-N1 erratum 3324349 1112 * ARM Neoverse N2 erratum 3324339 1113 * ARM Neoverse-N3 erratum 3456111 1114 * ARM Neoverse-V1 erratum 3324341 1115 * ARM Neoverse V2 erratum 3324336 1116 * ARM Neoverse-V3 erratum 3312417 1117 1118 On affected cores "MSR SSBS, #0" instructions may not affect 1119 subsequent speculative instructions, which may permit unexepected 1120 speculative store bypassing. 1121 1122 Work around this problem by placing a Speculation Barrier (SB) or 1123 Instruction Synchronization Barrier (ISB) after kernel changes to 1124 SSBS. The presence of the SSBS special-purpose register is hidden 1125 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1126 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1127 1128 If unsure, say Y. 1129 1130config CAVIUM_ERRATUM_22375 1131 bool "Cavium erratum 22375, 24313" 1132 default y 1133 help 1134 Enable workaround for errata 22375 and 24313. 1135 1136 This implements two gicv3-its errata workarounds for ThunderX. Both 1137 with a small impact affecting only ITS table allocation. 1138 1139 erratum 22375: only alloc 8MB table size 1140 erratum 24313: ignore memory access type 1141 1142 The fixes are in ITS initialization and basically ignore memory access 1143 type and table size provided by the TYPER and BASER registers. 1144 1145 If unsure, say Y. 1146 1147config CAVIUM_ERRATUM_23144 1148 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1149 depends on NUMA 1150 default y 1151 help 1152 ITS SYNC command hang for cross node io and collections/cpu mapping. 1153 1154 If unsure, say Y. 1155 1156config CAVIUM_ERRATUM_23154 1157 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1158 default y 1159 help 1160 The ThunderX GICv3 implementation requires a modified version for 1161 reading the IAR status to ensure data synchronization 1162 (access to icc_iar1_el1 is not sync'ed before and after). 1163 1164 It also suffers from erratum 38545 (also present on Marvell's 1165 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1166 spuriously presented to the CPU interface. 1167 1168 If unsure, say Y. 1169 1170config CAVIUM_ERRATUM_27456 1171 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1172 default y 1173 help 1174 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1175 instructions may cause the icache to become corrupted if it 1176 contains data for a non-current ASID. The fix is to 1177 invalidate the icache when changing the mm context. 1178 1179 If unsure, say Y. 1180 1181config CAVIUM_ERRATUM_30115 1182 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1183 default y 1184 help 1185 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1186 1.2, and T83 Pass 1.0, KVM guest execution may disable 1187 interrupts in host. Trapping both GICv3 group-0 and group-1 1188 accesses sidesteps the issue. 1189 1190 If unsure, say Y. 1191 1192config CAVIUM_TX2_ERRATUM_219 1193 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1194 default y 1195 help 1196 On Cavium ThunderX2, a load, store or prefetch instruction between a 1197 TTBR update and the corresponding context synchronizing operation can 1198 cause a spurious Data Abort to be delivered to any hardware thread in 1199 the CPU core. 1200 1201 Work around the issue by avoiding the problematic code sequence and 1202 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1203 trap handler performs the corresponding register access, skips the 1204 instruction and ensures context synchronization by virtue of the 1205 exception return. 1206 1207 If unsure, say Y. 1208 1209config FUJITSU_ERRATUM_010001 1210 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1211 default y 1212 help 1213 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1214 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1215 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1216 This fault occurs under a specific hardware condition when a 1217 load/store instruction performs an address translation using: 1218 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1219 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1220 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1221 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1222 1223 The workaround is to ensure these bits are clear in TCR_ELx. 1224 The workaround only affects the Fujitsu-A64FX. 1225 1226 If unsure, say Y. 1227 1228config HISILICON_ERRATUM_161600802 1229 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1230 default y 1231 help 1232 The HiSilicon Hip07 SoC uses the wrong redistributor base 1233 when issued ITS commands such as VMOVP and VMAPP, and requires 1234 a 128kB offset to be applied to the target address in this commands. 1235 1236 If unsure, say Y. 1237 1238config QCOM_FALKOR_ERRATUM_1003 1239 bool "Falkor E1003: Incorrect translation due to ASID change" 1240 default y 1241 help 1242 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1243 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1244 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1245 then only for entries in the walk cache, since the leaf translation 1246 is unchanged. Work around the erratum by invalidating the walk cache 1247 entries for the trampoline before entering the kernel proper. 1248 1249config QCOM_FALKOR_ERRATUM_1009 1250 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1251 default y 1252 select ARM64_WORKAROUND_REPEAT_TLBI 1253 help 1254 On Falkor v1, the CPU may prematurely complete a DSB following a 1255 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1256 one more time to fix the issue. 1257 1258 If unsure, say Y. 1259 1260config QCOM_QDF2400_ERRATUM_0065 1261 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1262 default y 1263 help 1264 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1265 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1266 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1267 1268 If unsure, say Y. 1269 1270config QCOM_FALKOR_ERRATUM_E1041 1271 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1272 default y 1273 help 1274 Falkor CPU may speculatively fetch instructions from an improper 1275 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1276 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1277 1278 If unsure, say Y. 1279 1280config NVIDIA_CARMEL_CNP_ERRATUM 1281 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1282 default y 1283 help 1284 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1285 invalidate shared TLB entries installed by a different core, as it would 1286 on standard ARM cores. 1287 1288 If unsure, say Y. 1289 1290config ROCKCHIP_ERRATUM_3588001 1291 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1292 default y 1293 help 1294 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1295 This means, that its sharability feature may not be used, even though it 1296 is supported by the IP itself. 1297 1298 If unsure, say Y. 1299 1300config SOCIONEXT_SYNQUACER_PREITS 1301 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1302 default y 1303 help 1304 Socionext Synquacer SoCs implement a separate h/w block to generate 1305 MSI doorbell writes with non-zero values for the device ID. 1306 1307 If unsure, say Y. 1308 1309endmenu # "ARM errata workarounds via the alternatives framework" 1310 1311choice 1312 prompt "Page size" 1313 default ARM64_4K_PAGES 1314 help 1315 Page size (translation granule) configuration. 1316 1317config ARM64_4K_PAGES 1318 bool "4KB" 1319 select HAVE_PAGE_SIZE_4KB 1320 help 1321 This feature enables 4KB pages support. 1322 1323config ARM64_16K_PAGES 1324 bool "16KB" 1325 select HAVE_PAGE_SIZE_16KB 1326 help 1327 The system will use 16KB pages support. AArch32 emulation 1328 requires applications compiled with 16K (or a multiple of 16K) 1329 aligned segments. 1330 1331config ARM64_64K_PAGES 1332 bool "64KB" 1333 select HAVE_PAGE_SIZE_64KB 1334 help 1335 This feature enables 64KB pages support (4KB by default) 1336 allowing only two levels of page tables and faster TLB 1337 look-up. AArch32 emulation requires applications compiled 1338 with 64K aligned segments. 1339 1340endchoice 1341 1342choice 1343 prompt "Virtual address space size" 1344 default ARM64_VA_BITS_52 1345 help 1346 Allows choosing one of multiple possible virtual address 1347 space sizes. The level of translation table is determined by 1348 a combination of page size and virtual address space size. 1349 1350config ARM64_VA_BITS_36 1351 bool "36-bit" if EXPERT 1352 depends on PAGE_SIZE_16KB 1353 1354config ARM64_VA_BITS_39 1355 bool "39-bit" 1356 depends on PAGE_SIZE_4KB 1357 1358config ARM64_VA_BITS_42 1359 bool "42-bit" 1360 depends on PAGE_SIZE_64KB 1361 1362config ARM64_VA_BITS_47 1363 bool "47-bit" 1364 depends on PAGE_SIZE_16KB 1365 1366config ARM64_VA_BITS_48 1367 bool "48-bit" 1368 1369config ARM64_VA_BITS_52 1370 bool "52-bit" 1371 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1372 help 1373 Enable 52-bit virtual addressing for userspace when explicitly 1374 requested via a hint to mmap(). The kernel will also use 52-bit 1375 virtual addresses for its own mappings (provided HW support for 1376 this feature is available, otherwise it reverts to 48-bit). 1377 1378 NOTE: Enabling 52-bit virtual addressing in conjunction with 1379 ARMv8.3 Pointer Authentication will result in the PAC being 1380 reduced from 7 bits to 3 bits, which may have a significant 1381 impact on its susceptibility to brute-force attacks. 1382 1383 If unsure, select 48-bit virtual addressing instead. 1384 1385endchoice 1386 1387config ARM64_FORCE_52BIT 1388 bool "Force 52-bit virtual addresses for userspace" 1389 depends on ARM64_VA_BITS_52 && EXPERT 1390 help 1391 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1392 to maintain compatibility with older software by providing 48-bit VAs 1393 unless a hint is supplied to mmap. 1394 1395 This configuration option disables the 48-bit compatibility logic, and 1396 forces all userspace addresses to be 52-bit on HW that supports it. One 1397 should only enable this configuration option for stress testing userspace 1398 memory management code. If unsure say N here. 1399 1400config ARM64_VA_BITS 1401 int 1402 default 36 if ARM64_VA_BITS_36 1403 default 39 if ARM64_VA_BITS_39 1404 default 42 if ARM64_VA_BITS_42 1405 default 47 if ARM64_VA_BITS_47 1406 default 48 if ARM64_VA_BITS_48 1407 default 52 if ARM64_VA_BITS_52 1408 1409choice 1410 prompt "Physical address space size" 1411 default ARM64_PA_BITS_48 1412 help 1413 Choose the maximum physical address range that the kernel will 1414 support. 1415 1416config ARM64_PA_BITS_48 1417 bool "48-bit" 1418 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1419 1420config ARM64_PA_BITS_52 1421 bool "52-bit" 1422 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1423 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1424 help 1425 Enable support for a 52-bit physical address space, introduced as 1426 part of the ARMv8.2-LPA extension. 1427 1428 With this enabled, the kernel will also continue to work on CPUs that 1429 do not support ARMv8.2-LPA, but with some added memory overhead (and 1430 minor performance overhead). 1431 1432endchoice 1433 1434config ARM64_PA_BITS 1435 int 1436 default 48 if ARM64_PA_BITS_48 1437 default 52 if ARM64_PA_BITS_52 1438 1439config ARM64_LPA2 1440 def_bool y 1441 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1442 1443choice 1444 prompt "Endianness" 1445 default CPU_LITTLE_ENDIAN 1446 help 1447 Select the endianness of data accesses performed by the CPU. Userspace 1448 applications will need to be compiled and linked for the endianness 1449 that is selected here. 1450 1451config CPU_BIG_ENDIAN 1452 bool "Build big-endian kernel" 1453 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1454 depends on AS_IS_GNU || AS_VERSION >= 150000 1455 help 1456 Say Y if you plan on running a kernel with a big-endian userspace. 1457 1458config CPU_LITTLE_ENDIAN 1459 bool "Build little-endian kernel" 1460 help 1461 Say Y if you plan on running a kernel with a little-endian userspace. 1462 This is usually the case for distributions targeting arm64. 1463 1464endchoice 1465 1466config SCHED_MC 1467 bool "Multi-core scheduler support" 1468 help 1469 Multi-core scheduler support improves the CPU scheduler's decision 1470 making when dealing with multi-core CPU chips at a cost of slightly 1471 increased overhead in some places. If unsure say N here. 1472 1473config SCHED_CLUSTER 1474 bool "Cluster scheduler support" 1475 help 1476 Cluster scheduler support improves the CPU scheduler's decision 1477 making when dealing with machines that have clusters of CPUs. 1478 Cluster usually means a couple of CPUs which are placed closely 1479 by sharing mid-level caches, last-level cache tags or internal 1480 busses. 1481 1482config SCHED_SMT 1483 bool "SMT scheduler support" 1484 help 1485 Improves the CPU scheduler's decision making when dealing with 1486 MultiThreading at a cost of slightly increased overhead in some 1487 places. If unsure say N here. 1488 1489config NR_CPUS 1490 int "Maximum number of CPUs (2-4096)" 1491 range 2 4096 1492 default "512" 1493 1494config HOTPLUG_CPU 1495 bool "Support for hot-pluggable CPUs" 1496 select GENERIC_IRQ_MIGRATION 1497 help 1498 Say Y here to experiment with turning CPUs off and on. CPUs 1499 can be controlled through /sys/devices/system/cpu. 1500 1501# Common NUMA Features 1502config NUMA 1503 bool "NUMA Memory Allocation and Scheduler Support" 1504 select GENERIC_ARCH_NUMA 1505 select OF_NUMA 1506 select HAVE_SETUP_PER_CPU_AREA 1507 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1508 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1509 select USE_PERCPU_NUMA_NODE_ID 1510 help 1511 Enable NUMA (Non-Uniform Memory Access) support. 1512 1513 The kernel will try to allocate memory used by a CPU on the 1514 local memory of the CPU and add some more 1515 NUMA awareness to the kernel. 1516 1517config NODES_SHIFT 1518 int "Maximum NUMA Nodes (as a power of 2)" 1519 range 1 10 1520 default "4" 1521 depends on NUMA 1522 help 1523 Specify the maximum number of NUMA Nodes available on the target 1524 system. Increases memory reserved to accommodate various tables. 1525 1526source "kernel/Kconfig.hz" 1527 1528config ARCH_SPARSEMEM_ENABLE 1529 def_bool y 1530 select SPARSEMEM_VMEMMAP_ENABLE 1531 select SPARSEMEM_VMEMMAP 1532 1533config HW_PERF_EVENTS 1534 def_bool y 1535 depends on ARM_PMU 1536 1537# Supported by clang >= 7.0 or GCC >= 12.0.0 1538config CC_HAVE_SHADOW_CALL_STACK 1539 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1540 1541config PARAVIRT 1542 bool "Enable paravirtualization code" 1543 help 1544 This changes the kernel so it can modify itself when it is run 1545 under a hypervisor, potentially improving performance significantly 1546 over full virtualization. 1547 1548config PARAVIRT_TIME_ACCOUNTING 1549 bool "Paravirtual steal time accounting" 1550 select PARAVIRT 1551 help 1552 Select this option to enable fine granularity task steal time 1553 accounting. Time spent executing other tasks in parallel with 1554 the current vCPU is discounted from the vCPU power. To account for 1555 that, there can be a small performance impact. 1556 1557 If in doubt, say N here. 1558 1559config ARCH_SUPPORTS_KEXEC 1560 def_bool PM_SLEEP_SMP 1561 1562config ARCH_SUPPORTS_KEXEC_FILE 1563 def_bool y 1564 1565config ARCH_SELECTS_KEXEC_FILE 1566 def_bool y 1567 depends on KEXEC_FILE 1568 select HAVE_IMA_KEXEC if IMA 1569 1570config ARCH_SUPPORTS_KEXEC_SIG 1571 def_bool y 1572 1573config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1574 def_bool y 1575 1576config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1577 def_bool y 1578 1579config ARCH_SUPPORTS_CRASH_DUMP 1580 def_bool y 1581 1582config ARCH_DEFAULT_CRASH_DUMP 1583 def_bool y 1584 1585config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1586 def_bool CRASH_RESERVE 1587 1588config TRANS_TABLE 1589 def_bool y 1590 depends on HIBERNATION || KEXEC_CORE 1591 1592config XEN_DOM0 1593 def_bool y 1594 depends on XEN 1595 1596config XEN 1597 bool "Xen guest support on ARM64" 1598 depends on ARM64 && OF 1599 select SWIOTLB_XEN 1600 select PARAVIRT 1601 help 1602 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1603 1604# include/linux/mmzone.h requires the following to be true: 1605# 1606# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1607# 1608# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1609# 1610# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1611# ----+-------------------+--------------+----------------------+-------------------------+ 1612# 4K | 27 | 12 | 15 | 10 | 1613# 16K | 27 | 14 | 13 | 11 | 1614# 64K | 29 | 16 | 13 | 13 | 1615config ARCH_FORCE_MAX_ORDER 1616 int 1617 default "13" if ARM64_64K_PAGES 1618 default "11" if ARM64_16K_PAGES 1619 default "10" 1620 help 1621 The kernel page allocator limits the size of maximal physically 1622 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1623 defines the maximal power of two of number of pages that can be 1624 allocated as a single contiguous block. This option allows 1625 overriding the default setting when ability to allocate very 1626 large blocks of physically contiguous memory is required. 1627 1628 The maximal size of allocation cannot exceed the size of the 1629 section, so the value of MAX_PAGE_ORDER should satisfy 1630 1631 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1632 1633 Don't change if unsure. 1634 1635config UNMAP_KERNEL_AT_EL0 1636 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1637 default y 1638 help 1639 Speculation attacks against some high-performance processors can 1640 be used to bypass MMU permission checks and leak kernel data to 1641 userspace. This can be defended against by unmapping the kernel 1642 when running in userspace, mapping it back in on exception entry 1643 via a trampoline page in the vector table. 1644 1645 If unsure, say Y. 1646 1647config MITIGATE_SPECTRE_BRANCH_HISTORY 1648 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1649 default y 1650 help 1651 Speculation attacks against some high-performance processors can 1652 make use of branch history to influence future speculation. 1653 When taking an exception from user-space, a sequence of branches 1654 or a firmware call overwrites the branch history. 1655 1656config RODATA_FULL_DEFAULT_ENABLED 1657 bool "Apply r/o permissions of VM areas also to their linear aliases" 1658 default y 1659 help 1660 Apply read-only attributes of VM areas to the linear alias of 1661 the backing pages as well. This prevents code or read-only data 1662 from being modified (inadvertently or intentionally) via another 1663 mapping of the same memory page. This additional enhancement can 1664 be turned off at runtime by passing rodata=[off|on] (and turned on 1665 with rodata=full if this option is set to 'n') 1666 1667 This requires the linear region to be mapped down to pages, 1668 which may adversely affect performance in some cases. 1669 1670config ARM64_SW_TTBR0_PAN 1671 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1672 depends on !KCSAN 1673 help 1674 Enabling this option prevents the kernel from accessing 1675 user-space memory directly by pointing TTBR0_EL1 to a reserved 1676 zeroed area and reserved ASID. The user access routines 1677 restore the valid TTBR0_EL1 temporarily. 1678 1679config ARM64_TAGGED_ADDR_ABI 1680 bool "Enable the tagged user addresses syscall ABI" 1681 default y 1682 help 1683 When this option is enabled, user applications can opt in to a 1684 relaxed ABI via prctl() allowing tagged addresses to be passed 1685 to system calls as pointer arguments. For details, see 1686 Documentation/arch/arm64/tagged-address-abi.rst. 1687 1688menuconfig COMPAT 1689 bool "Kernel support for 32-bit EL0" 1690 depends on ARM64_4K_PAGES || EXPERT 1691 select HAVE_UID16 1692 select OLD_SIGSUSPEND3 1693 select COMPAT_OLD_SIGACTION 1694 help 1695 This option enables support for a 32-bit EL0 running under a 64-bit 1696 kernel at EL1. AArch32-specific components such as system calls, 1697 the user helper functions, VFP support and the ptrace interface are 1698 handled appropriately by the kernel. 1699 1700 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1701 that you will only be able to execute AArch32 binaries that were compiled 1702 with page size aligned segments. 1703 1704 If you want to execute 32-bit userspace applications, say Y. 1705 1706if COMPAT 1707 1708config KUSER_HELPERS 1709 bool "Enable kuser helpers page for 32-bit applications" 1710 default y 1711 help 1712 Warning: disabling this option may break 32-bit user programs. 1713 1714 Provide kuser helpers to compat tasks. The kernel provides 1715 helper code to userspace in read only form at a fixed location 1716 to allow userspace to be independent of the CPU type fitted to 1717 the system. This permits binaries to be run on ARMv4 through 1718 to ARMv8 without modification. 1719 1720 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1721 1722 However, the fixed address nature of these helpers can be used 1723 by ROP (return orientated programming) authors when creating 1724 exploits. 1725 1726 If all of the binaries and libraries which run on your platform 1727 are built specifically for your platform, and make no use of 1728 these helpers, then you can turn this option off to hinder 1729 such exploits. However, in that case, if a binary or library 1730 relying on those helpers is run, it will not function correctly. 1731 1732 Say N here only if you are absolutely certain that you do not 1733 need these helpers; otherwise, the safe option is to say Y. 1734 1735config COMPAT_VDSO 1736 bool "Enable vDSO for 32-bit applications" 1737 depends on !CPU_BIG_ENDIAN 1738 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1739 select GENERIC_COMPAT_VDSO 1740 default y 1741 help 1742 Place in the process address space of 32-bit applications an 1743 ELF shared object providing fast implementations of gettimeofday 1744 and clock_gettime. 1745 1746 You must have a 32-bit build of glibc 2.22 or later for programs 1747 to seamlessly take advantage of this. 1748 1749config THUMB2_COMPAT_VDSO 1750 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1751 depends on COMPAT_VDSO 1752 default y 1753 help 1754 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1755 otherwise with '-marm'. 1756 1757config COMPAT_ALIGNMENT_FIXUPS 1758 bool "Fix up misaligned multi-word loads and stores in user space" 1759 1760menuconfig ARMV8_DEPRECATED 1761 bool "Emulate deprecated/obsolete ARMv8 instructions" 1762 depends on SYSCTL 1763 help 1764 Legacy software support may require certain instructions 1765 that have been deprecated or obsoleted in the architecture. 1766 1767 Enable this config to enable selective emulation of these 1768 features. 1769 1770 If unsure, say Y 1771 1772if ARMV8_DEPRECATED 1773 1774config SWP_EMULATION 1775 bool "Emulate SWP/SWPB instructions" 1776 help 1777 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1778 they are always undefined. Say Y here to enable software 1779 emulation of these instructions for userspace using LDXR/STXR. 1780 This feature can be controlled at runtime with the abi.swp 1781 sysctl which is disabled by default. 1782 1783 In some older versions of glibc [<=2.8] SWP is used during futex 1784 trylock() operations with the assumption that the code will not 1785 be preempted. This invalid assumption may be more likely to fail 1786 with SWP emulation enabled, leading to deadlock of the user 1787 application. 1788 1789 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1790 on an external transaction monitoring block called a global 1791 monitor to maintain update atomicity. If your system does not 1792 implement a global monitor, this option can cause programs that 1793 perform SWP operations to uncached memory to deadlock. 1794 1795 If unsure, say Y 1796 1797config CP15_BARRIER_EMULATION 1798 bool "Emulate CP15 Barrier instructions" 1799 help 1800 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1801 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1802 strongly recommended to use the ISB, DSB, and DMB 1803 instructions instead. 1804 1805 Say Y here to enable software emulation of these 1806 instructions for AArch32 userspace code. When this option is 1807 enabled, CP15 barrier usage is traced which can help 1808 identify software that needs updating. This feature can be 1809 controlled at runtime with the abi.cp15_barrier sysctl. 1810 1811 If unsure, say Y 1812 1813config SETEND_EMULATION 1814 bool "Emulate SETEND instruction" 1815 help 1816 The SETEND instruction alters the data-endianness of the 1817 AArch32 EL0, and is deprecated in ARMv8. 1818 1819 Say Y here to enable software emulation of the instruction 1820 for AArch32 userspace code. This feature can be controlled 1821 at runtime with the abi.setend sysctl. 1822 1823 Note: All the cpus on the system must have mixed endian support at EL0 1824 for this feature to be enabled. If a new CPU - which doesn't support mixed 1825 endian - is hotplugged in after this feature has been enabled, there could 1826 be unexpected results in the applications. 1827 1828 If unsure, say Y 1829endif # ARMV8_DEPRECATED 1830 1831endif # COMPAT 1832 1833menu "ARMv8.1 architectural features" 1834 1835config ARM64_HW_AFDBM 1836 bool "Support for hardware updates of the Access and Dirty page flags" 1837 default y 1838 help 1839 The ARMv8.1 architecture extensions introduce support for 1840 hardware updates of the access and dirty information in page 1841 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1842 capable processors, accesses to pages with PTE_AF cleared will 1843 set this bit instead of raising an access flag fault. 1844 Similarly, writes to read-only pages with the DBM bit set will 1845 clear the read-only bit (AP[2]) instead of raising a 1846 permission fault. 1847 1848 Kernels built with this configuration option enabled continue 1849 to work on pre-ARMv8.1 hardware and the performance impact is 1850 minimal. If unsure, say Y. 1851 1852config ARM64_PAN 1853 bool "Enable support for Privileged Access Never (PAN)" 1854 default y 1855 help 1856 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1857 prevents the kernel or hypervisor from accessing user-space (EL0) 1858 memory directly. 1859 1860 Choosing this option will cause any unprotected (not using 1861 copy_to_user et al) memory access to fail with a permission fault. 1862 1863 The feature is detected at runtime, and will remain as a 'nop' 1864 instruction if the cpu does not implement the feature. 1865 1866config AS_HAS_LSE_ATOMICS 1867 def_bool $(as-instr,.arch_extension lse) 1868 1869config ARM64_LSE_ATOMICS 1870 bool 1871 default ARM64_USE_LSE_ATOMICS 1872 depends on AS_HAS_LSE_ATOMICS 1873 1874config ARM64_USE_LSE_ATOMICS 1875 bool "Atomic instructions" 1876 default y 1877 help 1878 As part of the Large System Extensions, ARMv8.1 introduces new 1879 atomic instructions that are designed specifically to scale in 1880 very large systems. 1881 1882 Say Y here to make use of these instructions for the in-kernel 1883 atomic routines. This incurs a small overhead on CPUs that do 1884 not support these instructions and requires the kernel to be 1885 built with binutils >= 2.25 in order for the new instructions 1886 to be used. 1887 1888endmenu # "ARMv8.1 architectural features" 1889 1890menu "ARMv8.2 architectural features" 1891 1892config AS_HAS_ARMV8_2 1893 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1894 1895config AS_HAS_SHA3 1896 def_bool $(as-instr,.arch armv8.2-a+sha3) 1897 1898config ARM64_PMEM 1899 bool "Enable support for persistent memory" 1900 select ARCH_HAS_PMEM_API 1901 select ARCH_HAS_UACCESS_FLUSHCACHE 1902 help 1903 Say Y to enable support for the persistent memory API based on the 1904 ARMv8.2 DCPoP feature. 1905 1906 The feature is detected at runtime, and the kernel will use DC CVAC 1907 operations if DC CVAP is not supported (following the behaviour of 1908 DC CVAP itself if the system does not define a point of persistence). 1909 1910config ARM64_RAS_EXTN 1911 bool "Enable support for RAS CPU Extensions" 1912 default y 1913 help 1914 CPUs that support the Reliability, Availability and Serviceability 1915 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1916 errors, classify them and report them to software. 1917 1918 On CPUs with these extensions system software can use additional 1919 barriers to determine if faults are pending and read the 1920 classification from a new set of registers. 1921 1922 Selecting this feature will allow the kernel to use these barriers 1923 and access the new registers if the system supports the extension. 1924 Platform RAS features may additionally depend on firmware support. 1925 1926config ARM64_CNP 1927 bool "Enable support for Common Not Private (CNP) translations" 1928 default y 1929 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1930 help 1931 Common Not Private (CNP) allows translation table entries to 1932 be shared between different PEs in the same inner shareable 1933 domain, so the hardware can use this fact to optimise the 1934 caching of such entries in the TLB. 1935 1936 Selecting this option allows the CNP feature to be detected 1937 at runtime, and does not affect PEs that do not implement 1938 this feature. 1939 1940endmenu # "ARMv8.2 architectural features" 1941 1942menu "ARMv8.3 architectural features" 1943 1944config ARM64_PTR_AUTH 1945 bool "Enable support for pointer authentication" 1946 default y 1947 help 1948 Pointer authentication (part of the ARMv8.3 Extensions) provides 1949 instructions for signing and authenticating pointers against secret 1950 keys, which can be used to mitigate Return Oriented Programming (ROP) 1951 and other attacks. 1952 1953 This option enables these instructions at EL0 (i.e. for userspace). 1954 Choosing this option will cause the kernel to initialise secret keys 1955 for each process at exec() time, with these keys being 1956 context-switched along with the process. 1957 1958 The feature is detected at runtime. If the feature is not present in 1959 hardware it will not be advertised to userspace/KVM guest nor will it 1960 be enabled. 1961 1962 If the feature is present on the boot CPU but not on a late CPU, then 1963 the late CPU will be parked. Also, if the boot CPU does not have 1964 address auth and the late CPU has then the late CPU will still boot 1965 but with the feature disabled. On such a system, this option should 1966 not be selected. 1967 1968config ARM64_PTR_AUTH_KERNEL 1969 bool "Use pointer authentication for kernel" 1970 default y 1971 depends on ARM64_PTR_AUTH 1972 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1973 # Modern compilers insert a .note.gnu.property section note for PAC 1974 # which is only understood by binutils starting with version 2.33.1. 1975 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1976 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1977 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1978 help 1979 If the compiler supports the -mbranch-protection or 1980 -msign-return-address flag (e.g. GCC 7 or later), then this option 1981 will cause the kernel itself to be compiled with return address 1982 protection. In this case, and if the target hardware is known to 1983 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1984 disabled with minimal loss of protection. 1985 1986 This feature works with FUNCTION_GRAPH_TRACER option only if 1987 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1988 1989config CC_HAS_BRANCH_PROT_PAC_RET 1990 # GCC 9 or later, clang 8 or later 1991 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1992 1993config CC_HAS_SIGN_RETURN_ADDRESS 1994 # GCC 7, 8 1995 def_bool $(cc-option,-msign-return-address=all) 1996 1997config AS_HAS_ARMV8_3 1998 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1999 2000config AS_HAS_CFI_NEGATE_RA_STATE 2001 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2002 2003config AS_HAS_LDAPR 2004 def_bool $(as-instr,.arch_extension rcpc) 2005 2006endmenu # "ARMv8.3 architectural features" 2007 2008menu "ARMv8.4 architectural features" 2009 2010config ARM64_AMU_EXTN 2011 bool "Enable support for the Activity Monitors Unit CPU extension" 2012 default y 2013 help 2014 The activity monitors extension is an optional extension introduced 2015 by the ARMv8.4 CPU architecture. This enables support for version 1 2016 of the activity monitors architecture, AMUv1. 2017 2018 To enable the use of this extension on CPUs that implement it, say Y. 2019 2020 Note that for architectural reasons, firmware _must_ implement AMU 2021 support when running on CPUs that present the activity monitors 2022 extension. The required support is present in: 2023 * Version 1.5 and later of the ARM Trusted Firmware 2024 2025 For kernels that have this configuration enabled but boot with broken 2026 firmware, you may need to say N here until the firmware is fixed. 2027 Otherwise you may experience firmware panics or lockups when 2028 accessing the counter registers. Even if you are not observing these 2029 symptoms, the values returned by the register reads might not 2030 correctly reflect reality. Most commonly, the value read will be 0, 2031 indicating that the counter is not enabled. 2032 2033config AS_HAS_ARMV8_4 2034 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2035 2036config ARM64_TLB_RANGE 2037 bool "Enable support for tlbi range feature" 2038 default y 2039 depends on AS_HAS_ARMV8_4 2040 help 2041 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2042 range of input addresses. 2043 2044 The feature introduces new assembly instructions, and they were 2045 support when binutils >= 2.30. 2046 2047endmenu # "ARMv8.4 architectural features" 2048 2049menu "ARMv8.5 architectural features" 2050 2051config AS_HAS_ARMV8_5 2052 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2053 2054config ARM64_BTI 2055 bool "Branch Target Identification support" 2056 default y 2057 help 2058 Branch Target Identification (part of the ARMv8.5 Extensions) 2059 provides a mechanism to limit the set of locations to which computed 2060 branch instructions such as BR or BLR can jump. 2061 2062 To make use of BTI on CPUs that support it, say Y. 2063 2064 BTI is intended to provide complementary protection to other control 2065 flow integrity protection mechanisms, such as the Pointer 2066 authentication mechanism provided as part of the ARMv8.3 Extensions. 2067 For this reason, it does not make sense to enable this option without 2068 also enabling support for pointer authentication. Thus, when 2069 enabling this option you should also select ARM64_PTR_AUTH=y. 2070 2071 Userspace binaries must also be specifically compiled to make use of 2072 this mechanism. If you say N here or the hardware does not support 2073 BTI, such binaries can still run, but you get no additional 2074 enforcement of branch destinations. 2075 2076config ARM64_BTI_KERNEL 2077 bool "Use Branch Target Identification for kernel" 2078 default y 2079 depends on ARM64_BTI 2080 depends on ARM64_PTR_AUTH_KERNEL 2081 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2082 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2083 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2084 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2085 depends on !CC_IS_GCC 2086 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2087 help 2088 Build the kernel with Branch Target Identification annotations 2089 and enable enforcement of this for kernel code. When this option 2090 is enabled and the system supports BTI all kernel code including 2091 modular code must have BTI enabled. 2092 2093config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2094 # GCC 9 or later, clang 8 or later 2095 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2096 2097config ARM64_E0PD 2098 bool "Enable support for E0PD" 2099 default y 2100 help 2101 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2102 that EL0 accesses made via TTBR1 always fault in constant time, 2103 providing similar benefits to KASLR as those provided by KPTI, but 2104 with lower overhead and without disrupting legitimate access to 2105 kernel memory such as SPE. 2106 2107 This option enables E0PD for TTBR1 where available. 2108 2109config ARM64_AS_HAS_MTE 2110 # Initial support for MTE went in binutils 2.32.0, checked with 2111 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2112 # as a late addition to the final architecture spec (LDGM/STGM) 2113 # is only supported in the newer 2.32.x and 2.33 binutils 2114 # versions, hence the extra "stgm" instruction check below. 2115 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2116 2117config ARM64_MTE 2118 bool "Memory Tagging Extension support" 2119 default y 2120 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2121 depends on AS_HAS_ARMV8_5 2122 depends on AS_HAS_LSE_ATOMICS 2123 # Required for tag checking in the uaccess routines 2124 depends on ARM64_PAN 2125 select ARCH_HAS_SUBPAGE_FAULTS 2126 select ARCH_USES_HIGH_VMA_FLAGS 2127 select ARCH_USES_PG_ARCH_2 2128 select ARCH_USES_PG_ARCH_3 2129 help 2130 Memory Tagging (part of the ARMv8.5 Extensions) provides 2131 architectural support for run-time, always-on detection of 2132 various classes of memory error to aid with software debugging 2133 to eliminate vulnerabilities arising from memory-unsafe 2134 languages. 2135 2136 This option enables the support for the Memory Tagging 2137 Extension at EL0 (i.e. for userspace). 2138 2139 Selecting this option allows the feature to be detected at 2140 runtime. Any secondary CPU not implementing this feature will 2141 not be allowed a late bring-up. 2142 2143 Userspace binaries that want to use this feature must 2144 explicitly opt in. The mechanism for the userspace is 2145 described in: 2146 2147 Documentation/arch/arm64/memory-tagging-extension.rst. 2148 2149endmenu # "ARMv8.5 architectural features" 2150 2151menu "ARMv8.7 architectural features" 2152 2153config ARM64_EPAN 2154 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2155 default y 2156 depends on ARM64_PAN 2157 help 2158 Enhanced Privileged Access Never (EPAN) allows Privileged 2159 Access Never to be used with Execute-only mappings. 2160 2161 The feature is detected at runtime, and will remain disabled 2162 if the cpu does not implement the feature. 2163endmenu # "ARMv8.7 architectural features" 2164 2165config AS_HAS_MOPS 2166 def_bool $(as-instr,.arch_extension mops) 2167 2168menu "ARMv8.9 architectural features" 2169 2170config ARM64_POE 2171 prompt "Permission Overlay Extension" 2172 def_bool y 2173 select ARCH_USES_HIGH_VMA_FLAGS 2174 select ARCH_HAS_PKEYS 2175 help 2176 The Permission Overlay Extension is used to implement Memory 2177 Protection Keys. Memory Protection Keys provides a mechanism for 2178 enforcing page-based protections, but without requiring modification 2179 of the page tables when an application changes protection domains. 2180 2181 For details, see Documentation/core-api/protection-keys.rst 2182 2183 If unsure, say y. 2184 2185config ARCH_PKEY_BITS 2186 int 2187 default 3 2188 2189config ARM64_HAFT 2190 bool "Support for Hardware managed Access Flag for Table Descriptors" 2191 depends on ARM64_HW_AFDBM 2192 default y 2193 help 2194 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2195 Flag for Table descriptors. When enabled an architectural executed 2196 memory access will update the Access Flag in each Table descriptor 2197 which is accessed during the translation table walk and for which 2198 the Access Flag is 0. The Access Flag of the Table descriptor use 2199 the same bit of PTE_AF. 2200 2201 The feature will only be enabled if all the CPUs in the system 2202 support this feature. If unsure, say Y. 2203 2204endmenu # "ARMv8.9 architectural features" 2205 2206menu "v9.4 architectural features" 2207 2208config ARM64_GCS 2209 bool "Enable support for Guarded Control Stack (GCS)" 2210 default y 2211 select ARCH_HAS_USER_SHADOW_STACK 2212 select ARCH_USES_HIGH_VMA_FLAGS 2213 depends on !UPROBES 2214 help 2215 Guarded Control Stack (GCS) provides support for a separate 2216 stack with restricted access which contains only return 2217 addresses. This can be used to harden against some attacks 2218 by comparing return address used by the program with what is 2219 stored in the GCS, and may also be used to efficiently obtain 2220 the call stack for applications such as profiling. 2221 2222 The feature is detected at runtime, and will remain disabled 2223 if the system does not implement the feature. 2224 2225endmenu # "v9.4 architectural features" 2226 2227config ARM64_SVE 2228 bool "ARM Scalable Vector Extension support" 2229 default y 2230 help 2231 The Scalable Vector Extension (SVE) is an extension to the AArch64 2232 execution state which complements and extends the SIMD functionality 2233 of the base architecture to support much larger vectors and to enable 2234 additional vectorisation opportunities. 2235 2236 To enable use of this extension on CPUs that implement it, say Y. 2237 2238 On CPUs that support the SVE2 extensions, this option will enable 2239 those too. 2240 2241 Note that for architectural reasons, firmware _must_ implement SVE 2242 support when running on SVE capable hardware. The required support 2243 is present in: 2244 2245 * version 1.5 and later of the ARM Trusted Firmware 2246 * the AArch64 boot wrapper since commit 5e1261e08abf 2247 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2248 2249 For other firmware implementations, consult the firmware documentation 2250 or vendor. 2251 2252 If you need the kernel to boot on SVE-capable hardware with broken 2253 firmware, you may need to say N here until you get your firmware 2254 fixed. Otherwise, you may experience firmware panics or lockups when 2255 booting the kernel. If unsure and you are not observing these 2256 symptoms, you should assume that it is safe to say Y. 2257 2258config ARM64_SME 2259 bool "ARM Scalable Matrix Extension support" 2260 default y 2261 depends on ARM64_SVE 2262 depends on BROKEN 2263 help 2264 The Scalable Matrix Extension (SME) is an extension to the AArch64 2265 execution state which utilises a substantial subset of the SVE 2266 instruction set, together with the addition of new architectural 2267 register state capable of holding two dimensional matrix tiles to 2268 enable various matrix operations. 2269 2270config ARM64_PSEUDO_NMI 2271 bool "Support for NMI-like interrupts" 2272 select ARM_GIC_V3 2273 help 2274 Adds support for mimicking Non-Maskable Interrupts through the use of 2275 GIC interrupt priority. This support requires version 3 or later of 2276 ARM GIC. 2277 2278 This high priority configuration for interrupts needs to be 2279 explicitly enabled by setting the kernel parameter 2280 "irqchip.gicv3_pseudo_nmi" to 1. 2281 2282 If unsure, say N 2283 2284if ARM64_PSEUDO_NMI 2285config ARM64_DEBUG_PRIORITY_MASKING 2286 bool "Debug interrupt priority masking" 2287 help 2288 This adds runtime checks to functions enabling/disabling 2289 interrupts when using priority masking. The additional checks verify 2290 the validity of ICC_PMR_EL1 when calling concerned functions. 2291 2292 If unsure, say N 2293endif # ARM64_PSEUDO_NMI 2294 2295config RELOCATABLE 2296 bool "Build a relocatable kernel image" if EXPERT 2297 select ARCH_HAS_RELR 2298 default y 2299 help 2300 This builds the kernel as a Position Independent Executable (PIE), 2301 which retains all relocation metadata required to relocate the 2302 kernel binary at runtime to a different virtual address than the 2303 address it was linked at. 2304 Since AArch64 uses the RELA relocation format, this requires a 2305 relocation pass at runtime even if the kernel is loaded at the 2306 same address it was linked at. 2307 2308config RANDOMIZE_BASE 2309 bool "Randomize the address of the kernel image" 2310 select RELOCATABLE 2311 help 2312 Randomizes the virtual address at which the kernel image is 2313 loaded, as a security feature that deters exploit attempts 2314 relying on knowledge of the location of kernel internals. 2315 2316 It is the bootloader's job to provide entropy, by passing a 2317 random u64 value in /chosen/kaslr-seed at kernel entry. 2318 2319 When booting via the UEFI stub, it will invoke the firmware's 2320 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2321 to the kernel proper. In addition, it will randomise the physical 2322 location of the kernel Image as well. 2323 2324 If unsure, say N. 2325 2326config RANDOMIZE_MODULE_REGION_FULL 2327 bool "Randomize the module region over a 2 GB range" 2328 depends on RANDOMIZE_BASE 2329 default y 2330 help 2331 Randomizes the location of the module region inside a 2 GB window 2332 covering the core kernel. This way, it is less likely for modules 2333 to leak information about the location of core kernel data structures 2334 but it does imply that function calls between modules and the core 2335 kernel will need to be resolved via veneers in the module PLT. 2336 2337 When this option is not set, the module region will be randomized over 2338 a limited range that contains the [_stext, _etext] interval of the 2339 core kernel, so branch relocations are almost always in range unless 2340 the region is exhausted. In this particular case of region 2341 exhaustion, modules might be able to fall back to a larger 2GB area. 2342 2343config CC_HAVE_STACKPROTECTOR_SYSREG 2344 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2345 2346config STACKPROTECTOR_PER_TASK 2347 def_bool y 2348 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2349 2350config UNWIND_PATCH_PAC_INTO_SCS 2351 bool "Enable shadow call stack dynamically using code patching" 2352 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2353 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2354 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2355 depends on SHADOW_CALL_STACK 2356 select UNWIND_TABLES 2357 select DYNAMIC_SCS 2358 2359config ARM64_CONTPTE 2360 bool "Contiguous PTE mappings for user memory" if EXPERT 2361 depends on TRANSPARENT_HUGEPAGE 2362 default y 2363 help 2364 When enabled, user mappings are configured using the PTE contiguous 2365 bit, for any mappings that meet the size and alignment requirements. 2366 This reduces TLB pressure and improves performance. 2367 2368endmenu # "Kernel Features" 2369 2370menu "Boot options" 2371 2372config ARM64_ACPI_PARKING_PROTOCOL 2373 bool "Enable support for the ARM64 ACPI parking protocol" 2374 depends on ACPI 2375 help 2376 Enable support for the ARM64 ACPI parking protocol. If disabled 2377 the kernel will not allow booting through the ARM64 ACPI parking 2378 protocol even if the corresponding data is present in the ACPI 2379 MADT table. 2380 2381config CMDLINE 2382 string "Default kernel command string" 2383 default "" 2384 help 2385 Provide a set of default command-line options at build time by 2386 entering them here. As a minimum, you should specify the the 2387 root device (e.g. root=/dev/nfs). 2388 2389choice 2390 prompt "Kernel command line type" 2391 depends on CMDLINE != "" 2392 default CMDLINE_FROM_BOOTLOADER 2393 help 2394 Choose how the kernel will handle the provided default kernel 2395 command line string. 2396 2397config CMDLINE_FROM_BOOTLOADER 2398 bool "Use bootloader kernel arguments if available" 2399 help 2400 Uses the command-line options passed by the boot loader. If 2401 the boot loader doesn't provide any, the default kernel command 2402 string provided in CMDLINE will be used. 2403 2404config CMDLINE_FORCE 2405 bool "Always use the default kernel command string" 2406 help 2407 Always use the default kernel command string, even if the boot 2408 loader passes other arguments to the kernel. 2409 This is useful if you cannot or don't want to change the 2410 command-line options your boot loader passes to the kernel. 2411 2412endchoice 2413 2414config EFI_STUB 2415 bool 2416 2417config EFI 2418 bool "UEFI runtime support" 2419 depends on OF && !CPU_BIG_ENDIAN 2420 depends on KERNEL_MODE_NEON 2421 select ARCH_SUPPORTS_ACPI 2422 select LIBFDT 2423 select UCS2_STRING 2424 select EFI_PARAMS_FROM_FDT 2425 select EFI_RUNTIME_WRAPPERS 2426 select EFI_STUB 2427 select EFI_GENERIC_STUB 2428 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2429 default y 2430 help 2431 This option provides support for runtime services provided 2432 by UEFI firmware (such as non-volatile variables, realtime 2433 clock, and platform reset). A UEFI stub is also provided to 2434 allow the kernel to be booted as an EFI application. This 2435 is only useful on systems that have UEFI firmware. 2436 2437config COMPRESSED_INSTALL 2438 bool "Install compressed image by default" 2439 help 2440 This makes the regular "make install" install the compressed 2441 image we built, not the legacy uncompressed one. 2442 2443 You can check that a compressed image works for you by doing 2444 "make zinstall" first, and verifying that everything is fine 2445 in your environment before making "make install" do this for 2446 you. 2447 2448config DMI 2449 bool "Enable support for SMBIOS (DMI) tables" 2450 depends on EFI 2451 default y 2452 help 2453 This enables SMBIOS/DMI feature for systems. 2454 2455 This option is only useful on systems that have UEFI firmware. 2456 However, even with this option, the resultant kernel should 2457 continue to boot on existing non-UEFI platforms. 2458 2459endmenu # "Boot options" 2460 2461menu "Power management options" 2462 2463source "kernel/power/Kconfig" 2464 2465config ARCH_HIBERNATION_POSSIBLE 2466 def_bool y 2467 depends on CPU_PM 2468 2469config ARCH_HIBERNATION_HEADER 2470 def_bool y 2471 depends on HIBERNATION 2472 2473config ARCH_SUSPEND_POSSIBLE 2474 def_bool y 2475 2476endmenu # "Power management options" 2477 2478menu "CPU Power Management" 2479 2480source "drivers/cpuidle/Kconfig" 2481 2482source "drivers/cpufreq/Kconfig" 2483 2484endmenu # "CPU Power Management" 2485 2486source "drivers/acpi/Kconfig" 2487 2488source "arch/arm64/kvm/Kconfig" 2489 2490