1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_IORT if ACPI 9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 10 select ACPI_MCFG if (ACPI && PCI) 11 select ACPI_SPCR_TABLE if ACPI 12 select ACPI_PPTT if ACPI 13 select ARCH_HAS_DEBUG_WX 14 select ARCH_BINFMT_ELF_EXTRA_PHDRS 15 select ARCH_BINFMT_ELF_STATE 16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CURRENT_STACK_POINTER 24 select ARCH_HAS_DEBUG_VIRTUAL 25 select ARCH_HAS_DEBUG_VM_PGTABLE 26 select ARCH_HAS_DMA_PREP_COHERENT 27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 28 select ARCH_HAS_FAST_MULTIPLIER 29 select ARCH_HAS_FORTIFY_SOURCE 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_HAS_GIGANTIC_PAGE 32 select ARCH_HAS_KCOV 33 select ARCH_HAS_KEEPINITRD 34 select ARCH_HAS_MEMBARRIER_SYNC_CORE 35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 37 select ARCH_HAS_PTE_DEVMAP 38 select ARCH_HAS_PTE_SPECIAL 39 select ARCH_HAS_SETUP_DMA_OPS 40 select ARCH_HAS_SET_DIRECT_MAP 41 select ARCH_HAS_SET_MEMORY 42 select ARCH_STACKWALK 43 select ARCH_HAS_STRICT_KERNEL_RWX 44 select ARCH_HAS_STRICT_MODULE_RWX 45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 46 select ARCH_HAS_SYNC_DMA_FOR_CPU 47 select ARCH_HAS_SYSCALL_WRAPPER 48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 50 select ARCH_HAS_ZONE_DMA_SET if EXPERT 51 select ARCH_HAVE_ELF_PROT 52 select ARCH_HAVE_NMI_SAFE_CMPXCHG 53 select ARCH_HAVE_TRACE_MMIO_ACCESS 54 select ARCH_INLINE_READ_LOCK if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 80 select ARCH_KEEP_MEMBLOCK 81 select ARCH_USE_CMPXCHG_LOCKREF 82 select ARCH_USE_GNU_PROPERTY 83 select ARCH_USE_MEMTEST 84 select ARCH_USE_QUEUED_RWLOCKS 85 select ARCH_USE_QUEUED_SPINLOCKS 86 select ARCH_USE_SYM_ANNOTATIONS 87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 88 select ARCH_SUPPORTS_HUGETLBFS 89 select ARCH_SUPPORTS_MEMORY_FAILURE 90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 92 select ARCH_SUPPORTS_LTO_CLANG_THIN 93 select ARCH_SUPPORTS_CFI_CLANG 94 select ARCH_SUPPORTS_ATOMIC_RMW 95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 96 select ARCH_SUPPORTS_NUMA_BALANCING 97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 98 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 99 select ARCH_WANT_DEFAULT_BPF_JIT 100 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 101 select ARCH_WANT_FRAME_POINTERS 102 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 103 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP 104 select ARCH_WANT_LD_ORPHAN_WARN 105 select ARCH_WANTS_NO_INSTR 106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 107 select ARCH_HAS_UBSAN_SANITIZE_ALL 108 select ARM_AMBA 109 select ARM_ARCH_TIMER 110 select ARM_GIC 111 select AUDIT_ARCH_COMPAT_GENERIC 112 select ARM_GIC_V2M if PCI 113 select ARM_GIC_V3 114 select ARM_GIC_V3_ITS if PCI 115 select ARM_PSCI_FW 116 select BUILDTIME_TABLE_SORT 117 select CLONE_BACKWARDS 118 select COMMON_CLK 119 select CPU_PM if (SUSPEND || CPU_IDLE) 120 select CRC32 121 select DCACHE_WORD_ACCESS 122 select DYNAMIC_FTRACE if FUNCTION_TRACER 123 select DMA_DIRECT_REMAP 124 select EDAC_SUPPORT 125 select FRAME_POINTER 126 select GENERIC_ALLOCATOR 127 select GENERIC_ARCH_TOPOLOGY 128 select GENERIC_CLOCKEVENTS_BROADCAST 129 select GENERIC_CPU_AUTOPROBE 130 select GENERIC_CPU_VULNERABILITIES 131 select GENERIC_EARLY_IOREMAP 132 select GENERIC_IDLE_POLL_SETUP 133 select GENERIC_IOREMAP 134 select GENERIC_IRQ_IPI 135 select GENERIC_IRQ_PROBE 136 select GENERIC_IRQ_SHOW 137 select GENERIC_IRQ_SHOW_LEVEL 138 select GENERIC_LIB_DEVMEM_IS_ALLOWED 139 select GENERIC_PCI_IOMAP 140 select GENERIC_PTDUMP 141 select GENERIC_SCHED_CLOCK 142 select GENERIC_SMP_IDLE_THREAD 143 select GENERIC_TIME_VSYSCALL 144 select GENERIC_GETTIMEOFDAY 145 select GENERIC_VDSO_TIME_NS 146 select HARDIRQS_SW_RESEND 147 select HAVE_MOVE_PMD 148 select HAVE_MOVE_PUD 149 select HAVE_PCI 150 select HAVE_ACPI_APEI if (ACPI && EFI) 151 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 152 select HAVE_ARCH_AUDITSYSCALL 153 select HAVE_ARCH_BITREVERSE 154 select HAVE_ARCH_COMPILER_H 155 select HAVE_ARCH_HUGE_VMALLOC 156 select HAVE_ARCH_HUGE_VMAP 157 select HAVE_ARCH_JUMP_LABEL 158 select HAVE_ARCH_JUMP_LABEL_RELATIVE 159 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 160 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 161 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 162 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 163 # Some instrumentation may be unsound, hence EXPERT 164 select HAVE_ARCH_KCSAN if EXPERT 165 select HAVE_ARCH_KFENCE 166 select HAVE_ARCH_KGDB 167 select HAVE_ARCH_MMAP_RND_BITS 168 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 169 select HAVE_ARCH_PREL32_RELOCATIONS 170 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 171 select HAVE_ARCH_SECCOMP_FILTER 172 select HAVE_ARCH_STACKLEAK 173 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 174 select HAVE_ARCH_TRACEHOOK 175 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 176 select HAVE_ARCH_VMAP_STACK 177 select HAVE_ARM_SMCCC 178 select HAVE_ASM_MODVERSIONS 179 select HAVE_EBPF_JIT 180 select HAVE_C_RECORDMCOUNT 181 select HAVE_CMPXCHG_DOUBLE 182 select HAVE_CMPXCHG_LOCAL 183 select HAVE_CONTEXT_TRACKING_USER 184 select HAVE_DEBUG_KMEMLEAK 185 select HAVE_DMA_CONTIGUOUS 186 select HAVE_DYNAMIC_FTRACE 187 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 188 if DYNAMIC_FTRACE_WITH_ARGS 189 select HAVE_EFFICIENT_UNALIGNED_ACCESS 190 select HAVE_FAST_GUP 191 select HAVE_FTRACE_MCOUNT_RECORD 192 select HAVE_FUNCTION_TRACER 193 select HAVE_FUNCTION_ERROR_INJECTION 194 select HAVE_FUNCTION_GRAPH_TRACER 195 select HAVE_GCC_PLUGINS 196 select HAVE_HW_BREAKPOINT if PERF_EVENTS 197 select HAVE_IOREMAP_PROT 198 select HAVE_IRQ_TIME_ACCOUNTING 199 select HAVE_KVM 200 select HAVE_NMI 201 select HAVE_PERF_EVENTS 202 select HAVE_PERF_REGS 203 select HAVE_PERF_USER_STACK_DUMP 204 select HAVE_PREEMPT_DYNAMIC_KEY 205 select HAVE_REGS_AND_STACK_ACCESS_API 206 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 207 select HAVE_FUNCTION_ARG_ACCESS_API 208 select MMU_GATHER_RCU_TABLE_FREE 209 select HAVE_RSEQ 210 select HAVE_STACKPROTECTOR 211 select HAVE_SYSCALL_TRACEPOINTS 212 select HAVE_KPROBES 213 select HAVE_KRETPROBES 214 select HAVE_GENERIC_VDSO 215 select IRQ_DOMAIN 216 select IRQ_FORCED_THREADING 217 select KASAN_VMALLOC if KASAN 218 select MODULES_USE_ELF_RELA 219 select NEED_DMA_MAP_STATE 220 select NEED_SG_DMA_LENGTH 221 select OF 222 select OF_EARLY_FLATTREE 223 select PCI_DOMAINS_GENERIC if PCI 224 select PCI_ECAM if (ACPI && PCI) 225 select PCI_SYSCALL if PCI 226 select POWER_RESET 227 select POWER_SUPPLY 228 select SPARSE_IRQ 229 select SWIOTLB 230 select SYSCTL_EXCEPTION_TRACE 231 select THREAD_INFO_IN_TASK 232 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 233 select TRACE_IRQFLAGS_SUPPORT 234 select TRACE_IRQFLAGS_NMI_SUPPORT 235 select HAVE_SOFTIRQ_ON_OWN_STACK 236 help 237 ARM 64-bit (AArch64) Linux support. 238 239config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 240 def_bool CC_IS_CLANG 241 # https://github.com/ClangBuiltLinux/linux/issues/1507 242 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 243 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 244 245config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 246 def_bool CC_IS_GCC 247 depends on $(cc-option,-fpatchable-function-entry=2) 248 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 249 250config 64BIT 251 def_bool y 252 253config MMU 254 def_bool y 255 256config ARM64_PAGE_SHIFT 257 int 258 default 16 if ARM64_64K_PAGES 259 default 14 if ARM64_16K_PAGES 260 default 12 261 262config ARM64_CONT_PTE_SHIFT 263 int 264 default 5 if ARM64_64K_PAGES 265 default 7 if ARM64_16K_PAGES 266 default 4 267 268config ARM64_CONT_PMD_SHIFT 269 int 270 default 5 if ARM64_64K_PAGES 271 default 5 if ARM64_16K_PAGES 272 default 4 273 274config ARCH_MMAP_RND_BITS_MIN 275 default 14 if ARM64_64K_PAGES 276 default 16 if ARM64_16K_PAGES 277 default 18 278 279# max bits determined by the following formula: 280# VA_BITS - PAGE_SHIFT - 3 281config ARCH_MMAP_RND_BITS_MAX 282 default 19 if ARM64_VA_BITS=36 283 default 24 if ARM64_VA_BITS=39 284 default 27 if ARM64_VA_BITS=42 285 default 30 if ARM64_VA_BITS=47 286 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 287 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 288 default 33 if ARM64_VA_BITS=48 289 default 14 if ARM64_64K_PAGES 290 default 16 if ARM64_16K_PAGES 291 default 18 292 293config ARCH_MMAP_RND_COMPAT_BITS_MIN 294 default 7 if ARM64_64K_PAGES 295 default 9 if ARM64_16K_PAGES 296 default 11 297 298config ARCH_MMAP_RND_COMPAT_BITS_MAX 299 default 16 300 301config NO_IOPORT_MAP 302 def_bool y if !PCI 303 304config STACKTRACE_SUPPORT 305 def_bool y 306 307config ILLEGAL_POINTER_VALUE 308 hex 309 default 0xdead000000000000 310 311config LOCKDEP_SUPPORT 312 def_bool y 313 314config GENERIC_BUG 315 def_bool y 316 depends on BUG 317 318config GENERIC_BUG_RELATIVE_POINTERS 319 def_bool y 320 depends on GENERIC_BUG 321 322config GENERIC_HWEIGHT 323 def_bool y 324 325config GENERIC_CSUM 326 def_bool y 327 328config GENERIC_CALIBRATE_DELAY 329 def_bool y 330 331config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 332 def_bool y 333 334config SMP 335 def_bool y 336 337config KERNEL_MODE_NEON 338 def_bool y 339 340config FIX_EARLYCON_MEM 341 def_bool y 342 343config PGTABLE_LEVELS 344 int 345 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 346 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 347 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 348 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 349 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 350 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 351 352config ARCH_SUPPORTS_UPROBES 353 def_bool y 354 355config ARCH_PROC_KCORE_TEXT 356 def_bool y 357 358config BROKEN_GAS_INST 359 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 360 361config KASAN_SHADOW_OFFSET 362 hex 363 depends on KASAN_GENERIC || KASAN_SW_TAGS 364 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 365 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 366 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 367 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 368 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 369 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 370 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 371 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 372 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 373 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 374 default 0xffffffffffffffff 375 376config UNWIND_TABLES 377 bool 378 379source "arch/arm64/Kconfig.platforms" 380 381menu "Kernel Features" 382 383menu "ARM errata workarounds via the alternatives framework" 384 385config ARM64_WORKAROUND_CLEAN_CACHE 386 bool 387 388config ARM64_ERRATUM_826319 389 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 390 default y 391 select ARM64_WORKAROUND_CLEAN_CACHE 392 help 393 This option adds an alternative code sequence to work around ARM 394 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 395 AXI master interface and an L2 cache. 396 397 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 398 and is unable to accept a certain write via this interface, it will 399 not progress on read data presented on the read data channel and the 400 system can deadlock. 401 402 The workaround promotes data cache clean instructions to 403 data cache clean-and-invalidate. 404 Please note that this does not necessarily enable the workaround, 405 as it depends on the alternative framework, which will only patch 406 the kernel if an affected CPU is detected. 407 408 If unsure, say Y. 409 410config ARM64_ERRATUM_827319 411 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 412 default y 413 select ARM64_WORKAROUND_CLEAN_CACHE 414 help 415 This option adds an alternative code sequence to work around ARM 416 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 417 master interface and an L2 cache. 418 419 Under certain conditions this erratum can cause a clean line eviction 420 to occur at the same time as another transaction to the same address 421 on the AMBA 5 CHI interface, which can cause data corruption if the 422 interconnect reorders the two transactions. 423 424 The workaround promotes data cache clean instructions to 425 data cache clean-and-invalidate. 426 Please note that this does not necessarily enable the workaround, 427 as it depends on the alternative framework, which will only patch 428 the kernel if an affected CPU is detected. 429 430 If unsure, say Y. 431 432config ARM64_ERRATUM_824069 433 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 434 default y 435 select ARM64_WORKAROUND_CLEAN_CACHE 436 help 437 This option adds an alternative code sequence to work around ARM 438 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 439 to a coherent interconnect. 440 441 If a Cortex-A53 processor is executing a store or prefetch for 442 write instruction at the same time as a processor in another 443 cluster is executing a cache maintenance operation to the same 444 address, then this erratum might cause a clean cache line to be 445 incorrectly marked as dirty. 446 447 The workaround promotes data cache clean instructions to 448 data cache clean-and-invalidate. 449 Please note that this option does not necessarily enable the 450 workaround, as it depends on the alternative framework, which will 451 only patch the kernel if an affected CPU is detected. 452 453 If unsure, say Y. 454 455config ARM64_ERRATUM_819472 456 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 457 default y 458 select ARM64_WORKAROUND_CLEAN_CACHE 459 help 460 This option adds an alternative code sequence to work around ARM 461 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 462 present when it is connected to a coherent interconnect. 463 464 If the processor is executing a load and store exclusive sequence at 465 the same time as a processor in another cluster is executing a cache 466 maintenance operation to the same address, then this erratum might 467 cause data corruption. 468 469 The workaround promotes data cache clean instructions to 470 data cache clean-and-invalidate. 471 Please note that this does not necessarily enable the workaround, 472 as it depends on the alternative framework, which will only patch 473 the kernel if an affected CPU is detected. 474 475 If unsure, say Y. 476 477config ARM64_ERRATUM_832075 478 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 479 default y 480 help 481 This option adds an alternative code sequence to work around ARM 482 erratum 832075 on Cortex-A57 parts up to r1p2. 483 484 Affected Cortex-A57 parts might deadlock when exclusive load/store 485 instructions to Write-Back memory are mixed with Device loads. 486 487 The workaround is to promote device loads to use Load-Acquire 488 semantics. 489 Please note that this does not necessarily enable the workaround, 490 as it depends on the alternative framework, which will only patch 491 the kernel if an affected CPU is detected. 492 493 If unsure, say Y. 494 495config ARM64_ERRATUM_834220 496 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 497 depends on KVM 498 default y 499 help 500 This option adds an alternative code sequence to work around ARM 501 erratum 834220 on Cortex-A57 parts up to r1p2. 502 503 Affected Cortex-A57 parts might report a Stage 2 translation 504 fault as the result of a Stage 1 fault for load crossing a 505 page boundary when there is a permission or device memory 506 alignment fault at Stage 1 and a translation fault at Stage 2. 507 508 The workaround is to verify that the Stage 1 translation 509 doesn't generate a fault before handling the Stage 2 fault. 510 Please note that this does not necessarily enable the workaround, 511 as it depends on the alternative framework, which will only patch 512 the kernel if an affected CPU is detected. 513 514 If unsure, say Y. 515 516config ARM64_ERRATUM_1742098 517 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 518 depends on COMPAT 519 default y 520 help 521 This option removes the AES hwcap for aarch32 user-space to 522 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 523 524 Affected parts may corrupt the AES state if an interrupt is 525 taken between a pair of AES instructions. These instructions 526 are only present if the cryptography extensions are present. 527 All software should have a fallback implementation for CPUs 528 that don't implement the cryptography extensions. 529 530 If unsure, say Y. 531 532config ARM64_ERRATUM_845719 533 bool "Cortex-A53: 845719: a load might read incorrect data" 534 depends on COMPAT 535 default y 536 help 537 This option adds an alternative code sequence to work around ARM 538 erratum 845719 on Cortex-A53 parts up to r0p4. 539 540 When running a compat (AArch32) userspace on an affected Cortex-A53 541 part, a load at EL0 from a virtual address that matches the bottom 32 542 bits of the virtual address used by a recent load at (AArch64) EL1 543 might return incorrect data. 544 545 The workaround is to write the contextidr_el1 register on exception 546 return to a 32-bit task. 547 Please note that this does not necessarily enable the workaround, 548 as it depends on the alternative framework, which will only patch 549 the kernel if an affected CPU is detected. 550 551 If unsure, say Y. 552 553config ARM64_ERRATUM_843419 554 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 555 default y 556 select ARM64_MODULE_PLTS if MODULES 557 help 558 This option links the kernel with '--fix-cortex-a53-843419' and 559 enables PLT support to replace certain ADRP instructions, which can 560 cause subsequent memory accesses to use an incorrect address on 561 Cortex-A53 parts up to r0p4. 562 563 If unsure, say Y. 564 565config ARM64_LD_HAS_FIX_ERRATUM_843419 566 def_bool $(ld-option,--fix-cortex-a53-843419) 567 568config ARM64_ERRATUM_1024718 569 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 570 default y 571 help 572 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 573 574 Affected Cortex-A55 cores (all revisions) could cause incorrect 575 update of the hardware dirty bit when the DBM/AP bits are updated 576 without a break-before-make. The workaround is to disable the usage 577 of hardware DBM locally on the affected cores. CPUs not affected by 578 this erratum will continue to use the feature. 579 580 If unsure, say Y. 581 582config ARM64_ERRATUM_1418040 583 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 584 default y 585 depends on COMPAT 586 help 587 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 588 errata 1188873 and 1418040. 589 590 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 591 cause register corruption when accessing the timer registers 592 from AArch32 userspace. 593 594 If unsure, say Y. 595 596config ARM64_WORKAROUND_SPECULATIVE_AT 597 bool 598 599config ARM64_ERRATUM_1165522 600 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 601 default y 602 select ARM64_WORKAROUND_SPECULATIVE_AT 603 help 604 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 605 606 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 607 corrupted TLBs by speculating an AT instruction during a guest 608 context switch. 609 610 If unsure, say Y. 611 612config ARM64_ERRATUM_1319367 613 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 614 default y 615 select ARM64_WORKAROUND_SPECULATIVE_AT 616 help 617 This option adds work arounds for ARM Cortex-A57 erratum 1319537 618 and A72 erratum 1319367 619 620 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 621 speculating an AT instruction during a guest context switch. 622 623 If unsure, say Y. 624 625config ARM64_ERRATUM_1530923 626 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 627 default y 628 select ARM64_WORKAROUND_SPECULATIVE_AT 629 help 630 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 631 632 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 633 corrupted TLBs by speculating an AT instruction during a guest 634 context switch. 635 636 If unsure, say Y. 637 638config ARM64_WORKAROUND_REPEAT_TLBI 639 bool 640 641config ARM64_ERRATUM_2441007 642 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 643 default y 644 select ARM64_WORKAROUND_REPEAT_TLBI 645 help 646 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 647 648 Under very rare circumstances, affected Cortex-A55 CPUs 649 may not handle a race between a break-before-make sequence on one 650 CPU, and another CPU accessing the same page. This could allow a 651 store to a page that has been unmapped. 652 653 Work around this by adding the affected CPUs to the list that needs 654 TLB sequences to be done twice. 655 656 If unsure, say Y. 657 658config ARM64_ERRATUM_1286807 659 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 660 default y 661 select ARM64_WORKAROUND_REPEAT_TLBI 662 help 663 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 664 665 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 666 address for a cacheable mapping of a location is being 667 accessed by a core while another core is remapping the virtual 668 address to a new physical page using the recommended 669 break-before-make sequence, then under very rare circumstances 670 TLBI+DSB completes before a read using the translation being 671 invalidated has been observed by other observers. The 672 workaround repeats the TLBI+DSB operation. 673 674config ARM64_ERRATUM_1463225 675 bool "Cortex-A76: Software Step might prevent interrupt recognition" 676 default y 677 help 678 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 679 680 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 681 of a system call instruction (SVC) can prevent recognition of 682 subsequent interrupts when software stepping is disabled in the 683 exception handler of the system call and either kernel debugging 684 is enabled or VHE is in use. 685 686 Work around the erratum by triggering a dummy step exception 687 when handling a system call from a task that is being stepped 688 in a VHE configuration of the kernel. 689 690 If unsure, say Y. 691 692config ARM64_ERRATUM_1542419 693 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 694 default y 695 help 696 This option adds a workaround for ARM Neoverse-N1 erratum 697 1542419. 698 699 Affected Neoverse-N1 cores could execute a stale instruction when 700 modified by another CPU. The workaround depends on a firmware 701 counterpart. 702 703 Workaround the issue by hiding the DIC feature from EL0. This 704 forces user-space to perform cache maintenance. 705 706 If unsure, say Y. 707 708config ARM64_ERRATUM_1508412 709 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 710 default y 711 help 712 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 713 714 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 715 of a store-exclusive or read of PAR_EL1 and a load with device or 716 non-cacheable memory attributes. The workaround depends on a firmware 717 counterpart. 718 719 KVM guests must also have the workaround implemented or they can 720 deadlock the system. 721 722 Work around the issue by inserting DMB SY barriers around PAR_EL1 723 register reads and warning KVM users. The DMB barrier is sufficient 724 to prevent a speculative PAR_EL1 read. 725 726 If unsure, say Y. 727 728config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 729 bool 730 731config ARM64_ERRATUM_2051678 732 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 733 default y 734 help 735 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 736 Affected Cortex-A510 might not respect the ordering rules for 737 hardware update of the page table's dirty bit. The workaround 738 is to not enable the feature on affected CPUs. 739 740 If unsure, say Y. 741 742config ARM64_ERRATUM_2077057 743 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 744 default y 745 help 746 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 747 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 748 expected, but a Pointer Authentication trap is taken instead. The 749 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 750 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 751 752 This can only happen when EL2 is stepping EL1. 753 754 When these conditions occur, the SPSR_EL2 value is unchanged from the 755 previous guest entry, and can be restored from the in-memory copy. 756 757 If unsure, say Y. 758 759config ARM64_ERRATUM_2658417 760 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 761 default y 762 help 763 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 764 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 765 BFMMLA or VMMLA instructions in rare circumstances when a pair of 766 A510 CPUs are using shared neon hardware. As the sharing is not 767 discoverable by the kernel, hide the BF16 HWCAP to indicate that 768 user-space should not be using these instructions. 769 770 If unsure, say Y. 771 772config ARM64_ERRATUM_2119858 773 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 774 default y 775 depends on CORESIGHT_TRBE 776 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 777 help 778 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 779 780 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 781 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 782 the event of a WRAP event. 783 784 Work around the issue by always making sure we move the TRBPTR_EL1 by 785 256 bytes before enabling the buffer and filling the first 256 bytes of 786 the buffer with ETM ignore packets upon disabling. 787 788 If unsure, say Y. 789 790config ARM64_ERRATUM_2139208 791 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 792 default y 793 depends on CORESIGHT_TRBE 794 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 795 help 796 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 797 798 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 799 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 800 the event of a WRAP event. 801 802 Work around the issue by always making sure we move the TRBPTR_EL1 by 803 256 bytes before enabling the buffer and filling the first 256 bytes of 804 the buffer with ETM ignore packets upon disabling. 805 806 If unsure, say Y. 807 808config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 809 bool 810 811config ARM64_ERRATUM_2054223 812 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 813 default y 814 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 815 help 816 Enable workaround for ARM Cortex-A710 erratum 2054223 817 818 Affected cores may fail to flush the trace data on a TSB instruction, when 819 the PE is in trace prohibited state. This will cause losing a few bytes 820 of the trace cached. 821 822 Workaround is to issue two TSB consecutively on affected cores. 823 824 If unsure, say Y. 825 826config ARM64_ERRATUM_2067961 827 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 828 default y 829 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 830 help 831 Enable workaround for ARM Neoverse-N2 erratum 2067961 832 833 Affected cores may fail to flush the trace data on a TSB instruction, when 834 the PE is in trace prohibited state. This will cause losing a few bytes 835 of the trace cached. 836 837 Workaround is to issue two TSB consecutively on affected cores. 838 839 If unsure, say Y. 840 841config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 842 bool 843 844config ARM64_ERRATUM_2253138 845 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 846 depends on CORESIGHT_TRBE 847 default y 848 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 849 help 850 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 851 852 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 853 for TRBE. Under some conditions, the TRBE might generate a write to the next 854 virtually addressed page following the last page of the TRBE address space 855 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 856 857 Work around this in the driver by always making sure that there is a 858 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 859 860 If unsure, say Y. 861 862config ARM64_ERRATUM_2224489 863 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 864 depends on CORESIGHT_TRBE 865 default y 866 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 867 help 868 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 869 870 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 871 for TRBE. Under some conditions, the TRBE might generate a write to the next 872 virtually addressed page following the last page of the TRBE address space 873 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 874 875 Work around this in the driver by always making sure that there is a 876 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 877 878 If unsure, say Y. 879 880config ARM64_ERRATUM_2441009 881 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 882 default y 883 select ARM64_WORKAROUND_REPEAT_TLBI 884 help 885 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 886 887 Under very rare circumstances, affected Cortex-A510 CPUs 888 may not handle a race between a break-before-make sequence on one 889 CPU, and another CPU accessing the same page. This could allow a 890 store to a page that has been unmapped. 891 892 Work around this by adding the affected CPUs to the list that needs 893 TLB sequences to be done twice. 894 895 If unsure, say Y. 896 897config ARM64_ERRATUM_2064142 898 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 899 depends on CORESIGHT_TRBE 900 default y 901 help 902 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 903 904 Affected Cortex-A510 core might fail to write into system registers after the 905 TRBE has been disabled. Under some conditions after the TRBE has been disabled 906 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 907 and TRBTRG_EL1 will be ignored and will not be effected. 908 909 Work around this in the driver by executing TSB CSYNC and DSB after collection 910 is stopped and before performing a system register write to one of the affected 911 registers. 912 913 If unsure, say Y. 914 915config ARM64_ERRATUM_2038923 916 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 917 depends on CORESIGHT_TRBE 918 default y 919 help 920 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 921 922 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 923 prohibited within the CPU. As a result, the trace buffer or trace buffer state 924 might be corrupted. This happens after TRBE buffer has been enabled by setting 925 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 926 execution changes from a context, in which trace is prohibited to one where it 927 isn't, or vice versa. In these mentioned conditions, the view of whether trace 928 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 929 the trace buffer state might be corrupted. 930 931 Work around this in the driver by preventing an inconsistent view of whether the 932 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 933 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 934 two ISB instructions if no ERET is to take place. 935 936 If unsure, say Y. 937 938config ARM64_ERRATUM_1902691 939 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 940 depends on CORESIGHT_TRBE 941 default y 942 help 943 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 944 945 Affected Cortex-A510 core might cause trace data corruption, when being written 946 into the memory. Effectively TRBE is broken and hence cannot be used to capture 947 trace data. 948 949 Work around this problem in the driver by just preventing TRBE initialization on 950 affected cpus. The firmware must have disabled the access to TRBE for the kernel 951 on such implementations. This will cover the kernel for any firmware that doesn't 952 do this already. 953 954 If unsure, say Y. 955 956config ARM64_ERRATUM_2457168 957 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 958 depends on ARM64_AMU_EXTN 959 default y 960 help 961 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 962 963 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 964 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 965 incorrectly giving a significantly higher output value. 966 967 Work around this problem by returning 0 when reading the affected counter in 968 key locations that results in disabling all users of this counter. This effect 969 is the same to firmware disabling affected counters. 970 971 If unsure, say Y. 972 973config ARM64_ERRATUM_2645198 974 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 975 default y 976 help 977 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 978 979 If a Cortex-A715 cpu sees a page mapping permissions change from executable 980 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 981 next instruction abort caused by permission fault. 982 983 Only user-space does executable to non-executable permission transition via 984 mprotect() system call. Workaround the problem by doing a break-before-make 985 TLB invalidation, for all changes to executable user space mappings. 986 987 If unsure, say Y. 988 989config CAVIUM_ERRATUM_22375 990 bool "Cavium erratum 22375, 24313" 991 default y 992 help 993 Enable workaround for errata 22375 and 24313. 994 995 This implements two gicv3-its errata workarounds for ThunderX. Both 996 with a small impact affecting only ITS table allocation. 997 998 erratum 22375: only alloc 8MB table size 999 erratum 24313: ignore memory access type 1000 1001 The fixes are in ITS initialization and basically ignore memory access 1002 type and table size provided by the TYPER and BASER registers. 1003 1004 If unsure, say Y. 1005 1006config CAVIUM_ERRATUM_23144 1007 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1008 depends on NUMA 1009 default y 1010 help 1011 ITS SYNC command hang for cross node io and collections/cpu mapping. 1012 1013 If unsure, say Y. 1014 1015config CAVIUM_ERRATUM_23154 1016 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1017 default y 1018 help 1019 The ThunderX GICv3 implementation requires a modified version for 1020 reading the IAR status to ensure data synchronization 1021 (access to icc_iar1_el1 is not sync'ed before and after). 1022 1023 It also suffers from erratum 38545 (also present on Marvell's 1024 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1025 spuriously presented to the CPU interface. 1026 1027 If unsure, say Y. 1028 1029config CAVIUM_ERRATUM_27456 1030 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1031 default y 1032 help 1033 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1034 instructions may cause the icache to become corrupted if it 1035 contains data for a non-current ASID. The fix is to 1036 invalidate the icache when changing the mm context. 1037 1038 If unsure, say Y. 1039 1040config CAVIUM_ERRATUM_30115 1041 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1042 default y 1043 help 1044 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1045 1.2, and T83 Pass 1.0, KVM guest execution may disable 1046 interrupts in host. Trapping both GICv3 group-0 and group-1 1047 accesses sidesteps the issue. 1048 1049 If unsure, say Y. 1050 1051config CAVIUM_TX2_ERRATUM_219 1052 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1053 default y 1054 help 1055 On Cavium ThunderX2, a load, store or prefetch instruction between a 1056 TTBR update and the corresponding context synchronizing operation can 1057 cause a spurious Data Abort to be delivered to any hardware thread in 1058 the CPU core. 1059 1060 Work around the issue by avoiding the problematic code sequence and 1061 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1062 trap handler performs the corresponding register access, skips the 1063 instruction and ensures context synchronization by virtue of the 1064 exception return. 1065 1066 If unsure, say Y. 1067 1068config FUJITSU_ERRATUM_010001 1069 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1070 default y 1071 help 1072 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1073 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1074 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1075 This fault occurs under a specific hardware condition when a 1076 load/store instruction performs an address translation using: 1077 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1078 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1079 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1080 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1081 1082 The workaround is to ensure these bits are clear in TCR_ELx. 1083 The workaround only affects the Fujitsu-A64FX. 1084 1085 If unsure, say Y. 1086 1087config HISILICON_ERRATUM_161600802 1088 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1089 default y 1090 help 1091 The HiSilicon Hip07 SoC uses the wrong redistributor base 1092 when issued ITS commands such as VMOVP and VMAPP, and requires 1093 a 128kB offset to be applied to the target address in this commands. 1094 1095 If unsure, say Y. 1096 1097config QCOM_FALKOR_ERRATUM_1003 1098 bool "Falkor E1003: Incorrect translation due to ASID change" 1099 default y 1100 help 1101 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1102 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1103 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1104 then only for entries in the walk cache, since the leaf translation 1105 is unchanged. Work around the erratum by invalidating the walk cache 1106 entries for the trampoline before entering the kernel proper. 1107 1108config QCOM_FALKOR_ERRATUM_1009 1109 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1110 default y 1111 select ARM64_WORKAROUND_REPEAT_TLBI 1112 help 1113 On Falkor v1, the CPU may prematurely complete a DSB following a 1114 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1115 one more time to fix the issue. 1116 1117 If unsure, say Y. 1118 1119config QCOM_QDF2400_ERRATUM_0065 1120 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1121 default y 1122 help 1123 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1124 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1125 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1126 1127 If unsure, say Y. 1128 1129config QCOM_FALKOR_ERRATUM_E1041 1130 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1131 default y 1132 help 1133 Falkor CPU may speculatively fetch instructions from an improper 1134 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1135 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1136 1137 If unsure, say Y. 1138 1139config NVIDIA_CARMEL_CNP_ERRATUM 1140 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1141 default y 1142 help 1143 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1144 invalidate shared TLB entries installed by a different core, as it would 1145 on standard ARM cores. 1146 1147 If unsure, say Y. 1148 1149config SOCIONEXT_SYNQUACER_PREITS 1150 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1151 default y 1152 help 1153 Socionext Synquacer SoCs implement a separate h/w block to generate 1154 MSI doorbell writes with non-zero values for the device ID. 1155 1156 If unsure, say Y. 1157 1158endmenu # "ARM errata workarounds via the alternatives framework" 1159 1160choice 1161 prompt "Page size" 1162 default ARM64_4K_PAGES 1163 help 1164 Page size (translation granule) configuration. 1165 1166config ARM64_4K_PAGES 1167 bool "4KB" 1168 help 1169 This feature enables 4KB pages support. 1170 1171config ARM64_16K_PAGES 1172 bool "16KB" 1173 help 1174 The system will use 16KB pages support. AArch32 emulation 1175 requires applications compiled with 16K (or a multiple of 16K) 1176 aligned segments. 1177 1178config ARM64_64K_PAGES 1179 bool "64KB" 1180 help 1181 This feature enables 64KB pages support (4KB by default) 1182 allowing only two levels of page tables and faster TLB 1183 look-up. AArch32 emulation requires applications compiled 1184 with 64K aligned segments. 1185 1186endchoice 1187 1188choice 1189 prompt "Virtual address space size" 1190 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1191 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1192 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1193 help 1194 Allows choosing one of multiple possible virtual address 1195 space sizes. The level of translation table is determined by 1196 a combination of page size and virtual address space size. 1197 1198config ARM64_VA_BITS_36 1199 bool "36-bit" if EXPERT 1200 depends on ARM64_16K_PAGES 1201 1202config ARM64_VA_BITS_39 1203 bool "39-bit" 1204 depends on ARM64_4K_PAGES 1205 1206config ARM64_VA_BITS_42 1207 bool "42-bit" 1208 depends on ARM64_64K_PAGES 1209 1210config ARM64_VA_BITS_47 1211 bool "47-bit" 1212 depends on ARM64_16K_PAGES 1213 1214config ARM64_VA_BITS_48 1215 bool "48-bit" 1216 1217config ARM64_VA_BITS_52 1218 bool "52-bit" 1219 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1220 help 1221 Enable 52-bit virtual addressing for userspace when explicitly 1222 requested via a hint to mmap(). The kernel will also use 52-bit 1223 virtual addresses for its own mappings (provided HW support for 1224 this feature is available, otherwise it reverts to 48-bit). 1225 1226 NOTE: Enabling 52-bit virtual addressing in conjunction with 1227 ARMv8.3 Pointer Authentication will result in the PAC being 1228 reduced from 7 bits to 3 bits, which may have a significant 1229 impact on its susceptibility to brute-force attacks. 1230 1231 If unsure, select 48-bit virtual addressing instead. 1232 1233endchoice 1234 1235config ARM64_FORCE_52BIT 1236 bool "Force 52-bit virtual addresses for userspace" 1237 depends on ARM64_VA_BITS_52 && EXPERT 1238 help 1239 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1240 to maintain compatibility with older software by providing 48-bit VAs 1241 unless a hint is supplied to mmap. 1242 1243 This configuration option disables the 48-bit compatibility logic, and 1244 forces all userspace addresses to be 52-bit on HW that supports it. One 1245 should only enable this configuration option for stress testing userspace 1246 memory management code. If unsure say N here. 1247 1248config ARM64_VA_BITS 1249 int 1250 default 36 if ARM64_VA_BITS_36 1251 default 39 if ARM64_VA_BITS_39 1252 default 42 if ARM64_VA_BITS_42 1253 default 47 if ARM64_VA_BITS_47 1254 default 48 if ARM64_VA_BITS_48 1255 default 52 if ARM64_VA_BITS_52 1256 1257choice 1258 prompt "Physical address space size" 1259 default ARM64_PA_BITS_48 1260 help 1261 Choose the maximum physical address range that the kernel will 1262 support. 1263 1264config ARM64_PA_BITS_48 1265 bool "48-bit" 1266 1267config ARM64_PA_BITS_52 1268 bool "52-bit (ARMv8.2)" 1269 depends on ARM64_64K_PAGES 1270 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1271 help 1272 Enable support for a 52-bit physical address space, introduced as 1273 part of the ARMv8.2-LPA extension. 1274 1275 With this enabled, the kernel will also continue to work on CPUs that 1276 do not support ARMv8.2-LPA, but with some added memory overhead (and 1277 minor performance overhead). 1278 1279endchoice 1280 1281config ARM64_PA_BITS 1282 int 1283 default 48 if ARM64_PA_BITS_48 1284 default 52 if ARM64_PA_BITS_52 1285 1286choice 1287 prompt "Endianness" 1288 default CPU_LITTLE_ENDIAN 1289 help 1290 Select the endianness of data accesses performed by the CPU. Userspace 1291 applications will need to be compiled and linked for the endianness 1292 that is selected here. 1293 1294config CPU_BIG_ENDIAN 1295 bool "Build big-endian kernel" 1296 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1297 help 1298 Say Y if you plan on running a kernel with a big-endian userspace. 1299 1300config CPU_LITTLE_ENDIAN 1301 bool "Build little-endian kernel" 1302 help 1303 Say Y if you plan on running a kernel with a little-endian userspace. 1304 This is usually the case for distributions targeting arm64. 1305 1306endchoice 1307 1308config SCHED_MC 1309 bool "Multi-core scheduler support" 1310 help 1311 Multi-core scheduler support improves the CPU scheduler's decision 1312 making when dealing with multi-core CPU chips at a cost of slightly 1313 increased overhead in some places. If unsure say N here. 1314 1315config SCHED_CLUSTER 1316 bool "Cluster scheduler support" 1317 help 1318 Cluster scheduler support improves the CPU scheduler's decision 1319 making when dealing with machines that have clusters of CPUs. 1320 Cluster usually means a couple of CPUs which are placed closely 1321 by sharing mid-level caches, last-level cache tags or internal 1322 busses. 1323 1324config SCHED_SMT 1325 bool "SMT scheduler support" 1326 help 1327 Improves the CPU scheduler's decision making when dealing with 1328 MultiThreading at a cost of slightly increased overhead in some 1329 places. If unsure say N here. 1330 1331config NR_CPUS 1332 int "Maximum number of CPUs (2-4096)" 1333 range 2 4096 1334 default "256" 1335 1336config HOTPLUG_CPU 1337 bool "Support for hot-pluggable CPUs" 1338 select GENERIC_IRQ_MIGRATION 1339 help 1340 Say Y here to experiment with turning CPUs off and on. CPUs 1341 can be controlled through /sys/devices/system/cpu. 1342 1343# Common NUMA Features 1344config NUMA 1345 bool "NUMA Memory Allocation and Scheduler Support" 1346 select GENERIC_ARCH_NUMA 1347 select ACPI_NUMA if ACPI 1348 select OF_NUMA 1349 select HAVE_SETUP_PER_CPU_AREA 1350 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1351 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1352 select USE_PERCPU_NUMA_NODE_ID 1353 help 1354 Enable NUMA (Non-Uniform Memory Access) support. 1355 1356 The kernel will try to allocate memory used by a CPU on the 1357 local memory of the CPU and add some more 1358 NUMA awareness to the kernel. 1359 1360config NODES_SHIFT 1361 int "Maximum NUMA Nodes (as a power of 2)" 1362 range 1 10 1363 default "4" 1364 depends on NUMA 1365 help 1366 Specify the maximum number of NUMA Nodes available on the target 1367 system. Increases memory reserved to accommodate various tables. 1368 1369source "kernel/Kconfig.hz" 1370 1371config ARCH_SPARSEMEM_ENABLE 1372 def_bool y 1373 select SPARSEMEM_VMEMMAP_ENABLE 1374 select SPARSEMEM_VMEMMAP 1375 1376config HW_PERF_EVENTS 1377 def_bool y 1378 depends on ARM_PMU 1379 1380# Supported by clang >= 7.0 or GCC >= 12.0.0 1381config CC_HAVE_SHADOW_CALL_STACK 1382 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1383 1384config PARAVIRT 1385 bool "Enable paravirtualization code" 1386 help 1387 This changes the kernel so it can modify itself when it is run 1388 under a hypervisor, potentially improving performance significantly 1389 over full virtualization. 1390 1391config PARAVIRT_TIME_ACCOUNTING 1392 bool "Paravirtual steal time accounting" 1393 select PARAVIRT 1394 help 1395 Select this option to enable fine granularity task steal time 1396 accounting. Time spent executing other tasks in parallel with 1397 the current vCPU is discounted from the vCPU power. To account for 1398 that, there can be a small performance impact. 1399 1400 If in doubt, say N here. 1401 1402config KEXEC 1403 depends on PM_SLEEP_SMP 1404 select KEXEC_CORE 1405 bool "kexec system call" 1406 help 1407 kexec is a system call that implements the ability to shutdown your 1408 current kernel, and to start another kernel. It is like a reboot 1409 but it is independent of the system firmware. And like a reboot 1410 you can start any kernel with it, not just Linux. 1411 1412config KEXEC_FILE 1413 bool "kexec file based system call" 1414 select KEXEC_CORE 1415 select HAVE_IMA_KEXEC if IMA 1416 help 1417 This is new version of kexec system call. This system call is 1418 file based and takes file descriptors as system call argument 1419 for kernel and initramfs as opposed to list of segments as 1420 accepted by previous system call. 1421 1422config KEXEC_SIG 1423 bool "Verify kernel signature during kexec_file_load() syscall" 1424 depends on KEXEC_FILE 1425 help 1426 Select this option to verify a signature with loaded kernel 1427 image. If configured, any attempt of loading a image without 1428 valid signature will fail. 1429 1430 In addition to that option, you need to enable signature 1431 verification for the corresponding kernel image type being 1432 loaded in order for this to work. 1433 1434config KEXEC_IMAGE_VERIFY_SIG 1435 bool "Enable Image signature verification support" 1436 default y 1437 depends on KEXEC_SIG 1438 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1439 help 1440 Enable Image signature verification support. 1441 1442comment "Support for PE file signature verification disabled" 1443 depends on KEXEC_SIG 1444 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1445 1446config CRASH_DUMP 1447 bool "Build kdump crash kernel" 1448 help 1449 Generate crash dump after being started by kexec. This should 1450 be normally only set in special crash dump kernels which are 1451 loaded in the main kernel with kexec-tools into a specially 1452 reserved region and then later executed after a crash by 1453 kdump/kexec. 1454 1455 For more details see Documentation/admin-guide/kdump/kdump.rst 1456 1457config TRANS_TABLE 1458 def_bool y 1459 depends on HIBERNATION || KEXEC_CORE 1460 1461config XEN_DOM0 1462 def_bool y 1463 depends on XEN 1464 1465config XEN 1466 bool "Xen guest support on ARM64" 1467 depends on ARM64 && OF 1468 select SWIOTLB_XEN 1469 select PARAVIRT 1470 help 1471 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1472 1473config ARCH_FORCE_MAX_ORDER 1474 int 1475 default "14" if ARM64_64K_PAGES 1476 default "12" if ARM64_16K_PAGES 1477 default "11" 1478 help 1479 The kernel memory allocator divides physically contiguous memory 1480 blocks into "zones", where each zone is a power of two number of 1481 pages. This option selects the largest power of two that the kernel 1482 keeps in the memory allocator. If you need to allocate very large 1483 blocks of physically contiguous memory, then you may need to 1484 increase this value. 1485 1486 This config option is actually maximum order plus one. For example, 1487 a value of 11 means that the largest free memory block is 2^10 pages. 1488 1489 We make sure that we can allocate upto a HugePage size for each configuration. 1490 Hence we have : 1491 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1492 1493 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1494 4M allocations matching the default size used by generic code. 1495 1496config UNMAP_KERNEL_AT_EL0 1497 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1498 default y 1499 help 1500 Speculation attacks against some high-performance processors can 1501 be used to bypass MMU permission checks and leak kernel data to 1502 userspace. This can be defended against by unmapping the kernel 1503 when running in userspace, mapping it back in on exception entry 1504 via a trampoline page in the vector table. 1505 1506 If unsure, say Y. 1507 1508config MITIGATE_SPECTRE_BRANCH_HISTORY 1509 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1510 default y 1511 help 1512 Speculation attacks against some high-performance processors can 1513 make use of branch history to influence future speculation. 1514 When taking an exception from user-space, a sequence of branches 1515 or a firmware call overwrites the branch history. 1516 1517config RODATA_FULL_DEFAULT_ENABLED 1518 bool "Apply r/o permissions of VM areas also to their linear aliases" 1519 default y 1520 help 1521 Apply read-only attributes of VM areas to the linear alias of 1522 the backing pages as well. This prevents code or read-only data 1523 from being modified (inadvertently or intentionally) via another 1524 mapping of the same memory page. This additional enhancement can 1525 be turned off at runtime by passing rodata=[off|on] (and turned on 1526 with rodata=full if this option is set to 'n') 1527 1528 This requires the linear region to be mapped down to pages, 1529 which may adversely affect performance in some cases. 1530 1531config ARM64_SW_TTBR0_PAN 1532 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1533 help 1534 Enabling this option prevents the kernel from accessing 1535 user-space memory directly by pointing TTBR0_EL1 to a reserved 1536 zeroed area and reserved ASID. The user access routines 1537 restore the valid TTBR0_EL1 temporarily. 1538 1539config ARM64_TAGGED_ADDR_ABI 1540 bool "Enable the tagged user addresses syscall ABI" 1541 default y 1542 help 1543 When this option is enabled, user applications can opt in to a 1544 relaxed ABI via prctl() allowing tagged addresses to be passed 1545 to system calls as pointer arguments. For details, see 1546 Documentation/arm64/tagged-address-abi.rst. 1547 1548menuconfig COMPAT 1549 bool "Kernel support for 32-bit EL0" 1550 depends on ARM64_4K_PAGES || EXPERT 1551 select HAVE_UID16 1552 select OLD_SIGSUSPEND3 1553 select COMPAT_OLD_SIGACTION 1554 help 1555 This option enables support for a 32-bit EL0 running under a 64-bit 1556 kernel at EL1. AArch32-specific components such as system calls, 1557 the user helper functions, VFP support and the ptrace interface are 1558 handled appropriately by the kernel. 1559 1560 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1561 that you will only be able to execute AArch32 binaries that were compiled 1562 with page size aligned segments. 1563 1564 If you want to execute 32-bit userspace applications, say Y. 1565 1566if COMPAT 1567 1568config KUSER_HELPERS 1569 bool "Enable kuser helpers page for 32-bit applications" 1570 default y 1571 help 1572 Warning: disabling this option may break 32-bit user programs. 1573 1574 Provide kuser helpers to compat tasks. The kernel provides 1575 helper code to userspace in read only form at a fixed location 1576 to allow userspace to be independent of the CPU type fitted to 1577 the system. This permits binaries to be run on ARMv4 through 1578 to ARMv8 without modification. 1579 1580 See Documentation/arm/kernel_user_helpers.rst for details. 1581 1582 However, the fixed address nature of these helpers can be used 1583 by ROP (return orientated programming) authors when creating 1584 exploits. 1585 1586 If all of the binaries and libraries which run on your platform 1587 are built specifically for your platform, and make no use of 1588 these helpers, then you can turn this option off to hinder 1589 such exploits. However, in that case, if a binary or library 1590 relying on those helpers is run, it will not function correctly. 1591 1592 Say N here only if you are absolutely certain that you do not 1593 need these helpers; otherwise, the safe option is to say Y. 1594 1595config COMPAT_VDSO 1596 bool "Enable vDSO for 32-bit applications" 1597 depends on !CPU_BIG_ENDIAN 1598 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1599 select GENERIC_COMPAT_VDSO 1600 default y 1601 help 1602 Place in the process address space of 32-bit applications an 1603 ELF shared object providing fast implementations of gettimeofday 1604 and clock_gettime. 1605 1606 You must have a 32-bit build of glibc 2.22 or later for programs 1607 to seamlessly take advantage of this. 1608 1609config THUMB2_COMPAT_VDSO 1610 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1611 depends on COMPAT_VDSO 1612 default y 1613 help 1614 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1615 otherwise with '-marm'. 1616 1617config COMPAT_ALIGNMENT_FIXUPS 1618 bool "Fix up misaligned multi-word loads and stores in user space" 1619 1620menuconfig ARMV8_DEPRECATED 1621 bool "Emulate deprecated/obsolete ARMv8 instructions" 1622 depends on SYSCTL 1623 help 1624 Legacy software support may require certain instructions 1625 that have been deprecated or obsoleted in the architecture. 1626 1627 Enable this config to enable selective emulation of these 1628 features. 1629 1630 If unsure, say Y 1631 1632if ARMV8_DEPRECATED 1633 1634config SWP_EMULATION 1635 bool "Emulate SWP/SWPB instructions" 1636 help 1637 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1638 they are always undefined. Say Y here to enable software 1639 emulation of these instructions for userspace using LDXR/STXR. 1640 This feature can be controlled at runtime with the abi.swp 1641 sysctl which is disabled by default. 1642 1643 In some older versions of glibc [<=2.8] SWP is used during futex 1644 trylock() operations with the assumption that the code will not 1645 be preempted. This invalid assumption may be more likely to fail 1646 with SWP emulation enabled, leading to deadlock of the user 1647 application. 1648 1649 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1650 on an external transaction monitoring block called a global 1651 monitor to maintain update atomicity. If your system does not 1652 implement a global monitor, this option can cause programs that 1653 perform SWP operations to uncached memory to deadlock. 1654 1655 If unsure, say Y 1656 1657config CP15_BARRIER_EMULATION 1658 bool "Emulate CP15 Barrier instructions" 1659 help 1660 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1661 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1662 strongly recommended to use the ISB, DSB, and DMB 1663 instructions instead. 1664 1665 Say Y here to enable software emulation of these 1666 instructions for AArch32 userspace code. When this option is 1667 enabled, CP15 barrier usage is traced which can help 1668 identify software that needs updating. This feature can be 1669 controlled at runtime with the abi.cp15_barrier sysctl. 1670 1671 If unsure, say Y 1672 1673config SETEND_EMULATION 1674 bool "Emulate SETEND instruction" 1675 help 1676 The SETEND instruction alters the data-endianness of the 1677 AArch32 EL0, and is deprecated in ARMv8. 1678 1679 Say Y here to enable software emulation of the instruction 1680 for AArch32 userspace code. This feature can be controlled 1681 at runtime with the abi.setend sysctl. 1682 1683 Note: All the cpus on the system must have mixed endian support at EL0 1684 for this feature to be enabled. If a new CPU - which doesn't support mixed 1685 endian - is hotplugged in after this feature has been enabled, there could 1686 be unexpected results in the applications. 1687 1688 If unsure, say Y 1689endif # ARMV8_DEPRECATED 1690 1691endif # COMPAT 1692 1693menu "ARMv8.1 architectural features" 1694 1695config ARM64_HW_AFDBM 1696 bool "Support for hardware updates of the Access and Dirty page flags" 1697 default y 1698 help 1699 The ARMv8.1 architecture extensions introduce support for 1700 hardware updates of the access and dirty information in page 1701 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1702 capable processors, accesses to pages with PTE_AF cleared will 1703 set this bit instead of raising an access flag fault. 1704 Similarly, writes to read-only pages with the DBM bit set will 1705 clear the read-only bit (AP[2]) instead of raising a 1706 permission fault. 1707 1708 Kernels built with this configuration option enabled continue 1709 to work on pre-ARMv8.1 hardware and the performance impact is 1710 minimal. If unsure, say Y. 1711 1712config ARM64_PAN 1713 bool "Enable support for Privileged Access Never (PAN)" 1714 default y 1715 help 1716 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1717 prevents the kernel or hypervisor from accessing user-space (EL0) 1718 memory directly. 1719 1720 Choosing this option will cause any unprotected (not using 1721 copy_to_user et al) memory access to fail with a permission fault. 1722 1723 The feature is detected at runtime, and will remain as a 'nop' 1724 instruction if the cpu does not implement the feature. 1725 1726config AS_HAS_LDAPR 1727 def_bool $(as-instr,.arch_extension rcpc) 1728 1729config AS_HAS_LSE_ATOMICS 1730 def_bool $(as-instr,.arch_extension lse) 1731 1732config ARM64_LSE_ATOMICS 1733 bool 1734 default ARM64_USE_LSE_ATOMICS 1735 depends on AS_HAS_LSE_ATOMICS 1736 1737config ARM64_USE_LSE_ATOMICS 1738 bool "Atomic instructions" 1739 default y 1740 help 1741 As part of the Large System Extensions, ARMv8.1 introduces new 1742 atomic instructions that are designed specifically to scale in 1743 very large systems. 1744 1745 Say Y here to make use of these instructions for the in-kernel 1746 atomic routines. This incurs a small overhead on CPUs that do 1747 not support these instructions and requires the kernel to be 1748 built with binutils >= 2.25 in order for the new instructions 1749 to be used. 1750 1751endmenu # "ARMv8.1 architectural features" 1752 1753menu "ARMv8.2 architectural features" 1754 1755config AS_HAS_ARMV8_2 1756 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1757 1758config AS_HAS_SHA3 1759 def_bool $(as-instr,.arch armv8.2-a+sha3) 1760 1761config ARM64_PMEM 1762 bool "Enable support for persistent memory" 1763 select ARCH_HAS_PMEM_API 1764 select ARCH_HAS_UACCESS_FLUSHCACHE 1765 help 1766 Say Y to enable support for the persistent memory API based on the 1767 ARMv8.2 DCPoP feature. 1768 1769 The feature is detected at runtime, and the kernel will use DC CVAC 1770 operations if DC CVAP is not supported (following the behaviour of 1771 DC CVAP itself if the system does not define a point of persistence). 1772 1773config ARM64_RAS_EXTN 1774 bool "Enable support for RAS CPU Extensions" 1775 default y 1776 help 1777 CPUs that support the Reliability, Availability and Serviceability 1778 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1779 errors, classify them and report them to software. 1780 1781 On CPUs with these extensions system software can use additional 1782 barriers to determine if faults are pending and read the 1783 classification from a new set of registers. 1784 1785 Selecting this feature will allow the kernel to use these barriers 1786 and access the new registers if the system supports the extension. 1787 Platform RAS features may additionally depend on firmware support. 1788 1789config ARM64_CNP 1790 bool "Enable support for Common Not Private (CNP) translations" 1791 default y 1792 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1793 help 1794 Common Not Private (CNP) allows translation table entries to 1795 be shared between different PEs in the same inner shareable 1796 domain, so the hardware can use this fact to optimise the 1797 caching of such entries in the TLB. 1798 1799 Selecting this option allows the CNP feature to be detected 1800 at runtime, and does not affect PEs that do not implement 1801 this feature. 1802 1803endmenu # "ARMv8.2 architectural features" 1804 1805menu "ARMv8.3 architectural features" 1806 1807config ARM64_PTR_AUTH 1808 bool "Enable support for pointer authentication" 1809 default y 1810 help 1811 Pointer authentication (part of the ARMv8.3 Extensions) provides 1812 instructions for signing and authenticating pointers against secret 1813 keys, which can be used to mitigate Return Oriented Programming (ROP) 1814 and other attacks. 1815 1816 This option enables these instructions at EL0 (i.e. for userspace). 1817 Choosing this option will cause the kernel to initialise secret keys 1818 for each process at exec() time, with these keys being 1819 context-switched along with the process. 1820 1821 The feature is detected at runtime. If the feature is not present in 1822 hardware it will not be advertised to userspace/KVM guest nor will it 1823 be enabled. 1824 1825 If the feature is present on the boot CPU but not on a late CPU, then 1826 the late CPU will be parked. Also, if the boot CPU does not have 1827 address auth and the late CPU has then the late CPU will still boot 1828 but with the feature disabled. On such a system, this option should 1829 not be selected. 1830 1831config ARM64_PTR_AUTH_KERNEL 1832 bool "Use pointer authentication for kernel" 1833 default y 1834 depends on ARM64_PTR_AUTH 1835 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1836 # Modern compilers insert a .note.gnu.property section note for PAC 1837 # which is only understood by binutils starting with version 2.33.1. 1838 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1839 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1840 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1841 help 1842 If the compiler supports the -mbranch-protection or 1843 -msign-return-address flag (e.g. GCC 7 or later), then this option 1844 will cause the kernel itself to be compiled with return address 1845 protection. In this case, and if the target hardware is known to 1846 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1847 disabled with minimal loss of protection. 1848 1849 This feature works with FUNCTION_GRAPH_TRACER option only if 1850 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1851 1852config CC_HAS_BRANCH_PROT_PAC_RET 1853 # GCC 9 or later, clang 8 or later 1854 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1855 1856config CC_HAS_SIGN_RETURN_ADDRESS 1857 # GCC 7, 8 1858 def_bool $(cc-option,-msign-return-address=all) 1859 1860config AS_HAS_PAC 1861 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1862 1863config AS_HAS_CFI_NEGATE_RA_STATE 1864 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1865 1866endmenu # "ARMv8.3 architectural features" 1867 1868menu "ARMv8.4 architectural features" 1869 1870config ARM64_AMU_EXTN 1871 bool "Enable support for the Activity Monitors Unit CPU extension" 1872 default y 1873 help 1874 The activity monitors extension is an optional extension introduced 1875 by the ARMv8.4 CPU architecture. This enables support for version 1 1876 of the activity monitors architecture, AMUv1. 1877 1878 To enable the use of this extension on CPUs that implement it, say Y. 1879 1880 Note that for architectural reasons, firmware _must_ implement AMU 1881 support when running on CPUs that present the activity monitors 1882 extension. The required support is present in: 1883 * Version 1.5 and later of the ARM Trusted Firmware 1884 1885 For kernels that have this configuration enabled but boot with broken 1886 firmware, you may need to say N here until the firmware is fixed. 1887 Otherwise you may experience firmware panics or lockups when 1888 accessing the counter registers. Even if you are not observing these 1889 symptoms, the values returned by the register reads might not 1890 correctly reflect reality. Most commonly, the value read will be 0, 1891 indicating that the counter is not enabled. 1892 1893config AS_HAS_ARMV8_4 1894 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1895 1896config ARM64_TLB_RANGE 1897 bool "Enable support for tlbi range feature" 1898 default y 1899 depends on AS_HAS_ARMV8_4 1900 help 1901 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1902 range of input addresses. 1903 1904 The feature introduces new assembly instructions, and they were 1905 support when binutils >= 2.30. 1906 1907endmenu # "ARMv8.4 architectural features" 1908 1909menu "ARMv8.5 architectural features" 1910 1911config AS_HAS_ARMV8_5 1912 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1913 1914config ARM64_BTI 1915 bool "Branch Target Identification support" 1916 default y 1917 help 1918 Branch Target Identification (part of the ARMv8.5 Extensions) 1919 provides a mechanism to limit the set of locations to which computed 1920 branch instructions such as BR or BLR can jump. 1921 1922 To make use of BTI on CPUs that support it, say Y. 1923 1924 BTI is intended to provide complementary protection to other control 1925 flow integrity protection mechanisms, such as the Pointer 1926 authentication mechanism provided as part of the ARMv8.3 Extensions. 1927 For this reason, it does not make sense to enable this option without 1928 also enabling support for pointer authentication. Thus, when 1929 enabling this option you should also select ARM64_PTR_AUTH=y. 1930 1931 Userspace binaries must also be specifically compiled to make use of 1932 this mechanism. If you say N here or the hardware does not support 1933 BTI, such binaries can still run, but you get no additional 1934 enforcement of branch destinations. 1935 1936config ARM64_BTI_KERNEL 1937 bool "Use Branch Target Identification for kernel" 1938 default y 1939 depends on ARM64_BTI 1940 depends on ARM64_PTR_AUTH_KERNEL 1941 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1942 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1943 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1944 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 1945 depends on !CC_IS_GCC 1946 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1947 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1948 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1949 help 1950 Build the kernel with Branch Target Identification annotations 1951 and enable enforcement of this for kernel code. When this option 1952 is enabled and the system supports BTI all kernel code including 1953 modular code must have BTI enabled. 1954 1955config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1956 # GCC 9 or later, clang 8 or later 1957 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1958 1959config ARM64_E0PD 1960 bool "Enable support for E0PD" 1961 default y 1962 help 1963 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1964 that EL0 accesses made via TTBR1 always fault in constant time, 1965 providing similar benefits to KASLR as those provided by KPTI, but 1966 with lower overhead and without disrupting legitimate access to 1967 kernel memory such as SPE. 1968 1969 This option enables E0PD for TTBR1 where available. 1970 1971config ARM64_AS_HAS_MTE 1972 # Initial support for MTE went in binutils 2.32.0, checked with 1973 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1974 # as a late addition to the final architecture spec (LDGM/STGM) 1975 # is only supported in the newer 2.32.x and 2.33 binutils 1976 # versions, hence the extra "stgm" instruction check below. 1977 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1978 1979config ARM64_MTE 1980 bool "Memory Tagging Extension support" 1981 default y 1982 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1983 depends on AS_HAS_ARMV8_5 1984 depends on AS_HAS_LSE_ATOMICS 1985 # Required for tag checking in the uaccess routines 1986 depends on ARM64_PAN 1987 select ARCH_HAS_SUBPAGE_FAULTS 1988 select ARCH_USES_HIGH_VMA_FLAGS 1989 select ARCH_USES_PG_ARCH_X 1990 help 1991 Memory Tagging (part of the ARMv8.5 Extensions) provides 1992 architectural support for run-time, always-on detection of 1993 various classes of memory error to aid with software debugging 1994 to eliminate vulnerabilities arising from memory-unsafe 1995 languages. 1996 1997 This option enables the support for the Memory Tagging 1998 Extension at EL0 (i.e. for userspace). 1999 2000 Selecting this option allows the feature to be detected at 2001 runtime. Any secondary CPU not implementing this feature will 2002 not be allowed a late bring-up. 2003 2004 Userspace binaries that want to use this feature must 2005 explicitly opt in. The mechanism for the userspace is 2006 described in: 2007 2008 Documentation/arm64/memory-tagging-extension.rst. 2009 2010endmenu # "ARMv8.5 architectural features" 2011 2012menu "ARMv8.7 architectural features" 2013 2014config ARM64_EPAN 2015 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2016 default y 2017 depends on ARM64_PAN 2018 help 2019 Enhanced Privileged Access Never (EPAN) allows Privileged 2020 Access Never to be used with Execute-only mappings. 2021 2022 The feature is detected at runtime, and will remain disabled 2023 if the cpu does not implement the feature. 2024endmenu # "ARMv8.7 architectural features" 2025 2026config ARM64_SVE 2027 bool "ARM Scalable Vector Extension support" 2028 default y 2029 help 2030 The Scalable Vector Extension (SVE) is an extension to the AArch64 2031 execution state which complements and extends the SIMD functionality 2032 of the base architecture to support much larger vectors and to enable 2033 additional vectorisation opportunities. 2034 2035 To enable use of this extension on CPUs that implement it, say Y. 2036 2037 On CPUs that support the SVE2 extensions, this option will enable 2038 those too. 2039 2040 Note that for architectural reasons, firmware _must_ implement SVE 2041 support when running on SVE capable hardware. The required support 2042 is present in: 2043 2044 * version 1.5 and later of the ARM Trusted Firmware 2045 * the AArch64 boot wrapper since commit 5e1261e08abf 2046 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2047 2048 For other firmware implementations, consult the firmware documentation 2049 or vendor. 2050 2051 If you need the kernel to boot on SVE-capable hardware with broken 2052 firmware, you may need to say N here until you get your firmware 2053 fixed. Otherwise, you may experience firmware panics or lockups when 2054 booting the kernel. If unsure and you are not observing these 2055 symptoms, you should assume that it is safe to say Y. 2056 2057config ARM64_SME 2058 bool "ARM Scalable Matrix Extension support" 2059 default y 2060 depends on ARM64_SVE 2061 help 2062 The Scalable Matrix Extension (SME) is an extension to the AArch64 2063 execution state which utilises a substantial subset of the SVE 2064 instruction set, together with the addition of new architectural 2065 register state capable of holding two dimensional matrix tiles to 2066 enable various matrix operations. 2067 2068config ARM64_MODULE_PLTS 2069 bool "Use PLTs to allow module memory to spill over into vmalloc area" 2070 depends on MODULES 2071 select HAVE_MOD_ARCH_SPECIFIC 2072 help 2073 Allocate PLTs when loading modules so that jumps and calls whose 2074 targets are too far away for their relative offsets to be encoded 2075 in the instructions themselves can be bounced via veneers in the 2076 module's PLT. This allows modules to be allocated in the generic 2077 vmalloc area after the dedicated module memory area has been 2078 exhausted. 2079 2080 When running with address space randomization (KASLR), the module 2081 region itself may be too far away for ordinary relative jumps and 2082 calls, and so in that case, module PLTs are required and cannot be 2083 disabled. 2084 2085 Specific errata workaround(s) might also force module PLTs to be 2086 enabled (ARM64_ERRATUM_843419). 2087 2088config ARM64_PSEUDO_NMI 2089 bool "Support for NMI-like interrupts" 2090 select ARM_GIC_V3 2091 help 2092 Adds support for mimicking Non-Maskable Interrupts through the use of 2093 GIC interrupt priority. This support requires version 3 or later of 2094 ARM GIC. 2095 2096 This high priority configuration for interrupts needs to be 2097 explicitly enabled by setting the kernel parameter 2098 "irqchip.gicv3_pseudo_nmi" to 1. 2099 2100 If unsure, say N 2101 2102if ARM64_PSEUDO_NMI 2103config ARM64_DEBUG_PRIORITY_MASKING 2104 bool "Debug interrupt priority masking" 2105 help 2106 This adds runtime checks to functions enabling/disabling 2107 interrupts when using priority masking. The additional checks verify 2108 the validity of ICC_PMR_EL1 when calling concerned functions. 2109 2110 If unsure, say N 2111endif # ARM64_PSEUDO_NMI 2112 2113config RELOCATABLE 2114 bool "Build a relocatable kernel image" if EXPERT 2115 select ARCH_HAS_RELR 2116 default y 2117 help 2118 This builds the kernel as a Position Independent Executable (PIE), 2119 which retains all relocation metadata required to relocate the 2120 kernel binary at runtime to a different virtual address than the 2121 address it was linked at. 2122 Since AArch64 uses the RELA relocation format, this requires a 2123 relocation pass at runtime even if the kernel is loaded at the 2124 same address it was linked at. 2125 2126config RANDOMIZE_BASE 2127 bool "Randomize the address of the kernel image" 2128 select ARM64_MODULE_PLTS if MODULES 2129 select RELOCATABLE 2130 help 2131 Randomizes the virtual address at which the kernel image is 2132 loaded, as a security feature that deters exploit attempts 2133 relying on knowledge of the location of kernel internals. 2134 2135 It is the bootloader's job to provide entropy, by passing a 2136 random u64 value in /chosen/kaslr-seed at kernel entry. 2137 2138 When booting via the UEFI stub, it will invoke the firmware's 2139 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2140 to the kernel proper. In addition, it will randomise the physical 2141 location of the kernel Image as well. 2142 2143 If unsure, say N. 2144 2145config RANDOMIZE_MODULE_REGION_FULL 2146 bool "Randomize the module region over a 2 GB range" 2147 depends on RANDOMIZE_BASE 2148 default y 2149 help 2150 Randomizes the location of the module region inside a 2 GB window 2151 covering the core kernel. This way, it is less likely for modules 2152 to leak information about the location of core kernel data structures 2153 but it does imply that function calls between modules and the core 2154 kernel will need to be resolved via veneers in the module PLT. 2155 2156 When this option is not set, the module region will be randomized over 2157 a limited range that contains the [_stext, _etext] interval of the 2158 core kernel, so branch relocations are almost always in range unless 2159 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2160 particular case of region exhaustion, modules might be able to fall 2161 back to a larger 2GB area. 2162 2163config CC_HAVE_STACKPROTECTOR_SYSREG 2164 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2165 2166config STACKPROTECTOR_PER_TASK 2167 def_bool y 2168 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2169 2170config UNWIND_PATCH_PAC_INTO_SCS 2171 bool "Enable shadow call stack dynamically using code patching" 2172 # needs Clang with https://reviews.llvm.org/D111780 incorporated 2173 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2174 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2175 depends on SHADOW_CALL_STACK 2176 select UNWIND_TABLES 2177 select DYNAMIC_SCS 2178 2179endmenu # "Kernel Features" 2180 2181menu "Boot options" 2182 2183config ARM64_ACPI_PARKING_PROTOCOL 2184 bool "Enable support for the ARM64 ACPI parking protocol" 2185 depends on ACPI 2186 help 2187 Enable support for the ARM64 ACPI parking protocol. If disabled 2188 the kernel will not allow booting through the ARM64 ACPI parking 2189 protocol even if the corresponding data is present in the ACPI 2190 MADT table. 2191 2192config CMDLINE 2193 string "Default kernel command string" 2194 default "" 2195 help 2196 Provide a set of default command-line options at build time by 2197 entering them here. As a minimum, you should specify the the 2198 root device (e.g. root=/dev/nfs). 2199 2200choice 2201 prompt "Kernel command line type" if CMDLINE != "" 2202 default CMDLINE_FROM_BOOTLOADER 2203 help 2204 Choose how the kernel will handle the provided default kernel 2205 command line string. 2206 2207config CMDLINE_FROM_BOOTLOADER 2208 bool "Use bootloader kernel arguments if available" 2209 help 2210 Uses the command-line options passed by the boot loader. If 2211 the boot loader doesn't provide any, the default kernel command 2212 string provided in CMDLINE will be used. 2213 2214config CMDLINE_FORCE 2215 bool "Always use the default kernel command string" 2216 help 2217 Always use the default kernel command string, even if the boot 2218 loader passes other arguments to the kernel. 2219 This is useful if you cannot or don't want to change the 2220 command-line options your boot loader passes to the kernel. 2221 2222endchoice 2223 2224config EFI_STUB 2225 bool 2226 2227config EFI 2228 bool "UEFI runtime support" 2229 depends on OF && !CPU_BIG_ENDIAN 2230 depends on KERNEL_MODE_NEON 2231 select ARCH_SUPPORTS_ACPI 2232 select LIBFDT 2233 select UCS2_STRING 2234 select EFI_PARAMS_FROM_FDT 2235 select EFI_RUNTIME_WRAPPERS 2236 select EFI_STUB 2237 select EFI_GENERIC_STUB 2238 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2239 default y 2240 help 2241 This option provides support for runtime services provided 2242 by UEFI firmware (such as non-volatile variables, realtime 2243 clock, and platform reset). A UEFI stub is also provided to 2244 allow the kernel to be booted as an EFI application. This 2245 is only useful on systems that have UEFI firmware. 2246 2247config DMI 2248 bool "Enable support for SMBIOS (DMI) tables" 2249 depends on EFI 2250 default y 2251 help 2252 This enables SMBIOS/DMI feature for systems. 2253 2254 This option is only useful on systems that have UEFI firmware. 2255 However, even with this option, the resultant kernel should 2256 continue to boot on existing non-UEFI platforms. 2257 2258endmenu # "Boot options" 2259 2260menu "Power management options" 2261 2262source "kernel/power/Kconfig" 2263 2264config ARCH_HIBERNATION_POSSIBLE 2265 def_bool y 2266 depends on CPU_PM 2267 2268config ARCH_HIBERNATION_HEADER 2269 def_bool y 2270 depends on HIBERNATION 2271 2272config ARCH_SUSPEND_POSSIBLE 2273 def_bool y 2274 2275endmenu # "Power management options" 2276 2277menu "CPU Power Management" 2278 2279source "drivers/cpuidle/Kconfig" 2280 2281source "drivers/cpufreq/Kconfig" 2282 2283endmenu # "CPU Power Management" 2284 2285source "drivers/acpi/Kconfig" 2286 2287source "arch/arm64/kvm/Kconfig" 2288 2289