1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_INLINE_READ_LOCK if !PREEMPTION 52 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 55 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 59 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 63 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 67 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 73 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 77 select ARCH_KEEP_MEMBLOCK 78 select ARCH_USE_CMPXCHG_LOCKREF 79 select ARCH_USE_GNU_PROPERTY 80 select ARCH_USE_MEMTEST 81 select ARCH_USE_QUEUED_RWLOCKS 82 select ARCH_USE_QUEUED_SPINLOCKS 83 select ARCH_USE_SYM_ANNOTATIONS 84 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 85 select ARCH_SUPPORTS_HUGETLBFS 86 select ARCH_SUPPORTS_MEMORY_FAILURE 87 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 88 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 89 select ARCH_SUPPORTS_LTO_CLANG_THIN 90 select ARCH_SUPPORTS_CFI_CLANG 91 select ARCH_SUPPORTS_ATOMIC_RMW 92 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 93 select ARCH_SUPPORTS_NUMA_BALANCING 94 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 95 select ARCH_WANT_DEFAULT_BPF_JIT 96 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 97 select ARCH_WANT_FRAME_POINTERS 98 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 99 select ARCH_WANT_LD_ORPHAN_WARN 100 select ARCH_WANTS_NO_INSTR 101 select ARCH_HAS_UBSAN_SANITIZE_ALL 102 select ARM_AMBA 103 select ARM_ARCH_TIMER 104 select ARM_GIC 105 select AUDIT_ARCH_COMPAT_GENERIC 106 select ARM_GIC_V2M if PCI 107 select ARM_GIC_V3 108 select ARM_GIC_V3_ITS if PCI 109 select ARM_PSCI_FW 110 select BUILDTIME_TABLE_SORT 111 select CLONE_BACKWARDS 112 select COMMON_CLK 113 select CPU_PM if (SUSPEND || CPU_IDLE) 114 select CRC32 115 select DCACHE_WORD_ACCESS 116 select DMA_DIRECT_REMAP 117 select EDAC_SUPPORT 118 select FRAME_POINTER 119 select GENERIC_ALLOCATOR 120 select GENERIC_ARCH_TOPOLOGY 121 select GENERIC_CLOCKEVENTS_BROADCAST 122 select GENERIC_CPU_AUTOPROBE 123 select GENERIC_CPU_VULNERABILITIES 124 select GENERIC_EARLY_IOREMAP 125 select GENERIC_IDLE_POLL_SETUP 126 select GENERIC_IRQ_IPI 127 select GENERIC_IRQ_PROBE 128 select GENERIC_IRQ_SHOW 129 select GENERIC_IRQ_SHOW_LEVEL 130 select GENERIC_LIB_DEVMEM_IS_ALLOWED 131 select GENERIC_PCI_IOMAP 132 select GENERIC_PTDUMP 133 select GENERIC_SCHED_CLOCK 134 select GENERIC_SMP_IDLE_THREAD 135 select GENERIC_TIME_VSYSCALL 136 select GENERIC_GETTIMEOFDAY 137 select GENERIC_VDSO_TIME_NS 138 select HARDIRQS_SW_RESEND 139 select HAVE_MOVE_PMD 140 select HAVE_MOVE_PUD 141 select HAVE_PCI 142 select HAVE_ACPI_APEI if (ACPI && EFI) 143 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 144 select HAVE_ARCH_AUDITSYSCALL 145 select HAVE_ARCH_BITREVERSE 146 select HAVE_ARCH_COMPILER_H 147 select HAVE_ARCH_HUGE_VMAP 148 select HAVE_ARCH_JUMP_LABEL 149 select HAVE_ARCH_JUMP_LABEL_RELATIVE 150 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 151 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 152 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 153 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 154 # Some instrumentation may be unsound, hence EXPERT 155 select HAVE_ARCH_KCSAN if EXPERT 156 select HAVE_ARCH_KFENCE 157 select HAVE_ARCH_KGDB 158 select HAVE_ARCH_MMAP_RND_BITS 159 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 160 select HAVE_ARCH_PREL32_RELOCATIONS 161 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 162 select HAVE_ARCH_SECCOMP_FILTER 163 select HAVE_ARCH_STACKLEAK 164 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 165 select HAVE_ARCH_TRACEHOOK 166 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 167 select HAVE_ARCH_VMAP_STACK 168 select HAVE_ARM_SMCCC 169 select HAVE_ASM_MODVERSIONS 170 select HAVE_EBPF_JIT 171 select HAVE_C_RECORDMCOUNT 172 select HAVE_CMPXCHG_DOUBLE 173 select HAVE_CMPXCHG_LOCAL 174 select HAVE_CONTEXT_TRACKING 175 select HAVE_DEBUG_KMEMLEAK 176 select HAVE_DMA_CONTIGUOUS 177 select HAVE_DYNAMIC_FTRACE 178 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 179 if $(cc-option,-fpatchable-function-entry=2) 180 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 181 if DYNAMIC_FTRACE_WITH_REGS 182 select HAVE_EFFICIENT_UNALIGNED_ACCESS 183 select HAVE_FAST_GUP 184 select HAVE_FTRACE_MCOUNT_RECORD 185 select HAVE_FUNCTION_TRACER 186 select HAVE_FUNCTION_ERROR_INJECTION 187 select HAVE_FUNCTION_GRAPH_TRACER 188 select HAVE_GCC_PLUGINS 189 select HAVE_HW_BREAKPOINT if PERF_EVENTS 190 select HAVE_IRQ_TIME_ACCOUNTING 191 select HAVE_KVM 192 select HAVE_NMI 193 select HAVE_PATA_PLATFORM 194 select HAVE_PERF_EVENTS 195 select HAVE_PERF_REGS 196 select HAVE_PERF_USER_STACK_DUMP 197 select HAVE_PREEMPT_DYNAMIC_KEY 198 select HAVE_REGS_AND_STACK_ACCESS_API 199 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 200 select HAVE_FUNCTION_ARG_ACCESS_API 201 select MMU_GATHER_RCU_TABLE_FREE 202 select HAVE_RSEQ 203 select HAVE_STACKPROTECTOR 204 select HAVE_SYSCALL_TRACEPOINTS 205 select HAVE_KPROBES 206 select HAVE_KRETPROBES 207 select HAVE_GENERIC_VDSO 208 select IOMMU_DMA if IOMMU_SUPPORT 209 select IRQ_DOMAIN 210 select IRQ_FORCED_THREADING 211 select KASAN_VMALLOC if KASAN 212 select MODULES_USE_ELF_RELA 213 select NEED_DMA_MAP_STATE 214 select NEED_SG_DMA_LENGTH 215 select OF 216 select OF_EARLY_FLATTREE 217 select PCI_DOMAINS_GENERIC if PCI 218 select PCI_ECAM if (ACPI && PCI) 219 select PCI_SYSCALL if PCI 220 select POWER_RESET 221 select POWER_SUPPLY 222 select SPARSE_IRQ 223 select SWIOTLB 224 select SYSCTL_EXCEPTION_TRACE 225 select THREAD_INFO_IN_TASK 226 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 227 select TRACE_IRQFLAGS_SUPPORT 228 help 229 ARM 64-bit (AArch64) Linux support. 230 231config 64BIT 232 def_bool y 233 234config MMU 235 def_bool y 236 237config ARM64_PAGE_SHIFT 238 int 239 default 16 if ARM64_64K_PAGES 240 default 14 if ARM64_16K_PAGES 241 default 12 242 243config ARM64_CONT_PTE_SHIFT 244 int 245 default 5 if ARM64_64K_PAGES 246 default 7 if ARM64_16K_PAGES 247 default 4 248 249config ARM64_CONT_PMD_SHIFT 250 int 251 default 5 if ARM64_64K_PAGES 252 default 5 if ARM64_16K_PAGES 253 default 4 254 255config ARCH_MMAP_RND_BITS_MIN 256 default 14 if ARM64_64K_PAGES 257 default 16 if ARM64_16K_PAGES 258 default 18 259 260# max bits determined by the following formula: 261# VA_BITS - PAGE_SHIFT - 3 262config ARCH_MMAP_RND_BITS_MAX 263 default 19 if ARM64_VA_BITS=36 264 default 24 if ARM64_VA_BITS=39 265 default 27 if ARM64_VA_BITS=42 266 default 30 if ARM64_VA_BITS=47 267 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 268 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 269 default 33 if ARM64_VA_BITS=48 270 default 14 if ARM64_64K_PAGES 271 default 16 if ARM64_16K_PAGES 272 default 18 273 274config ARCH_MMAP_RND_COMPAT_BITS_MIN 275 default 7 if ARM64_64K_PAGES 276 default 9 if ARM64_16K_PAGES 277 default 11 278 279config ARCH_MMAP_RND_COMPAT_BITS_MAX 280 default 16 281 282config NO_IOPORT_MAP 283 def_bool y if !PCI 284 285config STACKTRACE_SUPPORT 286 def_bool y 287 288config ILLEGAL_POINTER_VALUE 289 hex 290 default 0xdead000000000000 291 292config LOCKDEP_SUPPORT 293 def_bool y 294 295config GENERIC_BUG 296 def_bool y 297 depends on BUG 298 299config GENERIC_BUG_RELATIVE_POINTERS 300 def_bool y 301 depends on GENERIC_BUG 302 303config GENERIC_HWEIGHT 304 def_bool y 305 306config GENERIC_CSUM 307 def_bool y 308 309config GENERIC_CALIBRATE_DELAY 310 def_bool y 311 312config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 313 def_bool y 314 315config SMP 316 def_bool y 317 318config KERNEL_MODE_NEON 319 def_bool y 320 321config FIX_EARLYCON_MEM 322 def_bool y 323 324config PGTABLE_LEVELS 325 int 326 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 327 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 328 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 329 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 330 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 331 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 332 333config ARCH_SUPPORTS_UPROBES 334 def_bool y 335 336config ARCH_PROC_KCORE_TEXT 337 def_bool y 338 339config BROKEN_GAS_INST 340 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 341 342config KASAN_SHADOW_OFFSET 343 hex 344 depends on KASAN_GENERIC || KASAN_SW_TAGS 345 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 346 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 347 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 348 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 349 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 350 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 351 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 352 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 353 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 354 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 355 default 0xffffffffffffffff 356 357source "arch/arm64/Kconfig.platforms" 358 359menu "Kernel Features" 360 361menu "ARM errata workarounds via the alternatives framework" 362 363config ARM64_WORKAROUND_CLEAN_CACHE 364 bool 365 366config ARM64_ERRATUM_826319 367 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 368 default y 369 select ARM64_WORKAROUND_CLEAN_CACHE 370 help 371 This option adds an alternative code sequence to work around ARM 372 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 373 AXI master interface and an L2 cache. 374 375 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 376 and is unable to accept a certain write via this interface, it will 377 not progress on read data presented on the read data channel and the 378 system can deadlock. 379 380 The workaround promotes data cache clean instructions to 381 data cache clean-and-invalidate. 382 Please note that this does not necessarily enable the workaround, 383 as it depends on the alternative framework, which will only patch 384 the kernel if an affected CPU is detected. 385 386 If unsure, say Y. 387 388config ARM64_ERRATUM_827319 389 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 390 default y 391 select ARM64_WORKAROUND_CLEAN_CACHE 392 help 393 This option adds an alternative code sequence to work around ARM 394 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 395 master interface and an L2 cache. 396 397 Under certain conditions this erratum can cause a clean line eviction 398 to occur at the same time as another transaction to the same address 399 on the AMBA 5 CHI interface, which can cause data corruption if the 400 interconnect reorders the two transactions. 401 402 The workaround promotes data cache clean instructions to 403 data cache clean-and-invalidate. 404 Please note that this does not necessarily enable the workaround, 405 as it depends on the alternative framework, which will only patch 406 the kernel if an affected CPU is detected. 407 408 If unsure, say Y. 409 410config ARM64_ERRATUM_824069 411 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 412 default y 413 select ARM64_WORKAROUND_CLEAN_CACHE 414 help 415 This option adds an alternative code sequence to work around ARM 416 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 417 to a coherent interconnect. 418 419 If a Cortex-A53 processor is executing a store or prefetch for 420 write instruction at the same time as a processor in another 421 cluster is executing a cache maintenance operation to the same 422 address, then this erratum might cause a clean cache line to be 423 incorrectly marked as dirty. 424 425 The workaround promotes data cache clean instructions to 426 data cache clean-and-invalidate. 427 Please note that this option does not necessarily enable the 428 workaround, as it depends on the alternative framework, which will 429 only patch the kernel if an affected CPU is detected. 430 431 If unsure, say Y. 432 433config ARM64_ERRATUM_819472 434 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 435 default y 436 select ARM64_WORKAROUND_CLEAN_CACHE 437 help 438 This option adds an alternative code sequence to work around ARM 439 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 440 present when it is connected to a coherent interconnect. 441 442 If the processor is executing a load and store exclusive sequence at 443 the same time as a processor in another cluster is executing a cache 444 maintenance operation to the same address, then this erratum might 445 cause data corruption. 446 447 The workaround promotes data cache clean instructions to 448 data cache clean-and-invalidate. 449 Please note that this does not necessarily enable the workaround, 450 as it depends on the alternative framework, which will only patch 451 the kernel if an affected CPU is detected. 452 453 If unsure, say Y. 454 455config ARM64_ERRATUM_832075 456 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 457 default y 458 help 459 This option adds an alternative code sequence to work around ARM 460 erratum 832075 on Cortex-A57 parts up to r1p2. 461 462 Affected Cortex-A57 parts might deadlock when exclusive load/store 463 instructions to Write-Back memory are mixed with Device loads. 464 465 The workaround is to promote device loads to use Load-Acquire 466 semantics. 467 Please note that this does not necessarily enable the workaround, 468 as it depends on the alternative framework, which will only patch 469 the kernel if an affected CPU is detected. 470 471 If unsure, say Y. 472 473config ARM64_ERRATUM_834220 474 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 475 depends on KVM 476 default y 477 help 478 This option adds an alternative code sequence to work around ARM 479 erratum 834220 on Cortex-A57 parts up to r1p2. 480 481 Affected Cortex-A57 parts might report a Stage 2 translation 482 fault as the result of a Stage 1 fault for load crossing a 483 page boundary when there is a permission or device memory 484 alignment fault at Stage 1 and a translation fault at Stage 2. 485 486 The workaround is to verify that the Stage 1 translation 487 doesn't generate a fault before handling the Stage 2 fault. 488 Please note that this does not necessarily enable the workaround, 489 as it depends on the alternative framework, which will only patch 490 the kernel if an affected CPU is detected. 491 492 If unsure, say Y. 493 494config ARM64_ERRATUM_845719 495 bool "Cortex-A53: 845719: a load might read incorrect data" 496 depends on COMPAT 497 default y 498 help 499 This option adds an alternative code sequence to work around ARM 500 erratum 845719 on Cortex-A53 parts up to r0p4. 501 502 When running a compat (AArch32) userspace on an affected Cortex-A53 503 part, a load at EL0 from a virtual address that matches the bottom 32 504 bits of the virtual address used by a recent load at (AArch64) EL1 505 might return incorrect data. 506 507 The workaround is to write the contextidr_el1 register on exception 508 return to a 32-bit task. 509 Please note that this does not necessarily enable the workaround, 510 as it depends on the alternative framework, which will only patch 511 the kernel if an affected CPU is detected. 512 513 If unsure, say Y. 514 515config ARM64_ERRATUM_843419 516 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 517 default y 518 select ARM64_MODULE_PLTS if MODULES 519 help 520 This option links the kernel with '--fix-cortex-a53-843419' and 521 enables PLT support to replace certain ADRP instructions, which can 522 cause subsequent memory accesses to use an incorrect address on 523 Cortex-A53 parts up to r0p4. 524 525 If unsure, say Y. 526 527config ARM64_LD_HAS_FIX_ERRATUM_843419 528 def_bool $(ld-option,--fix-cortex-a53-843419) 529 530config ARM64_ERRATUM_1024718 531 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 532 default y 533 help 534 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 535 536 Affected Cortex-A55 cores (all revisions) could cause incorrect 537 update of the hardware dirty bit when the DBM/AP bits are updated 538 without a break-before-make. The workaround is to disable the usage 539 of hardware DBM locally on the affected cores. CPUs not affected by 540 this erratum will continue to use the feature. 541 542 If unsure, say Y. 543 544config ARM64_ERRATUM_1418040 545 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 546 default y 547 depends on COMPAT 548 help 549 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 550 errata 1188873 and 1418040. 551 552 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 553 cause register corruption when accessing the timer registers 554 from AArch32 userspace. 555 556 If unsure, say Y. 557 558config ARM64_WORKAROUND_SPECULATIVE_AT 559 bool 560 561config ARM64_ERRATUM_1165522 562 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 563 default y 564 select ARM64_WORKAROUND_SPECULATIVE_AT 565 help 566 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 567 568 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 569 corrupted TLBs by speculating an AT instruction during a guest 570 context switch. 571 572 If unsure, say Y. 573 574config ARM64_ERRATUM_1319367 575 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 576 default y 577 select ARM64_WORKAROUND_SPECULATIVE_AT 578 help 579 This option adds work arounds for ARM Cortex-A57 erratum 1319537 580 and A72 erratum 1319367 581 582 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 583 speculating an AT instruction during a guest context switch. 584 585 If unsure, say Y. 586 587config ARM64_ERRATUM_1530923 588 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 589 default y 590 select ARM64_WORKAROUND_SPECULATIVE_AT 591 help 592 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 593 594 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 595 corrupted TLBs by speculating an AT instruction during a guest 596 context switch. 597 598 If unsure, say Y. 599 600config ARM64_WORKAROUND_REPEAT_TLBI 601 bool 602 603config ARM64_ERRATUM_1286807 604 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 605 default y 606 select ARM64_WORKAROUND_REPEAT_TLBI 607 help 608 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 609 610 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 611 address for a cacheable mapping of a location is being 612 accessed by a core while another core is remapping the virtual 613 address to a new physical page using the recommended 614 break-before-make sequence, then under very rare circumstances 615 TLBI+DSB completes before a read using the translation being 616 invalidated has been observed by other observers. The 617 workaround repeats the TLBI+DSB operation. 618 619config ARM64_ERRATUM_1463225 620 bool "Cortex-A76: Software Step might prevent interrupt recognition" 621 default y 622 help 623 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 624 625 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 626 of a system call instruction (SVC) can prevent recognition of 627 subsequent interrupts when software stepping is disabled in the 628 exception handler of the system call and either kernel debugging 629 is enabled or VHE is in use. 630 631 Work around the erratum by triggering a dummy step exception 632 when handling a system call from a task that is being stepped 633 in a VHE configuration of the kernel. 634 635 If unsure, say Y. 636 637config ARM64_ERRATUM_1542419 638 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 639 default y 640 help 641 This option adds a workaround for ARM Neoverse-N1 erratum 642 1542419. 643 644 Affected Neoverse-N1 cores could execute a stale instruction when 645 modified by another CPU. The workaround depends on a firmware 646 counterpart. 647 648 Workaround the issue by hiding the DIC feature from EL0. This 649 forces user-space to perform cache maintenance. 650 651 If unsure, say Y. 652 653config ARM64_ERRATUM_1508412 654 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 655 default y 656 help 657 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 658 659 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 660 of a store-exclusive or read of PAR_EL1 and a load with device or 661 non-cacheable memory attributes. The workaround depends on a firmware 662 counterpart. 663 664 KVM guests must also have the workaround implemented or they can 665 deadlock the system. 666 667 Work around the issue by inserting DMB SY barriers around PAR_EL1 668 register reads and warning KVM users. The DMB barrier is sufficient 669 to prevent a speculative PAR_EL1 read. 670 671 If unsure, say Y. 672 673config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 674 bool 675 676config ARM64_ERRATUM_2051678 677 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 678 default y 679 help 680 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 681 Affected Coretex-A510 might not respect the ordering rules for 682 hardware update of the page table's dirty bit. The workaround 683 is to not enable the feature on affected CPUs. 684 685 If unsure, say Y. 686 687config ARM64_ERRATUM_2077057 688 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 689 default y 690 help 691 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 692 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 693 expected, but a Pointer Authentication trap is taken instead. The 694 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 695 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 696 697 This can only happen when EL2 is stepping EL1. 698 699 When these conditions occur, the SPSR_EL2 value is unchanged from the 700 previous guest entry, and can be restored from the in-memory copy. 701 702 If unsure, say Y. 703 704config ARM64_ERRATUM_2119858 705 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 706 default y 707 depends on CORESIGHT_TRBE 708 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 709 help 710 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 711 712 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 713 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 714 the event of a WRAP event. 715 716 Work around the issue by always making sure we move the TRBPTR_EL1 by 717 256 bytes before enabling the buffer and filling the first 256 bytes of 718 the buffer with ETM ignore packets upon disabling. 719 720 If unsure, say Y. 721 722config ARM64_ERRATUM_2139208 723 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 724 default y 725 depends on CORESIGHT_TRBE 726 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 727 help 728 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 729 730 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 731 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 732 the event of a WRAP event. 733 734 Work around the issue by always making sure we move the TRBPTR_EL1 by 735 256 bytes before enabling the buffer and filling the first 256 bytes of 736 the buffer with ETM ignore packets upon disabling. 737 738 If unsure, say Y. 739 740config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 741 bool 742 743config ARM64_ERRATUM_2054223 744 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 745 default y 746 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 747 help 748 Enable workaround for ARM Cortex-A710 erratum 2054223 749 750 Affected cores may fail to flush the trace data on a TSB instruction, when 751 the PE is in trace prohibited state. This will cause losing a few bytes 752 of the trace cached. 753 754 Workaround is to issue two TSB consecutively on affected cores. 755 756 If unsure, say Y. 757 758config ARM64_ERRATUM_2067961 759 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 760 default y 761 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 762 help 763 Enable workaround for ARM Neoverse-N2 erratum 2067961 764 765 Affected cores may fail to flush the trace data on a TSB instruction, when 766 the PE is in trace prohibited state. This will cause losing a few bytes 767 of the trace cached. 768 769 Workaround is to issue two TSB consecutively on affected cores. 770 771 If unsure, say Y. 772 773config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 774 bool 775 776config ARM64_ERRATUM_2253138 777 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 778 depends on CORESIGHT_TRBE 779 default y 780 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 781 help 782 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 783 784 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 785 for TRBE. Under some conditions, the TRBE might generate a write to the next 786 virtually addressed page following the last page of the TRBE address space 787 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 788 789 Work around this in the driver by always making sure that there is a 790 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 791 792 If unsure, say Y. 793 794config ARM64_ERRATUM_2224489 795 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 796 depends on CORESIGHT_TRBE 797 default y 798 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 799 help 800 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 801 802 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 803 for TRBE. Under some conditions, the TRBE might generate a write to the next 804 virtually addressed page following the last page of the TRBE address space 805 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 806 807 Work around this in the driver by always making sure that there is a 808 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 809 810 If unsure, say Y. 811 812config ARM64_ERRATUM_2064142 813 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 814 depends on CORESIGHT_TRBE 815 default y 816 help 817 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 818 819 Affected Cortex-A510 core might fail to write into system registers after the 820 TRBE has been disabled. Under some conditions after the TRBE has been disabled 821 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 822 and TRBTRG_EL1 will be ignored and will not be effected. 823 824 Work around this in the driver by executing TSB CSYNC and DSB after collection 825 is stopped and before performing a system register write to one of the affected 826 registers. 827 828 If unsure, say Y. 829 830config ARM64_ERRATUM_2038923 831 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 832 depends on CORESIGHT_TRBE 833 default y 834 help 835 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 836 837 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 838 prohibited within the CPU. As a result, the trace buffer or trace buffer state 839 might be corrupted. This happens after TRBE buffer has been enabled by setting 840 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 841 execution changes from a context, in which trace is prohibited to one where it 842 isn't, or vice versa. In these mentioned conditions, the view of whether trace 843 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 844 the trace buffer state might be corrupted. 845 846 Work around this in the driver by preventing an inconsistent view of whether the 847 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 848 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 849 two ISB instructions if no ERET is to take place. 850 851 If unsure, say Y. 852 853config ARM64_ERRATUM_1902691 854 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 855 depends on CORESIGHT_TRBE 856 default y 857 help 858 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 859 860 Affected Cortex-A510 core might cause trace data corruption, when being written 861 into the memory. Effectively TRBE is broken and hence cannot be used to capture 862 trace data. 863 864 Work around this problem in the driver by just preventing TRBE initialization on 865 affected cpus. The firmware must have disabled the access to TRBE for the kernel 866 on such implementations. This will cover the kernel for any firmware that doesn't 867 do this already. 868 869 If unsure, say Y. 870 871config CAVIUM_ERRATUM_22375 872 bool "Cavium erratum 22375, 24313" 873 default y 874 help 875 Enable workaround for errata 22375 and 24313. 876 877 This implements two gicv3-its errata workarounds for ThunderX. Both 878 with a small impact affecting only ITS table allocation. 879 880 erratum 22375: only alloc 8MB table size 881 erratum 24313: ignore memory access type 882 883 The fixes are in ITS initialization and basically ignore memory access 884 type and table size provided by the TYPER and BASER registers. 885 886 If unsure, say Y. 887 888config CAVIUM_ERRATUM_23144 889 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 890 depends on NUMA 891 default y 892 help 893 ITS SYNC command hang for cross node io and collections/cpu mapping. 894 895 If unsure, say Y. 896 897config CAVIUM_ERRATUM_23154 898 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 899 default y 900 help 901 The ThunderX GICv3 implementation requires a modified version for 902 reading the IAR status to ensure data synchronization 903 (access to icc_iar1_el1 is not sync'ed before and after). 904 905 It also suffers from erratum 38545 (also present on Marvell's 906 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 907 spuriously presented to the CPU interface. 908 909 If unsure, say Y. 910 911config CAVIUM_ERRATUM_27456 912 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 913 default y 914 help 915 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 916 instructions may cause the icache to become corrupted if it 917 contains data for a non-current ASID. The fix is to 918 invalidate the icache when changing the mm context. 919 920 If unsure, say Y. 921 922config CAVIUM_ERRATUM_30115 923 bool "Cavium erratum 30115: Guest may disable interrupts in host" 924 default y 925 help 926 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 927 1.2, and T83 Pass 1.0, KVM guest execution may disable 928 interrupts in host. Trapping both GICv3 group-0 and group-1 929 accesses sidesteps the issue. 930 931 If unsure, say Y. 932 933config CAVIUM_TX2_ERRATUM_219 934 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 935 default y 936 help 937 On Cavium ThunderX2, a load, store or prefetch instruction between a 938 TTBR update and the corresponding context synchronizing operation can 939 cause a spurious Data Abort to be delivered to any hardware thread in 940 the CPU core. 941 942 Work around the issue by avoiding the problematic code sequence and 943 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 944 trap handler performs the corresponding register access, skips the 945 instruction and ensures context synchronization by virtue of the 946 exception return. 947 948 If unsure, say Y. 949 950config FUJITSU_ERRATUM_010001 951 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 952 default y 953 help 954 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 955 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 956 accesses may cause undefined fault (Data abort, DFSC=0b111111). 957 This fault occurs under a specific hardware condition when a 958 load/store instruction performs an address translation using: 959 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 960 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 961 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 962 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 963 964 The workaround is to ensure these bits are clear in TCR_ELx. 965 The workaround only affects the Fujitsu-A64FX. 966 967 If unsure, say Y. 968 969config HISILICON_ERRATUM_161600802 970 bool "Hip07 161600802: Erroneous redistributor VLPI base" 971 default y 972 help 973 The HiSilicon Hip07 SoC uses the wrong redistributor base 974 when issued ITS commands such as VMOVP and VMAPP, and requires 975 a 128kB offset to be applied to the target address in this commands. 976 977 If unsure, say Y. 978 979config QCOM_FALKOR_ERRATUM_1003 980 bool "Falkor E1003: Incorrect translation due to ASID change" 981 default y 982 help 983 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 984 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 985 in TTBR1_EL1, this situation only occurs in the entry trampoline and 986 then only for entries in the walk cache, since the leaf translation 987 is unchanged. Work around the erratum by invalidating the walk cache 988 entries for the trampoline before entering the kernel proper. 989 990config QCOM_FALKOR_ERRATUM_1009 991 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 992 default y 993 select ARM64_WORKAROUND_REPEAT_TLBI 994 help 995 On Falkor v1, the CPU may prematurely complete a DSB following a 996 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 997 one more time to fix the issue. 998 999 If unsure, say Y. 1000 1001config QCOM_QDF2400_ERRATUM_0065 1002 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1003 default y 1004 help 1005 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1006 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1007 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1008 1009 If unsure, say Y. 1010 1011config QCOM_FALKOR_ERRATUM_E1041 1012 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1013 default y 1014 help 1015 Falkor CPU may speculatively fetch instructions from an improper 1016 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1017 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1018 1019 If unsure, say Y. 1020 1021config NVIDIA_CARMEL_CNP_ERRATUM 1022 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1023 default y 1024 help 1025 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1026 invalidate shared TLB entries installed by a different core, as it would 1027 on standard ARM cores. 1028 1029 If unsure, say Y. 1030 1031config SOCIONEXT_SYNQUACER_PREITS 1032 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1033 default y 1034 help 1035 Socionext Synquacer SoCs implement a separate h/w block to generate 1036 MSI doorbell writes with non-zero values for the device ID. 1037 1038 If unsure, say Y. 1039 1040endmenu 1041 1042 1043choice 1044 prompt "Page size" 1045 default ARM64_4K_PAGES 1046 help 1047 Page size (translation granule) configuration. 1048 1049config ARM64_4K_PAGES 1050 bool "4KB" 1051 help 1052 This feature enables 4KB pages support. 1053 1054config ARM64_16K_PAGES 1055 bool "16KB" 1056 help 1057 The system will use 16KB pages support. AArch32 emulation 1058 requires applications compiled with 16K (or a multiple of 16K) 1059 aligned segments. 1060 1061config ARM64_64K_PAGES 1062 bool "64KB" 1063 help 1064 This feature enables 64KB pages support (4KB by default) 1065 allowing only two levels of page tables and faster TLB 1066 look-up. AArch32 emulation requires applications compiled 1067 with 64K aligned segments. 1068 1069endchoice 1070 1071choice 1072 prompt "Virtual address space size" 1073 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1074 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1075 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1076 help 1077 Allows choosing one of multiple possible virtual address 1078 space sizes. The level of translation table is determined by 1079 a combination of page size and virtual address space size. 1080 1081config ARM64_VA_BITS_36 1082 bool "36-bit" if EXPERT 1083 depends on ARM64_16K_PAGES 1084 1085config ARM64_VA_BITS_39 1086 bool "39-bit" 1087 depends on ARM64_4K_PAGES 1088 1089config ARM64_VA_BITS_42 1090 bool "42-bit" 1091 depends on ARM64_64K_PAGES 1092 1093config ARM64_VA_BITS_47 1094 bool "47-bit" 1095 depends on ARM64_16K_PAGES 1096 1097config ARM64_VA_BITS_48 1098 bool "48-bit" 1099 1100config ARM64_VA_BITS_52 1101 bool "52-bit" 1102 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1103 help 1104 Enable 52-bit virtual addressing for userspace when explicitly 1105 requested via a hint to mmap(). The kernel will also use 52-bit 1106 virtual addresses for its own mappings (provided HW support for 1107 this feature is available, otherwise it reverts to 48-bit). 1108 1109 NOTE: Enabling 52-bit virtual addressing in conjunction with 1110 ARMv8.3 Pointer Authentication will result in the PAC being 1111 reduced from 7 bits to 3 bits, which may have a significant 1112 impact on its susceptibility to brute-force attacks. 1113 1114 If unsure, select 48-bit virtual addressing instead. 1115 1116endchoice 1117 1118config ARM64_FORCE_52BIT 1119 bool "Force 52-bit virtual addresses for userspace" 1120 depends on ARM64_VA_BITS_52 && EXPERT 1121 help 1122 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1123 to maintain compatibility with older software by providing 48-bit VAs 1124 unless a hint is supplied to mmap. 1125 1126 This configuration option disables the 48-bit compatibility logic, and 1127 forces all userspace addresses to be 52-bit on HW that supports it. One 1128 should only enable this configuration option for stress testing userspace 1129 memory management code. If unsure say N here. 1130 1131config ARM64_VA_BITS 1132 int 1133 default 36 if ARM64_VA_BITS_36 1134 default 39 if ARM64_VA_BITS_39 1135 default 42 if ARM64_VA_BITS_42 1136 default 47 if ARM64_VA_BITS_47 1137 default 48 if ARM64_VA_BITS_48 1138 default 52 if ARM64_VA_BITS_52 1139 1140choice 1141 prompt "Physical address space size" 1142 default ARM64_PA_BITS_48 1143 help 1144 Choose the maximum physical address range that the kernel will 1145 support. 1146 1147config ARM64_PA_BITS_48 1148 bool "48-bit" 1149 1150config ARM64_PA_BITS_52 1151 bool "52-bit (ARMv8.2)" 1152 depends on ARM64_64K_PAGES 1153 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1154 help 1155 Enable support for a 52-bit physical address space, introduced as 1156 part of the ARMv8.2-LPA extension. 1157 1158 With this enabled, the kernel will also continue to work on CPUs that 1159 do not support ARMv8.2-LPA, but with some added memory overhead (and 1160 minor performance overhead). 1161 1162endchoice 1163 1164config ARM64_PA_BITS 1165 int 1166 default 48 if ARM64_PA_BITS_48 1167 default 52 if ARM64_PA_BITS_52 1168 1169choice 1170 prompt "Endianness" 1171 default CPU_LITTLE_ENDIAN 1172 help 1173 Select the endianness of data accesses performed by the CPU. Userspace 1174 applications will need to be compiled and linked for the endianness 1175 that is selected here. 1176 1177config CPU_BIG_ENDIAN 1178 bool "Build big-endian kernel" 1179 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1180 help 1181 Say Y if you plan on running a kernel with a big-endian userspace. 1182 1183config CPU_LITTLE_ENDIAN 1184 bool "Build little-endian kernel" 1185 help 1186 Say Y if you plan on running a kernel with a little-endian userspace. 1187 This is usually the case for distributions targeting arm64. 1188 1189endchoice 1190 1191config SCHED_MC 1192 bool "Multi-core scheduler support" 1193 help 1194 Multi-core scheduler support improves the CPU scheduler's decision 1195 making when dealing with multi-core CPU chips at a cost of slightly 1196 increased overhead in some places. If unsure say N here. 1197 1198config SCHED_CLUSTER 1199 bool "Cluster scheduler support" 1200 help 1201 Cluster scheduler support improves the CPU scheduler's decision 1202 making when dealing with machines that have clusters of CPUs. 1203 Cluster usually means a couple of CPUs which are placed closely 1204 by sharing mid-level caches, last-level cache tags or internal 1205 busses. 1206 1207config SCHED_SMT 1208 bool "SMT scheduler support" 1209 help 1210 Improves the CPU scheduler's decision making when dealing with 1211 MultiThreading at a cost of slightly increased overhead in some 1212 places. If unsure say N here. 1213 1214config NR_CPUS 1215 int "Maximum number of CPUs (2-4096)" 1216 range 2 4096 1217 default "256" 1218 1219config HOTPLUG_CPU 1220 bool "Support for hot-pluggable CPUs" 1221 select GENERIC_IRQ_MIGRATION 1222 help 1223 Say Y here to experiment with turning CPUs off and on. CPUs 1224 can be controlled through /sys/devices/system/cpu. 1225 1226# Common NUMA Features 1227config NUMA 1228 bool "NUMA Memory Allocation and Scheduler Support" 1229 select GENERIC_ARCH_NUMA 1230 select ACPI_NUMA if ACPI 1231 select OF_NUMA 1232 select HAVE_SETUP_PER_CPU_AREA 1233 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1234 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1235 select USE_PERCPU_NUMA_NODE_ID 1236 help 1237 Enable NUMA (Non-Uniform Memory Access) support. 1238 1239 The kernel will try to allocate memory used by a CPU on the 1240 local memory of the CPU and add some more 1241 NUMA awareness to the kernel. 1242 1243config NODES_SHIFT 1244 int "Maximum NUMA Nodes (as a power of 2)" 1245 range 1 10 1246 default "4" 1247 depends on NUMA 1248 help 1249 Specify the maximum number of NUMA Nodes available on the target 1250 system. Increases memory reserved to accommodate various tables. 1251 1252source "kernel/Kconfig.hz" 1253 1254config ARCH_SPARSEMEM_ENABLE 1255 def_bool y 1256 select SPARSEMEM_VMEMMAP_ENABLE 1257 select SPARSEMEM_VMEMMAP 1258 1259config HW_PERF_EVENTS 1260 def_bool y 1261 depends on ARM_PMU 1262 1263# Supported by clang >= 7.0 or GCC >= 12.0.0 1264config CC_HAVE_SHADOW_CALL_STACK 1265 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1266 1267config PARAVIRT 1268 bool "Enable paravirtualization code" 1269 help 1270 This changes the kernel so it can modify itself when it is run 1271 under a hypervisor, potentially improving performance significantly 1272 over full virtualization. 1273 1274config PARAVIRT_TIME_ACCOUNTING 1275 bool "Paravirtual steal time accounting" 1276 select PARAVIRT 1277 help 1278 Select this option to enable fine granularity task steal time 1279 accounting. Time spent executing other tasks in parallel with 1280 the current vCPU is discounted from the vCPU power. To account for 1281 that, there can be a small performance impact. 1282 1283 If in doubt, say N here. 1284 1285config KEXEC 1286 depends on PM_SLEEP_SMP 1287 select KEXEC_CORE 1288 bool "kexec system call" 1289 help 1290 kexec is a system call that implements the ability to shutdown your 1291 current kernel, and to start another kernel. It is like a reboot 1292 but it is independent of the system firmware. And like a reboot 1293 you can start any kernel with it, not just Linux. 1294 1295config KEXEC_FILE 1296 bool "kexec file based system call" 1297 select KEXEC_CORE 1298 select HAVE_IMA_KEXEC if IMA 1299 help 1300 This is new version of kexec system call. This system call is 1301 file based and takes file descriptors as system call argument 1302 for kernel and initramfs as opposed to list of segments as 1303 accepted by previous system call. 1304 1305config KEXEC_SIG 1306 bool "Verify kernel signature during kexec_file_load() syscall" 1307 depends on KEXEC_FILE 1308 help 1309 Select this option to verify a signature with loaded kernel 1310 image. If configured, any attempt of loading a image without 1311 valid signature will fail. 1312 1313 In addition to that option, you need to enable signature 1314 verification for the corresponding kernel image type being 1315 loaded in order for this to work. 1316 1317config KEXEC_IMAGE_VERIFY_SIG 1318 bool "Enable Image signature verification support" 1319 default y 1320 depends on KEXEC_SIG 1321 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1322 help 1323 Enable Image signature verification support. 1324 1325comment "Support for PE file signature verification disabled" 1326 depends on KEXEC_SIG 1327 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1328 1329config CRASH_DUMP 1330 bool "Build kdump crash kernel" 1331 help 1332 Generate crash dump after being started by kexec. This should 1333 be normally only set in special crash dump kernels which are 1334 loaded in the main kernel with kexec-tools into a specially 1335 reserved region and then later executed after a crash by 1336 kdump/kexec. 1337 1338 For more details see Documentation/admin-guide/kdump/kdump.rst 1339 1340config TRANS_TABLE 1341 def_bool y 1342 depends on HIBERNATION || KEXEC_CORE 1343 1344config XEN_DOM0 1345 def_bool y 1346 depends on XEN 1347 1348config XEN 1349 bool "Xen guest support on ARM64" 1350 depends on ARM64 && OF 1351 select SWIOTLB_XEN 1352 select PARAVIRT 1353 help 1354 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1355 1356config FORCE_MAX_ZONEORDER 1357 int 1358 default "14" if ARM64_64K_PAGES 1359 default "12" if ARM64_16K_PAGES 1360 default "11" 1361 help 1362 The kernel memory allocator divides physically contiguous memory 1363 blocks into "zones", where each zone is a power of two number of 1364 pages. This option selects the largest power of two that the kernel 1365 keeps in the memory allocator. If you need to allocate very large 1366 blocks of physically contiguous memory, then you may need to 1367 increase this value. 1368 1369 This config option is actually maximum order plus one. For example, 1370 a value of 11 means that the largest free memory block is 2^10 pages. 1371 1372 We make sure that we can allocate upto a HugePage size for each configuration. 1373 Hence we have : 1374 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1375 1376 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1377 4M allocations matching the default size used by generic code. 1378 1379config UNMAP_KERNEL_AT_EL0 1380 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1381 default y 1382 help 1383 Speculation attacks against some high-performance processors can 1384 be used to bypass MMU permission checks and leak kernel data to 1385 userspace. This can be defended against by unmapping the kernel 1386 when running in userspace, mapping it back in on exception entry 1387 via a trampoline page in the vector table. 1388 1389 If unsure, say Y. 1390 1391config MITIGATE_SPECTRE_BRANCH_HISTORY 1392 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1393 default y 1394 help 1395 Speculation attacks against some high-performance processors can 1396 make use of branch history to influence future speculation. 1397 When taking an exception from user-space, a sequence of branches 1398 or a firmware call overwrites the branch history. 1399 1400config RODATA_FULL_DEFAULT_ENABLED 1401 bool "Apply r/o permissions of VM areas also to their linear aliases" 1402 default y 1403 help 1404 Apply read-only attributes of VM areas to the linear alias of 1405 the backing pages as well. This prevents code or read-only data 1406 from being modified (inadvertently or intentionally) via another 1407 mapping of the same memory page. This additional enhancement can 1408 be turned off at runtime by passing rodata=[off|on] (and turned on 1409 with rodata=full if this option is set to 'n') 1410 1411 This requires the linear region to be mapped down to pages, 1412 which may adversely affect performance in some cases. 1413 1414config ARM64_SW_TTBR0_PAN 1415 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1416 help 1417 Enabling this option prevents the kernel from accessing 1418 user-space memory directly by pointing TTBR0_EL1 to a reserved 1419 zeroed area and reserved ASID. The user access routines 1420 restore the valid TTBR0_EL1 temporarily. 1421 1422config ARM64_TAGGED_ADDR_ABI 1423 bool "Enable the tagged user addresses syscall ABI" 1424 default y 1425 help 1426 When this option is enabled, user applications can opt in to a 1427 relaxed ABI via prctl() allowing tagged addresses to be passed 1428 to system calls as pointer arguments. For details, see 1429 Documentation/arm64/tagged-address-abi.rst. 1430 1431menuconfig COMPAT 1432 bool "Kernel support for 32-bit EL0" 1433 depends on ARM64_4K_PAGES || EXPERT 1434 select HAVE_UID16 1435 select OLD_SIGSUSPEND3 1436 select COMPAT_OLD_SIGACTION 1437 help 1438 This option enables support for a 32-bit EL0 running under a 64-bit 1439 kernel at EL1. AArch32-specific components such as system calls, 1440 the user helper functions, VFP support and the ptrace interface are 1441 handled appropriately by the kernel. 1442 1443 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1444 that you will only be able to execute AArch32 binaries that were compiled 1445 with page size aligned segments. 1446 1447 If you want to execute 32-bit userspace applications, say Y. 1448 1449if COMPAT 1450 1451config KUSER_HELPERS 1452 bool "Enable kuser helpers page for 32-bit applications" 1453 default y 1454 help 1455 Warning: disabling this option may break 32-bit user programs. 1456 1457 Provide kuser helpers to compat tasks. The kernel provides 1458 helper code to userspace in read only form at a fixed location 1459 to allow userspace to be independent of the CPU type fitted to 1460 the system. This permits binaries to be run on ARMv4 through 1461 to ARMv8 without modification. 1462 1463 See Documentation/arm/kernel_user_helpers.rst for details. 1464 1465 However, the fixed address nature of these helpers can be used 1466 by ROP (return orientated programming) authors when creating 1467 exploits. 1468 1469 If all of the binaries and libraries which run on your platform 1470 are built specifically for your platform, and make no use of 1471 these helpers, then you can turn this option off to hinder 1472 such exploits. However, in that case, if a binary or library 1473 relying on those helpers is run, it will not function correctly. 1474 1475 Say N here only if you are absolutely certain that you do not 1476 need these helpers; otherwise, the safe option is to say Y. 1477 1478config COMPAT_VDSO 1479 bool "Enable vDSO for 32-bit applications" 1480 depends on !CPU_BIG_ENDIAN 1481 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1482 select GENERIC_COMPAT_VDSO 1483 default y 1484 help 1485 Place in the process address space of 32-bit applications an 1486 ELF shared object providing fast implementations of gettimeofday 1487 and clock_gettime. 1488 1489 You must have a 32-bit build of glibc 2.22 or later for programs 1490 to seamlessly take advantage of this. 1491 1492config THUMB2_COMPAT_VDSO 1493 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1494 depends on COMPAT_VDSO 1495 default y 1496 help 1497 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1498 otherwise with '-marm'. 1499 1500menuconfig ARMV8_DEPRECATED 1501 bool "Emulate deprecated/obsolete ARMv8 instructions" 1502 depends on SYSCTL 1503 help 1504 Legacy software support may require certain instructions 1505 that have been deprecated or obsoleted in the architecture. 1506 1507 Enable this config to enable selective emulation of these 1508 features. 1509 1510 If unsure, say Y 1511 1512if ARMV8_DEPRECATED 1513 1514config SWP_EMULATION 1515 bool "Emulate SWP/SWPB instructions" 1516 help 1517 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1518 they are always undefined. Say Y here to enable software 1519 emulation of these instructions for userspace using LDXR/STXR. 1520 This feature can be controlled at runtime with the abi.swp 1521 sysctl which is disabled by default. 1522 1523 In some older versions of glibc [<=2.8] SWP is used during futex 1524 trylock() operations with the assumption that the code will not 1525 be preempted. This invalid assumption may be more likely to fail 1526 with SWP emulation enabled, leading to deadlock of the user 1527 application. 1528 1529 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1530 on an external transaction monitoring block called a global 1531 monitor to maintain update atomicity. If your system does not 1532 implement a global monitor, this option can cause programs that 1533 perform SWP operations to uncached memory to deadlock. 1534 1535 If unsure, say Y 1536 1537config CP15_BARRIER_EMULATION 1538 bool "Emulate CP15 Barrier instructions" 1539 help 1540 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1541 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1542 strongly recommended to use the ISB, DSB, and DMB 1543 instructions instead. 1544 1545 Say Y here to enable software emulation of these 1546 instructions for AArch32 userspace code. When this option is 1547 enabled, CP15 barrier usage is traced which can help 1548 identify software that needs updating. This feature can be 1549 controlled at runtime with the abi.cp15_barrier sysctl. 1550 1551 If unsure, say Y 1552 1553config SETEND_EMULATION 1554 bool "Emulate SETEND instruction" 1555 help 1556 The SETEND instruction alters the data-endianness of the 1557 AArch32 EL0, and is deprecated in ARMv8. 1558 1559 Say Y here to enable software emulation of the instruction 1560 for AArch32 userspace code. This feature can be controlled 1561 at runtime with the abi.setend sysctl. 1562 1563 Note: All the cpus on the system must have mixed endian support at EL0 1564 for this feature to be enabled. If a new CPU - which doesn't support mixed 1565 endian - is hotplugged in after this feature has been enabled, there could 1566 be unexpected results in the applications. 1567 1568 If unsure, say Y 1569endif 1570 1571endif 1572 1573menu "ARMv8.1 architectural features" 1574 1575config ARM64_HW_AFDBM 1576 bool "Support for hardware updates of the Access and Dirty page flags" 1577 default y 1578 help 1579 The ARMv8.1 architecture extensions introduce support for 1580 hardware updates of the access and dirty information in page 1581 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1582 capable processors, accesses to pages with PTE_AF cleared will 1583 set this bit instead of raising an access flag fault. 1584 Similarly, writes to read-only pages with the DBM bit set will 1585 clear the read-only bit (AP[2]) instead of raising a 1586 permission fault. 1587 1588 Kernels built with this configuration option enabled continue 1589 to work on pre-ARMv8.1 hardware and the performance impact is 1590 minimal. If unsure, say Y. 1591 1592config ARM64_PAN 1593 bool "Enable support for Privileged Access Never (PAN)" 1594 default y 1595 help 1596 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1597 prevents the kernel or hypervisor from accessing user-space (EL0) 1598 memory directly. 1599 1600 Choosing this option will cause any unprotected (not using 1601 copy_to_user et al) memory access to fail with a permission fault. 1602 1603 The feature is detected at runtime, and will remain as a 'nop' 1604 instruction if the cpu does not implement the feature. 1605 1606config AS_HAS_LDAPR 1607 def_bool $(as-instr,.arch_extension rcpc) 1608 1609config AS_HAS_LSE_ATOMICS 1610 def_bool $(as-instr,.arch_extension lse) 1611 1612config ARM64_LSE_ATOMICS 1613 bool 1614 default ARM64_USE_LSE_ATOMICS 1615 depends on AS_HAS_LSE_ATOMICS 1616 1617config ARM64_USE_LSE_ATOMICS 1618 bool "Atomic instructions" 1619 depends on JUMP_LABEL 1620 default y 1621 help 1622 As part of the Large System Extensions, ARMv8.1 introduces new 1623 atomic instructions that are designed specifically to scale in 1624 very large systems. 1625 1626 Say Y here to make use of these instructions for the in-kernel 1627 atomic routines. This incurs a small overhead on CPUs that do 1628 not support these instructions and requires the kernel to be 1629 built with binutils >= 2.25 in order for the new instructions 1630 to be used. 1631 1632endmenu 1633 1634menu "ARMv8.2 architectural features" 1635 1636config AS_HAS_ARMV8_2 1637 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1638 1639config AS_HAS_SHA3 1640 def_bool $(as-instr,.arch armv8.2-a+sha3) 1641 1642config ARM64_PMEM 1643 bool "Enable support for persistent memory" 1644 select ARCH_HAS_PMEM_API 1645 select ARCH_HAS_UACCESS_FLUSHCACHE 1646 help 1647 Say Y to enable support for the persistent memory API based on the 1648 ARMv8.2 DCPoP feature. 1649 1650 The feature is detected at runtime, and the kernel will use DC CVAC 1651 operations if DC CVAP is not supported (following the behaviour of 1652 DC CVAP itself if the system does not define a point of persistence). 1653 1654config ARM64_RAS_EXTN 1655 bool "Enable support for RAS CPU Extensions" 1656 default y 1657 help 1658 CPUs that support the Reliability, Availability and Serviceability 1659 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1660 errors, classify them and report them to software. 1661 1662 On CPUs with these extensions system software can use additional 1663 barriers to determine if faults are pending and read the 1664 classification from a new set of registers. 1665 1666 Selecting this feature will allow the kernel to use these barriers 1667 and access the new registers if the system supports the extension. 1668 Platform RAS features may additionally depend on firmware support. 1669 1670config ARM64_CNP 1671 bool "Enable support for Common Not Private (CNP) translations" 1672 default y 1673 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1674 help 1675 Common Not Private (CNP) allows translation table entries to 1676 be shared between different PEs in the same inner shareable 1677 domain, so the hardware can use this fact to optimise the 1678 caching of such entries in the TLB. 1679 1680 Selecting this option allows the CNP feature to be detected 1681 at runtime, and does not affect PEs that do not implement 1682 this feature. 1683 1684endmenu 1685 1686menu "ARMv8.3 architectural features" 1687 1688config ARM64_PTR_AUTH 1689 bool "Enable support for pointer authentication" 1690 default y 1691 help 1692 Pointer authentication (part of the ARMv8.3 Extensions) provides 1693 instructions for signing and authenticating pointers against secret 1694 keys, which can be used to mitigate Return Oriented Programming (ROP) 1695 and other attacks. 1696 1697 This option enables these instructions at EL0 (i.e. for userspace). 1698 Choosing this option will cause the kernel to initialise secret keys 1699 for each process at exec() time, with these keys being 1700 context-switched along with the process. 1701 1702 The feature is detected at runtime. If the feature is not present in 1703 hardware it will not be advertised to userspace/KVM guest nor will it 1704 be enabled. 1705 1706 If the feature is present on the boot CPU but not on a late CPU, then 1707 the late CPU will be parked. Also, if the boot CPU does not have 1708 address auth and the late CPU has then the late CPU will still boot 1709 but with the feature disabled. On such a system, this option should 1710 not be selected. 1711 1712config ARM64_PTR_AUTH_KERNEL 1713 bool "Use pointer authentication for kernel" 1714 default y 1715 depends on ARM64_PTR_AUTH 1716 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1717 # Modern compilers insert a .note.gnu.property section note for PAC 1718 # which is only understood by binutils starting with version 2.33.1. 1719 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1720 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1721 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1722 help 1723 If the compiler supports the -mbranch-protection or 1724 -msign-return-address flag (e.g. GCC 7 or later), then this option 1725 will cause the kernel itself to be compiled with return address 1726 protection. In this case, and if the target hardware is known to 1727 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1728 disabled with minimal loss of protection. 1729 1730 This feature works with FUNCTION_GRAPH_TRACER option only if 1731 DYNAMIC_FTRACE_WITH_REGS is enabled. 1732 1733config CC_HAS_BRANCH_PROT_PAC_RET 1734 # GCC 9 or later, clang 8 or later 1735 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1736 1737config CC_HAS_SIGN_RETURN_ADDRESS 1738 # GCC 7, 8 1739 def_bool $(cc-option,-msign-return-address=all) 1740 1741config AS_HAS_PAC 1742 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1743 1744config AS_HAS_CFI_NEGATE_RA_STATE 1745 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1746 1747endmenu 1748 1749menu "ARMv8.4 architectural features" 1750 1751config ARM64_AMU_EXTN 1752 bool "Enable support for the Activity Monitors Unit CPU extension" 1753 default y 1754 help 1755 The activity monitors extension is an optional extension introduced 1756 by the ARMv8.4 CPU architecture. This enables support for version 1 1757 of the activity monitors architecture, AMUv1. 1758 1759 To enable the use of this extension on CPUs that implement it, say Y. 1760 1761 Note that for architectural reasons, firmware _must_ implement AMU 1762 support when running on CPUs that present the activity monitors 1763 extension. The required support is present in: 1764 * Version 1.5 and later of the ARM Trusted Firmware 1765 1766 For kernels that have this configuration enabled but boot with broken 1767 firmware, you may need to say N here until the firmware is fixed. 1768 Otherwise you may experience firmware panics or lockups when 1769 accessing the counter registers. Even if you are not observing these 1770 symptoms, the values returned by the register reads might not 1771 correctly reflect reality. Most commonly, the value read will be 0, 1772 indicating that the counter is not enabled. 1773 1774config AS_HAS_ARMV8_4 1775 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1776 1777config ARM64_TLB_RANGE 1778 bool "Enable support for tlbi range feature" 1779 default y 1780 depends on AS_HAS_ARMV8_4 1781 help 1782 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1783 range of input addresses. 1784 1785 The feature introduces new assembly instructions, and they were 1786 support when binutils >= 2.30. 1787 1788endmenu 1789 1790menu "ARMv8.5 architectural features" 1791 1792config AS_HAS_ARMV8_5 1793 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1794 1795config ARM64_BTI 1796 bool "Branch Target Identification support" 1797 default y 1798 help 1799 Branch Target Identification (part of the ARMv8.5 Extensions) 1800 provides a mechanism to limit the set of locations to which computed 1801 branch instructions such as BR or BLR can jump. 1802 1803 To make use of BTI on CPUs that support it, say Y. 1804 1805 BTI is intended to provide complementary protection to other control 1806 flow integrity protection mechanisms, such as the Pointer 1807 authentication mechanism provided as part of the ARMv8.3 Extensions. 1808 For this reason, it does not make sense to enable this option without 1809 also enabling support for pointer authentication. Thus, when 1810 enabling this option you should also select ARM64_PTR_AUTH=y. 1811 1812 Userspace binaries must also be specifically compiled to make use of 1813 this mechanism. If you say N here or the hardware does not support 1814 BTI, such binaries can still run, but you get no additional 1815 enforcement of branch destinations. 1816 1817config ARM64_BTI_KERNEL 1818 bool "Use Branch Target Identification for kernel" 1819 default y 1820 depends on ARM64_BTI 1821 depends on ARM64_PTR_AUTH_KERNEL 1822 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1823 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1824 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1825 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1826 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1827 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1828 help 1829 Build the kernel with Branch Target Identification annotations 1830 and enable enforcement of this for kernel code. When this option 1831 is enabled and the system supports BTI all kernel code including 1832 modular code must have BTI enabled. 1833 1834config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1835 # GCC 9 or later, clang 8 or later 1836 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1837 1838config ARM64_E0PD 1839 bool "Enable support for E0PD" 1840 default y 1841 help 1842 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1843 that EL0 accesses made via TTBR1 always fault in constant time, 1844 providing similar benefits to KASLR as those provided by KPTI, but 1845 with lower overhead and without disrupting legitimate access to 1846 kernel memory such as SPE. 1847 1848 This option enables E0PD for TTBR1 where available. 1849 1850config ARCH_RANDOM 1851 bool "Enable support for random number generation" 1852 default y 1853 help 1854 Random number generation (part of the ARMv8.5 Extensions) 1855 provides a high bandwidth, cryptographically secure 1856 hardware random number generator. 1857 1858config ARM64_AS_HAS_MTE 1859 # Initial support for MTE went in binutils 2.32.0, checked with 1860 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1861 # as a late addition to the final architecture spec (LDGM/STGM) 1862 # is only supported in the newer 2.32.x and 2.33 binutils 1863 # versions, hence the extra "stgm" instruction check below. 1864 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1865 1866config ARM64_MTE 1867 bool "Memory Tagging Extension support" 1868 default y 1869 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1870 depends on AS_HAS_ARMV8_5 1871 depends on AS_HAS_LSE_ATOMICS 1872 # Required for tag checking in the uaccess routines 1873 depends on ARM64_PAN 1874 select ARCH_USES_HIGH_VMA_FLAGS 1875 help 1876 Memory Tagging (part of the ARMv8.5 Extensions) provides 1877 architectural support for run-time, always-on detection of 1878 various classes of memory error to aid with software debugging 1879 to eliminate vulnerabilities arising from memory-unsafe 1880 languages. 1881 1882 This option enables the support for the Memory Tagging 1883 Extension at EL0 (i.e. for userspace). 1884 1885 Selecting this option allows the feature to be detected at 1886 runtime. Any secondary CPU not implementing this feature will 1887 not be allowed a late bring-up. 1888 1889 Userspace binaries that want to use this feature must 1890 explicitly opt in. The mechanism for the userspace is 1891 described in: 1892 1893 Documentation/arm64/memory-tagging-extension.rst. 1894 1895endmenu 1896 1897menu "ARMv8.7 architectural features" 1898 1899config ARM64_EPAN 1900 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1901 default y 1902 depends on ARM64_PAN 1903 help 1904 Enhanced Privileged Access Never (EPAN) allows Privileged 1905 Access Never to be used with Execute-only mappings. 1906 1907 The feature is detected at runtime, and will remain disabled 1908 if the cpu does not implement the feature. 1909endmenu 1910 1911config ARM64_SVE 1912 bool "ARM Scalable Vector Extension support" 1913 default y 1914 help 1915 The Scalable Vector Extension (SVE) is an extension to the AArch64 1916 execution state which complements and extends the SIMD functionality 1917 of the base architecture to support much larger vectors and to enable 1918 additional vectorisation opportunities. 1919 1920 To enable use of this extension on CPUs that implement it, say Y. 1921 1922 On CPUs that support the SVE2 extensions, this option will enable 1923 those too. 1924 1925 Note that for architectural reasons, firmware _must_ implement SVE 1926 support when running on SVE capable hardware. The required support 1927 is present in: 1928 1929 * version 1.5 and later of the ARM Trusted Firmware 1930 * the AArch64 boot wrapper since commit 5e1261e08abf 1931 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1932 1933 For other firmware implementations, consult the firmware documentation 1934 or vendor. 1935 1936 If you need the kernel to boot on SVE-capable hardware with broken 1937 firmware, you may need to say N here until you get your firmware 1938 fixed. Otherwise, you may experience firmware panics or lockups when 1939 booting the kernel. If unsure and you are not observing these 1940 symptoms, you should assume that it is safe to say Y. 1941 1942config ARM64_MODULE_PLTS 1943 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1944 depends on MODULES 1945 select HAVE_MOD_ARCH_SPECIFIC 1946 help 1947 Allocate PLTs when loading modules so that jumps and calls whose 1948 targets are too far away for their relative offsets to be encoded 1949 in the instructions themselves can be bounced via veneers in the 1950 module's PLT. This allows modules to be allocated in the generic 1951 vmalloc area after the dedicated module memory area has been 1952 exhausted. 1953 1954 When running with address space randomization (KASLR), the module 1955 region itself may be too far away for ordinary relative jumps and 1956 calls, and so in that case, module PLTs are required and cannot be 1957 disabled. 1958 1959 Specific errata workaround(s) might also force module PLTs to be 1960 enabled (ARM64_ERRATUM_843419). 1961 1962config ARM64_PSEUDO_NMI 1963 bool "Support for NMI-like interrupts" 1964 select ARM_GIC_V3 1965 help 1966 Adds support for mimicking Non-Maskable Interrupts through the use of 1967 GIC interrupt priority. This support requires version 3 or later of 1968 ARM GIC. 1969 1970 This high priority configuration for interrupts needs to be 1971 explicitly enabled by setting the kernel parameter 1972 "irqchip.gicv3_pseudo_nmi" to 1. 1973 1974 If unsure, say N 1975 1976if ARM64_PSEUDO_NMI 1977config ARM64_DEBUG_PRIORITY_MASKING 1978 bool "Debug interrupt priority masking" 1979 help 1980 This adds runtime checks to functions enabling/disabling 1981 interrupts when using priority masking. The additional checks verify 1982 the validity of ICC_PMR_EL1 when calling concerned functions. 1983 1984 If unsure, say N 1985endif 1986 1987config RELOCATABLE 1988 bool "Build a relocatable kernel image" if EXPERT 1989 select ARCH_HAS_RELR 1990 default y 1991 help 1992 This builds the kernel as a Position Independent Executable (PIE), 1993 which retains all relocation metadata required to relocate the 1994 kernel binary at runtime to a different virtual address than the 1995 address it was linked at. 1996 Since AArch64 uses the RELA relocation format, this requires a 1997 relocation pass at runtime even if the kernel is loaded at the 1998 same address it was linked at. 1999 2000config RANDOMIZE_BASE 2001 bool "Randomize the address of the kernel image" 2002 select ARM64_MODULE_PLTS if MODULES 2003 select RELOCATABLE 2004 help 2005 Randomizes the virtual address at which the kernel image is 2006 loaded, as a security feature that deters exploit attempts 2007 relying on knowledge of the location of kernel internals. 2008 2009 It is the bootloader's job to provide entropy, by passing a 2010 random u64 value in /chosen/kaslr-seed at kernel entry. 2011 2012 When booting via the UEFI stub, it will invoke the firmware's 2013 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2014 to the kernel proper. In addition, it will randomise the physical 2015 location of the kernel Image as well. 2016 2017 If unsure, say N. 2018 2019config RANDOMIZE_MODULE_REGION_FULL 2020 bool "Randomize the module region over a 2 GB range" 2021 depends on RANDOMIZE_BASE 2022 default y 2023 help 2024 Randomizes the location of the module region inside a 2 GB window 2025 covering the core kernel. This way, it is less likely for modules 2026 to leak information about the location of core kernel data structures 2027 but it does imply that function calls between modules and the core 2028 kernel will need to be resolved via veneers in the module PLT. 2029 2030 When this option is not set, the module region will be randomized over 2031 a limited range that contains the [_stext, _etext] interval of the 2032 core kernel, so branch relocations are almost always in range unless 2033 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2034 particular case of region exhaustion, modules might be able to fall 2035 back to a larger 2GB area. 2036 2037config CC_HAVE_STACKPROTECTOR_SYSREG 2038 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2039 2040config STACKPROTECTOR_PER_TASK 2041 def_bool y 2042 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2043 2044endmenu 2045 2046menu "Boot options" 2047 2048config ARM64_ACPI_PARKING_PROTOCOL 2049 bool "Enable support for the ARM64 ACPI parking protocol" 2050 depends on ACPI 2051 help 2052 Enable support for the ARM64 ACPI parking protocol. If disabled 2053 the kernel will not allow booting through the ARM64 ACPI parking 2054 protocol even if the corresponding data is present in the ACPI 2055 MADT table. 2056 2057config CMDLINE 2058 string "Default kernel command string" 2059 default "" 2060 help 2061 Provide a set of default command-line options at build time by 2062 entering them here. As a minimum, you should specify the the 2063 root device (e.g. root=/dev/nfs). 2064 2065choice 2066 prompt "Kernel command line type" if CMDLINE != "" 2067 default CMDLINE_FROM_BOOTLOADER 2068 help 2069 Choose how the kernel will handle the provided default kernel 2070 command line string. 2071 2072config CMDLINE_FROM_BOOTLOADER 2073 bool "Use bootloader kernel arguments if available" 2074 help 2075 Uses the command-line options passed by the boot loader. If 2076 the boot loader doesn't provide any, the default kernel command 2077 string provided in CMDLINE will be used. 2078 2079config CMDLINE_FORCE 2080 bool "Always use the default kernel command string" 2081 help 2082 Always use the default kernel command string, even if the boot 2083 loader passes other arguments to the kernel. 2084 This is useful if you cannot or don't want to change the 2085 command-line options your boot loader passes to the kernel. 2086 2087endchoice 2088 2089config EFI_STUB 2090 bool 2091 2092config EFI 2093 bool "UEFI runtime support" 2094 depends on OF && !CPU_BIG_ENDIAN 2095 depends on KERNEL_MODE_NEON 2096 select ARCH_SUPPORTS_ACPI 2097 select LIBFDT 2098 select UCS2_STRING 2099 select EFI_PARAMS_FROM_FDT 2100 select EFI_RUNTIME_WRAPPERS 2101 select EFI_STUB 2102 select EFI_GENERIC_STUB 2103 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2104 default y 2105 help 2106 This option provides support for runtime services provided 2107 by UEFI firmware (such as non-volatile variables, realtime 2108 clock, and platform reset). A UEFI stub is also provided to 2109 allow the kernel to be booted as an EFI application. This 2110 is only useful on systems that have UEFI firmware. 2111 2112config DMI 2113 bool "Enable support for SMBIOS (DMI) tables" 2114 depends on EFI 2115 default y 2116 help 2117 This enables SMBIOS/DMI feature for systems. 2118 2119 This option is only useful on systems that have UEFI firmware. 2120 However, even with this option, the resultant kernel should 2121 continue to boot on existing non-UEFI platforms. 2122 2123endmenu 2124 2125config SYSVIPC_COMPAT 2126 def_bool y 2127 depends on COMPAT && SYSVIPC 2128 2129menu "Power management options" 2130 2131source "kernel/power/Kconfig" 2132 2133config ARCH_HIBERNATION_POSSIBLE 2134 def_bool y 2135 depends on CPU_PM 2136 2137config ARCH_HIBERNATION_HEADER 2138 def_bool y 2139 depends on HIBERNATION 2140 2141config ARCH_SUSPEND_POSSIBLE 2142 def_bool y 2143 2144endmenu 2145 2146menu "CPU Power Management" 2147 2148source "drivers/cpuidle/Kconfig" 2149 2150source "drivers/cpufreq/Kconfig" 2151 2152endmenu 2153 2154source "drivers/acpi/Kconfig" 2155 2156source "arch/arm64/kvm/Kconfig" 2157 2158if CRYPTO 2159source "arch/arm64/crypto/Kconfig" 2160endif 2161