1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 18 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 19 select ARCH_ENABLE_MEMORY_HOTPLUG 20 select ARCH_ENABLE_MEMORY_HOTREMOVE 21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 22 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 23 select ARCH_HAS_CACHE_LINE_SIZE 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 41 select ARCH_HAS_PTE_DEVMAP 42 select ARCH_HAS_PTE_SPECIAL 43 select ARCH_HAS_HW_PTE_YOUNG 44 select ARCH_HAS_SETUP_DMA_OPS 45 select ARCH_HAS_SET_DIRECT_MAP 46 select ARCH_HAS_SET_MEMORY 47 select ARCH_STACKWALK 48 select ARCH_HAS_STRICT_KERNEL_RWX 49 select ARCH_HAS_STRICT_MODULE_RWX 50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 51 select ARCH_HAS_SYNC_DMA_FOR_CPU 52 select ARCH_HAS_SYSCALL_WRAPPER 53 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 54 select ARCH_HAS_ZONE_DMA_SET if EXPERT 55 select ARCH_HAVE_ELF_PROT 56 select ARCH_HAVE_NMI_SAFE_CMPXCHG 57 select ARCH_HAVE_TRACE_MMIO_ACCESS 58 select ARCH_INLINE_READ_LOCK if !PREEMPTION 59 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 63 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 64 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 71 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 74 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 81 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 83 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 84 select ARCH_KEEP_MEMBLOCK 85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 86 select ARCH_USE_CMPXCHG_LOCKREF 87 select ARCH_USE_GNU_PROPERTY 88 select ARCH_USE_MEMTEST 89 select ARCH_USE_QUEUED_RWLOCKS 90 select ARCH_USE_QUEUED_SPINLOCKS 91 select ARCH_USE_SYM_ANNOTATIONS 92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 93 select ARCH_SUPPORTS_HUGETLBFS 94 select ARCH_SUPPORTS_MEMORY_FAILURE 95 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 96 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 97 select ARCH_SUPPORTS_LTO_CLANG_THIN 98 select ARCH_SUPPORTS_CFI_CLANG 99 select ARCH_SUPPORTS_ATOMIC_RMW 100 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 101 select ARCH_SUPPORTS_NUMA_BALANCING 102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 103 select ARCH_SUPPORTS_PER_VMA_LOCK 104 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 105 select ARCH_SUPPORTS_RT 106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 107 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 108 select ARCH_WANT_DEFAULT_BPF_JIT 109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 110 select ARCH_WANT_FRAME_POINTERS 111 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 112 select ARCH_WANT_LD_ORPHAN_WARN 113 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 114 select ARCH_WANTS_NO_INSTR 115 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 116 select ARCH_HAS_UBSAN 117 select ARM_AMBA 118 select ARM_ARCH_TIMER 119 select ARM_GIC 120 select AUDIT_ARCH_COMPAT_GENERIC 121 select ARM_GIC_V2M if PCI 122 select ARM_GIC_V3 123 select ARM_GIC_V3_ITS if PCI 124 select ARM_PSCI_FW 125 select BUILDTIME_TABLE_SORT 126 select CLONE_BACKWARDS 127 select COMMON_CLK 128 select CPU_PM if (SUSPEND || CPU_IDLE) 129 select CPUMASK_OFFSTACK if NR_CPUS > 256 130 select CRC32 131 select DCACHE_WORD_ACCESS 132 select DYNAMIC_FTRACE if FUNCTION_TRACER 133 select DMA_BOUNCE_UNALIGNED_KMALLOC 134 select DMA_DIRECT_REMAP 135 select EDAC_SUPPORT 136 select FRAME_POINTER 137 select FUNCTION_ALIGNMENT_4B 138 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 139 select GENERIC_ALLOCATOR 140 select GENERIC_ARCH_TOPOLOGY 141 select GENERIC_CLOCKEVENTS_BROADCAST 142 select GENERIC_CPU_AUTOPROBE 143 select GENERIC_CPU_DEVICES 144 select GENERIC_CPU_VULNERABILITIES 145 select GENERIC_EARLY_IOREMAP 146 select GENERIC_IDLE_POLL_SETUP 147 select GENERIC_IOREMAP 148 select GENERIC_IRQ_IPI 149 select GENERIC_IRQ_PROBE 150 select GENERIC_IRQ_SHOW 151 select GENERIC_IRQ_SHOW_LEVEL 152 select GENERIC_LIB_DEVMEM_IS_ALLOWED 153 select GENERIC_PCI_IOMAP 154 select GENERIC_PTDUMP 155 select GENERIC_SCHED_CLOCK 156 select GENERIC_SMP_IDLE_THREAD 157 select GENERIC_TIME_VSYSCALL 158 select GENERIC_GETTIMEOFDAY 159 select GENERIC_VDSO_TIME_NS 160 select HARDIRQS_SW_RESEND 161 select HAS_IOPORT 162 select HAVE_MOVE_PMD 163 select HAVE_MOVE_PUD 164 select HAVE_PCI 165 select HAVE_ACPI_APEI if (ACPI && EFI) 166 select HAVE_ALIGNED_STRUCT_PAGE 167 select HAVE_ARCH_AUDITSYSCALL 168 select HAVE_ARCH_BITREVERSE 169 select HAVE_ARCH_COMPILER_H 170 select HAVE_ARCH_HUGE_VMALLOC 171 select HAVE_ARCH_HUGE_VMAP 172 select HAVE_ARCH_JUMP_LABEL 173 select HAVE_ARCH_JUMP_LABEL_RELATIVE 174 select HAVE_ARCH_KASAN 175 select HAVE_ARCH_KASAN_VMALLOC 176 select HAVE_ARCH_KASAN_SW_TAGS 177 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 178 # Some instrumentation may be unsound, hence EXPERT 179 select HAVE_ARCH_KCSAN if EXPERT 180 select HAVE_ARCH_KFENCE 181 select HAVE_ARCH_KGDB 182 select HAVE_ARCH_MMAP_RND_BITS 183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 184 select HAVE_ARCH_PREL32_RELOCATIONS 185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 186 select HAVE_ARCH_SECCOMP_FILTER 187 select HAVE_ARCH_STACKLEAK 188 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 189 select HAVE_ARCH_TRACEHOOK 190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 191 select HAVE_ARCH_VMAP_STACK 192 select HAVE_ARM_SMCCC 193 select HAVE_ASM_MODVERSIONS 194 select HAVE_EBPF_JIT 195 select HAVE_C_RECORDMCOUNT 196 select HAVE_CMPXCHG_DOUBLE 197 select HAVE_CMPXCHG_LOCAL 198 select HAVE_CONTEXT_TRACKING_USER 199 select HAVE_DEBUG_KMEMLEAK 200 select HAVE_DMA_CONTIGUOUS 201 select HAVE_DYNAMIC_FTRACE 202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 203 if $(cc-option,-fpatchable-function-entry=2) 204 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 205 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 206 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 207 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 208 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 209 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 210 if DYNAMIC_FTRACE_WITH_ARGS 211 select HAVE_SAMPLE_FTRACE_DIRECT 212 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 213 select HAVE_EFFICIENT_UNALIGNED_ACCESS 214 select HAVE_GUP_FAST 215 select HAVE_FTRACE_MCOUNT_RECORD 216 select HAVE_FUNCTION_TRACER 217 select HAVE_FUNCTION_ERROR_INJECTION 218 select HAVE_FUNCTION_GRAPH_TRACER 219 select HAVE_FUNCTION_GRAPH_RETVAL 220 select HAVE_GCC_PLUGINS 221 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 222 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 223 select HAVE_HW_BREAKPOINT if PERF_EVENTS 224 select HAVE_IOREMAP_PROT 225 select HAVE_IRQ_TIME_ACCOUNTING 226 select HAVE_MOD_ARCH_SPECIFIC 227 select HAVE_NMI 228 select HAVE_PERF_EVENTS 229 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 230 select HAVE_PERF_REGS 231 select HAVE_PERF_USER_STACK_DUMP 232 select HAVE_PREEMPT_DYNAMIC_KEY 233 select HAVE_REGS_AND_STACK_ACCESS_API 234 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 235 select HAVE_FUNCTION_ARG_ACCESS_API 236 select MMU_GATHER_RCU_TABLE_FREE 237 select HAVE_RSEQ 238 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 239 select HAVE_STACKPROTECTOR 240 select HAVE_SYSCALL_TRACEPOINTS 241 select HAVE_KPROBES 242 select HAVE_KRETPROBES 243 select HAVE_GENERIC_VDSO 244 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 245 select IRQ_DOMAIN 246 select IRQ_FORCED_THREADING 247 select KASAN_VMALLOC if KASAN 248 select LOCK_MM_AND_FIND_VMA 249 select MODULES_USE_ELF_RELA 250 select NEED_DMA_MAP_STATE 251 select NEED_SG_DMA_LENGTH 252 select OF 253 select OF_EARLY_FLATTREE 254 select PCI_DOMAINS_GENERIC if PCI 255 select PCI_ECAM if (ACPI && PCI) 256 select PCI_SYSCALL if PCI 257 select POWER_RESET 258 select POWER_SUPPLY 259 select SPARSE_IRQ 260 select SWIOTLB 261 select SYSCTL_EXCEPTION_TRACE 262 select THREAD_INFO_IN_TASK 263 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 264 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 265 select TRACE_IRQFLAGS_SUPPORT 266 select TRACE_IRQFLAGS_NMI_SUPPORT 267 select HAVE_SOFTIRQ_ON_OWN_STACK 268 select USER_STACKTRACE_SUPPORT 269 select VDSO_GETRANDOM 270 help 271 ARM 64-bit (AArch64) Linux support. 272 273config RUSTC_SUPPORTS_ARM64 274 def_bool y 275 depends on CPU_LITTLE_ENDIAN 276 # Shadow call stack is only supported on certain rustc versions. 277 # 278 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 279 # required due to use of the -Zfixed-x18 flag. 280 # 281 # Otherwise, rustc version 1.82+ is required due to use of the 282 # -Zsanitizer=shadow-call-stack flag. 283 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 284 285config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 286 def_bool CC_IS_CLANG 287 # https://github.com/ClangBuiltLinux/linux/issues/1507 288 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 289 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 290 291config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 292 def_bool CC_IS_GCC 293 depends on $(cc-option,-fpatchable-function-entry=2) 294 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 295 296config 64BIT 297 def_bool y 298 299config MMU 300 def_bool y 301 302config ARM64_CONT_PTE_SHIFT 303 int 304 default 5 if PAGE_SIZE_64KB 305 default 7 if PAGE_SIZE_16KB 306 default 4 307 308config ARM64_CONT_PMD_SHIFT 309 int 310 default 5 if PAGE_SIZE_64KB 311 default 5 if PAGE_SIZE_16KB 312 default 4 313 314config ARCH_MMAP_RND_BITS_MIN 315 default 14 if PAGE_SIZE_64KB 316 default 16 if PAGE_SIZE_16KB 317 default 18 318 319# max bits determined by the following formula: 320# VA_BITS - PAGE_SHIFT - 3 321config ARCH_MMAP_RND_BITS_MAX 322 default 19 if ARM64_VA_BITS=36 323 default 24 if ARM64_VA_BITS=39 324 default 27 if ARM64_VA_BITS=42 325 default 30 if ARM64_VA_BITS=47 326 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 327 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 328 default 33 if ARM64_VA_BITS=48 329 default 14 if ARM64_64K_PAGES 330 default 16 if ARM64_16K_PAGES 331 default 18 332 333config ARCH_MMAP_RND_COMPAT_BITS_MIN 334 default 7 if ARM64_64K_PAGES 335 default 9 if ARM64_16K_PAGES 336 default 11 337 338config ARCH_MMAP_RND_COMPAT_BITS_MAX 339 default 16 340 341config NO_IOPORT_MAP 342 def_bool y if !PCI 343 344config STACKTRACE_SUPPORT 345 def_bool y 346 347config ILLEGAL_POINTER_VALUE 348 hex 349 default 0xdead000000000000 350 351config LOCKDEP_SUPPORT 352 def_bool y 353 354config GENERIC_BUG 355 def_bool y 356 depends on BUG 357 358config GENERIC_BUG_RELATIVE_POINTERS 359 def_bool y 360 depends on GENERIC_BUG 361 362config GENERIC_HWEIGHT 363 def_bool y 364 365config GENERIC_CSUM 366 def_bool y 367 368config GENERIC_CALIBRATE_DELAY 369 def_bool y 370 371config SMP 372 def_bool y 373 374config KERNEL_MODE_NEON 375 def_bool y 376 377config FIX_EARLYCON_MEM 378 def_bool y 379 380config PGTABLE_LEVELS 381 int 382 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 383 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 384 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 385 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 386 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 387 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 388 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 389 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 390 391config ARCH_SUPPORTS_UPROBES 392 def_bool y 393 394config ARCH_PROC_KCORE_TEXT 395 def_bool y 396 397config BROKEN_GAS_INST 398 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 399 400config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 401 bool 402 # Clang's __builtin_return_address() strips the PAC since 12.0.0 403 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 404 default y if CC_IS_CLANG 405 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 406 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 407 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 408 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 409 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 410 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 411 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 412 default n 413 414config KASAN_SHADOW_OFFSET 415 hex 416 depends on KASAN_GENERIC || KASAN_SW_TAGS 417 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 418 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 419 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 420 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 421 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 422 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 423 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 424 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 425 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 426 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 427 default 0xffffffffffffffff 428 429config UNWIND_TABLES 430 bool 431 432source "arch/arm64/Kconfig.platforms" 433 434menu "Kernel Features" 435 436menu "ARM errata workarounds via the alternatives framework" 437 438config AMPERE_ERRATUM_AC03_CPU_38 439 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 440 default y 441 help 442 This option adds an alternative code sequence to work around Ampere 443 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 444 445 The affected design reports FEAT_HAFDBS as not implemented in 446 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 447 as required by the architecture. The unadvertised HAFDBS 448 implementation suffers from an additional erratum where hardware 449 A/D updates can occur after a PTE has been marked invalid. 450 451 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 452 which avoids enabling unadvertised hardware Access Flag management 453 at stage-2. 454 455 If unsure, say Y. 456 457config ARM64_WORKAROUND_CLEAN_CACHE 458 bool 459 460config ARM64_ERRATUM_826319 461 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 462 default y 463 select ARM64_WORKAROUND_CLEAN_CACHE 464 help 465 This option adds an alternative code sequence to work around ARM 466 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 467 AXI master interface and an L2 cache. 468 469 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 470 and is unable to accept a certain write via this interface, it will 471 not progress on read data presented on the read data channel and the 472 system can deadlock. 473 474 The workaround promotes data cache clean instructions to 475 data cache clean-and-invalidate. 476 Please note that this does not necessarily enable the workaround, 477 as it depends on the alternative framework, which will only patch 478 the kernel if an affected CPU is detected. 479 480 If unsure, say Y. 481 482config ARM64_ERRATUM_827319 483 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 484 default y 485 select ARM64_WORKAROUND_CLEAN_CACHE 486 help 487 This option adds an alternative code sequence to work around ARM 488 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 489 master interface and an L2 cache. 490 491 Under certain conditions this erratum can cause a clean line eviction 492 to occur at the same time as another transaction to the same address 493 on the AMBA 5 CHI interface, which can cause data corruption if the 494 interconnect reorders the two transactions. 495 496 The workaround promotes data cache clean instructions to 497 data cache clean-and-invalidate. 498 Please note that this does not necessarily enable the workaround, 499 as it depends on the alternative framework, which will only patch 500 the kernel if an affected CPU is detected. 501 502 If unsure, say Y. 503 504config ARM64_ERRATUM_824069 505 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 506 default y 507 select ARM64_WORKAROUND_CLEAN_CACHE 508 help 509 This option adds an alternative code sequence to work around ARM 510 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 511 to a coherent interconnect. 512 513 If a Cortex-A53 processor is executing a store or prefetch for 514 write instruction at the same time as a processor in another 515 cluster is executing a cache maintenance operation to the same 516 address, then this erratum might cause a clean cache line to be 517 incorrectly marked as dirty. 518 519 The workaround promotes data cache clean instructions to 520 data cache clean-and-invalidate. 521 Please note that this option does not necessarily enable the 522 workaround, as it depends on the alternative framework, which will 523 only patch the kernel if an affected CPU is detected. 524 525 If unsure, say Y. 526 527config ARM64_ERRATUM_819472 528 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 529 default y 530 select ARM64_WORKAROUND_CLEAN_CACHE 531 help 532 This option adds an alternative code sequence to work around ARM 533 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 534 present when it is connected to a coherent interconnect. 535 536 If the processor is executing a load and store exclusive sequence at 537 the same time as a processor in another cluster is executing a cache 538 maintenance operation to the same address, then this erratum might 539 cause data corruption. 540 541 The workaround promotes data cache clean instructions to 542 data cache clean-and-invalidate. 543 Please note that this does not necessarily enable the workaround, 544 as it depends on the alternative framework, which will only patch 545 the kernel if an affected CPU is detected. 546 547 If unsure, say Y. 548 549config ARM64_ERRATUM_832075 550 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 551 default y 552 help 553 This option adds an alternative code sequence to work around ARM 554 erratum 832075 on Cortex-A57 parts up to r1p2. 555 556 Affected Cortex-A57 parts might deadlock when exclusive load/store 557 instructions to Write-Back memory are mixed with Device loads. 558 559 The workaround is to promote device loads to use Load-Acquire 560 semantics. 561 Please note that this does not necessarily enable the workaround, 562 as it depends on the alternative framework, which will only patch 563 the kernel if an affected CPU is detected. 564 565 If unsure, say Y. 566 567config ARM64_ERRATUM_834220 568 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 569 depends on KVM 570 help 571 This option adds an alternative code sequence to work around ARM 572 erratum 834220 on Cortex-A57 parts up to r1p2. 573 574 Affected Cortex-A57 parts might report a Stage 2 translation 575 fault as the result of a Stage 1 fault for load crossing a 576 page boundary when there is a permission or device memory 577 alignment fault at Stage 1 and a translation fault at Stage 2. 578 579 The workaround is to verify that the Stage 1 translation 580 doesn't generate a fault before handling the Stage 2 fault. 581 Please note that this does not necessarily enable the workaround, 582 as it depends on the alternative framework, which will only patch 583 the kernel if an affected CPU is detected. 584 585 If unsure, say N. 586 587config ARM64_ERRATUM_1742098 588 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 589 depends on COMPAT 590 default y 591 help 592 This option removes the AES hwcap for aarch32 user-space to 593 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 594 595 Affected parts may corrupt the AES state if an interrupt is 596 taken between a pair of AES instructions. These instructions 597 are only present if the cryptography extensions are present. 598 All software should have a fallback implementation for CPUs 599 that don't implement the cryptography extensions. 600 601 If unsure, say Y. 602 603config ARM64_ERRATUM_845719 604 bool "Cortex-A53: 845719: a load might read incorrect data" 605 depends on COMPAT 606 default y 607 help 608 This option adds an alternative code sequence to work around ARM 609 erratum 845719 on Cortex-A53 parts up to r0p4. 610 611 When running a compat (AArch32) userspace on an affected Cortex-A53 612 part, a load at EL0 from a virtual address that matches the bottom 32 613 bits of the virtual address used by a recent load at (AArch64) EL1 614 might return incorrect data. 615 616 The workaround is to write the contextidr_el1 register on exception 617 return to a 32-bit task. 618 Please note that this does not necessarily enable the workaround, 619 as it depends on the alternative framework, which will only patch 620 the kernel if an affected CPU is detected. 621 622 If unsure, say Y. 623 624config ARM64_ERRATUM_843419 625 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 626 default y 627 help 628 This option links the kernel with '--fix-cortex-a53-843419' and 629 enables PLT support to replace certain ADRP instructions, which can 630 cause subsequent memory accesses to use an incorrect address on 631 Cortex-A53 parts up to r0p4. 632 633 If unsure, say Y. 634 635config ARM64_LD_HAS_FIX_ERRATUM_843419 636 def_bool $(ld-option,--fix-cortex-a53-843419) 637 638config ARM64_ERRATUM_1024718 639 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 640 default y 641 help 642 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 643 644 Affected Cortex-A55 cores (all revisions) could cause incorrect 645 update of the hardware dirty bit when the DBM/AP bits are updated 646 without a break-before-make. The workaround is to disable the usage 647 of hardware DBM locally on the affected cores. CPUs not affected by 648 this erratum will continue to use the feature. 649 650 If unsure, say Y. 651 652config ARM64_ERRATUM_1418040 653 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 654 default y 655 depends on COMPAT 656 help 657 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 658 errata 1188873 and 1418040. 659 660 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 661 cause register corruption when accessing the timer registers 662 from AArch32 userspace. 663 664 If unsure, say Y. 665 666config ARM64_WORKAROUND_SPECULATIVE_AT 667 bool 668 669config ARM64_ERRATUM_1165522 670 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 671 default y 672 select ARM64_WORKAROUND_SPECULATIVE_AT 673 help 674 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 675 676 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 677 corrupted TLBs by speculating an AT instruction during a guest 678 context switch. 679 680 If unsure, say Y. 681 682config ARM64_ERRATUM_1319367 683 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 684 default y 685 select ARM64_WORKAROUND_SPECULATIVE_AT 686 help 687 This option adds work arounds for ARM Cortex-A57 erratum 1319537 688 and A72 erratum 1319367 689 690 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 691 speculating an AT instruction during a guest context switch. 692 693 If unsure, say Y. 694 695config ARM64_ERRATUM_1530923 696 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 697 default y 698 select ARM64_WORKAROUND_SPECULATIVE_AT 699 help 700 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 701 702 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 703 corrupted TLBs by speculating an AT instruction during a guest 704 context switch. 705 706 If unsure, say Y. 707 708config ARM64_WORKAROUND_REPEAT_TLBI 709 bool 710 711config ARM64_ERRATUM_2441007 712 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 713 select ARM64_WORKAROUND_REPEAT_TLBI 714 help 715 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 716 717 Under very rare circumstances, affected Cortex-A55 CPUs 718 may not handle a race between a break-before-make sequence on one 719 CPU, and another CPU accessing the same page. This could allow a 720 store to a page that has been unmapped. 721 722 Work around this by adding the affected CPUs to the list that needs 723 TLB sequences to be done twice. 724 725 If unsure, say N. 726 727config ARM64_ERRATUM_1286807 728 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 729 select ARM64_WORKAROUND_REPEAT_TLBI 730 help 731 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 732 733 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 734 address for a cacheable mapping of a location is being 735 accessed by a core while another core is remapping the virtual 736 address to a new physical page using the recommended 737 break-before-make sequence, then under very rare circumstances 738 TLBI+DSB completes before a read using the translation being 739 invalidated has been observed by other observers. The 740 workaround repeats the TLBI+DSB operation. 741 742 If unsure, say N. 743 744config ARM64_ERRATUM_1463225 745 bool "Cortex-A76: Software Step might prevent interrupt recognition" 746 default y 747 help 748 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 749 750 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 751 of a system call instruction (SVC) can prevent recognition of 752 subsequent interrupts when software stepping is disabled in the 753 exception handler of the system call and either kernel debugging 754 is enabled or VHE is in use. 755 756 Work around the erratum by triggering a dummy step exception 757 when handling a system call from a task that is being stepped 758 in a VHE configuration of the kernel. 759 760 If unsure, say Y. 761 762config ARM64_ERRATUM_1542419 763 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 764 help 765 This option adds a workaround for ARM Neoverse-N1 erratum 766 1542419. 767 768 Affected Neoverse-N1 cores could execute a stale instruction when 769 modified by another CPU. The workaround depends on a firmware 770 counterpart. 771 772 Workaround the issue by hiding the DIC feature from EL0. This 773 forces user-space to perform cache maintenance. 774 775 If unsure, say N. 776 777config ARM64_ERRATUM_1508412 778 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 779 default y 780 help 781 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 782 783 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 784 of a store-exclusive or read of PAR_EL1 and a load with device or 785 non-cacheable memory attributes. The workaround depends on a firmware 786 counterpart. 787 788 KVM guests must also have the workaround implemented or they can 789 deadlock the system. 790 791 Work around the issue by inserting DMB SY barriers around PAR_EL1 792 register reads and warning KVM users. The DMB barrier is sufficient 793 to prevent a speculative PAR_EL1 read. 794 795 If unsure, say Y. 796 797config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 798 bool 799 800config ARM64_ERRATUM_2051678 801 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 802 default y 803 help 804 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 805 Affected Cortex-A510 might not respect the ordering rules for 806 hardware update of the page table's dirty bit. The workaround 807 is to not enable the feature on affected CPUs. 808 809 If unsure, say Y. 810 811config ARM64_ERRATUM_2077057 812 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 813 default y 814 help 815 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 816 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 817 expected, but a Pointer Authentication trap is taken instead. The 818 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 819 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 820 821 This can only happen when EL2 is stepping EL1. 822 823 When these conditions occur, the SPSR_EL2 value is unchanged from the 824 previous guest entry, and can be restored from the in-memory copy. 825 826 If unsure, say Y. 827 828config ARM64_ERRATUM_2658417 829 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 830 default y 831 help 832 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 833 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 834 BFMMLA or VMMLA instructions in rare circumstances when a pair of 835 A510 CPUs are using shared neon hardware. As the sharing is not 836 discoverable by the kernel, hide the BF16 HWCAP to indicate that 837 user-space should not be using these instructions. 838 839 If unsure, say Y. 840 841config ARM64_ERRATUM_2119858 842 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 843 default y 844 depends on CORESIGHT_TRBE 845 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 846 help 847 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 848 849 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 850 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 851 the event of a WRAP event. 852 853 Work around the issue by always making sure we move the TRBPTR_EL1 by 854 256 bytes before enabling the buffer and filling the first 256 bytes of 855 the buffer with ETM ignore packets upon disabling. 856 857 If unsure, say Y. 858 859config ARM64_ERRATUM_2139208 860 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 861 default y 862 depends on CORESIGHT_TRBE 863 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 864 help 865 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 866 867 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 868 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 869 the event of a WRAP event. 870 871 Work around the issue by always making sure we move the TRBPTR_EL1 by 872 256 bytes before enabling the buffer and filling the first 256 bytes of 873 the buffer with ETM ignore packets upon disabling. 874 875 If unsure, say Y. 876 877config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 878 bool 879 880config ARM64_ERRATUM_2054223 881 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 882 default y 883 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 884 help 885 Enable workaround for ARM Cortex-A710 erratum 2054223 886 887 Affected cores may fail to flush the trace data on a TSB instruction, when 888 the PE is in trace prohibited state. This will cause losing a few bytes 889 of the trace cached. 890 891 Workaround is to issue two TSB consecutively on affected cores. 892 893 If unsure, say Y. 894 895config ARM64_ERRATUM_2067961 896 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 897 default y 898 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 899 help 900 Enable workaround for ARM Neoverse-N2 erratum 2067961 901 902 Affected cores may fail to flush the trace data on a TSB instruction, when 903 the PE is in trace prohibited state. This will cause losing a few bytes 904 of the trace cached. 905 906 Workaround is to issue two TSB consecutively on affected cores. 907 908 If unsure, say Y. 909 910config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 911 bool 912 913config ARM64_ERRATUM_2253138 914 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 915 depends on CORESIGHT_TRBE 916 default y 917 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 918 help 919 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 920 921 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 922 for TRBE. Under some conditions, the TRBE might generate a write to the next 923 virtually addressed page following the last page of the TRBE address space 924 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 925 926 Work around this in the driver by always making sure that there is a 927 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 928 929 If unsure, say Y. 930 931config ARM64_ERRATUM_2224489 932 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 933 depends on CORESIGHT_TRBE 934 default y 935 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 936 help 937 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 938 939 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 940 for TRBE. Under some conditions, the TRBE might generate a write to the next 941 virtually addressed page following the last page of the TRBE address space 942 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 943 944 Work around this in the driver by always making sure that there is a 945 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 946 947 If unsure, say Y. 948 949config ARM64_ERRATUM_2441009 950 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 951 select ARM64_WORKAROUND_REPEAT_TLBI 952 help 953 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 954 955 Under very rare circumstances, affected Cortex-A510 CPUs 956 may not handle a race between a break-before-make sequence on one 957 CPU, and another CPU accessing the same page. This could allow a 958 store to a page that has been unmapped. 959 960 Work around this by adding the affected CPUs to the list that needs 961 TLB sequences to be done twice. 962 963 If unsure, say N. 964 965config ARM64_ERRATUM_2064142 966 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 967 depends on CORESIGHT_TRBE 968 default y 969 help 970 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 971 972 Affected Cortex-A510 core might fail to write into system registers after the 973 TRBE has been disabled. Under some conditions after the TRBE has been disabled 974 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 975 and TRBTRG_EL1 will be ignored and will not be effected. 976 977 Work around this in the driver by executing TSB CSYNC and DSB after collection 978 is stopped and before performing a system register write to one of the affected 979 registers. 980 981 If unsure, say Y. 982 983config ARM64_ERRATUM_2038923 984 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 985 depends on CORESIGHT_TRBE 986 default y 987 help 988 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 989 990 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 991 prohibited within the CPU. As a result, the trace buffer or trace buffer state 992 might be corrupted. This happens after TRBE buffer has been enabled by setting 993 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 994 execution changes from a context, in which trace is prohibited to one where it 995 isn't, or vice versa. In these mentioned conditions, the view of whether trace 996 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 997 the trace buffer state might be corrupted. 998 999 Work around this in the driver by preventing an inconsistent view of whether the 1000 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1001 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1002 two ISB instructions if no ERET is to take place. 1003 1004 If unsure, say Y. 1005 1006config ARM64_ERRATUM_1902691 1007 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1008 depends on CORESIGHT_TRBE 1009 default y 1010 help 1011 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1012 1013 Affected Cortex-A510 core might cause trace data corruption, when being written 1014 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1015 trace data. 1016 1017 Work around this problem in the driver by just preventing TRBE initialization on 1018 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1019 on such implementations. This will cover the kernel for any firmware that doesn't 1020 do this already. 1021 1022 If unsure, say Y. 1023 1024config ARM64_ERRATUM_2457168 1025 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1026 depends on ARM64_AMU_EXTN 1027 default y 1028 help 1029 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1030 1031 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1032 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1033 incorrectly giving a significantly higher output value. 1034 1035 Work around this problem by returning 0 when reading the affected counter in 1036 key locations that results in disabling all users of this counter. This effect 1037 is the same to firmware disabling affected counters. 1038 1039 If unsure, say Y. 1040 1041config ARM64_ERRATUM_2645198 1042 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1043 default y 1044 help 1045 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1046 1047 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1048 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1049 next instruction abort caused by permission fault. 1050 1051 Only user-space does executable to non-executable permission transition via 1052 mprotect() system call. Workaround the problem by doing a break-before-make 1053 TLB invalidation, for all changes to executable user space mappings. 1054 1055 If unsure, say Y. 1056 1057config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1058 bool 1059 1060config ARM64_ERRATUM_2966298 1061 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1062 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1063 default y 1064 help 1065 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1066 1067 On an affected Cortex-A520 core, a speculatively executed unprivileged 1068 load might leak data from a privileged level via a cache side channel. 1069 1070 Work around this problem by executing a TLBI before returning to EL0. 1071 1072 If unsure, say Y. 1073 1074config ARM64_ERRATUM_3117295 1075 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1076 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1077 default y 1078 help 1079 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1080 1081 On an affected Cortex-A510 core, a speculatively executed unprivileged 1082 load might leak data from a privileged level via a cache side channel. 1083 1084 Work around this problem by executing a TLBI before returning to EL0. 1085 1086 If unsure, say Y. 1087 1088config ARM64_ERRATUM_3194386 1089 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1090 default y 1091 help 1092 This option adds the workaround for the following errata: 1093 1094 * ARM Cortex-A76 erratum 3324349 1095 * ARM Cortex-A77 erratum 3324348 1096 * ARM Cortex-A78 erratum 3324344 1097 * ARM Cortex-A78C erratum 3324346 1098 * ARM Cortex-A78C erratum 3324347 1099 * ARM Cortex-A710 erratam 3324338 1100 * ARM Cortex-A720 erratum 3456091 1101 * ARM Cortex-A725 erratum 3456106 1102 * ARM Cortex-X1 erratum 3324344 1103 * ARM Cortex-X1C erratum 3324346 1104 * ARM Cortex-X2 erratum 3324338 1105 * ARM Cortex-X3 erratum 3324335 1106 * ARM Cortex-X4 erratum 3194386 1107 * ARM Cortex-X925 erratum 3324334 1108 * ARM Neoverse-N1 erratum 3324349 1109 * ARM Neoverse N2 erratum 3324339 1110 * ARM Neoverse-V1 erratum 3324341 1111 * ARM Neoverse V2 erratum 3324336 1112 * ARM Neoverse-V3 erratum 3312417 1113 1114 On affected cores "MSR SSBS, #0" instructions may not affect 1115 subsequent speculative instructions, which may permit unexepected 1116 speculative store bypassing. 1117 1118 Work around this problem by placing a Speculation Barrier (SB) or 1119 Instruction Synchronization Barrier (ISB) after kernel changes to 1120 SSBS. The presence of the SSBS special-purpose register is hidden 1121 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1122 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1123 1124 If unsure, say Y. 1125 1126config CAVIUM_ERRATUM_22375 1127 bool "Cavium erratum 22375, 24313" 1128 default y 1129 help 1130 Enable workaround for errata 22375 and 24313. 1131 1132 This implements two gicv3-its errata workarounds for ThunderX. Both 1133 with a small impact affecting only ITS table allocation. 1134 1135 erratum 22375: only alloc 8MB table size 1136 erratum 24313: ignore memory access type 1137 1138 The fixes are in ITS initialization and basically ignore memory access 1139 type and table size provided by the TYPER and BASER registers. 1140 1141 If unsure, say Y. 1142 1143config CAVIUM_ERRATUM_23144 1144 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1145 depends on NUMA 1146 default y 1147 help 1148 ITS SYNC command hang for cross node io and collections/cpu mapping. 1149 1150 If unsure, say Y. 1151 1152config CAVIUM_ERRATUM_23154 1153 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1154 default y 1155 help 1156 The ThunderX GICv3 implementation requires a modified version for 1157 reading the IAR status to ensure data synchronization 1158 (access to icc_iar1_el1 is not sync'ed before and after). 1159 1160 It also suffers from erratum 38545 (also present on Marvell's 1161 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1162 spuriously presented to the CPU interface. 1163 1164 If unsure, say Y. 1165 1166config CAVIUM_ERRATUM_27456 1167 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1168 default y 1169 help 1170 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1171 instructions may cause the icache to become corrupted if it 1172 contains data for a non-current ASID. The fix is to 1173 invalidate the icache when changing the mm context. 1174 1175 If unsure, say Y. 1176 1177config CAVIUM_ERRATUM_30115 1178 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1179 default y 1180 help 1181 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1182 1.2, and T83 Pass 1.0, KVM guest execution may disable 1183 interrupts in host. Trapping both GICv3 group-0 and group-1 1184 accesses sidesteps the issue. 1185 1186 If unsure, say Y. 1187 1188config CAVIUM_TX2_ERRATUM_219 1189 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1190 default y 1191 help 1192 On Cavium ThunderX2, a load, store or prefetch instruction between a 1193 TTBR update and the corresponding context synchronizing operation can 1194 cause a spurious Data Abort to be delivered to any hardware thread in 1195 the CPU core. 1196 1197 Work around the issue by avoiding the problematic code sequence and 1198 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1199 trap handler performs the corresponding register access, skips the 1200 instruction and ensures context synchronization by virtue of the 1201 exception return. 1202 1203 If unsure, say Y. 1204 1205config FUJITSU_ERRATUM_010001 1206 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1207 default y 1208 help 1209 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1210 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1211 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1212 This fault occurs under a specific hardware condition when a 1213 load/store instruction performs an address translation using: 1214 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1215 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1216 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1217 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1218 1219 The workaround is to ensure these bits are clear in TCR_ELx. 1220 The workaround only affects the Fujitsu-A64FX. 1221 1222 If unsure, say Y. 1223 1224config HISILICON_ERRATUM_161600802 1225 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1226 default y 1227 help 1228 The HiSilicon Hip07 SoC uses the wrong redistributor base 1229 when issued ITS commands such as VMOVP and VMAPP, and requires 1230 a 128kB offset to be applied to the target address in this commands. 1231 1232 If unsure, say Y. 1233 1234config QCOM_FALKOR_ERRATUM_1003 1235 bool "Falkor E1003: Incorrect translation due to ASID change" 1236 default y 1237 help 1238 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1239 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1240 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1241 then only for entries in the walk cache, since the leaf translation 1242 is unchanged. Work around the erratum by invalidating the walk cache 1243 entries for the trampoline before entering the kernel proper. 1244 1245config QCOM_FALKOR_ERRATUM_1009 1246 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1247 default y 1248 select ARM64_WORKAROUND_REPEAT_TLBI 1249 help 1250 On Falkor v1, the CPU may prematurely complete a DSB following a 1251 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1252 one more time to fix the issue. 1253 1254 If unsure, say Y. 1255 1256config QCOM_QDF2400_ERRATUM_0065 1257 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1258 default y 1259 help 1260 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1261 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1262 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1263 1264 If unsure, say Y. 1265 1266config QCOM_FALKOR_ERRATUM_E1041 1267 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1268 default y 1269 help 1270 Falkor CPU may speculatively fetch instructions from an improper 1271 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1272 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1273 1274 If unsure, say Y. 1275 1276config NVIDIA_CARMEL_CNP_ERRATUM 1277 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1278 default y 1279 help 1280 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1281 invalidate shared TLB entries installed by a different core, as it would 1282 on standard ARM cores. 1283 1284 If unsure, say Y. 1285 1286config ROCKCHIP_ERRATUM_3588001 1287 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1288 default y 1289 help 1290 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1291 This means, that its sharability feature may not be used, even though it 1292 is supported by the IP itself. 1293 1294 If unsure, say Y. 1295 1296config SOCIONEXT_SYNQUACER_PREITS 1297 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1298 default y 1299 help 1300 Socionext Synquacer SoCs implement a separate h/w block to generate 1301 MSI doorbell writes with non-zero values for the device ID. 1302 1303 If unsure, say Y. 1304 1305endmenu # "ARM errata workarounds via the alternatives framework" 1306 1307choice 1308 prompt "Page size" 1309 default ARM64_4K_PAGES 1310 help 1311 Page size (translation granule) configuration. 1312 1313config ARM64_4K_PAGES 1314 bool "4KB" 1315 select HAVE_PAGE_SIZE_4KB 1316 help 1317 This feature enables 4KB pages support. 1318 1319config ARM64_16K_PAGES 1320 bool "16KB" 1321 select HAVE_PAGE_SIZE_16KB 1322 help 1323 The system will use 16KB pages support. AArch32 emulation 1324 requires applications compiled with 16K (or a multiple of 16K) 1325 aligned segments. 1326 1327config ARM64_64K_PAGES 1328 bool "64KB" 1329 select HAVE_PAGE_SIZE_64KB 1330 help 1331 This feature enables 64KB pages support (4KB by default) 1332 allowing only two levels of page tables and faster TLB 1333 look-up. AArch32 emulation requires applications compiled 1334 with 64K aligned segments. 1335 1336endchoice 1337 1338choice 1339 prompt "Virtual address space size" 1340 default ARM64_VA_BITS_52 1341 help 1342 Allows choosing one of multiple possible virtual address 1343 space sizes. The level of translation table is determined by 1344 a combination of page size and virtual address space size. 1345 1346config ARM64_VA_BITS_36 1347 bool "36-bit" if EXPERT 1348 depends on PAGE_SIZE_16KB 1349 1350config ARM64_VA_BITS_39 1351 bool "39-bit" 1352 depends on PAGE_SIZE_4KB 1353 1354config ARM64_VA_BITS_42 1355 bool "42-bit" 1356 depends on PAGE_SIZE_64KB 1357 1358config ARM64_VA_BITS_47 1359 bool "47-bit" 1360 depends on PAGE_SIZE_16KB 1361 1362config ARM64_VA_BITS_48 1363 bool "48-bit" 1364 1365config ARM64_VA_BITS_52 1366 bool "52-bit" 1367 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1368 help 1369 Enable 52-bit virtual addressing for userspace when explicitly 1370 requested via a hint to mmap(). The kernel will also use 52-bit 1371 virtual addresses for its own mappings (provided HW support for 1372 this feature is available, otherwise it reverts to 48-bit). 1373 1374 NOTE: Enabling 52-bit virtual addressing in conjunction with 1375 ARMv8.3 Pointer Authentication will result in the PAC being 1376 reduced from 7 bits to 3 bits, which may have a significant 1377 impact on its susceptibility to brute-force attacks. 1378 1379 If unsure, select 48-bit virtual addressing instead. 1380 1381endchoice 1382 1383config ARM64_FORCE_52BIT 1384 bool "Force 52-bit virtual addresses for userspace" 1385 depends on ARM64_VA_BITS_52 && EXPERT 1386 help 1387 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1388 to maintain compatibility with older software by providing 48-bit VAs 1389 unless a hint is supplied to mmap. 1390 1391 This configuration option disables the 48-bit compatibility logic, and 1392 forces all userspace addresses to be 52-bit on HW that supports it. One 1393 should only enable this configuration option for stress testing userspace 1394 memory management code. If unsure say N here. 1395 1396config ARM64_VA_BITS 1397 int 1398 default 36 if ARM64_VA_BITS_36 1399 default 39 if ARM64_VA_BITS_39 1400 default 42 if ARM64_VA_BITS_42 1401 default 47 if ARM64_VA_BITS_47 1402 default 48 if ARM64_VA_BITS_48 1403 default 52 if ARM64_VA_BITS_52 1404 1405choice 1406 prompt "Physical address space size" 1407 default ARM64_PA_BITS_48 1408 help 1409 Choose the maximum physical address range that the kernel will 1410 support. 1411 1412config ARM64_PA_BITS_48 1413 bool "48-bit" 1414 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1415 1416config ARM64_PA_BITS_52 1417 bool "52-bit" 1418 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1419 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1420 help 1421 Enable support for a 52-bit physical address space, introduced as 1422 part of the ARMv8.2-LPA extension. 1423 1424 With this enabled, the kernel will also continue to work on CPUs that 1425 do not support ARMv8.2-LPA, but with some added memory overhead (and 1426 minor performance overhead). 1427 1428endchoice 1429 1430config ARM64_PA_BITS 1431 int 1432 default 48 if ARM64_PA_BITS_48 1433 default 52 if ARM64_PA_BITS_52 1434 1435config ARM64_LPA2 1436 def_bool y 1437 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1438 1439choice 1440 prompt "Endianness" 1441 default CPU_LITTLE_ENDIAN 1442 help 1443 Select the endianness of data accesses performed by the CPU. Userspace 1444 applications will need to be compiled and linked for the endianness 1445 that is selected here. 1446 1447config CPU_BIG_ENDIAN 1448 bool "Build big-endian kernel" 1449 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1450 depends on AS_IS_GNU || AS_VERSION >= 150000 1451 help 1452 Say Y if you plan on running a kernel with a big-endian userspace. 1453 1454config CPU_LITTLE_ENDIAN 1455 bool "Build little-endian kernel" 1456 help 1457 Say Y if you plan on running a kernel with a little-endian userspace. 1458 This is usually the case for distributions targeting arm64. 1459 1460endchoice 1461 1462config SCHED_MC 1463 bool "Multi-core scheduler support" 1464 help 1465 Multi-core scheduler support improves the CPU scheduler's decision 1466 making when dealing with multi-core CPU chips at a cost of slightly 1467 increased overhead in some places. If unsure say N here. 1468 1469config SCHED_CLUSTER 1470 bool "Cluster scheduler support" 1471 help 1472 Cluster scheduler support improves the CPU scheduler's decision 1473 making when dealing with machines that have clusters of CPUs. 1474 Cluster usually means a couple of CPUs which are placed closely 1475 by sharing mid-level caches, last-level cache tags or internal 1476 busses. 1477 1478config SCHED_SMT 1479 bool "SMT scheduler support" 1480 help 1481 Improves the CPU scheduler's decision making when dealing with 1482 MultiThreading at a cost of slightly increased overhead in some 1483 places. If unsure say N here. 1484 1485config NR_CPUS 1486 int "Maximum number of CPUs (2-4096)" 1487 range 2 4096 1488 default "512" 1489 1490config HOTPLUG_CPU 1491 bool "Support for hot-pluggable CPUs" 1492 select GENERIC_IRQ_MIGRATION 1493 help 1494 Say Y here to experiment with turning CPUs off and on. CPUs 1495 can be controlled through /sys/devices/system/cpu. 1496 1497# Common NUMA Features 1498config NUMA 1499 bool "NUMA Memory Allocation and Scheduler Support" 1500 select GENERIC_ARCH_NUMA 1501 select OF_NUMA 1502 select HAVE_SETUP_PER_CPU_AREA 1503 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1504 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1505 select USE_PERCPU_NUMA_NODE_ID 1506 help 1507 Enable NUMA (Non-Uniform Memory Access) support. 1508 1509 The kernel will try to allocate memory used by a CPU on the 1510 local memory of the CPU and add some more 1511 NUMA awareness to the kernel. 1512 1513config NODES_SHIFT 1514 int "Maximum NUMA Nodes (as a power of 2)" 1515 range 1 10 1516 default "4" 1517 depends on NUMA 1518 help 1519 Specify the maximum number of NUMA Nodes available on the target 1520 system. Increases memory reserved to accommodate various tables. 1521 1522source "kernel/Kconfig.hz" 1523 1524config ARCH_SPARSEMEM_ENABLE 1525 def_bool y 1526 select SPARSEMEM_VMEMMAP_ENABLE 1527 select SPARSEMEM_VMEMMAP 1528 1529config HW_PERF_EVENTS 1530 def_bool y 1531 depends on ARM_PMU 1532 1533# Supported by clang >= 7.0 or GCC >= 12.0.0 1534config CC_HAVE_SHADOW_CALL_STACK 1535 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1536 1537config PARAVIRT 1538 bool "Enable paravirtualization code" 1539 help 1540 This changes the kernel so it can modify itself when it is run 1541 under a hypervisor, potentially improving performance significantly 1542 over full virtualization. 1543 1544config PARAVIRT_TIME_ACCOUNTING 1545 bool "Paravirtual steal time accounting" 1546 select PARAVIRT 1547 help 1548 Select this option to enable fine granularity task steal time 1549 accounting. Time spent executing other tasks in parallel with 1550 the current vCPU is discounted from the vCPU power. To account for 1551 that, there can be a small performance impact. 1552 1553 If in doubt, say N here. 1554 1555config ARCH_SUPPORTS_KEXEC 1556 def_bool PM_SLEEP_SMP 1557 1558config ARCH_SUPPORTS_KEXEC_FILE 1559 def_bool y 1560 1561config ARCH_SELECTS_KEXEC_FILE 1562 def_bool y 1563 depends on KEXEC_FILE 1564 select HAVE_IMA_KEXEC if IMA 1565 1566config ARCH_SUPPORTS_KEXEC_SIG 1567 def_bool y 1568 1569config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1570 def_bool y 1571 1572config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1573 def_bool y 1574 1575config ARCH_SUPPORTS_CRASH_DUMP 1576 def_bool y 1577 1578config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1579 def_bool CRASH_RESERVE 1580 1581config TRANS_TABLE 1582 def_bool y 1583 depends on HIBERNATION || KEXEC_CORE 1584 1585config XEN_DOM0 1586 def_bool y 1587 depends on XEN 1588 1589config XEN 1590 bool "Xen guest support on ARM64" 1591 depends on ARM64 && OF 1592 select SWIOTLB_XEN 1593 select PARAVIRT 1594 help 1595 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1596 1597# include/linux/mmzone.h requires the following to be true: 1598# 1599# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1600# 1601# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1602# 1603# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1604# ----+-------------------+--------------+----------------------+-------------------------+ 1605# 4K | 27 | 12 | 15 | 10 | 1606# 16K | 27 | 14 | 13 | 11 | 1607# 64K | 29 | 16 | 13 | 13 | 1608config ARCH_FORCE_MAX_ORDER 1609 int 1610 default "13" if ARM64_64K_PAGES 1611 default "11" if ARM64_16K_PAGES 1612 default "10" 1613 help 1614 The kernel page allocator limits the size of maximal physically 1615 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1616 defines the maximal power of two of number of pages that can be 1617 allocated as a single contiguous block. This option allows 1618 overriding the default setting when ability to allocate very 1619 large blocks of physically contiguous memory is required. 1620 1621 The maximal size of allocation cannot exceed the size of the 1622 section, so the value of MAX_PAGE_ORDER should satisfy 1623 1624 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1625 1626 Don't change if unsure. 1627 1628config UNMAP_KERNEL_AT_EL0 1629 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1630 default y 1631 help 1632 Speculation attacks against some high-performance processors can 1633 be used to bypass MMU permission checks and leak kernel data to 1634 userspace. This can be defended against by unmapping the kernel 1635 when running in userspace, mapping it back in on exception entry 1636 via a trampoline page in the vector table. 1637 1638 If unsure, say Y. 1639 1640config MITIGATE_SPECTRE_BRANCH_HISTORY 1641 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1642 default y 1643 help 1644 Speculation attacks against some high-performance processors can 1645 make use of branch history to influence future speculation. 1646 When taking an exception from user-space, a sequence of branches 1647 or a firmware call overwrites the branch history. 1648 1649config RODATA_FULL_DEFAULT_ENABLED 1650 bool "Apply r/o permissions of VM areas also to their linear aliases" 1651 default y 1652 help 1653 Apply read-only attributes of VM areas to the linear alias of 1654 the backing pages as well. This prevents code or read-only data 1655 from being modified (inadvertently or intentionally) via another 1656 mapping of the same memory page. This additional enhancement can 1657 be turned off at runtime by passing rodata=[off|on] (and turned on 1658 with rodata=full if this option is set to 'n') 1659 1660 This requires the linear region to be mapped down to pages, 1661 which may adversely affect performance in some cases. 1662 1663config ARM64_SW_TTBR0_PAN 1664 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1665 depends on !KCSAN 1666 help 1667 Enabling this option prevents the kernel from accessing 1668 user-space memory directly by pointing TTBR0_EL1 to a reserved 1669 zeroed area and reserved ASID. The user access routines 1670 restore the valid TTBR0_EL1 temporarily. 1671 1672config ARM64_TAGGED_ADDR_ABI 1673 bool "Enable the tagged user addresses syscall ABI" 1674 default y 1675 help 1676 When this option is enabled, user applications can opt in to a 1677 relaxed ABI via prctl() allowing tagged addresses to be passed 1678 to system calls as pointer arguments. For details, see 1679 Documentation/arch/arm64/tagged-address-abi.rst. 1680 1681menuconfig COMPAT 1682 bool "Kernel support for 32-bit EL0" 1683 depends on ARM64_4K_PAGES || EXPERT 1684 select HAVE_UID16 1685 select OLD_SIGSUSPEND3 1686 select COMPAT_OLD_SIGACTION 1687 help 1688 This option enables support for a 32-bit EL0 running under a 64-bit 1689 kernel at EL1. AArch32-specific components such as system calls, 1690 the user helper functions, VFP support and the ptrace interface are 1691 handled appropriately by the kernel. 1692 1693 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1694 that you will only be able to execute AArch32 binaries that were compiled 1695 with page size aligned segments. 1696 1697 If you want to execute 32-bit userspace applications, say Y. 1698 1699if COMPAT 1700 1701config KUSER_HELPERS 1702 bool "Enable kuser helpers page for 32-bit applications" 1703 default y 1704 help 1705 Warning: disabling this option may break 32-bit user programs. 1706 1707 Provide kuser helpers to compat tasks. The kernel provides 1708 helper code to userspace in read only form at a fixed location 1709 to allow userspace to be independent of the CPU type fitted to 1710 the system. This permits binaries to be run on ARMv4 through 1711 to ARMv8 without modification. 1712 1713 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1714 1715 However, the fixed address nature of these helpers can be used 1716 by ROP (return orientated programming) authors when creating 1717 exploits. 1718 1719 If all of the binaries and libraries which run on your platform 1720 are built specifically for your platform, and make no use of 1721 these helpers, then you can turn this option off to hinder 1722 such exploits. However, in that case, if a binary or library 1723 relying on those helpers is run, it will not function correctly. 1724 1725 Say N here only if you are absolutely certain that you do not 1726 need these helpers; otherwise, the safe option is to say Y. 1727 1728config COMPAT_VDSO 1729 bool "Enable vDSO for 32-bit applications" 1730 depends on !CPU_BIG_ENDIAN 1731 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1732 select GENERIC_COMPAT_VDSO 1733 default y 1734 help 1735 Place in the process address space of 32-bit applications an 1736 ELF shared object providing fast implementations of gettimeofday 1737 and clock_gettime. 1738 1739 You must have a 32-bit build of glibc 2.22 or later for programs 1740 to seamlessly take advantage of this. 1741 1742config THUMB2_COMPAT_VDSO 1743 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1744 depends on COMPAT_VDSO 1745 default y 1746 help 1747 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1748 otherwise with '-marm'. 1749 1750config COMPAT_ALIGNMENT_FIXUPS 1751 bool "Fix up misaligned multi-word loads and stores in user space" 1752 1753menuconfig ARMV8_DEPRECATED 1754 bool "Emulate deprecated/obsolete ARMv8 instructions" 1755 depends on SYSCTL 1756 help 1757 Legacy software support may require certain instructions 1758 that have been deprecated or obsoleted in the architecture. 1759 1760 Enable this config to enable selective emulation of these 1761 features. 1762 1763 If unsure, say Y 1764 1765if ARMV8_DEPRECATED 1766 1767config SWP_EMULATION 1768 bool "Emulate SWP/SWPB instructions" 1769 help 1770 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1771 they are always undefined. Say Y here to enable software 1772 emulation of these instructions for userspace using LDXR/STXR. 1773 This feature can be controlled at runtime with the abi.swp 1774 sysctl which is disabled by default. 1775 1776 In some older versions of glibc [<=2.8] SWP is used during futex 1777 trylock() operations with the assumption that the code will not 1778 be preempted. This invalid assumption may be more likely to fail 1779 with SWP emulation enabled, leading to deadlock of the user 1780 application. 1781 1782 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1783 on an external transaction monitoring block called a global 1784 monitor to maintain update atomicity. If your system does not 1785 implement a global monitor, this option can cause programs that 1786 perform SWP operations to uncached memory to deadlock. 1787 1788 If unsure, say Y 1789 1790config CP15_BARRIER_EMULATION 1791 bool "Emulate CP15 Barrier instructions" 1792 help 1793 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1794 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1795 strongly recommended to use the ISB, DSB, and DMB 1796 instructions instead. 1797 1798 Say Y here to enable software emulation of these 1799 instructions for AArch32 userspace code. When this option is 1800 enabled, CP15 barrier usage is traced which can help 1801 identify software that needs updating. This feature can be 1802 controlled at runtime with the abi.cp15_barrier sysctl. 1803 1804 If unsure, say Y 1805 1806config SETEND_EMULATION 1807 bool "Emulate SETEND instruction" 1808 help 1809 The SETEND instruction alters the data-endianness of the 1810 AArch32 EL0, and is deprecated in ARMv8. 1811 1812 Say Y here to enable software emulation of the instruction 1813 for AArch32 userspace code. This feature can be controlled 1814 at runtime with the abi.setend sysctl. 1815 1816 Note: All the cpus on the system must have mixed endian support at EL0 1817 for this feature to be enabled. If a new CPU - which doesn't support mixed 1818 endian - is hotplugged in after this feature has been enabled, there could 1819 be unexpected results in the applications. 1820 1821 If unsure, say Y 1822endif # ARMV8_DEPRECATED 1823 1824endif # COMPAT 1825 1826menu "ARMv8.1 architectural features" 1827 1828config ARM64_HW_AFDBM 1829 bool "Support for hardware updates of the Access and Dirty page flags" 1830 default y 1831 help 1832 The ARMv8.1 architecture extensions introduce support for 1833 hardware updates of the access and dirty information in page 1834 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1835 capable processors, accesses to pages with PTE_AF cleared will 1836 set this bit instead of raising an access flag fault. 1837 Similarly, writes to read-only pages with the DBM bit set will 1838 clear the read-only bit (AP[2]) instead of raising a 1839 permission fault. 1840 1841 Kernels built with this configuration option enabled continue 1842 to work on pre-ARMv8.1 hardware and the performance impact is 1843 minimal. If unsure, say Y. 1844 1845config ARM64_PAN 1846 bool "Enable support for Privileged Access Never (PAN)" 1847 default y 1848 help 1849 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1850 prevents the kernel or hypervisor from accessing user-space (EL0) 1851 memory directly. 1852 1853 Choosing this option will cause any unprotected (not using 1854 copy_to_user et al) memory access to fail with a permission fault. 1855 1856 The feature is detected at runtime, and will remain as a 'nop' 1857 instruction if the cpu does not implement the feature. 1858 1859config AS_HAS_LSE_ATOMICS 1860 def_bool $(as-instr,.arch_extension lse) 1861 1862config ARM64_LSE_ATOMICS 1863 bool 1864 default ARM64_USE_LSE_ATOMICS 1865 depends on AS_HAS_LSE_ATOMICS 1866 1867config ARM64_USE_LSE_ATOMICS 1868 bool "Atomic instructions" 1869 default y 1870 help 1871 As part of the Large System Extensions, ARMv8.1 introduces new 1872 atomic instructions that are designed specifically to scale in 1873 very large systems. 1874 1875 Say Y here to make use of these instructions for the in-kernel 1876 atomic routines. This incurs a small overhead on CPUs that do 1877 not support these instructions and requires the kernel to be 1878 built with binutils >= 2.25 in order for the new instructions 1879 to be used. 1880 1881endmenu # "ARMv8.1 architectural features" 1882 1883menu "ARMv8.2 architectural features" 1884 1885config AS_HAS_ARMV8_2 1886 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1887 1888config AS_HAS_SHA3 1889 def_bool $(as-instr,.arch armv8.2-a+sha3) 1890 1891config ARM64_PMEM 1892 bool "Enable support for persistent memory" 1893 select ARCH_HAS_PMEM_API 1894 select ARCH_HAS_UACCESS_FLUSHCACHE 1895 help 1896 Say Y to enable support for the persistent memory API based on the 1897 ARMv8.2 DCPoP feature. 1898 1899 The feature is detected at runtime, and the kernel will use DC CVAC 1900 operations if DC CVAP is not supported (following the behaviour of 1901 DC CVAP itself if the system does not define a point of persistence). 1902 1903config ARM64_RAS_EXTN 1904 bool "Enable support for RAS CPU Extensions" 1905 default y 1906 help 1907 CPUs that support the Reliability, Availability and Serviceability 1908 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1909 errors, classify them and report them to software. 1910 1911 On CPUs with these extensions system software can use additional 1912 barriers to determine if faults are pending and read the 1913 classification from a new set of registers. 1914 1915 Selecting this feature will allow the kernel to use these barriers 1916 and access the new registers if the system supports the extension. 1917 Platform RAS features may additionally depend on firmware support. 1918 1919config ARM64_CNP 1920 bool "Enable support for Common Not Private (CNP) translations" 1921 default y 1922 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1923 help 1924 Common Not Private (CNP) allows translation table entries to 1925 be shared between different PEs in the same inner shareable 1926 domain, so the hardware can use this fact to optimise the 1927 caching of such entries in the TLB. 1928 1929 Selecting this option allows the CNP feature to be detected 1930 at runtime, and does not affect PEs that do not implement 1931 this feature. 1932 1933endmenu # "ARMv8.2 architectural features" 1934 1935menu "ARMv8.3 architectural features" 1936 1937config ARM64_PTR_AUTH 1938 bool "Enable support for pointer authentication" 1939 default y 1940 help 1941 Pointer authentication (part of the ARMv8.3 Extensions) provides 1942 instructions for signing and authenticating pointers against secret 1943 keys, which can be used to mitigate Return Oriented Programming (ROP) 1944 and other attacks. 1945 1946 This option enables these instructions at EL0 (i.e. for userspace). 1947 Choosing this option will cause the kernel to initialise secret keys 1948 for each process at exec() time, with these keys being 1949 context-switched along with the process. 1950 1951 The feature is detected at runtime. If the feature is not present in 1952 hardware it will not be advertised to userspace/KVM guest nor will it 1953 be enabled. 1954 1955 If the feature is present on the boot CPU but not on a late CPU, then 1956 the late CPU will be parked. Also, if the boot CPU does not have 1957 address auth and the late CPU has then the late CPU will still boot 1958 but with the feature disabled. On such a system, this option should 1959 not be selected. 1960 1961config ARM64_PTR_AUTH_KERNEL 1962 bool "Use pointer authentication for kernel" 1963 default y 1964 depends on ARM64_PTR_AUTH 1965 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1966 # Modern compilers insert a .note.gnu.property section note for PAC 1967 # which is only understood by binutils starting with version 2.33.1. 1968 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1969 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1970 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1971 help 1972 If the compiler supports the -mbranch-protection or 1973 -msign-return-address flag (e.g. GCC 7 or later), then this option 1974 will cause the kernel itself to be compiled with return address 1975 protection. In this case, and if the target hardware is known to 1976 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1977 disabled with minimal loss of protection. 1978 1979 This feature works with FUNCTION_GRAPH_TRACER option only if 1980 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1981 1982config CC_HAS_BRANCH_PROT_PAC_RET 1983 # GCC 9 or later, clang 8 or later 1984 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1985 1986config CC_HAS_SIGN_RETURN_ADDRESS 1987 # GCC 7, 8 1988 def_bool $(cc-option,-msign-return-address=all) 1989 1990config AS_HAS_ARMV8_3 1991 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1992 1993config AS_HAS_CFI_NEGATE_RA_STATE 1994 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1995 1996config AS_HAS_LDAPR 1997 def_bool $(as-instr,.arch_extension rcpc) 1998 1999endmenu # "ARMv8.3 architectural features" 2000 2001menu "ARMv8.4 architectural features" 2002 2003config ARM64_AMU_EXTN 2004 bool "Enable support for the Activity Monitors Unit CPU extension" 2005 default y 2006 help 2007 The activity monitors extension is an optional extension introduced 2008 by the ARMv8.4 CPU architecture. This enables support for version 1 2009 of the activity monitors architecture, AMUv1. 2010 2011 To enable the use of this extension on CPUs that implement it, say Y. 2012 2013 Note that for architectural reasons, firmware _must_ implement AMU 2014 support when running on CPUs that present the activity monitors 2015 extension. The required support is present in: 2016 * Version 1.5 and later of the ARM Trusted Firmware 2017 2018 For kernels that have this configuration enabled but boot with broken 2019 firmware, you may need to say N here until the firmware is fixed. 2020 Otherwise you may experience firmware panics or lockups when 2021 accessing the counter registers. Even if you are not observing these 2022 symptoms, the values returned by the register reads might not 2023 correctly reflect reality. Most commonly, the value read will be 0, 2024 indicating that the counter is not enabled. 2025 2026config AS_HAS_ARMV8_4 2027 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2028 2029config ARM64_TLB_RANGE 2030 bool "Enable support for tlbi range feature" 2031 default y 2032 depends on AS_HAS_ARMV8_4 2033 help 2034 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2035 range of input addresses. 2036 2037 The feature introduces new assembly instructions, and they were 2038 support when binutils >= 2.30. 2039 2040endmenu # "ARMv8.4 architectural features" 2041 2042menu "ARMv8.5 architectural features" 2043 2044config AS_HAS_ARMV8_5 2045 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2046 2047config ARM64_BTI 2048 bool "Branch Target Identification support" 2049 default y 2050 help 2051 Branch Target Identification (part of the ARMv8.5 Extensions) 2052 provides a mechanism to limit the set of locations to which computed 2053 branch instructions such as BR or BLR can jump. 2054 2055 To make use of BTI on CPUs that support it, say Y. 2056 2057 BTI is intended to provide complementary protection to other control 2058 flow integrity protection mechanisms, such as the Pointer 2059 authentication mechanism provided as part of the ARMv8.3 Extensions. 2060 For this reason, it does not make sense to enable this option without 2061 also enabling support for pointer authentication. Thus, when 2062 enabling this option you should also select ARM64_PTR_AUTH=y. 2063 2064 Userspace binaries must also be specifically compiled to make use of 2065 this mechanism. If you say N here or the hardware does not support 2066 BTI, such binaries can still run, but you get no additional 2067 enforcement of branch destinations. 2068 2069config ARM64_BTI_KERNEL 2070 bool "Use Branch Target Identification for kernel" 2071 default y 2072 depends on ARM64_BTI 2073 depends on ARM64_PTR_AUTH_KERNEL 2074 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2075 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2076 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2077 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2078 depends on !CC_IS_GCC 2079 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2080 help 2081 Build the kernel with Branch Target Identification annotations 2082 and enable enforcement of this for kernel code. When this option 2083 is enabled and the system supports BTI all kernel code including 2084 modular code must have BTI enabled. 2085 2086config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2087 # GCC 9 or later, clang 8 or later 2088 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2089 2090config ARM64_E0PD 2091 bool "Enable support for E0PD" 2092 default y 2093 help 2094 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2095 that EL0 accesses made via TTBR1 always fault in constant time, 2096 providing similar benefits to KASLR as those provided by KPTI, but 2097 with lower overhead and without disrupting legitimate access to 2098 kernel memory such as SPE. 2099 2100 This option enables E0PD for TTBR1 where available. 2101 2102config ARM64_AS_HAS_MTE 2103 # Initial support for MTE went in binutils 2.32.0, checked with 2104 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2105 # as a late addition to the final architecture spec (LDGM/STGM) 2106 # is only supported in the newer 2.32.x and 2.33 binutils 2107 # versions, hence the extra "stgm" instruction check below. 2108 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2109 2110config ARM64_MTE 2111 bool "Memory Tagging Extension support" 2112 default y 2113 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2114 depends on AS_HAS_ARMV8_5 2115 depends on AS_HAS_LSE_ATOMICS 2116 # Required for tag checking in the uaccess routines 2117 depends on ARM64_PAN 2118 select ARCH_HAS_SUBPAGE_FAULTS 2119 select ARCH_USES_HIGH_VMA_FLAGS 2120 select ARCH_USES_PG_ARCH_2 2121 select ARCH_USES_PG_ARCH_3 2122 help 2123 Memory Tagging (part of the ARMv8.5 Extensions) provides 2124 architectural support for run-time, always-on detection of 2125 various classes of memory error to aid with software debugging 2126 to eliminate vulnerabilities arising from memory-unsafe 2127 languages. 2128 2129 This option enables the support for the Memory Tagging 2130 Extension at EL0 (i.e. for userspace). 2131 2132 Selecting this option allows the feature to be detected at 2133 runtime. Any secondary CPU not implementing this feature will 2134 not be allowed a late bring-up. 2135 2136 Userspace binaries that want to use this feature must 2137 explicitly opt in. The mechanism for the userspace is 2138 described in: 2139 2140 Documentation/arch/arm64/memory-tagging-extension.rst. 2141 2142endmenu # "ARMv8.5 architectural features" 2143 2144menu "ARMv8.7 architectural features" 2145 2146config ARM64_EPAN 2147 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2148 default y 2149 depends on ARM64_PAN 2150 help 2151 Enhanced Privileged Access Never (EPAN) allows Privileged 2152 Access Never to be used with Execute-only mappings. 2153 2154 The feature is detected at runtime, and will remain disabled 2155 if the cpu does not implement the feature. 2156endmenu # "ARMv8.7 architectural features" 2157 2158menu "ARMv8.9 architectural features" 2159 2160config ARM64_POE 2161 prompt "Permission Overlay Extension" 2162 def_bool y 2163 select ARCH_USES_HIGH_VMA_FLAGS 2164 select ARCH_HAS_PKEYS 2165 help 2166 The Permission Overlay Extension is used to implement Memory 2167 Protection Keys. Memory Protection Keys provides a mechanism for 2168 enforcing page-based protections, but without requiring modification 2169 of the page tables when an application changes protection domains. 2170 2171 For details, see Documentation/core-api/protection-keys.rst 2172 2173 If unsure, say y. 2174 2175config ARCH_PKEY_BITS 2176 int 2177 default 3 2178 2179endmenu # "ARMv8.9 architectural features" 2180 2181config ARM64_SVE 2182 bool "ARM Scalable Vector Extension support" 2183 default y 2184 help 2185 The Scalable Vector Extension (SVE) is an extension to the AArch64 2186 execution state which complements and extends the SIMD functionality 2187 of the base architecture to support much larger vectors and to enable 2188 additional vectorisation opportunities. 2189 2190 To enable use of this extension on CPUs that implement it, say Y. 2191 2192 On CPUs that support the SVE2 extensions, this option will enable 2193 those too. 2194 2195 Note that for architectural reasons, firmware _must_ implement SVE 2196 support when running on SVE capable hardware. The required support 2197 is present in: 2198 2199 * version 1.5 and later of the ARM Trusted Firmware 2200 * the AArch64 boot wrapper since commit 5e1261e08abf 2201 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2202 2203 For other firmware implementations, consult the firmware documentation 2204 or vendor. 2205 2206 If you need the kernel to boot on SVE-capable hardware with broken 2207 firmware, you may need to say N here until you get your firmware 2208 fixed. Otherwise, you may experience firmware panics or lockups when 2209 booting the kernel. If unsure and you are not observing these 2210 symptoms, you should assume that it is safe to say Y. 2211 2212config ARM64_SME 2213 bool "ARM Scalable Matrix Extension support" 2214 default y 2215 depends on ARM64_SVE 2216 help 2217 The Scalable Matrix Extension (SME) is an extension to the AArch64 2218 execution state which utilises a substantial subset of the SVE 2219 instruction set, together with the addition of new architectural 2220 register state capable of holding two dimensional matrix tiles to 2221 enable various matrix operations. 2222 2223config ARM64_PSEUDO_NMI 2224 bool "Support for NMI-like interrupts" 2225 select ARM_GIC_V3 2226 help 2227 Adds support for mimicking Non-Maskable Interrupts through the use of 2228 GIC interrupt priority. This support requires version 3 or later of 2229 ARM GIC. 2230 2231 This high priority configuration for interrupts needs to be 2232 explicitly enabled by setting the kernel parameter 2233 "irqchip.gicv3_pseudo_nmi" to 1. 2234 2235 If unsure, say N 2236 2237if ARM64_PSEUDO_NMI 2238config ARM64_DEBUG_PRIORITY_MASKING 2239 bool "Debug interrupt priority masking" 2240 help 2241 This adds runtime checks to functions enabling/disabling 2242 interrupts when using priority masking. The additional checks verify 2243 the validity of ICC_PMR_EL1 when calling concerned functions. 2244 2245 If unsure, say N 2246endif # ARM64_PSEUDO_NMI 2247 2248config RELOCATABLE 2249 bool "Build a relocatable kernel image" if EXPERT 2250 select ARCH_HAS_RELR 2251 default y 2252 help 2253 This builds the kernel as a Position Independent Executable (PIE), 2254 which retains all relocation metadata required to relocate the 2255 kernel binary at runtime to a different virtual address than the 2256 address it was linked at. 2257 Since AArch64 uses the RELA relocation format, this requires a 2258 relocation pass at runtime even if the kernel is loaded at the 2259 same address it was linked at. 2260 2261config RANDOMIZE_BASE 2262 bool "Randomize the address of the kernel image" 2263 select RELOCATABLE 2264 help 2265 Randomizes the virtual address at which the kernel image is 2266 loaded, as a security feature that deters exploit attempts 2267 relying on knowledge of the location of kernel internals. 2268 2269 It is the bootloader's job to provide entropy, by passing a 2270 random u64 value in /chosen/kaslr-seed at kernel entry. 2271 2272 When booting via the UEFI stub, it will invoke the firmware's 2273 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2274 to the kernel proper. In addition, it will randomise the physical 2275 location of the kernel Image as well. 2276 2277 If unsure, say N. 2278 2279config RANDOMIZE_MODULE_REGION_FULL 2280 bool "Randomize the module region over a 2 GB range" 2281 depends on RANDOMIZE_BASE 2282 default y 2283 help 2284 Randomizes the location of the module region inside a 2 GB window 2285 covering the core kernel. This way, it is less likely for modules 2286 to leak information about the location of core kernel data structures 2287 but it does imply that function calls between modules and the core 2288 kernel will need to be resolved via veneers in the module PLT. 2289 2290 When this option is not set, the module region will be randomized over 2291 a limited range that contains the [_stext, _etext] interval of the 2292 core kernel, so branch relocations are almost always in range unless 2293 the region is exhausted. In this particular case of region 2294 exhaustion, modules might be able to fall back to a larger 2GB area. 2295 2296config CC_HAVE_STACKPROTECTOR_SYSREG 2297 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2298 2299config STACKPROTECTOR_PER_TASK 2300 def_bool y 2301 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2302 2303config UNWIND_PATCH_PAC_INTO_SCS 2304 bool "Enable shadow call stack dynamically using code patching" 2305 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2306 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2307 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2308 depends on SHADOW_CALL_STACK 2309 select UNWIND_TABLES 2310 select DYNAMIC_SCS 2311 2312config ARM64_CONTPTE 2313 bool "Contiguous PTE mappings for user memory" if EXPERT 2314 depends on TRANSPARENT_HUGEPAGE 2315 default y 2316 help 2317 When enabled, user mappings are configured using the PTE contiguous 2318 bit, for any mappings that meet the size and alignment requirements. 2319 This reduces TLB pressure and improves performance. 2320 2321endmenu # "Kernel Features" 2322 2323menu "Boot options" 2324 2325config ARM64_ACPI_PARKING_PROTOCOL 2326 bool "Enable support for the ARM64 ACPI parking protocol" 2327 depends on ACPI 2328 help 2329 Enable support for the ARM64 ACPI parking protocol. If disabled 2330 the kernel will not allow booting through the ARM64 ACPI parking 2331 protocol even if the corresponding data is present in the ACPI 2332 MADT table. 2333 2334config CMDLINE 2335 string "Default kernel command string" 2336 default "" 2337 help 2338 Provide a set of default command-line options at build time by 2339 entering them here. As a minimum, you should specify the the 2340 root device (e.g. root=/dev/nfs). 2341 2342choice 2343 prompt "Kernel command line type" 2344 depends on CMDLINE != "" 2345 default CMDLINE_FROM_BOOTLOADER 2346 help 2347 Choose how the kernel will handle the provided default kernel 2348 command line string. 2349 2350config CMDLINE_FROM_BOOTLOADER 2351 bool "Use bootloader kernel arguments if available" 2352 help 2353 Uses the command-line options passed by the boot loader. If 2354 the boot loader doesn't provide any, the default kernel command 2355 string provided in CMDLINE will be used. 2356 2357config CMDLINE_FORCE 2358 bool "Always use the default kernel command string" 2359 help 2360 Always use the default kernel command string, even if the boot 2361 loader passes other arguments to the kernel. 2362 This is useful if you cannot or don't want to change the 2363 command-line options your boot loader passes to the kernel. 2364 2365endchoice 2366 2367config EFI_STUB 2368 bool 2369 2370config EFI 2371 bool "UEFI runtime support" 2372 depends on OF && !CPU_BIG_ENDIAN 2373 depends on KERNEL_MODE_NEON 2374 select ARCH_SUPPORTS_ACPI 2375 select LIBFDT 2376 select UCS2_STRING 2377 select EFI_PARAMS_FROM_FDT 2378 select EFI_RUNTIME_WRAPPERS 2379 select EFI_STUB 2380 select EFI_GENERIC_STUB 2381 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2382 default y 2383 help 2384 This option provides support for runtime services provided 2385 by UEFI firmware (such as non-volatile variables, realtime 2386 clock, and platform reset). A UEFI stub is also provided to 2387 allow the kernel to be booted as an EFI application. This 2388 is only useful on systems that have UEFI firmware. 2389 2390config COMPRESSED_INSTALL 2391 bool "Install compressed image by default" 2392 help 2393 This makes the regular "make install" install the compressed 2394 image we built, not the legacy uncompressed one. 2395 2396 You can check that a compressed image works for you by doing 2397 "make zinstall" first, and verifying that everything is fine 2398 in your environment before making "make install" do this for 2399 you. 2400 2401config DMI 2402 bool "Enable support for SMBIOS (DMI) tables" 2403 depends on EFI 2404 default y 2405 help 2406 This enables SMBIOS/DMI feature for systems. 2407 2408 This option is only useful on systems that have UEFI firmware. 2409 However, even with this option, the resultant kernel should 2410 continue to boot on existing non-UEFI platforms. 2411 2412endmenu # "Boot options" 2413 2414menu "Power management options" 2415 2416source "kernel/power/Kconfig" 2417 2418config ARCH_HIBERNATION_POSSIBLE 2419 def_bool y 2420 depends on CPU_PM 2421 2422config ARCH_HIBERNATION_HEADER 2423 def_bool y 2424 depends on HIBERNATION 2425 2426config ARCH_SUSPEND_POSSIBLE 2427 def_bool y 2428 2429endmenu # "Power management options" 2430 2431menu "CPU Power Management" 2432 2433source "drivers/cpuidle/Kconfig" 2434 2435source "drivers/cpufreq/Kconfig" 2436 2437endmenu # "CPU Power Management" 2438 2439source "drivers/acpi/Kconfig" 2440 2441source "arch/arm64/kvm/Kconfig" 2442 2443