1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_GTDT if ACPI 6 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 7 select ACPI_MCFG if ACPI 8 select ACPI_SPCR_TABLE if ACPI 9 select ARCH_CLOCKSOURCE_DATA 10 select ARCH_HAS_DEBUG_VIRTUAL 11 select ARCH_HAS_DEVMEM_IS_ALLOWED 12 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 13 select ARCH_HAS_ELF_RANDOMIZE 14 select ARCH_HAS_GCOV_PROFILE_ALL 15 select ARCH_HAS_GIGANTIC_PAGE 16 select ARCH_HAS_KCOV 17 select ARCH_HAS_SET_MEMORY 18 select ARCH_HAS_SG_CHAIN 19 select ARCH_HAS_STRICT_KERNEL_RWX 20 select ARCH_HAS_STRICT_MODULE_RWX 21 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 22 select ARCH_USE_CMPXCHG_LOCKREF 23 select ARCH_SUPPORTS_MEMORY_FAILURE 24 select ARCH_SUPPORTS_ATOMIC_RMW 25 select ARCH_SUPPORTS_NUMA_BALANCING 26 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 27 select ARCH_WANT_FRAME_POINTERS 28 select ARCH_HAS_UBSAN_SANITIZE_ALL 29 select ARM_AMBA 30 select ARM_ARCH_TIMER 31 select ARM_GIC 32 select AUDIT_ARCH_COMPAT_GENERIC 33 select ARM_GIC_V2M if PCI 34 select ARM_GIC_V3 35 select ARM_GIC_V3_ITS if PCI 36 select ARM_PSCI_FW 37 select BUILDTIME_EXTABLE_SORT 38 select CLONE_BACKWARDS 39 select COMMON_CLK 40 select CPU_PM if (SUSPEND || CPU_IDLE) 41 select DCACHE_WORD_ACCESS 42 select EDAC_SUPPORT 43 select FRAME_POINTER 44 select GENERIC_ALLOCATOR 45 select GENERIC_CLOCKEVENTS 46 select GENERIC_CLOCKEVENTS_BROADCAST 47 select GENERIC_CPU_AUTOPROBE 48 select GENERIC_EARLY_IOREMAP 49 select GENERIC_IDLE_POLL_SETUP 50 select GENERIC_IRQ_PROBE 51 select GENERIC_IRQ_SHOW 52 select GENERIC_IRQ_SHOW_LEVEL 53 select GENERIC_PCI_IOMAP 54 select GENERIC_SCHED_CLOCK 55 select GENERIC_SMP_IDLE_THREAD 56 select GENERIC_STRNCPY_FROM_USER 57 select GENERIC_STRNLEN_USER 58 select GENERIC_TIME_VSYSCALL 59 select HANDLE_DOMAIN_IRQ 60 select HARDIRQS_SW_RESEND 61 select HAVE_ACPI_APEI if (ACPI && EFI) 62 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 63 select HAVE_ARCH_AUDITSYSCALL 64 select HAVE_ARCH_BITREVERSE 65 select HAVE_ARCH_HUGE_VMAP 66 select HAVE_ARCH_JUMP_LABEL 67 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 68 select HAVE_ARCH_KGDB 69 select HAVE_ARCH_MMAP_RND_BITS 70 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 71 select HAVE_ARCH_SECCOMP_FILTER 72 select HAVE_ARCH_TRACEHOOK 73 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 74 select HAVE_ARM_SMCCC 75 select HAVE_EBPF_JIT 76 select HAVE_C_RECORDMCOUNT 77 select HAVE_CC_STACKPROTECTOR 78 select HAVE_CMPXCHG_DOUBLE 79 select HAVE_CMPXCHG_LOCAL 80 select HAVE_CONTEXT_TRACKING 81 select HAVE_DEBUG_BUGVERBOSE 82 select HAVE_DEBUG_KMEMLEAK 83 select HAVE_DMA_API_DEBUG 84 select HAVE_DMA_CONTIGUOUS 85 select HAVE_DYNAMIC_FTRACE 86 select HAVE_EFFICIENT_UNALIGNED_ACCESS 87 select HAVE_FTRACE_MCOUNT_RECORD 88 select HAVE_FUNCTION_TRACER 89 select HAVE_FUNCTION_GRAPH_TRACER 90 select HAVE_GCC_PLUGINS 91 select HAVE_GENERIC_DMA_COHERENT 92 select HAVE_HW_BREAKPOINT if PERF_EVENTS 93 select HAVE_IRQ_TIME_ACCOUNTING 94 select HAVE_MEMBLOCK 95 select HAVE_MEMBLOCK_NODE_MAP if NUMA 96 select HAVE_PATA_PLATFORM 97 select HAVE_PERF_EVENTS 98 select HAVE_PERF_REGS 99 select HAVE_PERF_USER_STACK_DUMP 100 select HAVE_REGS_AND_STACK_ACCESS_API 101 select HAVE_RCU_TABLE_FREE 102 select HAVE_SYSCALL_TRACEPOINTS 103 select HAVE_KPROBES 104 select HAVE_KRETPROBES 105 select IOMMU_DMA if IOMMU_SUPPORT 106 select IRQ_DOMAIN 107 select IRQ_FORCED_THREADING 108 select MODULES_USE_ELF_RELA 109 select NO_BOOTMEM 110 select OF 111 select OF_EARLY_FLATTREE 112 select OF_RESERVED_MEM 113 select PCI_ECAM if ACPI 114 select POWER_RESET 115 select POWER_SUPPLY 116 select SPARSE_IRQ 117 select SYSCTL_EXCEPTION_TRACE 118 select THREAD_INFO_IN_TASK 119 help 120 ARM 64-bit (AArch64) Linux support. 121 122config 64BIT 123 def_bool y 124 125config ARCH_PHYS_ADDR_T_64BIT 126 def_bool y 127 128config MMU 129 def_bool y 130 131config ARM64_PAGE_SHIFT 132 int 133 default 16 if ARM64_64K_PAGES 134 default 14 if ARM64_16K_PAGES 135 default 12 136 137config ARM64_CONT_SHIFT 138 int 139 default 5 if ARM64_64K_PAGES 140 default 7 if ARM64_16K_PAGES 141 default 4 142 143config ARCH_MMAP_RND_BITS_MIN 144 default 14 if ARM64_64K_PAGES 145 default 16 if ARM64_16K_PAGES 146 default 18 147 148# max bits determined by the following formula: 149# VA_BITS - PAGE_SHIFT - 3 150config ARCH_MMAP_RND_BITS_MAX 151 default 19 if ARM64_VA_BITS=36 152 default 24 if ARM64_VA_BITS=39 153 default 27 if ARM64_VA_BITS=42 154 default 30 if ARM64_VA_BITS=47 155 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 156 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 157 default 33 if ARM64_VA_BITS=48 158 default 14 if ARM64_64K_PAGES 159 default 16 if ARM64_16K_PAGES 160 default 18 161 162config ARCH_MMAP_RND_COMPAT_BITS_MIN 163 default 7 if ARM64_64K_PAGES 164 default 9 if ARM64_16K_PAGES 165 default 11 166 167config ARCH_MMAP_RND_COMPAT_BITS_MAX 168 default 16 169 170config NO_IOPORT_MAP 171 def_bool y if !PCI 172 173config STACKTRACE_SUPPORT 174 def_bool y 175 176config ILLEGAL_POINTER_VALUE 177 hex 178 default 0xdead000000000000 179 180config LOCKDEP_SUPPORT 181 def_bool y 182 183config TRACE_IRQFLAGS_SUPPORT 184 def_bool y 185 186config RWSEM_XCHGADD_ALGORITHM 187 def_bool y 188 189config GENERIC_BUG 190 def_bool y 191 depends on BUG 192 193config GENERIC_BUG_RELATIVE_POINTERS 194 def_bool y 195 depends on GENERIC_BUG 196 197config GENERIC_HWEIGHT 198 def_bool y 199 200config GENERIC_CSUM 201 def_bool y 202 203config GENERIC_CALIBRATE_DELAY 204 def_bool y 205 206config ZONE_DMA 207 def_bool y 208 209config HAVE_GENERIC_RCU_GUP 210 def_bool y 211 212config ARCH_DMA_ADDR_T_64BIT 213 def_bool y 214 215config NEED_DMA_MAP_STATE 216 def_bool y 217 218config NEED_SG_DMA_LENGTH 219 def_bool y 220 221config SMP 222 def_bool y 223 224config SWIOTLB 225 def_bool y 226 227config IOMMU_HELPER 228 def_bool SWIOTLB 229 230config KERNEL_MODE_NEON 231 def_bool y 232 233config FIX_EARLYCON_MEM 234 def_bool y 235 236config PGTABLE_LEVELS 237 int 238 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 239 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 240 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 241 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 242 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 243 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 244 245config ARCH_SUPPORTS_UPROBES 246 def_bool y 247 248source "init/Kconfig" 249 250source "kernel/Kconfig.freezer" 251 252source "arch/arm64/Kconfig.platforms" 253 254menu "Bus support" 255 256config PCI 257 bool "PCI support" 258 help 259 This feature enables support for PCI bus system. If you say Y 260 here, the kernel will include drivers and infrastructure code 261 to support PCI bus devices. 262 263config PCI_DOMAINS 264 def_bool PCI 265 266config PCI_DOMAINS_GENERIC 267 def_bool PCI 268 269config PCI_SYSCALL 270 def_bool PCI 271 272source "drivers/pci/Kconfig" 273 274endmenu 275 276menu "Kernel Features" 277 278menu "ARM errata workarounds via the alternatives framework" 279 280config ARM64_ERRATUM_826319 281 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 282 default y 283 help 284 This option adds an alternative code sequence to work around ARM 285 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 286 AXI master interface and an L2 cache. 287 288 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 289 and is unable to accept a certain write via this interface, it will 290 not progress on read data presented on the read data channel and the 291 system can deadlock. 292 293 The workaround promotes data cache clean instructions to 294 data cache clean-and-invalidate. 295 Please note that this does not necessarily enable the workaround, 296 as it depends on the alternative framework, which will only patch 297 the kernel if an affected CPU is detected. 298 299 If unsure, say Y. 300 301config ARM64_ERRATUM_827319 302 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 303 default y 304 help 305 This option adds an alternative code sequence to work around ARM 306 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 307 master interface and an L2 cache. 308 309 Under certain conditions this erratum can cause a clean line eviction 310 to occur at the same time as another transaction to the same address 311 on the AMBA 5 CHI interface, which can cause data corruption if the 312 interconnect reorders the two transactions. 313 314 The workaround promotes data cache clean instructions to 315 data cache clean-and-invalidate. 316 Please note that this does not necessarily enable the workaround, 317 as it depends on the alternative framework, which will only patch 318 the kernel if an affected CPU is detected. 319 320 If unsure, say Y. 321 322config ARM64_ERRATUM_824069 323 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 324 default y 325 help 326 This option adds an alternative code sequence to work around ARM 327 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 328 to a coherent interconnect. 329 330 If a Cortex-A53 processor is executing a store or prefetch for 331 write instruction at the same time as a processor in another 332 cluster is executing a cache maintenance operation to the same 333 address, then this erratum might cause a clean cache line to be 334 incorrectly marked as dirty. 335 336 The workaround promotes data cache clean instructions to 337 data cache clean-and-invalidate. 338 Please note that this option does not necessarily enable the 339 workaround, as it depends on the alternative framework, which will 340 only patch the kernel if an affected CPU is detected. 341 342 If unsure, say Y. 343 344config ARM64_ERRATUM_819472 345 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 346 default y 347 help 348 This option adds an alternative code sequence to work around ARM 349 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 350 present when it is connected to a coherent interconnect. 351 352 If the processor is executing a load and store exclusive sequence at 353 the same time as a processor in another cluster is executing a cache 354 maintenance operation to the same address, then this erratum might 355 cause data corruption. 356 357 The workaround promotes data cache clean instructions to 358 data cache clean-and-invalidate. 359 Please note that this does not necessarily enable the workaround, 360 as it depends on the alternative framework, which will only patch 361 the kernel if an affected CPU is detected. 362 363 If unsure, say Y. 364 365config ARM64_ERRATUM_832075 366 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 367 default y 368 help 369 This option adds an alternative code sequence to work around ARM 370 erratum 832075 on Cortex-A57 parts up to r1p2. 371 372 Affected Cortex-A57 parts might deadlock when exclusive load/store 373 instructions to Write-Back memory are mixed with Device loads. 374 375 The workaround is to promote device loads to use Load-Acquire 376 semantics. 377 Please note that this does not necessarily enable the workaround, 378 as it depends on the alternative framework, which will only patch 379 the kernel if an affected CPU is detected. 380 381 If unsure, say Y. 382 383config ARM64_ERRATUM_834220 384 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 385 depends on KVM 386 default y 387 help 388 This option adds an alternative code sequence to work around ARM 389 erratum 834220 on Cortex-A57 parts up to r1p2. 390 391 Affected Cortex-A57 parts might report a Stage 2 translation 392 fault as the result of a Stage 1 fault for load crossing a 393 page boundary when there is a permission or device memory 394 alignment fault at Stage 1 and a translation fault at Stage 2. 395 396 The workaround is to verify that the Stage 1 translation 397 doesn't generate a fault before handling the Stage 2 fault. 398 Please note that this does not necessarily enable the workaround, 399 as it depends on the alternative framework, which will only patch 400 the kernel if an affected CPU is detected. 401 402 If unsure, say Y. 403 404config ARM64_ERRATUM_845719 405 bool "Cortex-A53: 845719: a load might read incorrect data" 406 depends on COMPAT 407 default y 408 help 409 This option adds an alternative code sequence to work around ARM 410 erratum 845719 on Cortex-A53 parts up to r0p4. 411 412 When running a compat (AArch32) userspace on an affected Cortex-A53 413 part, a load at EL0 from a virtual address that matches the bottom 32 414 bits of the virtual address used by a recent load at (AArch64) EL1 415 might return incorrect data. 416 417 The workaround is to write the contextidr_el1 register on exception 418 return to a 32-bit task. 419 Please note that this does not necessarily enable the workaround, 420 as it depends on the alternative framework, which will only patch 421 the kernel if an affected CPU is detected. 422 423 If unsure, say Y. 424 425config ARM64_ERRATUM_843419 426 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 427 default y 428 select ARM64_MODULE_CMODEL_LARGE if MODULES 429 help 430 This option links the kernel with '--fix-cortex-a53-843419' and 431 builds modules using the large memory model in order to avoid the use 432 of the ADRP instruction, which can cause a subsequent memory access 433 to use an incorrect address on Cortex-A53 parts up to r0p4. 434 435 If unsure, say Y. 436 437config CAVIUM_ERRATUM_22375 438 bool "Cavium erratum 22375, 24313" 439 default y 440 help 441 Enable workaround for erratum 22375, 24313. 442 443 This implements two gicv3-its errata workarounds for ThunderX. Both 444 with small impact affecting only ITS table allocation. 445 446 erratum 22375: only alloc 8MB table size 447 erratum 24313: ignore memory access type 448 449 The fixes are in ITS initialization and basically ignore memory access 450 type and table size provided by the TYPER and BASER registers. 451 452 If unsure, say Y. 453 454config CAVIUM_ERRATUM_23144 455 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 456 depends on NUMA 457 default y 458 help 459 ITS SYNC command hang for cross node io and collections/cpu mapping. 460 461 If unsure, say Y. 462 463config CAVIUM_ERRATUM_23154 464 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 465 default y 466 help 467 The gicv3 of ThunderX requires a modified version for 468 reading the IAR status to ensure data synchronization 469 (access to icc_iar1_el1 is not sync'ed before and after). 470 471 If unsure, say Y. 472 473config CAVIUM_ERRATUM_27456 474 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 475 default y 476 help 477 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 478 instructions may cause the icache to become corrupted if it 479 contains data for a non-current ASID. The fix is to 480 invalidate the icache when changing the mm context. 481 482 If unsure, say Y. 483 484config QCOM_FALKOR_ERRATUM_1003 485 bool "Falkor E1003: Incorrect translation due to ASID change" 486 default y 487 select ARM64_PAN if ARM64_SW_TTBR0_PAN 488 help 489 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 490 and BADDR are changed together in TTBRx_EL1. The workaround for this 491 issue is to use a reserved ASID in cpu_do_switch_mm() before 492 switching to the new ASID. Saying Y here selects ARM64_PAN if 493 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and 494 maintaining the E1003 workaround in the software PAN emulation code 495 would be an unnecessary complication. The affected Falkor v1 CPU 496 implements ARMv8.1 hardware PAN support and using hardware PAN 497 support versus software PAN emulation is mutually exclusive at 498 runtime. 499 500 If unsure, say Y. 501 502config QCOM_FALKOR_ERRATUM_1009 503 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 504 default y 505 help 506 On Falkor v1, the CPU may prematurely complete a DSB following a 507 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 508 one more time to fix the issue. 509 510 If unsure, say Y. 511 512config QCOM_QDF2400_ERRATUM_0065 513 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 514 default y 515 help 516 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 517 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 518 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 519 520 If unsure, say Y. 521 522endmenu 523 524 525choice 526 prompt "Page size" 527 default ARM64_4K_PAGES 528 help 529 Page size (translation granule) configuration. 530 531config ARM64_4K_PAGES 532 bool "4KB" 533 help 534 This feature enables 4KB pages support. 535 536config ARM64_16K_PAGES 537 bool "16KB" 538 help 539 The system will use 16KB pages support. AArch32 emulation 540 requires applications compiled with 16K (or a multiple of 16K) 541 aligned segments. 542 543config ARM64_64K_PAGES 544 bool "64KB" 545 help 546 This feature enables 64KB pages support (4KB by default) 547 allowing only two levels of page tables and faster TLB 548 look-up. AArch32 emulation requires applications compiled 549 with 64K aligned segments. 550 551endchoice 552 553choice 554 prompt "Virtual address space size" 555 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 556 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 557 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 558 help 559 Allows choosing one of multiple possible virtual address 560 space sizes. The level of translation table is determined by 561 a combination of page size and virtual address space size. 562 563config ARM64_VA_BITS_36 564 bool "36-bit" if EXPERT 565 depends on ARM64_16K_PAGES 566 567config ARM64_VA_BITS_39 568 bool "39-bit" 569 depends on ARM64_4K_PAGES 570 571config ARM64_VA_BITS_42 572 bool "42-bit" 573 depends on ARM64_64K_PAGES 574 575config ARM64_VA_BITS_47 576 bool "47-bit" 577 depends on ARM64_16K_PAGES 578 579config ARM64_VA_BITS_48 580 bool "48-bit" 581 582endchoice 583 584config ARM64_VA_BITS 585 int 586 default 36 if ARM64_VA_BITS_36 587 default 39 if ARM64_VA_BITS_39 588 default 42 if ARM64_VA_BITS_42 589 default 47 if ARM64_VA_BITS_47 590 default 48 if ARM64_VA_BITS_48 591 592config CPU_BIG_ENDIAN 593 bool "Build big-endian kernel" 594 help 595 Say Y if you plan on running a kernel in big-endian mode. 596 597config SCHED_MC 598 bool "Multi-core scheduler support" 599 help 600 Multi-core scheduler support improves the CPU scheduler's decision 601 making when dealing with multi-core CPU chips at a cost of slightly 602 increased overhead in some places. If unsure say N here. 603 604config SCHED_SMT 605 bool "SMT scheduler support" 606 help 607 Improves the CPU scheduler's decision making when dealing with 608 MultiThreading at a cost of slightly increased overhead in some 609 places. If unsure say N here. 610 611config NR_CPUS 612 int "Maximum number of CPUs (2-4096)" 613 range 2 4096 614 # These have to remain sorted largest to smallest 615 default "64" 616 617config HOTPLUG_CPU 618 bool "Support for hot-pluggable CPUs" 619 select GENERIC_IRQ_MIGRATION 620 help 621 Say Y here to experiment with turning CPUs off and on. CPUs 622 can be controlled through /sys/devices/system/cpu. 623 624# Common NUMA Features 625config NUMA 626 bool "Numa Memory Allocation and Scheduler Support" 627 select ACPI_NUMA if ACPI 628 select OF_NUMA 629 help 630 Enable NUMA (Non Uniform Memory Access) support. 631 632 The kernel will try to allocate memory used by a CPU on the 633 local memory of the CPU and add some more 634 NUMA awareness to the kernel. 635 636config NODES_SHIFT 637 int "Maximum NUMA Nodes (as a power of 2)" 638 range 1 10 639 default "2" 640 depends on NEED_MULTIPLE_NODES 641 help 642 Specify the maximum number of NUMA Nodes available on the target 643 system. Increases memory reserved to accommodate various tables. 644 645config USE_PERCPU_NUMA_NODE_ID 646 def_bool y 647 depends on NUMA 648 649config HAVE_SETUP_PER_CPU_AREA 650 def_bool y 651 depends on NUMA 652 653config NEED_PER_CPU_EMBED_FIRST_CHUNK 654 def_bool y 655 depends on NUMA 656 657config HOLES_IN_ZONE 658 def_bool y 659 depends on NUMA 660 661source kernel/Kconfig.preempt 662source kernel/Kconfig.hz 663 664config ARCH_SUPPORTS_DEBUG_PAGEALLOC 665 def_bool y 666 667config ARCH_HAS_HOLES_MEMORYMODEL 668 def_bool y if SPARSEMEM 669 670config ARCH_SPARSEMEM_ENABLE 671 def_bool y 672 select SPARSEMEM_VMEMMAP_ENABLE 673 674config ARCH_SPARSEMEM_DEFAULT 675 def_bool ARCH_SPARSEMEM_ENABLE 676 677config ARCH_SELECT_MEMORY_MODEL 678 def_bool ARCH_SPARSEMEM_ENABLE 679 680config HAVE_ARCH_PFN_VALID 681 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 682 683config HW_PERF_EVENTS 684 def_bool y 685 depends on ARM_PMU 686 687config SYS_SUPPORTS_HUGETLBFS 688 def_bool y 689 690config ARCH_WANT_HUGE_PMD_SHARE 691 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 692 693config ARCH_HAS_CACHE_LINE_SIZE 694 def_bool y 695 696source "mm/Kconfig" 697 698config SECCOMP 699 bool "Enable seccomp to safely compute untrusted bytecode" 700 ---help--- 701 This kernel feature is useful for number crunching applications 702 that may need to compute untrusted bytecode during their 703 execution. By using pipes or other transports made available to 704 the process as file descriptors supporting the read/write 705 syscalls, it's possible to isolate those applications in 706 their own address space using seccomp. Once seccomp is 707 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 708 and the task is only allowed to execute a few safe syscalls 709 defined by each seccomp mode. 710 711config PARAVIRT 712 bool "Enable paravirtualization code" 713 help 714 This changes the kernel so it can modify itself when it is run 715 under a hypervisor, potentially improving performance significantly 716 over full virtualization. 717 718config PARAVIRT_TIME_ACCOUNTING 719 bool "Paravirtual steal time accounting" 720 select PARAVIRT 721 default n 722 help 723 Select this option to enable fine granularity task steal time 724 accounting. Time spent executing other tasks in parallel with 725 the current vCPU is discounted from the vCPU power. To account for 726 that, there can be a small performance impact. 727 728 If in doubt, say N here. 729 730config KEXEC 731 depends on PM_SLEEP_SMP 732 select KEXEC_CORE 733 bool "kexec system call" 734 ---help--- 735 kexec is a system call that implements the ability to shutdown your 736 current kernel, and to start another kernel. It is like a reboot 737 but it is independent of the system firmware. And like a reboot 738 you can start any kernel with it, not just Linux. 739 740config CRASH_DUMP 741 bool "Build kdump crash kernel" 742 help 743 Generate crash dump after being started by kexec. This should 744 be normally only set in special crash dump kernels which are 745 loaded in the main kernel with kexec-tools into a specially 746 reserved region and then later executed after a crash by 747 kdump/kexec. 748 749 For more details see Documentation/kdump/kdump.txt 750 751config XEN_DOM0 752 def_bool y 753 depends on XEN 754 755config XEN 756 bool "Xen guest support on ARM64" 757 depends on ARM64 && OF 758 select SWIOTLB_XEN 759 select PARAVIRT 760 help 761 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 762 763config FORCE_MAX_ZONEORDER 764 int 765 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 766 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 767 default "11" 768 help 769 The kernel memory allocator divides physically contiguous memory 770 blocks into "zones", where each zone is a power of two number of 771 pages. This option selects the largest power of two that the kernel 772 keeps in the memory allocator. If you need to allocate very large 773 blocks of physically contiguous memory, then you may need to 774 increase this value. 775 776 This config option is actually maximum order plus one. For example, 777 a value of 11 means that the largest free memory block is 2^10 pages. 778 779 We make sure that we can allocate upto a HugePage size for each configuration. 780 Hence we have : 781 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 782 783 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 784 4M allocations matching the default size used by generic code. 785 786menuconfig ARMV8_DEPRECATED 787 bool "Emulate deprecated/obsolete ARMv8 instructions" 788 depends on COMPAT 789 help 790 Legacy software support may require certain instructions 791 that have been deprecated or obsoleted in the architecture. 792 793 Enable this config to enable selective emulation of these 794 features. 795 796 If unsure, say Y 797 798if ARMV8_DEPRECATED 799 800config SWP_EMULATION 801 bool "Emulate SWP/SWPB instructions" 802 help 803 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 804 they are always undefined. Say Y here to enable software 805 emulation of these instructions for userspace using LDXR/STXR. 806 807 In some older versions of glibc [<=2.8] SWP is used during futex 808 trylock() operations with the assumption that the code will not 809 be preempted. This invalid assumption may be more likely to fail 810 with SWP emulation enabled, leading to deadlock of the user 811 application. 812 813 NOTE: when accessing uncached shared regions, LDXR/STXR rely 814 on an external transaction monitoring block called a global 815 monitor to maintain update atomicity. If your system does not 816 implement a global monitor, this option can cause programs that 817 perform SWP operations to uncached memory to deadlock. 818 819 If unsure, say Y 820 821config CP15_BARRIER_EMULATION 822 bool "Emulate CP15 Barrier instructions" 823 help 824 The CP15 barrier instructions - CP15ISB, CP15DSB, and 825 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 826 strongly recommended to use the ISB, DSB, and DMB 827 instructions instead. 828 829 Say Y here to enable software emulation of these 830 instructions for AArch32 userspace code. When this option is 831 enabled, CP15 barrier usage is traced which can help 832 identify software that needs updating. 833 834 If unsure, say Y 835 836config SETEND_EMULATION 837 bool "Emulate SETEND instruction" 838 help 839 The SETEND instruction alters the data-endianness of the 840 AArch32 EL0, and is deprecated in ARMv8. 841 842 Say Y here to enable software emulation of the instruction 843 for AArch32 userspace code. 844 845 Note: All the cpus on the system must have mixed endian support at EL0 846 for this feature to be enabled. If a new CPU - which doesn't support mixed 847 endian - is hotplugged in after this feature has been enabled, there could 848 be unexpected results in the applications. 849 850 If unsure, say Y 851endif 852 853config ARM64_SW_TTBR0_PAN 854 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 855 help 856 Enabling this option prevents the kernel from accessing 857 user-space memory directly by pointing TTBR0_EL1 to a reserved 858 zeroed area and reserved ASID. The user access routines 859 restore the valid TTBR0_EL1 temporarily. 860 861menu "ARMv8.1 architectural features" 862 863config ARM64_HW_AFDBM 864 bool "Support for hardware updates of the Access and Dirty page flags" 865 default y 866 help 867 The ARMv8.1 architecture extensions introduce support for 868 hardware updates of the access and dirty information in page 869 table entries. When enabled in TCR_EL1 (HA and HD bits) on 870 capable processors, accesses to pages with PTE_AF cleared will 871 set this bit instead of raising an access flag fault. 872 Similarly, writes to read-only pages with the DBM bit set will 873 clear the read-only bit (AP[2]) instead of raising a 874 permission fault. 875 876 Kernels built with this configuration option enabled continue 877 to work on pre-ARMv8.1 hardware and the performance impact is 878 minimal. If unsure, say Y. 879 880config ARM64_PAN 881 bool "Enable support for Privileged Access Never (PAN)" 882 default y 883 help 884 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 885 prevents the kernel or hypervisor from accessing user-space (EL0) 886 memory directly. 887 888 Choosing this option will cause any unprotected (not using 889 copy_to_user et al) memory access to fail with a permission fault. 890 891 The feature is detected at runtime, and will remain as a 'nop' 892 instruction if the cpu does not implement the feature. 893 894config ARM64_LSE_ATOMICS 895 bool "Atomic instructions" 896 help 897 As part of the Large System Extensions, ARMv8.1 introduces new 898 atomic instructions that are designed specifically to scale in 899 very large systems. 900 901 Say Y here to make use of these instructions for the in-kernel 902 atomic routines. This incurs a small overhead on CPUs that do 903 not support these instructions and requires the kernel to be 904 built with binutils >= 2.25. 905 906config ARM64_VHE 907 bool "Enable support for Virtualization Host Extensions (VHE)" 908 default y 909 help 910 Virtualization Host Extensions (VHE) allow the kernel to run 911 directly at EL2 (instead of EL1) on processors that support 912 it. This leads to better performance for KVM, as they reduce 913 the cost of the world switch. 914 915 Selecting this option allows the VHE feature to be detected 916 at runtime, and does not affect processors that do not 917 implement this feature. 918 919endmenu 920 921menu "ARMv8.2 architectural features" 922 923config ARM64_UAO 924 bool "Enable support for User Access Override (UAO)" 925 default y 926 help 927 User Access Override (UAO; part of the ARMv8.2 Extensions) 928 causes the 'unprivileged' variant of the load/store instructions to 929 be overriden to be privileged. 930 931 This option changes get_user() and friends to use the 'unprivileged' 932 variant of the load/store instructions. This ensures that user-space 933 really did have access to the supplied memory. When addr_limit is 934 set to kernel memory the UAO bit will be set, allowing privileged 935 access to kernel memory. 936 937 Choosing this option will cause copy_to_user() et al to use user-space 938 memory permissions. 939 940 The feature is detected at runtime, the kernel will use the 941 regular load/store instructions if the cpu does not implement the 942 feature. 943 944endmenu 945 946config ARM64_MODULE_CMODEL_LARGE 947 bool 948 949config ARM64_MODULE_PLTS 950 bool 951 select ARM64_MODULE_CMODEL_LARGE 952 select HAVE_MOD_ARCH_SPECIFIC 953 954config RELOCATABLE 955 bool 956 help 957 This builds the kernel as a Position Independent Executable (PIE), 958 which retains all relocation metadata required to relocate the 959 kernel binary at runtime to a different virtual address than the 960 address it was linked at. 961 Since AArch64 uses the RELA relocation format, this requires a 962 relocation pass at runtime even if the kernel is loaded at the 963 same address it was linked at. 964 965config RANDOMIZE_BASE 966 bool "Randomize the address of the kernel image" 967 select ARM64_MODULE_PLTS if MODULES 968 select RELOCATABLE 969 help 970 Randomizes the virtual address at which the kernel image is 971 loaded, as a security feature that deters exploit attempts 972 relying on knowledge of the location of kernel internals. 973 974 It is the bootloader's job to provide entropy, by passing a 975 random u64 value in /chosen/kaslr-seed at kernel entry. 976 977 When booting via the UEFI stub, it will invoke the firmware's 978 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 979 to the kernel proper. In addition, it will randomise the physical 980 location of the kernel Image as well. 981 982 If unsure, say N. 983 984config RANDOMIZE_MODULE_REGION_FULL 985 bool "Randomize the module region independently from the core kernel" 986 depends on RANDOMIZE_BASE 987 default y 988 help 989 Randomizes the location of the module region without considering the 990 location of the core kernel. This way, it is impossible for modules 991 to leak information about the location of core kernel data structures 992 but it does imply that function calls between modules and the core 993 kernel will need to be resolved via veneers in the module PLT. 994 995 When this option is not set, the module region will be randomized over 996 a limited range that contains the [_stext, _etext] interval of the 997 core kernel, so branch relocations are always in range. 998 999endmenu 1000 1001menu "Boot options" 1002 1003config ARM64_ACPI_PARKING_PROTOCOL 1004 bool "Enable support for the ARM64 ACPI parking protocol" 1005 depends on ACPI 1006 help 1007 Enable support for the ARM64 ACPI parking protocol. If disabled 1008 the kernel will not allow booting through the ARM64 ACPI parking 1009 protocol even if the corresponding data is present in the ACPI 1010 MADT table. 1011 1012config CMDLINE 1013 string "Default kernel command string" 1014 default "" 1015 help 1016 Provide a set of default command-line options at build time by 1017 entering them here. As a minimum, you should specify the the 1018 root device (e.g. root=/dev/nfs). 1019 1020config CMDLINE_FORCE 1021 bool "Always use the default kernel command string" 1022 help 1023 Always use the default kernel command string, even if the boot 1024 loader passes other arguments to the kernel. 1025 This is useful if you cannot or don't want to change the 1026 command-line options your boot loader passes to the kernel. 1027 1028config EFI_STUB 1029 bool 1030 1031config EFI 1032 bool "UEFI runtime support" 1033 depends on OF && !CPU_BIG_ENDIAN 1034 select LIBFDT 1035 select UCS2_STRING 1036 select EFI_PARAMS_FROM_FDT 1037 select EFI_RUNTIME_WRAPPERS 1038 select EFI_STUB 1039 select EFI_ARMSTUB 1040 default y 1041 help 1042 This option provides support for runtime services provided 1043 by UEFI firmware (such as non-volatile variables, realtime 1044 clock, and platform reset). A UEFI stub is also provided to 1045 allow the kernel to be booted as an EFI application. This 1046 is only useful on systems that have UEFI firmware. 1047 1048config DMI 1049 bool "Enable support for SMBIOS (DMI) tables" 1050 depends on EFI 1051 default y 1052 help 1053 This enables SMBIOS/DMI feature for systems. 1054 1055 This option is only useful on systems that have UEFI firmware. 1056 However, even with this option, the resultant kernel should 1057 continue to boot on existing non-UEFI platforms. 1058 1059endmenu 1060 1061menu "Userspace binary formats" 1062 1063source "fs/Kconfig.binfmt" 1064 1065config COMPAT 1066 bool "Kernel support for 32-bit EL0" 1067 depends on ARM64_4K_PAGES || EXPERT 1068 select COMPAT_BINFMT_ELF if BINFMT_ELF 1069 select HAVE_UID16 1070 select OLD_SIGSUSPEND3 1071 select COMPAT_OLD_SIGACTION 1072 help 1073 This option enables support for a 32-bit EL0 running under a 64-bit 1074 kernel at EL1. AArch32-specific components such as system calls, 1075 the user helper functions, VFP support and the ptrace interface are 1076 handled appropriately by the kernel. 1077 1078 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1079 that you will only be able to execute AArch32 binaries that were compiled 1080 with page size aligned segments. 1081 1082 If you want to execute 32-bit userspace applications, say Y. 1083 1084config SYSVIPC_COMPAT 1085 def_bool y 1086 depends on COMPAT && SYSVIPC 1087 1088config KEYS_COMPAT 1089 def_bool y 1090 depends on COMPAT && KEYS 1091 1092endmenu 1093 1094menu "Power management options" 1095 1096source "kernel/power/Kconfig" 1097 1098config ARCH_HIBERNATION_POSSIBLE 1099 def_bool y 1100 depends on CPU_PM 1101 1102config ARCH_HIBERNATION_HEADER 1103 def_bool y 1104 depends on HIBERNATION 1105 1106config ARCH_SUSPEND_POSSIBLE 1107 def_bool y 1108 1109endmenu 1110 1111menu "CPU Power Management" 1112 1113source "drivers/cpuidle/Kconfig" 1114 1115source "drivers/cpufreq/Kconfig" 1116 1117endmenu 1118 1119source "net/Kconfig" 1120 1121source "drivers/Kconfig" 1122 1123source "drivers/firmware/Kconfig" 1124 1125source "drivers/acpi/Kconfig" 1126 1127source "fs/Kconfig" 1128 1129source "arch/arm64/kvm/Kconfig" 1130 1131source "arch/arm64/Kconfig.debug" 1132 1133source "security/Kconfig" 1134 1135source "crypto/Kconfig" 1136if CRYPTO 1137source "arch/arm64/crypto/Kconfig" 1138endif 1139 1140source "lib/Kconfig" 1141