xref: /linux/arch/arm64/Kconfig (revision c02ce1735b150cf7c3b43790b48e23dcd17c0d46)
1# SPDX-License-Identifier: GPL-2.0-only
2config ARM64
3	def_bool y
4	select ACPI_APMT if ACPI
5	select ACPI_CCA_REQUIRED if ACPI
6	select ACPI_GENERIC_GSI if ACPI
7	select ACPI_GTDT if ACPI
8	select ACPI_IORT if ACPI
9	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
10	select ACPI_MCFG if (ACPI && PCI)
11	select ACPI_SPCR_TABLE if ACPI
12	select ACPI_PPTT if ACPI
13	select ARCH_HAS_DEBUG_WX
14	select ARCH_BINFMT_ELF_EXTRA_PHDRS
15	select ARCH_BINFMT_ELF_STATE
16	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
17	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
18	select ARCH_ENABLE_MEMORY_HOTPLUG
19	select ARCH_ENABLE_MEMORY_HOTREMOVE
20	select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
21	select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
22	select ARCH_HAS_CACHE_LINE_SIZE
23	select ARCH_HAS_CURRENT_STACK_POINTER
24	select ARCH_HAS_DEBUG_VIRTUAL
25	select ARCH_HAS_DEBUG_VM_PGTABLE
26	select ARCH_HAS_DMA_PREP_COHERENT
27	select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
28	select ARCH_HAS_FAST_MULTIPLIER
29	select ARCH_HAS_FORTIFY_SOURCE
30	select ARCH_HAS_GCOV_PROFILE_ALL
31	select ARCH_HAS_GIGANTIC_PAGE
32	select ARCH_HAS_KCOV
33	select ARCH_HAS_KEEPINITRD
34	select ARCH_HAS_MEMBARRIER_SYNC_CORE
35	select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
36	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
37	select ARCH_HAS_PTE_DEVMAP
38	select ARCH_HAS_PTE_SPECIAL
39	select ARCH_HAS_HW_PTE_YOUNG
40	select ARCH_HAS_SETUP_DMA_OPS
41	select ARCH_HAS_SET_DIRECT_MAP
42	select ARCH_HAS_SET_MEMORY
43	select ARCH_STACKWALK
44	select ARCH_HAS_STRICT_KERNEL_RWX
45	select ARCH_HAS_STRICT_MODULE_RWX
46	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
47	select ARCH_HAS_SYNC_DMA_FOR_CPU
48	select ARCH_HAS_SYSCALL_WRAPPER
49	select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT
50	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
51	select ARCH_HAS_ZONE_DMA_SET if EXPERT
52	select ARCH_HAVE_ELF_PROT
53	select ARCH_HAVE_NMI_SAFE_CMPXCHG
54	select ARCH_HAVE_TRACE_MMIO_ACCESS
55	select ARCH_INLINE_READ_LOCK if !PREEMPTION
56	select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION
57	select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION
58	select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION
59	select ARCH_INLINE_READ_UNLOCK if !PREEMPTION
60	select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION
61	select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION
62	select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION
63	select ARCH_INLINE_WRITE_LOCK if !PREEMPTION
64	select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION
65	select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION
66	select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION
67	select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION
68	select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION
69	select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION
70	select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION
71	select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION
72	select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION
73	select ARCH_INLINE_SPIN_LOCK if !PREEMPTION
74	select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION
75	select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION
76	select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION
77	select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION
78	select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION
79	select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION
80	select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION
81	select ARCH_KEEP_MEMBLOCK
82	select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE
83	select ARCH_USE_CMPXCHG_LOCKREF
84	select ARCH_USE_GNU_PROPERTY
85	select ARCH_USE_MEMTEST
86	select ARCH_USE_QUEUED_RWLOCKS
87	select ARCH_USE_QUEUED_SPINLOCKS
88	select ARCH_USE_SYM_ANNOTATIONS
89	select ARCH_SUPPORTS_DEBUG_PAGEALLOC
90	select ARCH_SUPPORTS_HUGETLBFS
91	select ARCH_SUPPORTS_MEMORY_FAILURE
92	select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK
93	select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN
94	select ARCH_SUPPORTS_LTO_CLANG_THIN
95	select ARCH_SUPPORTS_CFI_CLANG
96	select ARCH_SUPPORTS_ATOMIC_RMW
97	select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
98	select ARCH_SUPPORTS_NUMA_BALANCING
99	select ARCH_SUPPORTS_PAGE_TABLE_CHECK
100	select ARCH_SUPPORTS_PER_VMA_LOCK
101	select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH
102	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT
103	select ARCH_WANT_DEFAULT_BPF_JIT
104	select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
105	select ARCH_WANT_FRAME_POINTERS
106	select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
107	select ARCH_WANT_LD_ORPHAN_WARN
108	select ARCH_WANTS_NO_INSTR
109	select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
110	select ARCH_HAS_UBSAN
111	select ARM_AMBA
112	select ARM_ARCH_TIMER
113	select ARM_GIC
114	select AUDIT_ARCH_COMPAT_GENERIC
115	select ARM_GIC_V2M if PCI
116	select ARM_GIC_V3
117	select ARM_GIC_V3_ITS if PCI
118	select ARM_PSCI_FW
119	select BUILDTIME_TABLE_SORT
120	select CLONE_BACKWARDS
121	select COMMON_CLK
122	select CPU_PM if (SUSPEND || CPU_IDLE)
123	select CPUMASK_OFFSTACK if NR_CPUS > 256
124	select CRC32
125	select DCACHE_WORD_ACCESS
126	select DYNAMIC_FTRACE if FUNCTION_TRACER
127	select DMA_BOUNCE_UNALIGNED_KMALLOC
128	select DMA_DIRECT_REMAP
129	select EDAC_SUPPORT
130	select FRAME_POINTER
131	select FUNCTION_ALIGNMENT_4B
132	select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS
133	select GENERIC_ALLOCATOR
134	select GENERIC_ARCH_TOPOLOGY
135	select GENERIC_CLOCKEVENTS_BROADCAST
136	select GENERIC_CPU_AUTOPROBE
137	select GENERIC_CPU_DEVICES
138	select GENERIC_CPU_VULNERABILITIES
139	select GENERIC_EARLY_IOREMAP
140	select GENERIC_IDLE_POLL_SETUP
141	select GENERIC_IOREMAP
142	select GENERIC_IRQ_IPI
143	select GENERIC_IRQ_PROBE
144	select GENERIC_IRQ_SHOW
145	select GENERIC_IRQ_SHOW_LEVEL
146	select GENERIC_LIB_DEVMEM_IS_ALLOWED
147	select GENERIC_PCI_IOMAP
148	select GENERIC_PTDUMP
149	select GENERIC_SCHED_CLOCK
150	select GENERIC_SMP_IDLE_THREAD
151	select GENERIC_TIME_VSYSCALL
152	select GENERIC_GETTIMEOFDAY
153	select GENERIC_VDSO_TIME_NS
154	select HARDIRQS_SW_RESEND
155	select HAS_IOPORT
156	select HAVE_MOVE_PMD
157	select HAVE_MOVE_PUD
158	select HAVE_PCI
159	select HAVE_ACPI_APEI if (ACPI && EFI)
160	select HAVE_ALIGNED_STRUCT_PAGE
161	select HAVE_ARCH_AUDITSYSCALL
162	select HAVE_ARCH_BITREVERSE
163	select HAVE_ARCH_COMPILER_H
164	select HAVE_ARCH_HUGE_VMALLOC
165	select HAVE_ARCH_HUGE_VMAP
166	select HAVE_ARCH_JUMP_LABEL
167	select HAVE_ARCH_JUMP_LABEL_RELATIVE
168	select HAVE_ARCH_KASAN
169	select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN
170	select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN
171	select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE)
172	# Some instrumentation may be unsound, hence EXPERT
173	select HAVE_ARCH_KCSAN if EXPERT
174	select HAVE_ARCH_KFENCE
175	select HAVE_ARCH_KGDB
176	select HAVE_ARCH_MMAP_RND_BITS
177	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
178	select HAVE_ARCH_PREL32_RELOCATIONS
179	select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
180	select HAVE_ARCH_SECCOMP_FILTER
181	select HAVE_ARCH_STACKLEAK
182	select HAVE_ARCH_THREAD_STRUCT_WHITELIST
183	select HAVE_ARCH_TRACEHOOK
184	select HAVE_ARCH_TRANSPARENT_HUGEPAGE
185	select HAVE_ARCH_VMAP_STACK
186	select HAVE_ARM_SMCCC
187	select HAVE_ASM_MODVERSIONS
188	select HAVE_EBPF_JIT
189	select HAVE_C_RECORDMCOUNT
190	select HAVE_CMPXCHG_DOUBLE
191	select HAVE_CMPXCHG_LOCAL
192	select HAVE_CONTEXT_TRACKING_USER
193	select HAVE_DEBUG_KMEMLEAK
194	select HAVE_DMA_CONTIGUOUS
195	select HAVE_DYNAMIC_FTRACE
196	select HAVE_DYNAMIC_FTRACE_WITH_ARGS \
197		if $(cc-option,-fpatchable-function-entry=2)
198	select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \
199		if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS
200	select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \
201		if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \
202		    (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE))
203	select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \
204		if DYNAMIC_FTRACE_WITH_ARGS
205	select HAVE_SAMPLE_FTRACE_DIRECT
206	select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
207	select HAVE_EFFICIENT_UNALIGNED_ACCESS
208	select HAVE_FAST_GUP
209	select HAVE_FTRACE_MCOUNT_RECORD
210	select HAVE_FUNCTION_TRACER
211	select HAVE_FUNCTION_ERROR_INJECTION
212	select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER
213	select HAVE_FUNCTION_GRAPH_TRACER
214	select HAVE_GCC_PLUGINS
215	select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \
216		HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI
217	select HAVE_HW_BREAKPOINT if PERF_EVENTS
218	select HAVE_IOREMAP_PROT
219	select HAVE_IRQ_TIME_ACCOUNTING
220	select HAVE_MOD_ARCH_SPECIFIC
221	select HAVE_NMI
222	select HAVE_PERF_EVENTS
223	select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI
224	select HAVE_PERF_REGS
225	select HAVE_PERF_USER_STACK_DUMP
226	select HAVE_PREEMPT_DYNAMIC_KEY
227	select HAVE_REGS_AND_STACK_ACCESS_API
228	select HAVE_POSIX_CPU_TIMERS_TASK_WORK
229	select HAVE_FUNCTION_ARG_ACCESS_API
230	select MMU_GATHER_RCU_TABLE_FREE
231	select HAVE_RSEQ
232	select HAVE_RUST if CPU_LITTLE_ENDIAN
233	select HAVE_STACKPROTECTOR
234	select HAVE_SYSCALL_TRACEPOINTS
235	select HAVE_KPROBES
236	select HAVE_KRETPROBES
237	select HAVE_GENERIC_VDSO
238	select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU
239	select IRQ_DOMAIN
240	select IRQ_FORCED_THREADING
241	select KASAN_VMALLOC if KASAN
242	select LOCK_MM_AND_FIND_VMA
243	select MODULES_USE_ELF_RELA
244	select NEED_DMA_MAP_STATE
245	select NEED_SG_DMA_LENGTH
246	select OF
247	select OF_EARLY_FLATTREE
248	select PCI_DOMAINS_GENERIC if PCI
249	select PCI_ECAM if (ACPI && PCI)
250	select PCI_SYSCALL if PCI
251	select POWER_RESET
252	select POWER_SUPPLY
253	select SPARSE_IRQ
254	select SWIOTLB
255	select SYSCTL_EXCEPTION_TRACE
256	select THREAD_INFO_IN_TASK
257	select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
258	select TRACE_IRQFLAGS_SUPPORT
259	select TRACE_IRQFLAGS_NMI_SUPPORT
260	select HAVE_SOFTIRQ_ON_OWN_STACK
261	help
262	  ARM 64-bit (AArch64) Linux support.
263
264config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
265	def_bool CC_IS_CLANG
266	# https://github.com/ClangBuiltLinux/linux/issues/1507
267	depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600))
268	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
269
270config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS
271	def_bool CC_IS_GCC
272	depends on $(cc-option,-fpatchable-function-entry=2)
273	select HAVE_DYNAMIC_FTRACE_WITH_ARGS
274
275config 64BIT
276	def_bool y
277
278config MMU
279	def_bool y
280
281config ARM64_CONT_PTE_SHIFT
282	int
283	default 5 if PAGE_SIZE_64KB
284	default 7 if PAGE_SIZE_16KB
285	default 4
286
287config ARM64_CONT_PMD_SHIFT
288	int
289	default 5 if PAGE_SIZE_64KB
290	default 5 if PAGE_SIZE_16KB
291	default 4
292
293config ARCH_MMAP_RND_BITS_MIN
294	default 14 if PAGE_SIZE_64KB
295	default 16 if PAGE_SIZE_16KB
296	default 18
297
298# max bits determined by the following formula:
299#  VA_BITS - PAGE_SHIFT - 3
300config ARCH_MMAP_RND_BITS_MAX
301	default 19 if ARM64_VA_BITS=36
302	default 24 if ARM64_VA_BITS=39
303	default 27 if ARM64_VA_BITS=42
304	default 30 if ARM64_VA_BITS=47
305	default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
306	default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
307	default 33 if ARM64_VA_BITS=48
308	default 14 if ARM64_64K_PAGES
309	default 16 if ARM64_16K_PAGES
310	default 18
311
312config ARCH_MMAP_RND_COMPAT_BITS_MIN
313	default 7 if ARM64_64K_PAGES
314	default 9 if ARM64_16K_PAGES
315	default 11
316
317config ARCH_MMAP_RND_COMPAT_BITS_MAX
318	default 16
319
320config NO_IOPORT_MAP
321	def_bool y if !PCI
322
323config STACKTRACE_SUPPORT
324	def_bool y
325
326config ILLEGAL_POINTER_VALUE
327	hex
328	default 0xdead000000000000
329
330config LOCKDEP_SUPPORT
331	def_bool y
332
333config GENERIC_BUG
334	def_bool y
335	depends on BUG
336
337config GENERIC_BUG_RELATIVE_POINTERS
338	def_bool y
339	depends on GENERIC_BUG
340
341config GENERIC_HWEIGHT
342	def_bool y
343
344config GENERIC_CSUM
345	def_bool y
346
347config GENERIC_CALIBRATE_DELAY
348	def_bool y
349
350config SMP
351	def_bool y
352
353config KERNEL_MODE_NEON
354	def_bool y
355
356config FIX_EARLYCON_MEM
357	def_bool y
358
359config PGTABLE_LEVELS
360	int
361	default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
362	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
363	default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
364	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
365	default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
366	default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52)
367	default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
368	default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52
369
370config ARCH_SUPPORTS_UPROBES
371	def_bool y
372
373config ARCH_PROC_KCORE_TEXT
374	def_bool y
375
376config BROKEN_GAS_INST
377	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
378
379config BUILTIN_RETURN_ADDRESS_STRIPS_PAC
380	bool
381	# Clang's __builtin_return_adddress() strips the PAC since 12.0.0
382	# https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2
383	default y if CC_IS_CLANG
384	# GCC's __builtin_return_address() strips the PAC since 11.1.0,
385	# and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
386	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891
387	default y if CC_IS_GCC && (GCC_VERSION >= 110100)
388	default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000)
389	default y if CC_IS_GCC && (GCC_VERSION >=  90400) && (GCC_VERSION < 100000)
390	default y if CC_IS_GCC && (GCC_VERSION >=  80500) && (GCC_VERSION <  90000)
391	default n
392
393config KASAN_SHADOW_OFFSET
394	hex
395	depends on KASAN_GENERIC || KASAN_SW_TAGS
396	default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS
397	default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS
398	default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS
399	default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS
400	default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS
401	default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS
402	default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS
403	default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS
404	default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS
405	default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
406	default 0xffffffffffffffff
407
408config UNWIND_TABLES
409	bool
410
411source "arch/arm64/Kconfig.platforms"
412
413menu "Kernel Features"
414
415menu "ARM errata workarounds via the alternatives framework"
416
417config AMPERE_ERRATUM_AC03_CPU_38
418        bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics"
419	default y
420	help
421	  This option adds an alternative code sequence to work around Ampere
422	  erratum AC03_CPU_38 on AmpereOne.
423
424	  The affected design reports FEAT_HAFDBS as not implemented in
425	  ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0
426	  as required by the architecture. The unadvertised HAFDBS
427	  implementation suffers from an additional erratum where hardware
428	  A/D updates can occur after a PTE has been marked invalid.
429
430	  The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
431	  which avoids enabling unadvertised hardware Access Flag management
432	  at stage-2.
433
434	  If unsure, say Y.
435
436config ARM64_WORKAROUND_CLEAN_CACHE
437	bool
438
439config ARM64_ERRATUM_826319
440	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
441	default y
442	select ARM64_WORKAROUND_CLEAN_CACHE
443	help
444	  This option adds an alternative code sequence to work around ARM
445	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
446	  AXI master interface and an L2 cache.
447
448	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
449	  and is unable to accept a certain write via this interface, it will
450	  not progress on read data presented on the read data channel and the
451	  system can deadlock.
452
453	  The workaround promotes data cache clean instructions to
454	  data cache clean-and-invalidate.
455	  Please note that this does not necessarily enable the workaround,
456	  as it depends on the alternative framework, which will only patch
457	  the kernel if an affected CPU is detected.
458
459	  If unsure, say Y.
460
461config ARM64_ERRATUM_827319
462	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
463	default y
464	select ARM64_WORKAROUND_CLEAN_CACHE
465	help
466	  This option adds an alternative code sequence to work around ARM
467	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
468	  master interface and an L2 cache.
469
470	  Under certain conditions this erratum can cause a clean line eviction
471	  to occur at the same time as another transaction to the same address
472	  on the AMBA 5 CHI interface, which can cause data corruption if the
473	  interconnect reorders the two transactions.
474
475	  The workaround promotes data cache clean instructions to
476	  data cache clean-and-invalidate.
477	  Please note that this does not necessarily enable the workaround,
478	  as it depends on the alternative framework, which will only patch
479	  the kernel if an affected CPU is detected.
480
481	  If unsure, say Y.
482
483config ARM64_ERRATUM_824069
484	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
485	default y
486	select ARM64_WORKAROUND_CLEAN_CACHE
487	help
488	  This option adds an alternative code sequence to work around ARM
489	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
490	  to a coherent interconnect.
491
492	  If a Cortex-A53 processor is executing a store or prefetch for
493	  write instruction at the same time as a processor in another
494	  cluster is executing a cache maintenance operation to the same
495	  address, then this erratum might cause a clean cache line to be
496	  incorrectly marked as dirty.
497
498	  The workaround promotes data cache clean instructions to
499	  data cache clean-and-invalidate.
500	  Please note that this option does not necessarily enable the
501	  workaround, as it depends on the alternative framework, which will
502	  only patch the kernel if an affected CPU is detected.
503
504	  If unsure, say Y.
505
506config ARM64_ERRATUM_819472
507	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
508	default y
509	select ARM64_WORKAROUND_CLEAN_CACHE
510	help
511	  This option adds an alternative code sequence to work around ARM
512	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
513	  present when it is connected to a coherent interconnect.
514
515	  If the processor is executing a load and store exclusive sequence at
516	  the same time as a processor in another cluster is executing a cache
517	  maintenance operation to the same address, then this erratum might
518	  cause data corruption.
519
520	  The workaround promotes data cache clean instructions to
521	  data cache clean-and-invalidate.
522	  Please note that this does not necessarily enable the workaround,
523	  as it depends on the alternative framework, which will only patch
524	  the kernel if an affected CPU is detected.
525
526	  If unsure, say Y.
527
528config ARM64_ERRATUM_832075
529	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
530	default y
531	help
532	  This option adds an alternative code sequence to work around ARM
533	  erratum 832075 on Cortex-A57 parts up to r1p2.
534
535	  Affected Cortex-A57 parts might deadlock when exclusive load/store
536	  instructions to Write-Back memory are mixed with Device loads.
537
538	  The workaround is to promote device loads to use Load-Acquire
539	  semantics.
540	  Please note that this does not necessarily enable the workaround,
541	  as it depends on the alternative framework, which will only patch
542	  the kernel if an affected CPU is detected.
543
544	  If unsure, say Y.
545
546config ARM64_ERRATUM_834220
547	bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"
548	depends on KVM
549	help
550	  This option adds an alternative code sequence to work around ARM
551	  erratum 834220 on Cortex-A57 parts up to r1p2.
552
553	  Affected Cortex-A57 parts might report a Stage 2 translation
554	  fault as the result of a Stage 1 fault for load crossing a
555	  page boundary when there is a permission or device memory
556	  alignment fault at Stage 1 and a translation fault at Stage 2.
557
558	  The workaround is to verify that the Stage 1 translation
559	  doesn't generate a fault before handling the Stage 2 fault.
560	  Please note that this does not necessarily enable the workaround,
561	  as it depends on the alternative framework, which will only patch
562	  the kernel if an affected CPU is detected.
563
564	  If unsure, say N.
565
566config ARM64_ERRATUM_1742098
567	bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence"
568	depends on COMPAT
569	default y
570	help
571	  This option removes the AES hwcap for aarch32 user-space to
572	  workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
573
574	  Affected parts may corrupt the AES state if an interrupt is
575	  taken between a pair of AES instructions. These instructions
576	  are only present if the cryptography extensions are present.
577	  All software should have a fallback implementation for CPUs
578	  that don't implement the cryptography extensions.
579
580	  If unsure, say Y.
581
582config ARM64_ERRATUM_845719
583	bool "Cortex-A53: 845719: a load might read incorrect data"
584	depends on COMPAT
585	default y
586	help
587	  This option adds an alternative code sequence to work around ARM
588	  erratum 845719 on Cortex-A53 parts up to r0p4.
589
590	  When running a compat (AArch32) userspace on an affected Cortex-A53
591	  part, a load at EL0 from a virtual address that matches the bottom 32
592	  bits of the virtual address used by a recent load at (AArch64) EL1
593	  might return incorrect data.
594
595	  The workaround is to write the contextidr_el1 register on exception
596	  return to a 32-bit task.
597	  Please note that this does not necessarily enable the workaround,
598	  as it depends on the alternative framework, which will only patch
599	  the kernel if an affected CPU is detected.
600
601	  If unsure, say Y.
602
603config ARM64_ERRATUM_843419
604	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
605	default y
606	help
607	  This option links the kernel with '--fix-cortex-a53-843419' and
608	  enables PLT support to replace certain ADRP instructions, which can
609	  cause subsequent memory accesses to use an incorrect address on
610	  Cortex-A53 parts up to r0p4.
611
612	  If unsure, say Y.
613
614config ARM64_LD_HAS_FIX_ERRATUM_843419
615	def_bool $(ld-option,--fix-cortex-a53-843419)
616
617config ARM64_ERRATUM_1024718
618	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
619	default y
620	help
621	  This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
622
623	  Affected Cortex-A55 cores (all revisions) could cause incorrect
624	  update of the hardware dirty bit when the DBM/AP bits are updated
625	  without a break-before-make. The workaround is to disable the usage
626	  of hardware DBM locally on the affected cores. CPUs not affected by
627	  this erratum will continue to use the feature.
628
629	  If unsure, say Y.
630
631config ARM64_ERRATUM_1418040
632	bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
633	default y
634	depends on COMPAT
635	help
636	  This option adds a workaround for ARM Cortex-A76/Neoverse-N1
637	  errata 1188873 and 1418040.
638
639	  Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
640	  cause register corruption when accessing the timer registers
641	  from AArch32 userspace.
642
643	  If unsure, say Y.
644
645config ARM64_WORKAROUND_SPECULATIVE_AT
646	bool
647
648config ARM64_ERRATUM_1165522
649	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
650	default y
651	select ARM64_WORKAROUND_SPECULATIVE_AT
652	help
653	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
654
655	  Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
656	  corrupted TLBs by speculating an AT instruction during a guest
657	  context switch.
658
659	  If unsure, say Y.
660
661config ARM64_ERRATUM_1319367
662	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
663	default y
664	select ARM64_WORKAROUND_SPECULATIVE_AT
665	help
666	  This option adds work arounds for ARM Cortex-A57 erratum 1319537
667	  and A72 erratum 1319367
668
669	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by
670	  speculating an AT instruction during a guest context switch.
671
672	  If unsure, say Y.
673
674config ARM64_ERRATUM_1530923
675	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
676	default y
677	select ARM64_WORKAROUND_SPECULATIVE_AT
678	help
679	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
680
681	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
682	  corrupted TLBs by speculating an AT instruction during a guest
683	  context switch.
684
685	  If unsure, say Y.
686
687config ARM64_WORKAROUND_REPEAT_TLBI
688	bool
689
690config ARM64_ERRATUM_2441007
691	bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
692	select ARM64_WORKAROUND_REPEAT_TLBI
693	help
694	  This option adds a workaround for ARM Cortex-A55 erratum #2441007.
695
696	  Under very rare circumstances, affected Cortex-A55 CPUs
697	  may not handle a race between a break-before-make sequence on one
698	  CPU, and another CPU accessing the same page. This could allow a
699	  store to a page that has been unmapped.
700
701	  Work around this by adding the affected CPUs to the list that needs
702	  TLB sequences to be done twice.
703
704	  If unsure, say N.
705
706config ARM64_ERRATUM_1286807
707	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)"
708	select ARM64_WORKAROUND_REPEAT_TLBI
709	help
710	  This option adds a workaround for ARM Cortex-A76 erratum 1286807.
711
712	  On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
713	  address for a cacheable mapping of a location is being
714	  accessed by a core while another core is remapping the virtual
715	  address to a new physical page using the recommended
716	  break-before-make sequence, then under very rare circumstances
717	  TLBI+DSB completes before a read using the translation being
718	  invalidated has been observed by other observers. The
719	  workaround repeats the TLBI+DSB operation.
720
721	  If unsure, say N.
722
723config ARM64_ERRATUM_1463225
724	bool "Cortex-A76: Software Step might prevent interrupt recognition"
725	default y
726	help
727	  This option adds a workaround for Arm Cortex-A76 erratum 1463225.
728
729	  On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
730	  of a system call instruction (SVC) can prevent recognition of
731	  subsequent interrupts when software stepping is disabled in the
732	  exception handler of the system call and either kernel debugging
733	  is enabled or VHE is in use.
734
735	  Work around the erratum by triggering a dummy step exception
736	  when handling a system call from a task that is being stepped
737	  in a VHE configuration of the kernel.
738
739	  If unsure, say Y.
740
741config ARM64_ERRATUM_1542419
742	bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)"
743	help
744	  This option adds a workaround for ARM Neoverse-N1 erratum
745	  1542419.
746
747	  Affected Neoverse-N1 cores could execute a stale instruction when
748	  modified by another CPU. The workaround depends on a firmware
749	  counterpart.
750
751	  Workaround the issue by hiding the DIC feature from EL0. This
752	  forces user-space to perform cache maintenance.
753
754	  If unsure, say N.
755
756config ARM64_ERRATUM_1508412
757	bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read"
758	default y
759	help
760	  This option adds a workaround for Arm Cortex-A77 erratum 1508412.
761
762	  Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
763	  of a store-exclusive or read of PAR_EL1 and a load with device or
764	  non-cacheable memory attributes. The workaround depends on a firmware
765	  counterpart.
766
767	  KVM guests must also have the workaround implemented or they can
768	  deadlock the system.
769
770	  Work around the issue by inserting DMB SY barriers around PAR_EL1
771	  register reads and warning KVM users. The DMB barrier is sufficient
772	  to prevent a speculative PAR_EL1 read.
773
774	  If unsure, say Y.
775
776config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
777	bool
778
779config ARM64_ERRATUM_2051678
780	bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
781	default y
782	help
783	  This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
784	  Affected Cortex-A510 might not respect the ordering rules for
785	  hardware update of the page table's dirty bit. The workaround
786	  is to not enable the feature on affected CPUs.
787
788	  If unsure, say Y.
789
790config ARM64_ERRATUM_2077057
791	bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
792	default y
793	help
794	  This option adds the workaround for ARM Cortex-A510 erratum 2077057.
795	  Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
796	  expected, but a Pointer Authentication trap is taken instead. The
797	  erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow
798	  EL1 to cause a return to EL2 with a guest controlled ELR_EL2.
799
800	  This can only happen when EL2 is stepping EL1.
801
802	  When these conditions occur, the SPSR_EL2 value is unchanged from the
803	  previous guest entry, and can be restored from the in-memory copy.
804
805	  If unsure, say Y.
806
807config ARM64_ERRATUM_2658417
808	bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
809	default y
810	help
811	  This option adds the workaround for ARM Cortex-A510 erratum 2658417.
812	  Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
813	  BFMMLA or VMMLA instructions in rare circumstances when a pair of
814	  A510 CPUs are using shared neon hardware. As the sharing is not
815	  discoverable by the kernel, hide the BF16 HWCAP to indicate that
816	  user-space should not be using these instructions.
817
818	  If unsure, say Y.
819
820config ARM64_ERRATUM_2119858
821	bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
822	default y
823	depends on CORESIGHT_TRBE
824	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
825	help
826	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
827
828	  Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
829	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
830	  the event of a WRAP event.
831
832	  Work around the issue by always making sure we move the TRBPTR_EL1 by
833	  256 bytes before enabling the buffer and filling the first 256 bytes of
834	  the buffer with ETM ignore packets upon disabling.
835
836	  If unsure, say Y.
837
838config ARM64_ERRATUM_2139208
839	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
840	default y
841	depends on CORESIGHT_TRBE
842	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
843	help
844	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
845
846	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
847	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
848	  the event of a WRAP event.
849
850	  Work around the issue by always making sure we move the TRBPTR_EL1 by
851	  256 bytes before enabling the buffer and filling the first 256 bytes of
852	  the buffer with ETM ignore packets upon disabling.
853
854	  If unsure, say Y.
855
856config ARM64_WORKAROUND_TSB_FLUSH_FAILURE
857	bool
858
859config ARM64_ERRATUM_2054223
860	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
861	default y
862	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
863	help
864	  Enable workaround for ARM Cortex-A710 erratum 2054223
865
866	  Affected cores may fail to flush the trace data on a TSB instruction, when
867	  the PE is in trace prohibited state. This will cause losing a few bytes
868	  of the trace cached.
869
870	  Workaround is to issue two TSB consecutively on affected cores.
871
872	  If unsure, say Y.
873
874config ARM64_ERRATUM_2067961
875	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
876	default y
877	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE
878	help
879	  Enable workaround for ARM Neoverse-N2 erratum 2067961
880
881	  Affected cores may fail to flush the trace data on a TSB instruction, when
882	  the PE is in trace prohibited state. This will cause losing a few bytes
883	  of the trace cached.
884
885	  Workaround is to issue two TSB consecutively on affected cores.
886
887	  If unsure, say Y.
888
889config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
890	bool
891
892config ARM64_ERRATUM_2253138
893	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
894	depends on CORESIGHT_TRBE
895	default y
896	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
897	help
898	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
899
900	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
901	  for TRBE. Under some conditions, the TRBE might generate a write to the next
902	  virtually addressed page following the last page of the TRBE address space
903	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
904
905	  Work around this in the driver by always making sure that there is a
906	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
907
908	  If unsure, say Y.
909
910config ARM64_ERRATUM_2224489
911	bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
912	depends on CORESIGHT_TRBE
913	default y
914	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
915	help
916	  This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
917
918	  Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
919	  for TRBE. Under some conditions, the TRBE might generate a write to the next
920	  virtually addressed page following the last page of the TRBE address space
921	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
922
923	  Work around this in the driver by always making sure that there is a
924	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.
925
926	  If unsure, say Y.
927
928config ARM64_ERRATUM_2441009
929	bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)"
930	select ARM64_WORKAROUND_REPEAT_TLBI
931	help
932	  This option adds a workaround for ARM Cortex-A510 erratum #2441009.
933
934	  Under very rare circumstances, affected Cortex-A510 CPUs
935	  may not handle a race between a break-before-make sequence on one
936	  CPU, and another CPU accessing the same page. This could allow a
937	  store to a page that has been unmapped.
938
939	  Work around this by adding the affected CPUs to the list that needs
940	  TLB sequences to be done twice.
941
942	  If unsure, say N.
943
944config ARM64_ERRATUM_2064142
945	bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
946	depends on CORESIGHT_TRBE
947	default y
948	help
949	  This option adds the workaround for ARM Cortex-A510 erratum 2064142.
950
951	  Affected Cortex-A510 core might fail to write into system registers after the
952	  TRBE has been disabled. Under some conditions after the TRBE has been disabled
953	  writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1,
954	  and TRBTRG_EL1 will be ignored and will not be effected.
955
956	  Work around this in the driver by executing TSB CSYNC and DSB after collection
957	  is stopped and before performing a system register write to one of the affected
958	  registers.
959
960	  If unsure, say Y.
961
962config ARM64_ERRATUM_2038923
963	bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
964	depends on CORESIGHT_TRBE
965	default y
966	help
967	  This option adds the workaround for ARM Cortex-A510 erratum 2038923.
968
969	  Affected Cortex-A510 core might cause an inconsistent view on whether trace is
970	  prohibited within the CPU. As a result, the trace buffer or trace buffer state
971	  might be corrupted. This happens after TRBE buffer has been enabled by setting
972	  TRBLIMITR_EL1.E, followed by just a single context synchronization event before
973	  execution changes from a context, in which trace is prohibited to one where it
974	  isn't, or vice versa. In these mentioned conditions, the view of whether trace
975	  is prohibited is inconsistent between parts of the CPU, and the trace buffer or
976	  the trace buffer state might be corrupted.
977
978	  Work around this in the driver by preventing an inconsistent view of whether the
979	  trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a
980	  change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or
981	  two ISB instructions if no ERET is to take place.
982
983	  If unsure, say Y.
984
985config ARM64_ERRATUM_1902691
986	bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
987	depends on CORESIGHT_TRBE
988	default y
989	help
990	  This option adds the workaround for ARM Cortex-A510 erratum 1902691.
991
992	  Affected Cortex-A510 core might cause trace data corruption, when being written
993	  into the memory. Effectively TRBE is broken and hence cannot be used to capture
994	  trace data.
995
996	  Work around this problem in the driver by just preventing TRBE initialization on
997	  affected cpus. The firmware must have disabled the access to TRBE for the kernel
998	  on such implementations. This will cover the kernel for any firmware that doesn't
999	  do this already.
1000
1001	  If unsure, say Y.
1002
1003config ARM64_ERRATUM_2457168
1004	bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1005	depends on ARM64_AMU_EXTN
1006	default y
1007	help
1008	  This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1009
1010	  The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate
1011	  as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1012	  incorrectly giving a significantly higher output value.
1013
1014	  Work around this problem by returning 0 when reading the affected counter in
1015	  key locations that results in disabling all users of this counter. This effect
1016	  is the same to firmware disabling affected counters.
1017
1018	  If unsure, say Y.
1019
1020config ARM64_ERRATUM_2645198
1021	bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1022	default y
1023	help
1024	  This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1025
1026	  If a Cortex-A715 cpu sees a page mapping permissions change from executable
1027	  to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1028	  next instruction abort caused by permission fault.
1029
1030	  Only user-space does executable to non-executable permission transition via
1031	  mprotect() system call. Workaround the problem by doing a break-before-make
1032	  TLB invalidation, for all changes to executable user space mappings.
1033
1034	  If unsure, say Y.
1035
1036config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1037	bool
1038
1039config ARM64_ERRATUM_2966298
1040	bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1041	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1042	default y
1043	help
1044	  This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1045
1046	  On an affected Cortex-A520 core, a speculatively executed unprivileged
1047	  load might leak data from a privileged level via a cache side channel.
1048
1049	  Work around this problem by executing a TLBI before returning to EL0.
1050
1051	  If unsure, say Y.
1052
1053config ARM64_ERRATUM_3117295
1054	bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load"
1055	select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD
1056	default y
1057	help
1058	  This option adds the workaround for ARM Cortex-A510 erratum 3117295.
1059
1060	  On an affected Cortex-A510 core, a speculatively executed unprivileged
1061	  load might leak data from a privileged level via a cache side channel.
1062
1063	  Work around this problem by executing a TLBI before returning to EL0.
1064
1065	  If unsure, say Y.
1066
1067config CAVIUM_ERRATUM_22375
1068	bool "Cavium erratum 22375, 24313"
1069	default y
1070	help
1071	  Enable workaround for errata 22375 and 24313.
1072
1073	  This implements two gicv3-its errata workarounds for ThunderX. Both
1074	  with a small impact affecting only ITS table allocation.
1075
1076	    erratum 22375: only alloc 8MB table size
1077	    erratum 24313: ignore memory access type
1078
1079	  The fixes are in ITS initialization and basically ignore memory access
1080	  type and table size provided by the TYPER and BASER registers.
1081
1082	  If unsure, say Y.
1083
1084config CAVIUM_ERRATUM_23144
1085	bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
1086	depends on NUMA
1087	default y
1088	help
1089	  ITS SYNC command hang for cross node io and collections/cpu mapping.
1090
1091	  If unsure, say Y.
1092
1093config CAVIUM_ERRATUM_23154
1094	bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1095	default y
1096	help
1097	  The ThunderX GICv3 implementation requires a modified version for
1098	  reading the IAR status to ensure data synchronization
1099	  (access to icc_iar1_el1 is not sync'ed before and after).
1100
1101	  It also suffers from erratum 38545 (also present on Marvell's
1102	  OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1103	  spuriously presented to the CPU interface.
1104
1105	  If unsure, say Y.
1106
1107config CAVIUM_ERRATUM_27456
1108	bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
1109	default y
1110	help
1111	  On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
1112	  instructions may cause the icache to become corrupted if it
1113	  contains data for a non-current ASID.  The fix is to
1114	  invalidate the icache when changing the mm context.
1115
1116	  If unsure, say Y.
1117
1118config CAVIUM_ERRATUM_30115
1119	bool "Cavium erratum 30115: Guest may disable interrupts in host"
1120	default y
1121	help
1122	  On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
1123	  1.2, and T83 Pass 1.0, KVM guest execution may disable
1124	  interrupts in host. Trapping both GICv3 group-0 and group-1
1125	  accesses sidesteps the issue.
1126
1127	  If unsure, say Y.
1128
1129config CAVIUM_TX2_ERRATUM_219
1130	bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1131	default y
1132	help
1133	  On Cavium ThunderX2, a load, store or prefetch instruction between a
1134	  TTBR update and the corresponding context synchronizing operation can
1135	  cause a spurious Data Abort to be delivered to any hardware thread in
1136	  the CPU core.
1137
1138	  Work around the issue by avoiding the problematic code sequence and
1139	  trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The
1140	  trap handler performs the corresponding register access, skips the
1141	  instruction and ensures context synchronization by virtue of the
1142	  exception return.
1143
1144	  If unsure, say Y.
1145
1146config FUJITSU_ERRATUM_010001
1147	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1148	default y
1149	help
1150	  This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1151	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1152	  accesses may cause undefined fault (Data abort, DFSC=0b111111).
1153	  This fault occurs under a specific hardware condition when a
1154	  load/store instruction performs an address translation using:
1155	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1156	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1157	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1158	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1159
1160	  The workaround is to ensure these bits are clear in TCR_ELx.
1161	  The workaround only affects the Fujitsu-A64FX.
1162
1163	  If unsure, say Y.
1164
1165config HISILICON_ERRATUM_161600802
1166	bool "Hip07 161600802: Erroneous redistributor VLPI base"
1167	default y
1168	help
1169	  The HiSilicon Hip07 SoC uses the wrong redistributor base
1170	  when issued ITS commands such as VMOVP and VMAPP, and requires
1171	  a 128kB offset to be applied to the target address in this commands.
1172
1173	  If unsure, say Y.
1174
1175config QCOM_FALKOR_ERRATUM_1003
1176	bool "Falkor E1003: Incorrect translation due to ASID change"
1177	default y
1178	help
1179	  On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1180	  and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1181	  in TTBR1_EL1, this situation only occurs in the entry trampoline and
1182	  then only for entries in the walk cache, since the leaf translation
1183	  is unchanged. Work around the erratum by invalidating the walk cache
1184	  entries for the trampoline before entering the kernel proper.
1185
1186config QCOM_FALKOR_ERRATUM_1009
1187	bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
1188	default y
1189	select ARM64_WORKAROUND_REPEAT_TLBI
1190	help
1191	  On Falkor v1, the CPU may prematurely complete a DSB following a
1192	  TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
1193	  one more time to fix the issue.
1194
1195	  If unsure, say Y.
1196
1197config QCOM_QDF2400_ERRATUM_0065
1198	bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
1199	default y
1200	help
1201	  On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
1202	  ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
1203	  been indicated as 16Bytes (0xf), not 8Bytes (0x7).
1204
1205	  If unsure, say Y.
1206
1207config QCOM_FALKOR_ERRATUM_E1041
1208	bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
1209	default y
1210	help
1211	  Falkor CPU may speculatively fetch instructions from an improper
1212	  memory location when MMU translation is changed from SCTLR_ELn[M]=1
1213	  to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
1214
1215	  If unsure, say Y.
1216
1217config NVIDIA_CARMEL_CNP_ERRATUM
1218	bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores"
1219	default y
1220	help
1221	  If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1222	  invalidate shared TLB entries installed by a different core, as it would
1223	  on standard ARM cores.
1224
1225	  If unsure, say Y.
1226
1227config ROCKCHIP_ERRATUM_3588001
1228	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
1229	default y
1230	help
1231	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1232	  This means, that its sharability feature may not be used, even though it
1233	  is supported by the IP itself.
1234
1235	  If unsure, say Y.
1236
1237config SOCIONEXT_SYNQUACER_PREITS
1238	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1239	default y
1240	help
1241	  Socionext Synquacer SoCs implement a separate h/w block to generate
1242	  MSI doorbell writes with non-zero values for the device ID.
1243
1244	  If unsure, say Y.
1245
1246endmenu # "ARM errata workarounds via the alternatives framework"
1247
1248choice
1249	prompt "Page size"
1250	default ARM64_4K_PAGES
1251	help
1252	  Page size (translation granule) configuration.
1253
1254config ARM64_4K_PAGES
1255	bool "4KB"
1256	select HAVE_PAGE_SIZE_4KB
1257	help
1258	  This feature enables 4KB pages support.
1259
1260config ARM64_16K_PAGES
1261	bool "16KB"
1262	select HAVE_PAGE_SIZE_16KB
1263	help
1264	  The system will use 16KB pages support. AArch32 emulation
1265	  requires applications compiled with 16K (or a multiple of 16K)
1266	  aligned segments.
1267
1268config ARM64_64K_PAGES
1269	bool "64KB"
1270	select HAVE_PAGE_SIZE_64KB
1271	help
1272	  This feature enables 64KB pages support (4KB by default)
1273	  allowing only two levels of page tables and faster TLB
1274	  look-up. AArch32 emulation requires applications compiled
1275	  with 64K aligned segments.
1276
1277endchoice
1278
1279choice
1280	prompt "Virtual address space size"
1281	default ARM64_VA_BITS_52
1282	help
1283	  Allows choosing one of multiple possible virtual address
1284	  space sizes. The level of translation table is determined by
1285	  a combination of page size and virtual address space size.
1286
1287config ARM64_VA_BITS_36
1288	bool "36-bit" if EXPERT
1289	depends on PAGE_SIZE_16KB
1290
1291config ARM64_VA_BITS_39
1292	bool "39-bit"
1293	depends on PAGE_SIZE_4KB
1294
1295config ARM64_VA_BITS_42
1296	bool "42-bit"
1297	depends on PAGE_SIZE_64KB
1298
1299config ARM64_VA_BITS_47
1300	bool "47-bit"
1301	depends on PAGE_SIZE_16KB
1302
1303config ARM64_VA_BITS_48
1304	bool "48-bit"
1305
1306config ARM64_VA_BITS_52
1307	bool "52-bit"
1308	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1309	help
1310	  Enable 52-bit virtual addressing for userspace when explicitly
1311	  requested via a hint to mmap(). The kernel will also use 52-bit
1312	  virtual addresses for its own mappings (provided HW support for
1313	  this feature is available, otherwise it reverts to 48-bit).
1314
1315	  NOTE: Enabling 52-bit virtual addressing in conjunction with
1316	  ARMv8.3 Pointer Authentication will result in the PAC being
1317	  reduced from 7 bits to 3 bits, which may have a significant
1318	  impact on its susceptibility to brute-force attacks.
1319
1320	  If unsure, select 48-bit virtual addressing instead.
1321
1322endchoice
1323
1324config ARM64_FORCE_52BIT
1325	bool "Force 52-bit virtual addresses for userspace"
1326	depends on ARM64_VA_BITS_52 && EXPERT
1327	help
1328	  For systems with 52-bit userspace VAs enabled, the kernel will attempt
1329	  to maintain compatibility with older software by providing 48-bit VAs
1330	  unless a hint is supplied to mmap.
1331
1332	  This configuration option disables the 48-bit compatibility logic, and
1333	  forces all userspace addresses to be 52-bit on HW that supports it. One
1334	  should only enable this configuration option for stress testing userspace
1335	  memory management code. If unsure say N here.
1336
1337config ARM64_VA_BITS
1338	int
1339	default 36 if ARM64_VA_BITS_36
1340	default 39 if ARM64_VA_BITS_39
1341	default 42 if ARM64_VA_BITS_42
1342	default 47 if ARM64_VA_BITS_47
1343	default 48 if ARM64_VA_BITS_48
1344	default 52 if ARM64_VA_BITS_52
1345
1346choice
1347	prompt "Physical address space size"
1348	default ARM64_PA_BITS_48
1349	help
1350	  Choose the maximum physical address range that the kernel will
1351	  support.
1352
1353config ARM64_PA_BITS_48
1354	bool "48-bit"
1355	depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52
1356
1357config ARM64_PA_BITS_52
1358	bool "52-bit"
1359	depends on ARM64_64K_PAGES || ARM64_VA_BITS_52
1360	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1361	help
1362	  Enable support for a 52-bit physical address space, introduced as
1363	  part of the ARMv8.2-LPA extension.
1364
1365	  With this enabled, the kernel will also continue to work on CPUs that
1366	  do not support ARMv8.2-LPA, but with some added memory overhead (and
1367	  minor performance overhead).
1368
1369endchoice
1370
1371config ARM64_PA_BITS
1372	int
1373	default 48 if ARM64_PA_BITS_48
1374	default 52 if ARM64_PA_BITS_52
1375
1376config ARM64_LPA2
1377	def_bool y
1378	depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES
1379
1380choice
1381	prompt "Endianness"
1382	default CPU_LITTLE_ENDIAN
1383	help
1384	  Select the endianness of data accesses performed by the CPU. Userspace
1385	  applications will need to be compiled and linked for the endianness
1386	  that is selected here.
1387
1388config CPU_BIG_ENDIAN
1389	bool "Build big-endian kernel"
1390	# https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c
1391	depends on AS_IS_GNU || AS_VERSION >= 150000
1392	help
1393	  Say Y if you plan on running a kernel with a big-endian userspace.
1394
1395config CPU_LITTLE_ENDIAN
1396	bool "Build little-endian kernel"
1397	help
1398	  Say Y if you plan on running a kernel with a little-endian userspace.
1399	  This is usually the case for distributions targeting arm64.
1400
1401endchoice
1402
1403config SCHED_MC
1404	bool "Multi-core scheduler support"
1405	help
1406	  Multi-core scheduler support improves the CPU scheduler's decision
1407	  making when dealing with multi-core CPU chips at a cost of slightly
1408	  increased overhead in some places. If unsure say N here.
1409
1410config SCHED_CLUSTER
1411	bool "Cluster scheduler support"
1412	help
1413	  Cluster scheduler support improves the CPU scheduler's decision
1414	  making when dealing with machines that have clusters of CPUs.
1415	  Cluster usually means a couple of CPUs which are placed closely
1416	  by sharing mid-level caches, last-level cache tags or internal
1417	  busses.
1418
1419config SCHED_SMT
1420	bool "SMT scheduler support"
1421	help
1422	  Improves the CPU scheduler's decision making when dealing with
1423	  MultiThreading at a cost of slightly increased overhead in some
1424	  places. If unsure say N here.
1425
1426config NR_CPUS
1427	int "Maximum number of CPUs (2-4096)"
1428	range 2 4096
1429	default "512"
1430
1431config HOTPLUG_CPU
1432	bool "Support for hot-pluggable CPUs"
1433	select GENERIC_IRQ_MIGRATION
1434	help
1435	  Say Y here to experiment with turning CPUs off and on.  CPUs
1436	  can be controlled through /sys/devices/system/cpu.
1437
1438# Common NUMA Features
1439config NUMA
1440	bool "NUMA Memory Allocation and Scheduler Support"
1441	select GENERIC_ARCH_NUMA
1442	select ACPI_NUMA if ACPI
1443	select OF_NUMA
1444	select HAVE_SETUP_PER_CPU_AREA
1445	select NEED_PER_CPU_EMBED_FIRST_CHUNK
1446	select NEED_PER_CPU_PAGE_FIRST_CHUNK
1447	select USE_PERCPU_NUMA_NODE_ID
1448	help
1449	  Enable NUMA (Non-Uniform Memory Access) support.
1450
1451	  The kernel will try to allocate memory used by a CPU on the
1452	  local memory of the CPU and add some more
1453	  NUMA awareness to the kernel.
1454
1455config NODES_SHIFT
1456	int "Maximum NUMA Nodes (as a power of 2)"
1457	range 1 10
1458	default "4"
1459	depends on NUMA
1460	help
1461	  Specify the maximum number of NUMA Nodes available on the target
1462	  system.  Increases memory reserved to accommodate various tables.
1463
1464source "kernel/Kconfig.hz"
1465
1466config ARCH_SPARSEMEM_ENABLE
1467	def_bool y
1468	select SPARSEMEM_VMEMMAP_ENABLE
1469	select SPARSEMEM_VMEMMAP
1470
1471config HW_PERF_EVENTS
1472	def_bool y
1473	depends on ARM_PMU
1474
1475# Supported by clang >= 7.0 or GCC >= 12.0.0
1476config CC_HAVE_SHADOW_CALL_STACK
1477	def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1478
1479config PARAVIRT
1480	bool "Enable paravirtualization code"
1481	help
1482	  This changes the kernel so it can modify itself when it is run
1483	  under a hypervisor, potentially improving performance significantly
1484	  over full virtualization.
1485
1486config PARAVIRT_TIME_ACCOUNTING
1487	bool "Paravirtual steal time accounting"
1488	select PARAVIRT
1489	help
1490	  Select this option to enable fine granularity task steal time
1491	  accounting. Time spent executing other tasks in parallel with
1492	  the current vCPU is discounted from the vCPU power. To account for
1493	  that, there can be a small performance impact.
1494
1495	  If in doubt, say N here.
1496
1497config ARCH_SUPPORTS_KEXEC
1498	def_bool PM_SLEEP_SMP
1499
1500config ARCH_SUPPORTS_KEXEC_FILE
1501	def_bool y
1502
1503config ARCH_SELECTS_KEXEC_FILE
1504	def_bool y
1505	depends on KEXEC_FILE
1506	select HAVE_IMA_KEXEC if IMA
1507
1508config ARCH_SUPPORTS_KEXEC_SIG
1509	def_bool y
1510
1511config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG
1512	def_bool y
1513
1514config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG
1515	def_bool y
1516
1517config ARCH_SUPPORTS_CRASH_DUMP
1518	def_bool y
1519
1520config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
1521	def_bool CRASH_RESERVE
1522
1523config TRANS_TABLE
1524	def_bool y
1525	depends on HIBERNATION || KEXEC_CORE
1526
1527config XEN_DOM0
1528	def_bool y
1529	depends on XEN
1530
1531config XEN
1532	bool "Xen guest support on ARM64"
1533	depends on ARM64 && OF
1534	select SWIOTLB_XEN
1535	select PARAVIRT
1536	help
1537	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1538
1539# include/linux/mmzone.h requires the following to be true:
1540#
1541#   MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1542#
1543# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1544#
1545#     | SECTION_SIZE_BITS |  PAGE_SHIFT  |  max MAX_PAGE_ORDER  |  default MAX_PAGE_ORDER |
1546# ----+-------------------+--------------+----------------------+-------------------------+
1547# 4K  |       27          |      12      |       15             |         10              |
1548# 16K |       27          |      14      |       13             |         11              |
1549# 64K |       29          |      16      |       13             |         13              |
1550config ARCH_FORCE_MAX_ORDER
1551	int
1552	default "13" if ARM64_64K_PAGES
1553	default "11" if ARM64_16K_PAGES
1554	default "10"
1555	help
1556	  The kernel page allocator limits the size of maximal physically
1557	  contiguous allocations. The limit is called MAX_PAGE_ORDER and it
1558	  defines the maximal power of two of number of pages that can be
1559	  allocated as a single contiguous block. This option allows
1560	  overriding the default setting when ability to allocate very
1561	  large blocks of physically contiguous memory is required.
1562
1563	  The maximal size of allocation cannot exceed the size of the
1564	  section, so the value of MAX_PAGE_ORDER should satisfy
1565
1566	    MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS
1567
1568	  Don't change if unsure.
1569
1570config UNMAP_KERNEL_AT_EL0
1571	bool "Unmap kernel when running in userspace (KPTI)" if EXPERT
1572	default y
1573	help
1574	  Speculation attacks against some high-performance processors can
1575	  be used to bypass MMU permission checks and leak kernel data to
1576	  userspace. This can be defended against by unmapping the kernel
1577	  when running in userspace, mapping it back in on exception entry
1578	  via a trampoline page in the vector table.
1579
1580	  If unsure, say Y.
1581
1582config MITIGATE_SPECTRE_BRANCH_HISTORY
1583	bool "Mitigate Spectre style attacks against branch history" if EXPERT
1584	default y
1585	help
1586	  Speculation attacks against some high-performance processors can
1587	  make use of branch history to influence future speculation.
1588	  When taking an exception from user-space, a sequence of branches
1589	  or a firmware call overwrites the branch history.
1590
1591config RODATA_FULL_DEFAULT_ENABLED
1592	bool "Apply r/o permissions of VM areas also to their linear aliases"
1593	default y
1594	help
1595	  Apply read-only attributes of VM areas to the linear alias of
1596	  the backing pages as well. This prevents code or read-only data
1597	  from being modified (inadvertently or intentionally) via another
1598	  mapping of the same memory page. This additional enhancement can
1599	  be turned off at runtime by passing rodata=[off|on] (and turned on
1600	  with rodata=full if this option is set to 'n')
1601
1602	  This requires the linear region to be mapped down to pages,
1603	  which may adversely affect performance in some cases.
1604
1605config ARM64_SW_TTBR0_PAN
1606	bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1607	help
1608	  Enabling this option prevents the kernel from accessing
1609	  user-space memory directly by pointing TTBR0_EL1 to a reserved
1610	  zeroed area and reserved ASID. The user access routines
1611	  restore the valid TTBR0_EL1 temporarily.
1612
1613config ARM64_TAGGED_ADDR_ABI
1614	bool "Enable the tagged user addresses syscall ABI"
1615	default y
1616	help
1617	  When this option is enabled, user applications can opt in to a
1618	  relaxed ABI via prctl() allowing tagged addresses to be passed
1619	  to system calls as pointer arguments. For details, see
1620	  Documentation/arch/arm64/tagged-address-abi.rst.
1621
1622menuconfig COMPAT
1623	bool "Kernel support for 32-bit EL0"
1624	depends on ARM64_4K_PAGES || EXPERT
1625	select HAVE_UID16
1626	select OLD_SIGSUSPEND3
1627	select COMPAT_OLD_SIGACTION
1628	help
1629	  This option enables support for a 32-bit EL0 running under a 64-bit
1630	  kernel at EL1. AArch32-specific components such as system calls,
1631	  the user helper functions, VFP support and the ptrace interface are
1632	  handled appropriately by the kernel.
1633
1634	  If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1635	  that you will only be able to execute AArch32 binaries that were compiled
1636	  with page size aligned segments.
1637
1638	  If you want to execute 32-bit userspace applications, say Y.
1639
1640if COMPAT
1641
1642config KUSER_HELPERS
1643	bool "Enable kuser helpers page for 32-bit applications"
1644	default y
1645	help
1646	  Warning: disabling this option may break 32-bit user programs.
1647
1648	  Provide kuser helpers to compat tasks. The kernel provides
1649	  helper code to userspace in read only form at a fixed location
1650	  to allow userspace to be independent of the CPU type fitted to
1651	  the system. This permits binaries to be run on ARMv4 through
1652	  to ARMv8 without modification.
1653
1654	  See Documentation/arch/arm/kernel_user_helpers.rst for details.
1655
1656	  However, the fixed address nature of these helpers can be used
1657	  by ROP (return orientated programming) authors when creating
1658	  exploits.
1659
1660	  If all of the binaries and libraries which run on your platform
1661	  are built specifically for your platform, and make no use of
1662	  these helpers, then you can turn this option off to hinder
1663	  such exploits. However, in that case, if a binary or library
1664	  relying on those helpers is run, it will not function correctly.
1665
1666	  Say N here only if you are absolutely certain that you do not
1667	  need these helpers; otherwise, the safe option is to say Y.
1668
1669config COMPAT_VDSO
1670	bool "Enable vDSO for 32-bit applications"
1671	depends on !CPU_BIG_ENDIAN
1672	depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != ""
1673	select GENERIC_COMPAT_VDSO
1674	default y
1675	help
1676	  Place in the process address space of 32-bit applications an
1677	  ELF shared object providing fast implementations of gettimeofday
1678	  and clock_gettime.
1679
1680	  You must have a 32-bit build of glibc 2.22 or later for programs
1681	  to seamlessly take advantage of this.
1682
1683config THUMB2_COMPAT_VDSO
1684	bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1685	depends on COMPAT_VDSO
1686	default y
1687	help
1688	  Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1689	  otherwise with '-marm'.
1690
1691config COMPAT_ALIGNMENT_FIXUPS
1692	bool "Fix up misaligned multi-word loads and stores in user space"
1693
1694menuconfig ARMV8_DEPRECATED
1695	bool "Emulate deprecated/obsolete ARMv8 instructions"
1696	depends on SYSCTL
1697	help
1698	  Legacy software support may require certain instructions
1699	  that have been deprecated or obsoleted in the architecture.
1700
1701	  Enable this config to enable selective emulation of these
1702	  features.
1703
1704	  If unsure, say Y
1705
1706if ARMV8_DEPRECATED
1707
1708config SWP_EMULATION
1709	bool "Emulate SWP/SWPB instructions"
1710	help
1711	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
1712	  they are always undefined. Say Y here to enable software
1713	  emulation of these instructions for userspace using LDXR/STXR.
1714	  This feature can be controlled at runtime with the abi.swp
1715	  sysctl which is disabled by default.
1716
1717	  In some older versions of glibc [<=2.8] SWP is used during futex
1718	  trylock() operations with the assumption that the code will not
1719	  be preempted. This invalid assumption may be more likely to fail
1720	  with SWP emulation enabled, leading to deadlock of the user
1721	  application.
1722
1723	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
1724	  on an external transaction monitoring block called a global
1725	  monitor to maintain update atomicity. If your system does not
1726	  implement a global monitor, this option can cause programs that
1727	  perform SWP operations to uncached memory to deadlock.
1728
1729	  If unsure, say Y
1730
1731config CP15_BARRIER_EMULATION
1732	bool "Emulate CP15 Barrier instructions"
1733	help
1734	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
1735	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1736	  strongly recommended to use the ISB, DSB, and DMB
1737	  instructions instead.
1738
1739	  Say Y here to enable software emulation of these
1740	  instructions for AArch32 userspace code. When this option is
1741	  enabled, CP15 barrier usage is traced which can help
1742	  identify software that needs updating. This feature can be
1743	  controlled at runtime with the abi.cp15_barrier sysctl.
1744
1745	  If unsure, say Y
1746
1747config SETEND_EMULATION
1748	bool "Emulate SETEND instruction"
1749	help
1750	  The SETEND instruction alters the data-endianness of the
1751	  AArch32 EL0, and is deprecated in ARMv8.
1752
1753	  Say Y here to enable software emulation of the instruction
1754	  for AArch32 userspace code. This feature can be controlled
1755	  at runtime with the abi.setend sysctl.
1756
1757	  Note: All the cpus on the system must have mixed endian support at EL0
1758	  for this feature to be enabled. If a new CPU - which doesn't support mixed
1759	  endian - is hotplugged in after this feature has been enabled, there could
1760	  be unexpected results in the applications.
1761
1762	  If unsure, say Y
1763endif # ARMV8_DEPRECATED
1764
1765endif # COMPAT
1766
1767menu "ARMv8.1 architectural features"
1768
1769config ARM64_HW_AFDBM
1770	bool "Support for hardware updates of the Access and Dirty page flags"
1771	default y
1772	help
1773	  The ARMv8.1 architecture extensions introduce support for
1774	  hardware updates of the access and dirty information in page
1775	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
1776	  capable processors, accesses to pages with PTE_AF cleared will
1777	  set this bit instead of raising an access flag fault.
1778	  Similarly, writes to read-only pages with the DBM bit set will
1779	  clear the read-only bit (AP[2]) instead of raising a
1780	  permission fault.
1781
1782	  Kernels built with this configuration option enabled continue
1783	  to work on pre-ARMv8.1 hardware and the performance impact is
1784	  minimal. If unsure, say Y.
1785
1786config ARM64_PAN
1787	bool "Enable support for Privileged Access Never (PAN)"
1788	default y
1789	help
1790	  Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1791	  prevents the kernel or hypervisor from accessing user-space (EL0)
1792	  memory directly.
1793
1794	  Choosing this option will cause any unprotected (not using
1795	  copy_to_user et al) memory access to fail with a permission fault.
1796
1797	  The feature is detected at runtime, and will remain as a 'nop'
1798	  instruction if the cpu does not implement the feature.
1799
1800config AS_HAS_LSE_ATOMICS
1801	def_bool $(as-instr,.arch_extension lse)
1802
1803config ARM64_LSE_ATOMICS
1804	bool
1805	default ARM64_USE_LSE_ATOMICS
1806	depends on AS_HAS_LSE_ATOMICS
1807
1808config ARM64_USE_LSE_ATOMICS
1809	bool "Atomic instructions"
1810	default y
1811	help
1812	  As part of the Large System Extensions, ARMv8.1 introduces new
1813	  atomic instructions that are designed specifically to scale in
1814	  very large systems.
1815
1816	  Say Y here to make use of these instructions for the in-kernel
1817	  atomic routines. This incurs a small overhead on CPUs that do
1818	  not support these instructions and requires the kernel to be
1819	  built with binutils >= 2.25 in order for the new instructions
1820	  to be used.
1821
1822endmenu # "ARMv8.1 architectural features"
1823
1824menu "ARMv8.2 architectural features"
1825
1826config AS_HAS_ARMV8_2
1827	def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1828
1829config AS_HAS_SHA3
1830	def_bool $(as-instr,.arch armv8.2-a+sha3)
1831
1832config ARM64_PMEM
1833	bool "Enable support for persistent memory"
1834	select ARCH_HAS_PMEM_API
1835	select ARCH_HAS_UACCESS_FLUSHCACHE
1836	help
1837	  Say Y to enable support for the persistent memory API based on the
1838	  ARMv8.2 DCPoP feature.
1839
1840	  The feature is detected at runtime, and the kernel will use DC CVAC
1841	  operations if DC CVAP is not supported (following the behaviour of
1842	  DC CVAP itself if the system does not define a point of persistence).
1843
1844config ARM64_RAS_EXTN
1845	bool "Enable support for RAS CPU Extensions"
1846	default y
1847	help
1848	  CPUs that support the Reliability, Availability and Serviceability
1849	  (RAS) Extensions, part of ARMv8.2 are able to track faults and
1850	  errors, classify them and report them to software.
1851
1852	  On CPUs with these extensions system software can use additional
1853	  barriers to determine if faults are pending and read the
1854	  classification from a new set of registers.
1855
1856	  Selecting this feature will allow the kernel to use these barriers
1857	  and access the new registers if the system supports the extension.
1858	  Platform RAS features may additionally depend on firmware support.
1859
1860config ARM64_CNP
1861	bool "Enable support for Common Not Private (CNP) translations"
1862	default y
1863	depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1864	help
1865	  Common Not Private (CNP) allows translation table entries to
1866	  be shared between different PEs in the same inner shareable
1867	  domain, so the hardware can use this fact to optimise the
1868	  caching of such entries in the TLB.
1869
1870	  Selecting this option allows the CNP feature to be detected
1871	  at runtime, and does not affect PEs that do not implement
1872	  this feature.
1873
1874endmenu # "ARMv8.2 architectural features"
1875
1876menu "ARMv8.3 architectural features"
1877
1878config ARM64_PTR_AUTH
1879	bool "Enable support for pointer authentication"
1880	default y
1881	help
1882	  Pointer authentication (part of the ARMv8.3 Extensions) provides
1883	  instructions for signing and authenticating pointers against secret
1884	  keys, which can be used to mitigate Return Oriented Programming (ROP)
1885	  and other attacks.
1886
1887	  This option enables these instructions at EL0 (i.e. for userspace).
1888	  Choosing this option will cause the kernel to initialise secret keys
1889	  for each process at exec() time, with these keys being
1890	  context-switched along with the process.
1891
1892	  The feature is detected at runtime. If the feature is not present in
1893	  hardware it will not be advertised to userspace/KVM guest nor will it
1894	  be enabled.
1895
1896	  If the feature is present on the boot CPU but not on a late CPU, then
1897	  the late CPU will be parked. Also, if the boot CPU does not have
1898	  address auth and the late CPU has then the late CPU will still boot
1899	  but with the feature disabled. On such a system, this option should
1900	  not be selected.
1901
1902config ARM64_PTR_AUTH_KERNEL
1903	bool "Use pointer authentication for kernel"
1904	default y
1905	depends on ARM64_PTR_AUTH
1906	depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3
1907	# Modern compilers insert a .note.gnu.property section note for PAC
1908	# which is only understood by binutils starting with version 2.33.1.
1909	depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100)
1910	depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE
1911	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
1912	help
1913	  If the compiler supports the -mbranch-protection or
1914	  -msign-return-address flag (e.g. GCC 7 or later), then this option
1915	  will cause the kernel itself to be compiled with return address
1916	  protection. In this case, and if the target hardware is known to
1917	  support pointer authentication, then CONFIG_STACKPROTECTOR can be
1918	  disabled with minimal loss of protection.
1919
1920	  This feature works with FUNCTION_GRAPH_TRACER option only if
1921	  DYNAMIC_FTRACE_WITH_ARGS is enabled.
1922
1923config CC_HAS_BRANCH_PROT_PAC_RET
1924	# GCC 9 or later, clang 8 or later
1925	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1926
1927config CC_HAS_SIGN_RETURN_ADDRESS
1928	# GCC 7, 8
1929	def_bool $(cc-option,-msign-return-address=all)
1930
1931config AS_HAS_ARMV8_3
1932	def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1933
1934config AS_HAS_CFI_NEGATE_RA_STATE
1935	def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1936
1937config AS_HAS_LDAPR
1938	def_bool $(as-instr,.arch_extension rcpc)
1939
1940endmenu # "ARMv8.3 architectural features"
1941
1942menu "ARMv8.4 architectural features"
1943
1944config ARM64_AMU_EXTN
1945	bool "Enable support for the Activity Monitors Unit CPU extension"
1946	default y
1947	help
1948	  The activity monitors extension is an optional extension introduced
1949	  by the ARMv8.4 CPU architecture. This enables support for version 1
1950	  of the activity monitors architecture, AMUv1.
1951
1952	  To enable the use of this extension on CPUs that implement it, say Y.
1953
1954	  Note that for architectural reasons, firmware _must_ implement AMU
1955	  support when running on CPUs that present the activity monitors
1956	  extension. The required support is present in:
1957	    * Version 1.5 and later of the ARM Trusted Firmware
1958
1959	  For kernels that have this configuration enabled but boot with broken
1960	  firmware, you may need to say N here until the firmware is fixed.
1961	  Otherwise you may experience firmware panics or lockups when
1962	  accessing the counter registers. Even if you are not observing these
1963	  symptoms, the values returned by the register reads might not
1964	  correctly reflect reality. Most commonly, the value read will be 0,
1965	  indicating that the counter is not enabled.
1966
1967config AS_HAS_ARMV8_4
1968	def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1969
1970config ARM64_TLB_RANGE
1971	bool "Enable support for tlbi range feature"
1972	default y
1973	depends on AS_HAS_ARMV8_4
1974	help
1975	  ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1976	  range of input addresses.
1977
1978	  The feature introduces new assembly instructions, and they were
1979	  support when binutils >= 2.30.
1980
1981endmenu # "ARMv8.4 architectural features"
1982
1983menu "ARMv8.5 architectural features"
1984
1985config AS_HAS_ARMV8_5
1986	def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1987
1988config ARM64_BTI
1989	bool "Branch Target Identification support"
1990	default y
1991	help
1992	  Branch Target Identification (part of the ARMv8.5 Extensions)
1993	  provides a mechanism to limit the set of locations to which computed
1994	  branch instructions such as BR or BLR can jump.
1995
1996	  To make use of BTI on CPUs that support it, say Y.
1997
1998	  BTI is intended to provide complementary protection to other control
1999	  flow integrity protection mechanisms, such as the Pointer
2000	  authentication mechanism provided as part of the ARMv8.3 Extensions.
2001	  For this reason, it does not make sense to enable this option without
2002	  also enabling support for pointer authentication.  Thus, when
2003	  enabling this option you should also select ARM64_PTR_AUTH=y.
2004
2005	  Userspace binaries must also be specifically compiled to make use of
2006	  this mechanism.  If you say N here or the hardware does not support
2007	  BTI, such binaries can still run, but you get no additional
2008	  enforcement of branch destinations.
2009
2010config ARM64_BTI_KERNEL
2011	bool "Use Branch Target Identification for kernel"
2012	default y
2013	depends on ARM64_BTI
2014	depends on ARM64_PTR_AUTH_KERNEL
2015	depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
2016	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
2017	depends on !CC_IS_GCC || GCC_VERSION >= 100100
2018	# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
2019	depends on !CC_IS_GCC
2020	depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS)
2021	help
2022	  Build the kernel with Branch Target Identification annotations
2023	  and enable enforcement of this for kernel code. When this option
2024	  is enabled and the system supports BTI all kernel code including
2025	  modular code must have BTI enabled.
2026
2027config CC_HAS_BRANCH_PROT_PAC_RET_BTI
2028	# GCC 9 or later, clang 8 or later
2029	def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2030
2031config ARM64_E0PD
2032	bool "Enable support for E0PD"
2033	default y
2034	help
2035	  E0PD (part of the ARMv8.5 extensions) allows us to ensure
2036	  that EL0 accesses made via TTBR1 always fault in constant time,
2037	  providing similar benefits to KASLR as those provided by KPTI, but
2038	  with lower overhead and without disrupting legitimate access to
2039	  kernel memory such as SPE.
2040
2041	  This option enables E0PD for TTBR1 where available.
2042
2043config ARM64_AS_HAS_MTE
2044	# Initial support for MTE went in binutils 2.32.0, checked with
2045	# ".arch armv8.5-a+memtag" below. However, this was incomplete
2046	# as a late addition to the final architecture spec (LDGM/STGM)
2047	# is only supported in the newer 2.32.x and 2.33 binutils
2048	# versions, hence the extra "stgm" instruction check below.
2049	def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2050
2051config ARM64_MTE
2052	bool "Memory Tagging Extension support"
2053	default y
2054	depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI
2055	depends on AS_HAS_ARMV8_5
2056	depends on AS_HAS_LSE_ATOMICS
2057	# Required for tag checking in the uaccess routines
2058	depends on ARM64_PAN
2059	select ARCH_HAS_SUBPAGE_FAULTS
2060	select ARCH_USES_HIGH_VMA_FLAGS
2061	select ARCH_USES_PG_ARCH_X
2062	help
2063	  Memory Tagging (part of the ARMv8.5 Extensions) provides
2064	  architectural support for run-time, always-on detection of
2065	  various classes of memory error to aid with software debugging
2066	  to eliminate vulnerabilities arising from memory-unsafe
2067	  languages.
2068
2069	  This option enables the support for the Memory Tagging
2070	  Extension at EL0 (i.e. for userspace).
2071
2072	  Selecting this option allows the feature to be detected at
2073	  runtime. Any secondary CPU not implementing this feature will
2074	  not be allowed a late bring-up.
2075
2076	  Userspace binaries that want to use this feature must
2077	  explicitly opt in. The mechanism for the userspace is
2078	  described in:
2079
2080	  Documentation/arch/arm64/memory-tagging-extension.rst.
2081
2082endmenu # "ARMv8.5 architectural features"
2083
2084menu "ARMv8.7 architectural features"
2085
2086config ARM64_EPAN
2087	bool "Enable support for Enhanced Privileged Access Never (EPAN)"
2088	default y
2089	depends on ARM64_PAN
2090	help
2091	  Enhanced Privileged Access Never (EPAN) allows Privileged
2092	  Access Never to be used with Execute-only mappings.
2093
2094	  The feature is detected at runtime, and will remain disabled
2095	  if the cpu does not implement the feature.
2096endmenu # "ARMv8.7 architectural features"
2097
2098config ARM64_SVE
2099	bool "ARM Scalable Vector Extension support"
2100	default y
2101	help
2102	  The Scalable Vector Extension (SVE) is an extension to the AArch64
2103	  execution state which complements and extends the SIMD functionality
2104	  of the base architecture to support much larger vectors and to enable
2105	  additional vectorisation opportunities.
2106
2107	  To enable use of this extension on CPUs that implement it, say Y.
2108
2109	  On CPUs that support the SVE2 extensions, this option will enable
2110	  those too.
2111
2112	  Note that for architectural reasons, firmware _must_ implement SVE
2113	  support when running on SVE capable hardware.  The required support
2114	  is present in:
2115
2116	    * version 1.5 and later of the ARM Trusted Firmware
2117	    * the AArch64 boot wrapper since commit 5e1261e08abf
2118	      ("bootwrapper: SVE: Enable SVE for EL2 and below").
2119
2120	  For other firmware implementations, consult the firmware documentation
2121	  or vendor.
2122
2123	  If you need the kernel to boot on SVE-capable hardware with broken
2124	  firmware, you may need to say N here until you get your firmware
2125	  fixed.  Otherwise, you may experience firmware panics or lockups when
2126	  booting the kernel.  If unsure and you are not observing these
2127	  symptoms, you should assume that it is safe to say Y.
2128
2129config ARM64_SME
2130	bool "ARM Scalable Matrix Extension support"
2131	default y
2132	depends on ARM64_SVE
2133	help
2134	  The Scalable Matrix Extension (SME) is an extension to the AArch64
2135	  execution state which utilises a substantial subset of the SVE
2136	  instruction set, together with the addition of new architectural
2137	  register state capable of holding two dimensional matrix tiles to
2138	  enable various matrix operations.
2139
2140config ARM64_PSEUDO_NMI
2141	bool "Support for NMI-like interrupts"
2142	select ARM_GIC_V3
2143	help
2144	  Adds support for mimicking Non-Maskable Interrupts through the use of
2145	  GIC interrupt priority. This support requires version 3 or later of
2146	  ARM GIC.
2147
2148	  This high priority configuration for interrupts needs to be
2149	  explicitly enabled by setting the kernel parameter
2150	  "irqchip.gicv3_pseudo_nmi" to 1.
2151
2152	  If unsure, say N
2153
2154if ARM64_PSEUDO_NMI
2155config ARM64_DEBUG_PRIORITY_MASKING
2156	bool "Debug interrupt priority masking"
2157	help
2158	  This adds runtime checks to functions enabling/disabling
2159	  interrupts when using priority masking. The additional checks verify
2160	  the validity of ICC_PMR_EL1 when calling concerned functions.
2161
2162	  If unsure, say N
2163endif # ARM64_PSEUDO_NMI
2164
2165config RELOCATABLE
2166	bool "Build a relocatable kernel image" if EXPERT
2167	select ARCH_HAS_RELR
2168	default y
2169	help
2170	  This builds the kernel as a Position Independent Executable (PIE),
2171	  which retains all relocation metadata required to relocate the
2172	  kernel binary at runtime to a different virtual address than the
2173	  address it was linked at.
2174	  Since AArch64 uses the RELA relocation format, this requires a
2175	  relocation pass at runtime even if the kernel is loaded at the
2176	  same address it was linked at.
2177
2178config RANDOMIZE_BASE
2179	bool "Randomize the address of the kernel image"
2180	select RELOCATABLE
2181	help
2182	  Randomizes the virtual address at which the kernel image is
2183	  loaded, as a security feature that deters exploit attempts
2184	  relying on knowledge of the location of kernel internals.
2185
2186	  It is the bootloader's job to provide entropy, by passing a
2187	  random u64 value in /chosen/kaslr-seed at kernel entry.
2188
2189	  When booting via the UEFI stub, it will invoke the firmware's
2190	  EFI_RNG_PROTOCOL implementation (if available) to supply entropy
2191	  to the kernel proper. In addition, it will randomise the physical
2192	  location of the kernel Image as well.
2193
2194	  If unsure, say N.
2195
2196config RANDOMIZE_MODULE_REGION_FULL
2197	bool "Randomize the module region over a 2 GB range"
2198	depends on RANDOMIZE_BASE
2199	default y
2200	help
2201	  Randomizes the location of the module region inside a 2 GB window
2202	  covering the core kernel. This way, it is less likely for modules
2203	  to leak information about the location of core kernel data structures
2204	  but it does imply that function calls between modules and the core
2205	  kernel will need to be resolved via veneers in the module PLT.
2206
2207	  When this option is not set, the module region will be randomized over
2208	  a limited range that contains the [_stext, _etext] interval of the
2209	  core kernel, so branch relocations are almost always in range unless
2210	  the region is exhausted. In this particular case of region
2211	  exhaustion, modules might be able to fall back to a larger 2GB area.
2212
2213config CC_HAVE_STACKPROTECTOR_SYSREG
2214	def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0)
2215
2216config STACKPROTECTOR_PER_TASK
2217	def_bool y
2218	depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG
2219
2220config UNWIND_PATCH_PAC_INTO_SCS
2221	bool "Enable shadow call stack dynamically using code patching"
2222	# needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated
2223	depends on CC_IS_CLANG && CLANG_VERSION >= 150000
2224	depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET
2225	depends on SHADOW_CALL_STACK
2226	select UNWIND_TABLES
2227	select DYNAMIC_SCS
2228
2229config ARM64_CONTPTE
2230	bool "Contiguous PTE mappings for user memory" if EXPERT
2231	depends on TRANSPARENT_HUGEPAGE
2232	default y
2233	help
2234	  When enabled, user mappings are configured using the PTE contiguous
2235	  bit, for any mappings that meet the size and alignment requirements.
2236	  This reduces TLB pressure and improves performance.
2237
2238endmenu # "Kernel Features"
2239
2240menu "Boot options"
2241
2242config ARM64_ACPI_PARKING_PROTOCOL
2243	bool "Enable support for the ARM64 ACPI parking protocol"
2244	depends on ACPI
2245	help
2246	  Enable support for the ARM64 ACPI parking protocol. If disabled
2247	  the kernel will not allow booting through the ARM64 ACPI parking
2248	  protocol even if the corresponding data is present in the ACPI
2249	  MADT table.
2250
2251config CMDLINE
2252	string "Default kernel command string"
2253	default ""
2254	help
2255	  Provide a set of default command-line options at build time by
2256	  entering them here. As a minimum, you should specify the the
2257	  root device (e.g. root=/dev/nfs).
2258
2259choice
2260	prompt "Kernel command line type" if CMDLINE != ""
2261	default CMDLINE_FROM_BOOTLOADER
2262	help
2263	  Choose how the kernel will handle the provided default kernel
2264	  command line string.
2265
2266config CMDLINE_FROM_BOOTLOADER
2267	bool "Use bootloader kernel arguments if available"
2268	help
2269	  Uses the command-line options passed by the boot loader. If
2270	  the boot loader doesn't provide any, the default kernel command
2271	  string provided in CMDLINE will be used.
2272
2273config CMDLINE_FORCE
2274	bool "Always use the default kernel command string"
2275	help
2276	  Always use the default kernel command string, even if the boot
2277	  loader passes other arguments to the kernel.
2278	  This is useful if you cannot or don't want to change the
2279	  command-line options your boot loader passes to the kernel.
2280
2281endchoice
2282
2283config EFI_STUB
2284	bool
2285
2286config EFI
2287	bool "UEFI runtime support"
2288	depends on OF && !CPU_BIG_ENDIAN
2289	depends on KERNEL_MODE_NEON
2290	select ARCH_SUPPORTS_ACPI
2291	select LIBFDT
2292	select UCS2_STRING
2293	select EFI_PARAMS_FROM_FDT
2294	select EFI_RUNTIME_WRAPPERS
2295	select EFI_STUB
2296	select EFI_GENERIC_STUB
2297	imply IMA_SECURE_AND_OR_TRUSTED_BOOT
2298	default y
2299	help
2300	  This option provides support for runtime services provided
2301	  by UEFI firmware (such as non-volatile variables, realtime
2302	  clock, and platform reset). A UEFI stub is also provided to
2303	  allow the kernel to be booted as an EFI application. This
2304	  is only useful on systems that have UEFI firmware.
2305
2306config DMI
2307	bool "Enable support for SMBIOS (DMI) tables"
2308	depends on EFI
2309	default y
2310	help
2311	  This enables SMBIOS/DMI feature for systems.
2312
2313	  This option is only useful on systems that have UEFI firmware.
2314	  However, even with this option, the resultant kernel should
2315	  continue to boot on existing non-UEFI platforms.
2316
2317endmenu # "Boot options"
2318
2319menu "Power management options"
2320
2321source "kernel/power/Kconfig"
2322
2323config ARCH_HIBERNATION_POSSIBLE
2324	def_bool y
2325	depends on CPU_PM
2326
2327config ARCH_HIBERNATION_HEADER
2328	def_bool y
2329	depends on HIBERNATION
2330
2331config ARCH_SUSPEND_POSSIBLE
2332	def_bool y
2333
2334endmenu # "Power management options"
2335
2336menu "CPU Power Management"
2337
2338source "drivers/cpuidle/Kconfig"
2339
2340source "drivers/cpufreq/Kconfig"
2341
2342endmenu # "CPU Power Management"
2343
2344source "drivers/acpi/Kconfig"
2345
2346source "arch/arm64/kvm/Kconfig"
2347
2348