1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 6 select ARCH_HAS_DEVMEM_IS_ALLOWED 7 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE 8 select ARCH_HAS_ELF_RANDOMIZE 9 select ARCH_HAS_GCOV_PROFILE_ALL 10 select ARCH_HAS_SG_CHAIN 11 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 12 select ARCH_USE_CMPXCHG_LOCKREF 13 select ARCH_SUPPORTS_ATOMIC_RMW 14 select ARCH_SUPPORTS_NUMA_BALANCING 15 select ARCH_WANT_OPTIONAL_GPIOLIB 16 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 17 select ARCH_WANT_FRAME_POINTERS 18 select ARCH_HAS_UBSAN_SANITIZE_ALL 19 select ARM_AMBA 20 select ARM_ARCH_TIMER 21 select ARM_GIC 22 select AUDIT_ARCH_COMPAT_GENERIC 23 select ARM_GIC_V2M if PCI_MSI 24 select ARM_GIC_V3 25 select ARM_GIC_V3_ITS if PCI_MSI 26 select ARM_PSCI_FW 27 select BUILDTIME_EXTABLE_SORT 28 select CLONE_BACKWARDS 29 select COMMON_CLK 30 select CPU_PM if (SUSPEND || CPU_IDLE) 31 select DCACHE_WORD_ACCESS 32 select EDAC_SUPPORT 33 select FRAME_POINTER 34 select GENERIC_ALLOCATOR 35 select GENERIC_CLOCKEVENTS 36 select GENERIC_CLOCKEVENTS_BROADCAST 37 select GENERIC_CPU_AUTOPROBE 38 select GENERIC_EARLY_IOREMAP 39 select GENERIC_IDLE_POLL_SETUP 40 select GENERIC_IRQ_PROBE 41 select GENERIC_IRQ_SHOW 42 select GENERIC_IRQ_SHOW_LEVEL 43 select GENERIC_PCI_IOMAP 44 select GENERIC_SCHED_CLOCK 45 select GENERIC_SMP_IDLE_THREAD 46 select GENERIC_STRNCPY_FROM_USER 47 select GENERIC_STRNLEN_USER 48 select GENERIC_TIME_VSYSCALL 49 select HANDLE_DOMAIN_IRQ 50 select HARDIRQS_SW_RESEND 51 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 52 select HAVE_ARCH_AUDITSYSCALL 53 select HAVE_ARCH_BITREVERSE 54 select HAVE_ARCH_HUGE_VMAP 55 select HAVE_ARCH_JUMP_LABEL 56 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 57 select HAVE_ARCH_KGDB 58 select HAVE_ARCH_MMAP_RND_BITS 59 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 60 select HAVE_ARCH_SECCOMP_FILTER 61 select HAVE_ARCH_TRACEHOOK 62 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 63 select HAVE_ARM_SMCCC 64 select HAVE_EBPF_JIT 65 select HAVE_C_RECORDMCOUNT 66 select HAVE_CC_STACKPROTECTOR 67 select HAVE_CMPXCHG_DOUBLE 68 select HAVE_CMPXCHG_LOCAL 69 select HAVE_CONTEXT_TRACKING 70 select HAVE_DEBUG_BUGVERBOSE 71 select HAVE_DEBUG_KMEMLEAK 72 select HAVE_DMA_API_DEBUG 73 select HAVE_DMA_CONTIGUOUS 74 select HAVE_DYNAMIC_FTRACE 75 select HAVE_EFFICIENT_UNALIGNED_ACCESS 76 select HAVE_FTRACE_MCOUNT_RECORD 77 select HAVE_FUNCTION_TRACER 78 select HAVE_FUNCTION_GRAPH_TRACER 79 select HAVE_GENERIC_DMA_COHERENT 80 select HAVE_HW_BREAKPOINT if PERF_EVENTS 81 select HAVE_IRQ_TIME_ACCOUNTING 82 select HAVE_MEMBLOCK 83 select HAVE_MEMBLOCK_NODE_MAP if NUMA 84 select HAVE_PATA_PLATFORM 85 select HAVE_PERF_EVENTS 86 select HAVE_PERF_REGS 87 select HAVE_PERF_USER_STACK_DUMP 88 select HAVE_RCU_TABLE_FREE 89 select HAVE_SYSCALL_TRACEPOINTS 90 select IOMMU_DMA if IOMMU_SUPPORT 91 select IRQ_DOMAIN 92 select IRQ_FORCED_THREADING 93 select MODULES_USE_ELF_RELA 94 select NO_BOOTMEM 95 select OF 96 select OF_EARLY_FLATTREE 97 select OF_NUMA if NUMA && OF 98 select OF_RESERVED_MEM 99 select PERF_USE_VMALLOC 100 select POWER_RESET 101 select POWER_SUPPLY 102 select SPARSE_IRQ 103 select SYSCTL_EXCEPTION_TRACE 104 help 105 ARM 64-bit (AArch64) Linux support. 106 107config 64BIT 108 def_bool y 109 110config ARCH_PHYS_ADDR_T_64BIT 111 def_bool y 112 113config MMU 114 def_bool y 115 116config ARM64_PAGE_SHIFT 117 int 118 default 16 if ARM64_64K_PAGES 119 default 14 if ARM64_16K_PAGES 120 default 12 121 122config ARM64_CONT_SHIFT 123 int 124 default 5 if ARM64_64K_PAGES 125 default 7 if ARM64_16K_PAGES 126 default 4 127 128config ARCH_MMAP_RND_BITS_MIN 129 default 14 if ARM64_64K_PAGES 130 default 16 if ARM64_16K_PAGES 131 default 18 132 133# max bits determined by the following formula: 134# VA_BITS - PAGE_SHIFT - 3 135config ARCH_MMAP_RND_BITS_MAX 136 default 19 if ARM64_VA_BITS=36 137 default 24 if ARM64_VA_BITS=39 138 default 27 if ARM64_VA_BITS=42 139 default 30 if ARM64_VA_BITS=47 140 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 141 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 142 default 33 if ARM64_VA_BITS=48 143 default 14 if ARM64_64K_PAGES 144 default 16 if ARM64_16K_PAGES 145 default 18 146 147config ARCH_MMAP_RND_COMPAT_BITS_MIN 148 default 7 if ARM64_64K_PAGES 149 default 9 if ARM64_16K_PAGES 150 default 11 151 152config ARCH_MMAP_RND_COMPAT_BITS_MAX 153 default 16 154 155config NO_IOPORT_MAP 156 def_bool y if !PCI 157 158config STACKTRACE_SUPPORT 159 def_bool y 160 161config ILLEGAL_POINTER_VALUE 162 hex 163 default 0xdead000000000000 164 165config LOCKDEP_SUPPORT 166 def_bool y 167 168config TRACE_IRQFLAGS_SUPPORT 169 def_bool y 170 171config RWSEM_XCHGADD_ALGORITHM 172 def_bool y 173 174config GENERIC_BUG 175 def_bool y 176 depends on BUG 177 178config GENERIC_BUG_RELATIVE_POINTERS 179 def_bool y 180 depends on GENERIC_BUG 181 182config GENERIC_HWEIGHT 183 def_bool y 184 185config GENERIC_CSUM 186 def_bool y 187 188config GENERIC_CALIBRATE_DELAY 189 def_bool y 190 191config ZONE_DMA 192 def_bool y 193 194config HAVE_GENERIC_RCU_GUP 195 def_bool y 196 197config ARCH_DMA_ADDR_T_64BIT 198 def_bool y 199 200config NEED_DMA_MAP_STATE 201 def_bool y 202 203config NEED_SG_DMA_LENGTH 204 def_bool y 205 206config SMP 207 def_bool y 208 209config SWIOTLB 210 def_bool y 211 212config IOMMU_HELPER 213 def_bool SWIOTLB 214 215config KERNEL_MODE_NEON 216 def_bool y 217 218config FIX_EARLYCON_MEM 219 def_bool y 220 221config PGTABLE_LEVELS 222 int 223 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 224 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 225 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 226 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 227 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 228 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 229 230source "init/Kconfig" 231 232source "kernel/Kconfig.freezer" 233 234source "arch/arm64/Kconfig.platforms" 235 236menu "Bus support" 237 238config PCI 239 bool "PCI support" 240 help 241 This feature enables support for PCI bus system. If you say Y 242 here, the kernel will include drivers and infrastructure code 243 to support PCI bus devices. 244 245config PCI_DOMAINS 246 def_bool PCI 247 248config PCI_DOMAINS_GENERIC 249 def_bool PCI 250 251config PCI_SYSCALL 252 def_bool PCI 253 254source "drivers/pci/Kconfig" 255 256endmenu 257 258menu "Kernel Features" 259 260menu "ARM errata workarounds via the alternatives framework" 261 262config ARM64_ERRATUM_826319 263 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 264 default y 265 help 266 This option adds an alternative code sequence to work around ARM 267 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 268 AXI master interface and an L2 cache. 269 270 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 271 and is unable to accept a certain write via this interface, it will 272 not progress on read data presented on the read data channel and the 273 system can deadlock. 274 275 The workaround promotes data cache clean instructions to 276 data cache clean-and-invalidate. 277 Please note that this does not necessarily enable the workaround, 278 as it depends on the alternative framework, which will only patch 279 the kernel if an affected CPU is detected. 280 281 If unsure, say Y. 282 283config ARM64_ERRATUM_827319 284 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 285 default y 286 help 287 This option adds an alternative code sequence to work around ARM 288 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 289 master interface and an L2 cache. 290 291 Under certain conditions this erratum can cause a clean line eviction 292 to occur at the same time as another transaction to the same address 293 on the AMBA 5 CHI interface, which can cause data corruption if the 294 interconnect reorders the two transactions. 295 296 The workaround promotes data cache clean instructions to 297 data cache clean-and-invalidate. 298 Please note that this does not necessarily enable the workaround, 299 as it depends on the alternative framework, which will only patch 300 the kernel if an affected CPU is detected. 301 302 If unsure, say Y. 303 304config ARM64_ERRATUM_824069 305 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 306 default y 307 help 308 This option adds an alternative code sequence to work around ARM 309 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 310 to a coherent interconnect. 311 312 If a Cortex-A53 processor is executing a store or prefetch for 313 write instruction at the same time as a processor in another 314 cluster is executing a cache maintenance operation to the same 315 address, then this erratum might cause a clean cache line to be 316 incorrectly marked as dirty. 317 318 The workaround promotes data cache clean instructions to 319 data cache clean-and-invalidate. 320 Please note that this option does not necessarily enable the 321 workaround, as it depends on the alternative framework, which will 322 only patch the kernel if an affected CPU is detected. 323 324 If unsure, say Y. 325 326config ARM64_ERRATUM_819472 327 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 328 default y 329 help 330 This option adds an alternative code sequence to work around ARM 331 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 332 present when it is connected to a coherent interconnect. 333 334 If the processor is executing a load and store exclusive sequence at 335 the same time as a processor in another cluster is executing a cache 336 maintenance operation to the same address, then this erratum might 337 cause data corruption. 338 339 The workaround promotes data cache clean instructions to 340 data cache clean-and-invalidate. 341 Please note that this does not necessarily enable the workaround, 342 as it depends on the alternative framework, which will only patch 343 the kernel if an affected CPU is detected. 344 345 If unsure, say Y. 346 347config ARM64_ERRATUM_832075 348 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 349 default y 350 help 351 This option adds an alternative code sequence to work around ARM 352 erratum 832075 on Cortex-A57 parts up to r1p2. 353 354 Affected Cortex-A57 parts might deadlock when exclusive load/store 355 instructions to Write-Back memory are mixed with Device loads. 356 357 The workaround is to promote device loads to use Load-Acquire 358 semantics. 359 Please note that this does not necessarily enable the workaround, 360 as it depends on the alternative framework, which will only patch 361 the kernel if an affected CPU is detected. 362 363 If unsure, say Y. 364 365config ARM64_ERRATUM_834220 366 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 367 depends on KVM 368 default y 369 help 370 This option adds an alternative code sequence to work around ARM 371 erratum 834220 on Cortex-A57 parts up to r1p2. 372 373 Affected Cortex-A57 parts might report a Stage 2 translation 374 fault as the result of a Stage 1 fault for load crossing a 375 page boundary when there is a permission or device memory 376 alignment fault at Stage 1 and a translation fault at Stage 2. 377 378 The workaround is to verify that the Stage 1 translation 379 doesn't generate a fault before handling the Stage 2 fault. 380 Please note that this does not necessarily enable the workaround, 381 as it depends on the alternative framework, which will only patch 382 the kernel if an affected CPU is detected. 383 384 If unsure, say Y. 385 386config ARM64_ERRATUM_845719 387 bool "Cortex-A53: 845719: a load might read incorrect data" 388 depends on COMPAT 389 default y 390 help 391 This option adds an alternative code sequence to work around ARM 392 erratum 845719 on Cortex-A53 parts up to r0p4. 393 394 When running a compat (AArch32) userspace on an affected Cortex-A53 395 part, a load at EL0 from a virtual address that matches the bottom 32 396 bits of the virtual address used by a recent load at (AArch64) EL1 397 might return incorrect data. 398 399 The workaround is to write the contextidr_el1 register on exception 400 return to a 32-bit task. 401 Please note that this does not necessarily enable the workaround, 402 as it depends on the alternative framework, which will only patch 403 the kernel if an affected CPU is detected. 404 405 If unsure, say Y. 406 407config ARM64_ERRATUM_843419 408 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 409 depends on MODULES 410 default y 411 select ARM64_MODULE_CMODEL_LARGE 412 help 413 This option builds kernel modules using the large memory model in 414 order to avoid the use of the ADRP instruction, which can cause 415 a subsequent memory access to use an incorrect address on Cortex-A53 416 parts up to r0p4. 417 418 Note that the kernel itself must be linked with a version of ld 419 which fixes potentially affected ADRP instructions through the 420 use of veneers. 421 422 If unsure, say Y. 423 424config CAVIUM_ERRATUM_22375 425 bool "Cavium erratum 22375, 24313" 426 default y 427 help 428 Enable workaround for erratum 22375, 24313. 429 430 This implements two gicv3-its errata workarounds for ThunderX. Both 431 with small impact affecting only ITS table allocation. 432 433 erratum 22375: only alloc 8MB table size 434 erratum 24313: ignore memory access type 435 436 The fixes are in ITS initialization and basically ignore memory access 437 type and table size provided by the TYPER and BASER registers. 438 439 If unsure, say Y. 440 441config CAVIUM_ERRATUM_23144 442 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 443 depends on NUMA 444 default y 445 help 446 ITS SYNC command hang for cross node io and collections/cpu mapping. 447 448 If unsure, say Y. 449 450config CAVIUM_ERRATUM_23154 451 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 452 default y 453 help 454 The gicv3 of ThunderX requires a modified version for 455 reading the IAR status to ensure data synchronization 456 (access to icc_iar1_el1 is not sync'ed before and after). 457 458 If unsure, say Y. 459 460config CAVIUM_ERRATUM_27456 461 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 462 default y 463 help 464 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 465 instructions may cause the icache to become corrupted if it 466 contains data for a non-current ASID. The fix is to 467 invalidate the icache when changing the mm context. 468 469 If unsure, say Y. 470 471endmenu 472 473 474choice 475 prompt "Page size" 476 default ARM64_4K_PAGES 477 help 478 Page size (translation granule) configuration. 479 480config ARM64_4K_PAGES 481 bool "4KB" 482 help 483 This feature enables 4KB pages support. 484 485config ARM64_16K_PAGES 486 bool "16KB" 487 help 488 The system will use 16KB pages support. AArch32 emulation 489 requires applications compiled with 16K (or a multiple of 16K) 490 aligned segments. 491 492config ARM64_64K_PAGES 493 bool "64KB" 494 help 495 This feature enables 64KB pages support (4KB by default) 496 allowing only two levels of page tables and faster TLB 497 look-up. AArch32 emulation requires applications compiled 498 with 64K aligned segments. 499 500endchoice 501 502choice 503 prompt "Virtual address space size" 504 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 505 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 506 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 507 help 508 Allows choosing one of multiple possible virtual address 509 space sizes. The level of translation table is determined by 510 a combination of page size and virtual address space size. 511 512config ARM64_VA_BITS_36 513 bool "36-bit" if EXPERT 514 depends on ARM64_16K_PAGES 515 516config ARM64_VA_BITS_39 517 bool "39-bit" 518 depends on ARM64_4K_PAGES 519 520config ARM64_VA_BITS_42 521 bool "42-bit" 522 depends on ARM64_64K_PAGES 523 524config ARM64_VA_BITS_47 525 bool "47-bit" 526 depends on ARM64_16K_PAGES 527 528config ARM64_VA_BITS_48 529 bool "48-bit" 530 531endchoice 532 533config ARM64_VA_BITS 534 int 535 default 36 if ARM64_VA_BITS_36 536 default 39 if ARM64_VA_BITS_39 537 default 42 if ARM64_VA_BITS_42 538 default 47 if ARM64_VA_BITS_47 539 default 48 if ARM64_VA_BITS_48 540 541config CPU_BIG_ENDIAN 542 bool "Build big-endian kernel" 543 help 544 Say Y if you plan on running a kernel in big-endian mode. 545 546config SCHED_MC 547 bool "Multi-core scheduler support" 548 help 549 Multi-core scheduler support improves the CPU scheduler's decision 550 making when dealing with multi-core CPU chips at a cost of slightly 551 increased overhead in some places. If unsure say N here. 552 553config SCHED_SMT 554 bool "SMT scheduler support" 555 help 556 Improves the CPU scheduler's decision making when dealing with 557 MultiThreading at a cost of slightly increased overhead in some 558 places. If unsure say N here. 559 560config NR_CPUS 561 int "Maximum number of CPUs (2-4096)" 562 range 2 4096 563 # These have to remain sorted largest to smallest 564 default "64" 565 566config HOTPLUG_CPU 567 bool "Support for hot-pluggable CPUs" 568 select GENERIC_IRQ_MIGRATION 569 help 570 Say Y here to experiment with turning CPUs off and on. CPUs 571 can be controlled through /sys/devices/system/cpu. 572 573# Common NUMA Features 574config NUMA 575 bool "Numa Memory Allocation and Scheduler Support" 576 depends on SMP 577 help 578 Enable NUMA (Non Uniform Memory Access) support. 579 580 The kernel will try to allocate memory used by a CPU on the 581 local memory of the CPU and add some more 582 NUMA awareness to the kernel. 583 584config NODES_SHIFT 585 int "Maximum NUMA Nodes (as a power of 2)" 586 range 1 10 587 default "2" 588 depends on NEED_MULTIPLE_NODES 589 help 590 Specify the maximum number of NUMA Nodes available on the target 591 system. Increases memory reserved to accommodate various tables. 592 593config USE_PERCPU_NUMA_NODE_ID 594 def_bool y 595 depends on NUMA 596 597source kernel/Kconfig.preempt 598source kernel/Kconfig.hz 599 600config ARCH_SUPPORTS_DEBUG_PAGEALLOC 601 depends on !HIBERNATION 602 def_bool y 603 604config ARCH_HAS_HOLES_MEMORYMODEL 605 def_bool y if SPARSEMEM 606 607config ARCH_SPARSEMEM_ENABLE 608 def_bool y 609 select SPARSEMEM_VMEMMAP_ENABLE 610 611config ARCH_SPARSEMEM_DEFAULT 612 def_bool ARCH_SPARSEMEM_ENABLE 613 614config ARCH_SELECT_MEMORY_MODEL 615 def_bool ARCH_SPARSEMEM_ENABLE 616 617config HAVE_ARCH_PFN_VALID 618 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 619 620config HW_PERF_EVENTS 621 def_bool y 622 depends on ARM_PMU 623 624config SYS_SUPPORTS_HUGETLBFS 625 def_bool y 626 627config ARCH_WANT_HUGE_PMD_SHARE 628 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 629 630config ARCH_HAS_CACHE_LINE_SIZE 631 def_bool y 632 633source "mm/Kconfig" 634 635config SECCOMP 636 bool "Enable seccomp to safely compute untrusted bytecode" 637 ---help--- 638 This kernel feature is useful for number crunching applications 639 that may need to compute untrusted bytecode during their 640 execution. By using pipes or other transports made available to 641 the process as file descriptors supporting the read/write 642 syscalls, it's possible to isolate those applications in 643 their own address space using seccomp. Once seccomp is 644 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 645 and the task is only allowed to execute a few safe syscalls 646 defined by each seccomp mode. 647 648config PARAVIRT 649 bool "Enable paravirtualization code" 650 help 651 This changes the kernel so it can modify itself when it is run 652 under a hypervisor, potentially improving performance significantly 653 over full virtualization. 654 655config PARAVIRT_TIME_ACCOUNTING 656 bool "Paravirtual steal time accounting" 657 select PARAVIRT 658 default n 659 help 660 Select this option to enable fine granularity task steal time 661 accounting. Time spent executing other tasks in parallel with 662 the current vCPU is discounted from the vCPU power. To account for 663 that, there can be a small performance impact. 664 665 If in doubt, say N here. 666 667config XEN_DOM0 668 def_bool y 669 depends on XEN 670 671config XEN 672 bool "Xen guest support on ARM64" 673 depends on ARM64 && OF 674 select SWIOTLB_XEN 675 select PARAVIRT 676 help 677 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 678 679config FORCE_MAX_ZONEORDER 680 int 681 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 682 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 683 default "11" 684 help 685 The kernel memory allocator divides physically contiguous memory 686 blocks into "zones", where each zone is a power of two number of 687 pages. This option selects the largest power of two that the kernel 688 keeps in the memory allocator. If you need to allocate very large 689 blocks of physically contiguous memory, then you may need to 690 increase this value. 691 692 This config option is actually maximum order plus one. For example, 693 a value of 11 means that the largest free memory block is 2^10 pages. 694 695 We make sure that we can allocate upto a HugePage size for each configuration. 696 Hence we have : 697 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 698 699 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 700 4M allocations matching the default size used by generic code. 701 702menuconfig ARMV8_DEPRECATED 703 bool "Emulate deprecated/obsolete ARMv8 instructions" 704 depends on COMPAT 705 help 706 Legacy software support may require certain instructions 707 that have been deprecated or obsoleted in the architecture. 708 709 Enable this config to enable selective emulation of these 710 features. 711 712 If unsure, say Y 713 714if ARMV8_DEPRECATED 715 716config SWP_EMULATION 717 bool "Emulate SWP/SWPB instructions" 718 help 719 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 720 they are always undefined. Say Y here to enable software 721 emulation of these instructions for userspace using LDXR/STXR. 722 723 In some older versions of glibc [<=2.8] SWP is used during futex 724 trylock() operations with the assumption that the code will not 725 be preempted. This invalid assumption may be more likely to fail 726 with SWP emulation enabled, leading to deadlock of the user 727 application. 728 729 NOTE: when accessing uncached shared regions, LDXR/STXR rely 730 on an external transaction monitoring block called a global 731 monitor to maintain update atomicity. If your system does not 732 implement a global monitor, this option can cause programs that 733 perform SWP operations to uncached memory to deadlock. 734 735 If unsure, say Y 736 737config CP15_BARRIER_EMULATION 738 bool "Emulate CP15 Barrier instructions" 739 help 740 The CP15 barrier instructions - CP15ISB, CP15DSB, and 741 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 742 strongly recommended to use the ISB, DSB, and DMB 743 instructions instead. 744 745 Say Y here to enable software emulation of these 746 instructions for AArch32 userspace code. When this option is 747 enabled, CP15 barrier usage is traced which can help 748 identify software that needs updating. 749 750 If unsure, say Y 751 752config SETEND_EMULATION 753 bool "Emulate SETEND instruction" 754 help 755 The SETEND instruction alters the data-endianness of the 756 AArch32 EL0, and is deprecated in ARMv8. 757 758 Say Y here to enable software emulation of the instruction 759 for AArch32 userspace code. 760 761 Note: All the cpus on the system must have mixed endian support at EL0 762 for this feature to be enabled. If a new CPU - which doesn't support mixed 763 endian - is hotplugged in after this feature has been enabled, there could 764 be unexpected results in the applications. 765 766 If unsure, say Y 767endif 768 769menu "ARMv8.1 architectural features" 770 771config ARM64_HW_AFDBM 772 bool "Support for hardware updates of the Access and Dirty page flags" 773 default y 774 help 775 The ARMv8.1 architecture extensions introduce support for 776 hardware updates of the access and dirty information in page 777 table entries. When enabled in TCR_EL1 (HA and HD bits) on 778 capable processors, accesses to pages with PTE_AF cleared will 779 set this bit instead of raising an access flag fault. 780 Similarly, writes to read-only pages with the DBM bit set will 781 clear the read-only bit (AP[2]) instead of raising a 782 permission fault. 783 784 Kernels built with this configuration option enabled continue 785 to work on pre-ARMv8.1 hardware and the performance impact is 786 minimal. If unsure, say Y. 787 788config ARM64_PAN 789 bool "Enable support for Privileged Access Never (PAN)" 790 default y 791 help 792 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 793 prevents the kernel or hypervisor from accessing user-space (EL0) 794 memory directly. 795 796 Choosing this option will cause any unprotected (not using 797 copy_to_user et al) memory access to fail with a permission fault. 798 799 The feature is detected at runtime, and will remain as a 'nop' 800 instruction if the cpu does not implement the feature. 801 802config ARM64_LSE_ATOMICS 803 bool "Atomic instructions" 804 help 805 As part of the Large System Extensions, ARMv8.1 introduces new 806 atomic instructions that are designed specifically to scale in 807 very large systems. 808 809 Say Y here to make use of these instructions for the in-kernel 810 atomic routines. This incurs a small overhead on CPUs that do 811 not support these instructions and requires the kernel to be 812 built with binutils >= 2.25. 813 814config ARM64_VHE 815 bool "Enable support for Virtualization Host Extensions (VHE)" 816 default y 817 help 818 Virtualization Host Extensions (VHE) allow the kernel to run 819 directly at EL2 (instead of EL1) on processors that support 820 it. This leads to better performance for KVM, as they reduce 821 the cost of the world switch. 822 823 Selecting this option allows the VHE feature to be detected 824 at runtime, and does not affect processors that do not 825 implement this feature. 826 827endmenu 828 829menu "ARMv8.2 architectural features" 830 831config ARM64_UAO 832 bool "Enable support for User Access Override (UAO)" 833 default y 834 help 835 User Access Override (UAO; part of the ARMv8.2 Extensions) 836 causes the 'unprivileged' variant of the load/store instructions to 837 be overriden to be privileged. 838 839 This option changes get_user() and friends to use the 'unprivileged' 840 variant of the load/store instructions. This ensures that user-space 841 really did have access to the supplied memory. When addr_limit is 842 set to kernel memory the UAO bit will be set, allowing privileged 843 access to kernel memory. 844 845 Choosing this option will cause copy_to_user() et al to use user-space 846 memory permissions. 847 848 The feature is detected at runtime, the kernel will use the 849 regular load/store instructions if the cpu does not implement the 850 feature. 851 852endmenu 853 854config ARM64_MODULE_CMODEL_LARGE 855 bool 856 857config ARM64_MODULE_PLTS 858 bool 859 select ARM64_MODULE_CMODEL_LARGE 860 select HAVE_MOD_ARCH_SPECIFIC 861 862config RELOCATABLE 863 bool 864 help 865 This builds the kernel as a Position Independent Executable (PIE), 866 which retains all relocation metadata required to relocate the 867 kernel binary at runtime to a different virtual address than the 868 address it was linked at. 869 Since AArch64 uses the RELA relocation format, this requires a 870 relocation pass at runtime even if the kernel is loaded at the 871 same address it was linked at. 872 873config RANDOMIZE_BASE 874 bool "Randomize the address of the kernel image" 875 select ARM64_MODULE_PLTS 876 select RELOCATABLE 877 help 878 Randomizes the virtual address at which the kernel image is 879 loaded, as a security feature that deters exploit attempts 880 relying on knowledge of the location of kernel internals. 881 882 It is the bootloader's job to provide entropy, by passing a 883 random u64 value in /chosen/kaslr-seed at kernel entry. 884 885 When booting via the UEFI stub, it will invoke the firmware's 886 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 887 to the kernel proper. In addition, it will randomise the physical 888 location of the kernel Image as well. 889 890 If unsure, say N. 891 892config RANDOMIZE_MODULE_REGION_FULL 893 bool "Randomize the module region independently from the core kernel" 894 depends on RANDOMIZE_BASE 895 default y 896 help 897 Randomizes the location of the module region without considering the 898 location of the core kernel. This way, it is impossible for modules 899 to leak information about the location of core kernel data structures 900 but it does imply that function calls between modules and the core 901 kernel will need to be resolved via veneers in the module PLT. 902 903 When this option is not set, the module region will be randomized over 904 a limited range that contains the [_stext, _etext] interval of the 905 core kernel, so branch relocations are always in range. 906 907endmenu 908 909menu "Boot options" 910 911config ARM64_ACPI_PARKING_PROTOCOL 912 bool "Enable support for the ARM64 ACPI parking protocol" 913 depends on ACPI 914 help 915 Enable support for the ARM64 ACPI parking protocol. If disabled 916 the kernel will not allow booting through the ARM64 ACPI parking 917 protocol even if the corresponding data is present in the ACPI 918 MADT table. 919 920config CMDLINE 921 string "Default kernel command string" 922 default "" 923 help 924 Provide a set of default command-line options at build time by 925 entering them here. As a minimum, you should specify the the 926 root device (e.g. root=/dev/nfs). 927 928config CMDLINE_FORCE 929 bool "Always use the default kernel command string" 930 help 931 Always use the default kernel command string, even if the boot 932 loader passes other arguments to the kernel. 933 This is useful if you cannot or don't want to change the 934 command-line options your boot loader passes to the kernel. 935 936config EFI_STUB 937 bool 938 939config EFI 940 bool "UEFI runtime support" 941 depends on OF && !CPU_BIG_ENDIAN 942 select LIBFDT 943 select UCS2_STRING 944 select EFI_PARAMS_FROM_FDT 945 select EFI_RUNTIME_WRAPPERS 946 select EFI_STUB 947 select EFI_ARMSTUB 948 default y 949 help 950 This option provides support for runtime services provided 951 by UEFI firmware (such as non-volatile variables, realtime 952 clock, and platform reset). A UEFI stub is also provided to 953 allow the kernel to be booted as an EFI application. This 954 is only useful on systems that have UEFI firmware. 955 956config DMI 957 bool "Enable support for SMBIOS (DMI) tables" 958 depends on EFI 959 default y 960 help 961 This enables SMBIOS/DMI feature for systems. 962 963 This option is only useful on systems that have UEFI firmware. 964 However, even with this option, the resultant kernel should 965 continue to boot on existing non-UEFI platforms. 966 967endmenu 968 969menu "Userspace binary formats" 970 971source "fs/Kconfig.binfmt" 972 973config COMPAT 974 bool "Kernel support for 32-bit EL0" 975 depends on ARM64_4K_PAGES || EXPERT 976 select COMPAT_BINFMT_ELF 977 select HAVE_UID16 978 select OLD_SIGSUSPEND3 979 select COMPAT_OLD_SIGACTION 980 help 981 This option enables support for a 32-bit EL0 running under a 64-bit 982 kernel at EL1. AArch32-specific components such as system calls, 983 the user helper functions, VFP support and the ptrace interface are 984 handled appropriately by the kernel. 985 986 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 987 that you will only be able to execute AArch32 binaries that were compiled 988 with page size aligned segments. 989 990 If you want to execute 32-bit userspace applications, say Y. 991 992config SYSVIPC_COMPAT 993 def_bool y 994 depends on COMPAT && SYSVIPC 995 996endmenu 997 998menu "Power management options" 999 1000source "kernel/power/Kconfig" 1001 1002config ARCH_HIBERNATION_POSSIBLE 1003 def_bool y 1004 depends on CPU_PM 1005 1006config ARCH_HIBERNATION_HEADER 1007 def_bool y 1008 depends on HIBERNATION 1009 1010config ARCH_SUSPEND_POSSIBLE 1011 def_bool y 1012 1013endmenu 1014 1015menu "CPU Power Management" 1016 1017source "drivers/cpuidle/Kconfig" 1018 1019source "drivers/cpufreq/Kconfig" 1020 1021endmenu 1022 1023source "net/Kconfig" 1024 1025source "drivers/Kconfig" 1026 1027source "drivers/firmware/Kconfig" 1028 1029source "drivers/acpi/Kconfig" 1030 1031source "fs/Kconfig" 1032 1033source "arch/arm64/kvm/Kconfig" 1034 1035source "arch/arm64/Kconfig.debug" 1036 1037source "security/Kconfig" 1038 1039source "crypto/Kconfig" 1040if CRYPTO 1041source "arch/arm64/crypto/Kconfig" 1042endif 1043 1044source "lib/Kconfig" 1045