1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_INLINE_READ_LOCK if !PREEMPTION 52 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 55 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 59 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 63 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 67 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 73 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 77 select ARCH_KEEP_MEMBLOCK 78 select ARCH_USE_CMPXCHG_LOCKREF 79 select ARCH_USE_GNU_PROPERTY 80 select ARCH_USE_MEMTEST 81 select ARCH_USE_QUEUED_RWLOCKS 82 select ARCH_USE_QUEUED_SPINLOCKS 83 select ARCH_USE_SYM_ANNOTATIONS 84 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 85 select ARCH_SUPPORTS_HUGETLBFS 86 select ARCH_SUPPORTS_MEMORY_FAILURE 87 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 88 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 89 select ARCH_SUPPORTS_LTO_CLANG_THIN 90 select ARCH_SUPPORTS_CFI_CLANG 91 select ARCH_SUPPORTS_ATOMIC_RMW 92 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 93 select ARCH_SUPPORTS_NUMA_BALANCING 94 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 95 select ARCH_WANT_DEFAULT_BPF_JIT 96 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 97 select ARCH_WANT_FRAME_POINTERS 98 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 99 select ARCH_WANT_LD_ORPHAN_WARN 100 select ARCH_WANTS_NO_INSTR 101 select ARCH_HAS_UBSAN_SANITIZE_ALL 102 select ARM_AMBA 103 select ARM_ARCH_TIMER 104 select ARM_GIC 105 select AUDIT_ARCH_COMPAT_GENERIC 106 select ARM_GIC_V2M if PCI 107 select ARM_GIC_V3 108 select ARM_GIC_V3_ITS if PCI 109 select ARM_PSCI_FW 110 select BUILDTIME_TABLE_SORT 111 select CLONE_BACKWARDS 112 select COMMON_CLK 113 select CPU_PM if (SUSPEND || CPU_IDLE) 114 select CRC32 115 select DCACHE_WORD_ACCESS 116 select DMA_DIRECT_REMAP 117 select EDAC_SUPPORT 118 select FRAME_POINTER 119 select GENERIC_ALLOCATOR 120 select GENERIC_ARCH_TOPOLOGY 121 select GENERIC_CLOCKEVENTS_BROADCAST 122 select GENERIC_CPU_AUTOPROBE 123 select GENERIC_CPU_VULNERABILITIES 124 select GENERIC_EARLY_IOREMAP 125 select GENERIC_IDLE_POLL_SETUP 126 select GENERIC_IRQ_IPI 127 select GENERIC_IRQ_PROBE 128 select GENERIC_IRQ_SHOW 129 select GENERIC_IRQ_SHOW_LEVEL 130 select GENERIC_LIB_DEVMEM_IS_ALLOWED 131 select GENERIC_PCI_IOMAP 132 select GENERIC_PTDUMP 133 select GENERIC_SCHED_CLOCK 134 select GENERIC_SMP_IDLE_THREAD 135 select GENERIC_TIME_VSYSCALL 136 select GENERIC_GETTIMEOFDAY 137 select GENERIC_VDSO_TIME_NS 138 select HARDIRQS_SW_RESEND 139 select HAVE_MOVE_PMD 140 select HAVE_MOVE_PUD 141 select HAVE_PCI 142 select HAVE_ACPI_APEI if (ACPI && EFI) 143 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 144 select HAVE_ARCH_AUDITSYSCALL 145 select HAVE_ARCH_BITREVERSE 146 select HAVE_ARCH_COMPILER_H 147 select HAVE_ARCH_HUGE_VMAP 148 select HAVE_ARCH_JUMP_LABEL 149 select HAVE_ARCH_JUMP_LABEL_RELATIVE 150 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 151 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 152 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 153 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 154 # Some instrumentation may be unsound, hence EXPERT 155 select HAVE_ARCH_KCSAN if EXPERT 156 select HAVE_ARCH_KFENCE 157 select HAVE_ARCH_KGDB 158 select HAVE_ARCH_MMAP_RND_BITS 159 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 160 select HAVE_ARCH_PREL32_RELOCATIONS 161 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 162 select HAVE_ARCH_SECCOMP_FILTER 163 select HAVE_ARCH_STACKLEAK 164 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 165 select HAVE_ARCH_TRACEHOOK 166 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 167 select HAVE_ARCH_VMAP_STACK 168 select HAVE_ARM_SMCCC 169 select HAVE_ASM_MODVERSIONS 170 select HAVE_EBPF_JIT 171 select HAVE_C_RECORDMCOUNT 172 select HAVE_CMPXCHG_DOUBLE 173 select HAVE_CMPXCHG_LOCAL 174 select HAVE_CONTEXT_TRACKING 175 select HAVE_DEBUG_KMEMLEAK 176 select HAVE_DMA_CONTIGUOUS 177 select HAVE_DYNAMIC_FTRACE 178 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 179 if $(cc-option,-fpatchable-function-entry=2) 180 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 181 if DYNAMIC_FTRACE_WITH_REGS 182 select HAVE_EFFICIENT_UNALIGNED_ACCESS 183 select HAVE_FAST_GUP 184 select HAVE_FTRACE_MCOUNT_RECORD 185 select HAVE_FUNCTION_TRACER 186 select HAVE_FUNCTION_ERROR_INJECTION 187 select HAVE_FUNCTION_GRAPH_TRACER 188 select HAVE_GCC_PLUGINS 189 select HAVE_HW_BREAKPOINT if PERF_EVENTS 190 select HAVE_IRQ_TIME_ACCOUNTING 191 select HAVE_KVM 192 select HAVE_NMI 193 select HAVE_PATA_PLATFORM 194 select HAVE_PERF_EVENTS 195 select HAVE_PERF_REGS 196 select HAVE_PERF_USER_STACK_DUMP 197 select HAVE_PREEMPT_DYNAMIC_KEY 198 select HAVE_REGS_AND_STACK_ACCESS_API 199 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 200 select HAVE_FUNCTION_ARG_ACCESS_API 201 select MMU_GATHER_RCU_TABLE_FREE 202 select HAVE_RSEQ 203 select HAVE_STACKPROTECTOR 204 select HAVE_SYSCALL_TRACEPOINTS 205 select HAVE_KPROBES 206 select HAVE_KRETPROBES 207 select HAVE_GENERIC_VDSO 208 select IOMMU_DMA if IOMMU_SUPPORT 209 select IRQ_DOMAIN 210 select IRQ_FORCED_THREADING 211 select KASAN_VMALLOC if KASAN_GENERIC 212 select MODULES_USE_ELF_RELA 213 select NEED_DMA_MAP_STATE 214 select NEED_SG_DMA_LENGTH 215 select OF 216 select OF_EARLY_FLATTREE 217 select PCI_DOMAINS_GENERIC if PCI 218 select PCI_ECAM if (ACPI && PCI) 219 select PCI_SYSCALL if PCI 220 select POWER_RESET 221 select POWER_SUPPLY 222 select SPARSE_IRQ 223 select SWIOTLB 224 select SYSCTL_EXCEPTION_TRACE 225 select THREAD_INFO_IN_TASK 226 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 227 select TRACE_IRQFLAGS_SUPPORT 228 help 229 ARM 64-bit (AArch64) Linux support. 230 231config 64BIT 232 def_bool y 233 234config MMU 235 def_bool y 236 237config ARM64_PAGE_SHIFT 238 int 239 default 16 if ARM64_64K_PAGES 240 default 14 if ARM64_16K_PAGES 241 default 12 242 243config ARM64_CONT_PTE_SHIFT 244 int 245 default 5 if ARM64_64K_PAGES 246 default 7 if ARM64_16K_PAGES 247 default 4 248 249config ARM64_CONT_PMD_SHIFT 250 int 251 default 5 if ARM64_64K_PAGES 252 default 5 if ARM64_16K_PAGES 253 default 4 254 255config ARCH_MMAP_RND_BITS_MIN 256 default 14 if ARM64_64K_PAGES 257 default 16 if ARM64_16K_PAGES 258 default 18 259 260# max bits determined by the following formula: 261# VA_BITS - PAGE_SHIFT - 3 262config ARCH_MMAP_RND_BITS_MAX 263 default 19 if ARM64_VA_BITS=36 264 default 24 if ARM64_VA_BITS=39 265 default 27 if ARM64_VA_BITS=42 266 default 30 if ARM64_VA_BITS=47 267 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 268 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 269 default 33 if ARM64_VA_BITS=48 270 default 14 if ARM64_64K_PAGES 271 default 16 if ARM64_16K_PAGES 272 default 18 273 274config ARCH_MMAP_RND_COMPAT_BITS_MIN 275 default 7 if ARM64_64K_PAGES 276 default 9 if ARM64_16K_PAGES 277 default 11 278 279config ARCH_MMAP_RND_COMPAT_BITS_MAX 280 default 16 281 282config NO_IOPORT_MAP 283 def_bool y if !PCI 284 285config STACKTRACE_SUPPORT 286 def_bool y 287 288config ILLEGAL_POINTER_VALUE 289 hex 290 default 0xdead000000000000 291 292config LOCKDEP_SUPPORT 293 def_bool y 294 295config GENERIC_BUG 296 def_bool y 297 depends on BUG 298 299config GENERIC_BUG_RELATIVE_POINTERS 300 def_bool y 301 depends on GENERIC_BUG 302 303config GENERIC_HWEIGHT 304 def_bool y 305 306config GENERIC_CSUM 307 def_bool y 308 309config GENERIC_CALIBRATE_DELAY 310 def_bool y 311 312config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 313 def_bool y 314 315config SMP 316 def_bool y 317 318config KERNEL_MODE_NEON 319 def_bool y 320 321config FIX_EARLYCON_MEM 322 def_bool y 323 324config PGTABLE_LEVELS 325 int 326 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 327 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 328 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 329 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 330 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 331 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 332 333config ARCH_SUPPORTS_UPROBES 334 def_bool y 335 336config ARCH_PROC_KCORE_TEXT 337 def_bool y 338 339config BROKEN_GAS_INST 340 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 341 342config KASAN_SHADOW_OFFSET 343 hex 344 depends on KASAN_GENERIC || KASAN_SW_TAGS 345 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 346 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 347 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 348 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 349 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 350 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 351 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 352 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 353 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 354 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 355 default 0xffffffffffffffff 356 357source "arch/arm64/Kconfig.platforms" 358 359menu "Kernel Features" 360 361menu "ARM errata workarounds via the alternatives framework" 362 363config ARM64_WORKAROUND_CLEAN_CACHE 364 bool 365 366config ARM64_ERRATUM_826319 367 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 368 default y 369 select ARM64_WORKAROUND_CLEAN_CACHE 370 help 371 This option adds an alternative code sequence to work around ARM 372 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 373 AXI master interface and an L2 cache. 374 375 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 376 and is unable to accept a certain write via this interface, it will 377 not progress on read data presented on the read data channel and the 378 system can deadlock. 379 380 The workaround promotes data cache clean instructions to 381 data cache clean-and-invalidate. 382 Please note that this does not necessarily enable the workaround, 383 as it depends on the alternative framework, which will only patch 384 the kernel if an affected CPU is detected. 385 386 If unsure, say Y. 387 388config ARM64_ERRATUM_827319 389 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 390 default y 391 select ARM64_WORKAROUND_CLEAN_CACHE 392 help 393 This option adds an alternative code sequence to work around ARM 394 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 395 master interface and an L2 cache. 396 397 Under certain conditions this erratum can cause a clean line eviction 398 to occur at the same time as another transaction to the same address 399 on the AMBA 5 CHI interface, which can cause data corruption if the 400 interconnect reorders the two transactions. 401 402 The workaround promotes data cache clean instructions to 403 data cache clean-and-invalidate. 404 Please note that this does not necessarily enable the workaround, 405 as it depends on the alternative framework, which will only patch 406 the kernel if an affected CPU is detected. 407 408 If unsure, say Y. 409 410config ARM64_ERRATUM_824069 411 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 412 default y 413 select ARM64_WORKAROUND_CLEAN_CACHE 414 help 415 This option adds an alternative code sequence to work around ARM 416 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 417 to a coherent interconnect. 418 419 If a Cortex-A53 processor is executing a store or prefetch for 420 write instruction at the same time as a processor in another 421 cluster is executing a cache maintenance operation to the same 422 address, then this erratum might cause a clean cache line to be 423 incorrectly marked as dirty. 424 425 The workaround promotes data cache clean instructions to 426 data cache clean-and-invalidate. 427 Please note that this option does not necessarily enable the 428 workaround, as it depends on the alternative framework, which will 429 only patch the kernel if an affected CPU is detected. 430 431 If unsure, say Y. 432 433config ARM64_ERRATUM_819472 434 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 435 default y 436 select ARM64_WORKAROUND_CLEAN_CACHE 437 help 438 This option adds an alternative code sequence to work around ARM 439 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 440 present when it is connected to a coherent interconnect. 441 442 If the processor is executing a load and store exclusive sequence at 443 the same time as a processor in another cluster is executing a cache 444 maintenance operation to the same address, then this erratum might 445 cause data corruption. 446 447 The workaround promotes data cache clean instructions to 448 data cache clean-and-invalidate. 449 Please note that this does not necessarily enable the workaround, 450 as it depends on the alternative framework, which will only patch 451 the kernel if an affected CPU is detected. 452 453 If unsure, say Y. 454 455config ARM64_ERRATUM_832075 456 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 457 default y 458 help 459 This option adds an alternative code sequence to work around ARM 460 erratum 832075 on Cortex-A57 parts up to r1p2. 461 462 Affected Cortex-A57 parts might deadlock when exclusive load/store 463 instructions to Write-Back memory are mixed with Device loads. 464 465 The workaround is to promote device loads to use Load-Acquire 466 semantics. 467 Please note that this does not necessarily enable the workaround, 468 as it depends on the alternative framework, which will only patch 469 the kernel if an affected CPU is detected. 470 471 If unsure, say Y. 472 473config ARM64_ERRATUM_834220 474 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 475 depends on KVM 476 default y 477 help 478 This option adds an alternative code sequence to work around ARM 479 erratum 834220 on Cortex-A57 parts up to r1p2. 480 481 Affected Cortex-A57 parts might report a Stage 2 translation 482 fault as the result of a Stage 1 fault for load crossing a 483 page boundary when there is a permission or device memory 484 alignment fault at Stage 1 and a translation fault at Stage 2. 485 486 The workaround is to verify that the Stage 1 translation 487 doesn't generate a fault before handling the Stage 2 fault. 488 Please note that this does not necessarily enable the workaround, 489 as it depends on the alternative framework, which will only patch 490 the kernel if an affected CPU is detected. 491 492 If unsure, say Y. 493 494config ARM64_ERRATUM_845719 495 bool "Cortex-A53: 845719: a load might read incorrect data" 496 depends on COMPAT 497 default y 498 help 499 This option adds an alternative code sequence to work around ARM 500 erratum 845719 on Cortex-A53 parts up to r0p4. 501 502 When running a compat (AArch32) userspace on an affected Cortex-A53 503 part, a load at EL0 from a virtual address that matches the bottom 32 504 bits of the virtual address used by a recent load at (AArch64) EL1 505 might return incorrect data. 506 507 The workaround is to write the contextidr_el1 register on exception 508 return to a 32-bit task. 509 Please note that this does not necessarily enable the workaround, 510 as it depends on the alternative framework, which will only patch 511 the kernel if an affected CPU is detected. 512 513 If unsure, say Y. 514 515config ARM64_ERRATUM_843419 516 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 517 default y 518 select ARM64_MODULE_PLTS if MODULES 519 help 520 This option links the kernel with '--fix-cortex-a53-843419' and 521 enables PLT support to replace certain ADRP instructions, which can 522 cause subsequent memory accesses to use an incorrect address on 523 Cortex-A53 parts up to r0p4. 524 525 If unsure, say Y. 526 527config ARM64_LD_HAS_FIX_ERRATUM_843419 528 def_bool $(ld-option,--fix-cortex-a53-843419) 529 530config ARM64_ERRATUM_1024718 531 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 532 default y 533 help 534 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 535 536 Affected Cortex-A55 cores (all revisions) could cause incorrect 537 update of the hardware dirty bit when the DBM/AP bits are updated 538 without a break-before-make. The workaround is to disable the usage 539 of hardware DBM locally on the affected cores. CPUs not affected by 540 this erratum will continue to use the feature. 541 542 If unsure, say Y. 543 544config ARM64_ERRATUM_1418040 545 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 546 default y 547 depends on COMPAT 548 help 549 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 550 errata 1188873 and 1418040. 551 552 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 553 cause register corruption when accessing the timer registers 554 from AArch32 userspace. 555 556 If unsure, say Y. 557 558config ARM64_WORKAROUND_SPECULATIVE_AT 559 bool 560 561config ARM64_ERRATUM_1165522 562 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 563 default y 564 select ARM64_WORKAROUND_SPECULATIVE_AT 565 help 566 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 567 568 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 569 corrupted TLBs by speculating an AT instruction during a guest 570 context switch. 571 572 If unsure, say Y. 573 574config ARM64_ERRATUM_1319367 575 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 576 default y 577 select ARM64_WORKAROUND_SPECULATIVE_AT 578 help 579 This option adds work arounds for ARM Cortex-A57 erratum 1319537 580 and A72 erratum 1319367 581 582 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 583 speculating an AT instruction during a guest context switch. 584 585 If unsure, say Y. 586 587config ARM64_ERRATUM_1530923 588 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 589 default y 590 select ARM64_WORKAROUND_SPECULATIVE_AT 591 help 592 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 593 594 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 595 corrupted TLBs by speculating an AT instruction during a guest 596 context switch. 597 598 If unsure, say Y. 599 600config ARM64_WORKAROUND_REPEAT_TLBI 601 bool 602 603config ARM64_ERRATUM_1286807 604 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 605 default y 606 select ARM64_WORKAROUND_REPEAT_TLBI 607 help 608 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 609 610 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 611 address for a cacheable mapping of a location is being 612 accessed by a core while another core is remapping the virtual 613 address to a new physical page using the recommended 614 break-before-make sequence, then under very rare circumstances 615 TLBI+DSB completes before a read using the translation being 616 invalidated has been observed by other observers. The 617 workaround repeats the TLBI+DSB operation. 618 619config ARM64_ERRATUM_1463225 620 bool "Cortex-A76: Software Step might prevent interrupt recognition" 621 default y 622 help 623 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 624 625 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 626 of a system call instruction (SVC) can prevent recognition of 627 subsequent interrupts when software stepping is disabled in the 628 exception handler of the system call and either kernel debugging 629 is enabled or VHE is in use. 630 631 Work around the erratum by triggering a dummy step exception 632 when handling a system call from a task that is being stepped 633 in a VHE configuration of the kernel. 634 635 If unsure, say Y. 636 637config ARM64_ERRATUM_1542419 638 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 639 default y 640 help 641 This option adds a workaround for ARM Neoverse-N1 erratum 642 1542419. 643 644 Affected Neoverse-N1 cores could execute a stale instruction when 645 modified by another CPU. The workaround depends on a firmware 646 counterpart. 647 648 Workaround the issue by hiding the DIC feature from EL0. This 649 forces user-space to perform cache maintenance. 650 651 If unsure, say Y. 652 653config ARM64_ERRATUM_1508412 654 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 655 default y 656 help 657 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 658 659 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 660 of a store-exclusive or read of PAR_EL1 and a load with device or 661 non-cacheable memory attributes. The workaround depends on a firmware 662 counterpart. 663 664 KVM guests must also have the workaround implemented or they can 665 deadlock the system. 666 667 Work around the issue by inserting DMB SY barriers around PAR_EL1 668 register reads and warning KVM users. The DMB barrier is sufficient 669 to prevent a speculative PAR_EL1 read. 670 671 If unsure, say Y. 672 673config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 674 bool 675 676config ARM64_ERRATUM_2051678 677 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 678 default y 679 help 680 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 681 Affected Coretex-A510 might not respect the ordering rules for 682 hardware update of the page table's dirty bit. The workaround 683 is to not enable the feature on affected CPUs. 684 685 If unsure, say Y. 686 687config ARM64_ERRATUM_2077057 688 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 689 help 690 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 691 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 692 expected, but a Pointer Authentication trap is taken instead. The 693 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 694 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 695 696 This can only happen when EL2 is stepping EL1. 697 698 When these conditions occur, the SPSR_EL2 value is unchanged from the 699 previous guest entry, and can be restored from the in-memory copy. 700 701 If unsure, say Y. 702 703config ARM64_ERRATUM_2119858 704 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 705 default y 706 depends on CORESIGHT_TRBE 707 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 708 help 709 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 710 711 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 712 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 713 the event of a WRAP event. 714 715 Work around the issue by always making sure we move the TRBPTR_EL1 by 716 256 bytes before enabling the buffer and filling the first 256 bytes of 717 the buffer with ETM ignore packets upon disabling. 718 719 If unsure, say Y. 720 721config ARM64_ERRATUM_2139208 722 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 723 default y 724 depends on CORESIGHT_TRBE 725 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 726 help 727 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 728 729 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 730 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 731 the event of a WRAP event. 732 733 Work around the issue by always making sure we move the TRBPTR_EL1 by 734 256 bytes before enabling the buffer and filling the first 256 bytes of 735 the buffer with ETM ignore packets upon disabling. 736 737 If unsure, say Y. 738 739config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 740 bool 741 742config ARM64_ERRATUM_2054223 743 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 744 default y 745 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 746 help 747 Enable workaround for ARM Cortex-A710 erratum 2054223 748 749 Affected cores may fail to flush the trace data on a TSB instruction, when 750 the PE is in trace prohibited state. This will cause losing a few bytes 751 of the trace cached. 752 753 Workaround is to issue two TSB consecutively on affected cores. 754 755 If unsure, say Y. 756 757config ARM64_ERRATUM_2067961 758 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 759 default y 760 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 761 help 762 Enable workaround for ARM Neoverse-N2 erratum 2067961 763 764 Affected cores may fail to flush the trace data on a TSB instruction, when 765 the PE is in trace prohibited state. This will cause losing a few bytes 766 of the trace cached. 767 768 Workaround is to issue two TSB consecutively on affected cores. 769 770 If unsure, say Y. 771 772config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 773 bool 774 775config ARM64_ERRATUM_2253138 776 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 777 depends on CORESIGHT_TRBE 778 default y 779 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 780 help 781 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 782 783 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 784 for TRBE. Under some conditions, the TRBE might generate a write to the next 785 virtually addressed page following the last page of the TRBE address space 786 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 787 788 Work around this in the driver by always making sure that there is a 789 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 790 791 If unsure, say Y. 792 793config ARM64_ERRATUM_2224489 794 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 795 depends on CORESIGHT_TRBE 796 default y 797 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 798 help 799 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 800 801 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 802 for TRBE. Under some conditions, the TRBE might generate a write to the next 803 virtually addressed page following the last page of the TRBE address space 804 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 805 806 Work around this in the driver by always making sure that there is a 807 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 808 809 If unsure, say Y. 810 811config ARM64_ERRATUM_2064142 812 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 813 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 814 default y 815 help 816 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 817 818 Affected Cortex-A510 core might fail to write into system registers after the 819 TRBE has been disabled. Under some conditions after the TRBE has been disabled 820 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 821 and TRBTRG_EL1 will be ignored and will not be effected. 822 823 Work around this in the driver by executing TSB CSYNC and DSB after collection 824 is stopped and before performing a system register write to one of the affected 825 registers. 826 827 If unsure, say Y. 828 829config ARM64_ERRATUM_2038923 830 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 831 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 832 default y 833 help 834 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 835 836 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 837 prohibited within the CPU. As a result, the trace buffer or trace buffer state 838 might be corrupted. This happens after TRBE buffer has been enabled by setting 839 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 840 execution changes from a context, in which trace is prohibited to one where it 841 isn't, or vice versa. In these mentioned conditions, the view of whether trace 842 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 843 the trace buffer state might be corrupted. 844 845 Work around this in the driver by preventing an inconsistent view of whether the 846 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 847 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 848 two ISB instructions if no ERET is to take place. 849 850 If unsure, say Y. 851 852config ARM64_ERRATUM_1902691 853 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 854 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 855 default y 856 help 857 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 858 859 Affected Cortex-A510 core might cause trace data corruption, when being written 860 into the memory. Effectively TRBE is broken and hence cannot be used to capture 861 trace data. 862 863 Work around this problem in the driver by just preventing TRBE initialization on 864 affected cpus. The firmware must have disabled the access to TRBE for the kernel 865 on such implementations. This will cover the kernel for any firmware that doesn't 866 do this already. 867 868 If unsure, say Y. 869 870config CAVIUM_ERRATUM_22375 871 bool "Cavium erratum 22375, 24313" 872 default y 873 help 874 Enable workaround for errata 22375 and 24313. 875 876 This implements two gicv3-its errata workarounds for ThunderX. Both 877 with a small impact affecting only ITS table allocation. 878 879 erratum 22375: only alloc 8MB table size 880 erratum 24313: ignore memory access type 881 882 The fixes are in ITS initialization and basically ignore memory access 883 type and table size provided by the TYPER and BASER registers. 884 885 If unsure, say Y. 886 887config CAVIUM_ERRATUM_23144 888 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 889 depends on NUMA 890 default y 891 help 892 ITS SYNC command hang for cross node io and collections/cpu mapping. 893 894 If unsure, say Y. 895 896config CAVIUM_ERRATUM_23154 897 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 898 default y 899 help 900 The ThunderX GICv3 implementation requires a modified version for 901 reading the IAR status to ensure data synchronization 902 (access to icc_iar1_el1 is not sync'ed before and after). 903 904 It also suffers from erratum 38545 (also present on Marvell's 905 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 906 spuriously presented to the CPU interface. 907 908 If unsure, say Y. 909 910config CAVIUM_ERRATUM_27456 911 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 912 default y 913 help 914 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 915 instructions may cause the icache to become corrupted if it 916 contains data for a non-current ASID. The fix is to 917 invalidate the icache when changing the mm context. 918 919 If unsure, say Y. 920 921config CAVIUM_ERRATUM_30115 922 bool "Cavium erratum 30115: Guest may disable interrupts in host" 923 default y 924 help 925 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 926 1.2, and T83 Pass 1.0, KVM guest execution may disable 927 interrupts in host. Trapping both GICv3 group-0 and group-1 928 accesses sidesteps the issue. 929 930 If unsure, say Y. 931 932config CAVIUM_TX2_ERRATUM_219 933 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 934 default y 935 help 936 On Cavium ThunderX2, a load, store or prefetch instruction between a 937 TTBR update and the corresponding context synchronizing operation can 938 cause a spurious Data Abort to be delivered to any hardware thread in 939 the CPU core. 940 941 Work around the issue by avoiding the problematic code sequence and 942 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 943 trap handler performs the corresponding register access, skips the 944 instruction and ensures context synchronization by virtue of the 945 exception return. 946 947 If unsure, say Y. 948 949config FUJITSU_ERRATUM_010001 950 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 951 default y 952 help 953 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 954 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 955 accesses may cause undefined fault (Data abort, DFSC=0b111111). 956 This fault occurs under a specific hardware condition when a 957 load/store instruction performs an address translation using: 958 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 959 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 960 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 961 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 962 963 The workaround is to ensure these bits are clear in TCR_ELx. 964 The workaround only affects the Fujitsu-A64FX. 965 966 If unsure, say Y. 967 968config HISILICON_ERRATUM_161600802 969 bool "Hip07 161600802: Erroneous redistributor VLPI base" 970 default y 971 help 972 The HiSilicon Hip07 SoC uses the wrong redistributor base 973 when issued ITS commands such as VMOVP and VMAPP, and requires 974 a 128kB offset to be applied to the target address in this commands. 975 976 If unsure, say Y. 977 978config QCOM_FALKOR_ERRATUM_1003 979 bool "Falkor E1003: Incorrect translation due to ASID change" 980 default y 981 help 982 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 983 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 984 in TTBR1_EL1, this situation only occurs in the entry trampoline and 985 then only for entries in the walk cache, since the leaf translation 986 is unchanged. Work around the erratum by invalidating the walk cache 987 entries for the trampoline before entering the kernel proper. 988 989config QCOM_FALKOR_ERRATUM_1009 990 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 991 default y 992 select ARM64_WORKAROUND_REPEAT_TLBI 993 help 994 On Falkor v1, the CPU may prematurely complete a DSB following a 995 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 996 one more time to fix the issue. 997 998 If unsure, say Y. 999 1000config QCOM_QDF2400_ERRATUM_0065 1001 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1002 default y 1003 help 1004 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1005 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1006 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1007 1008 If unsure, say Y. 1009 1010config QCOM_FALKOR_ERRATUM_E1041 1011 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1012 default y 1013 help 1014 Falkor CPU may speculatively fetch instructions from an improper 1015 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1016 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1017 1018 If unsure, say Y. 1019 1020config NVIDIA_CARMEL_CNP_ERRATUM 1021 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1022 default y 1023 help 1024 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1025 invalidate shared TLB entries installed by a different core, as it would 1026 on standard ARM cores. 1027 1028 If unsure, say Y. 1029 1030config SOCIONEXT_SYNQUACER_PREITS 1031 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1032 default y 1033 help 1034 Socionext Synquacer SoCs implement a separate h/w block to generate 1035 MSI doorbell writes with non-zero values for the device ID. 1036 1037 If unsure, say Y. 1038 1039endmenu 1040 1041 1042choice 1043 prompt "Page size" 1044 default ARM64_4K_PAGES 1045 help 1046 Page size (translation granule) configuration. 1047 1048config ARM64_4K_PAGES 1049 bool "4KB" 1050 help 1051 This feature enables 4KB pages support. 1052 1053config ARM64_16K_PAGES 1054 bool "16KB" 1055 help 1056 The system will use 16KB pages support. AArch32 emulation 1057 requires applications compiled with 16K (or a multiple of 16K) 1058 aligned segments. 1059 1060config ARM64_64K_PAGES 1061 bool "64KB" 1062 help 1063 This feature enables 64KB pages support (4KB by default) 1064 allowing only two levels of page tables and faster TLB 1065 look-up. AArch32 emulation requires applications compiled 1066 with 64K aligned segments. 1067 1068endchoice 1069 1070choice 1071 prompt "Virtual address space size" 1072 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1073 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1074 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1075 help 1076 Allows choosing one of multiple possible virtual address 1077 space sizes. The level of translation table is determined by 1078 a combination of page size and virtual address space size. 1079 1080config ARM64_VA_BITS_36 1081 bool "36-bit" if EXPERT 1082 depends on ARM64_16K_PAGES 1083 1084config ARM64_VA_BITS_39 1085 bool "39-bit" 1086 depends on ARM64_4K_PAGES 1087 1088config ARM64_VA_BITS_42 1089 bool "42-bit" 1090 depends on ARM64_64K_PAGES 1091 1092config ARM64_VA_BITS_47 1093 bool "47-bit" 1094 depends on ARM64_16K_PAGES 1095 1096config ARM64_VA_BITS_48 1097 bool "48-bit" 1098 1099config ARM64_VA_BITS_52 1100 bool "52-bit" 1101 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1102 help 1103 Enable 52-bit virtual addressing for userspace when explicitly 1104 requested via a hint to mmap(). The kernel will also use 52-bit 1105 virtual addresses for its own mappings (provided HW support for 1106 this feature is available, otherwise it reverts to 48-bit). 1107 1108 NOTE: Enabling 52-bit virtual addressing in conjunction with 1109 ARMv8.3 Pointer Authentication will result in the PAC being 1110 reduced from 7 bits to 3 bits, which may have a significant 1111 impact on its susceptibility to brute-force attacks. 1112 1113 If unsure, select 48-bit virtual addressing instead. 1114 1115endchoice 1116 1117config ARM64_FORCE_52BIT 1118 bool "Force 52-bit virtual addresses for userspace" 1119 depends on ARM64_VA_BITS_52 && EXPERT 1120 help 1121 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1122 to maintain compatibility with older software by providing 48-bit VAs 1123 unless a hint is supplied to mmap. 1124 1125 This configuration option disables the 48-bit compatibility logic, and 1126 forces all userspace addresses to be 52-bit on HW that supports it. One 1127 should only enable this configuration option for stress testing userspace 1128 memory management code. If unsure say N here. 1129 1130config ARM64_VA_BITS 1131 int 1132 default 36 if ARM64_VA_BITS_36 1133 default 39 if ARM64_VA_BITS_39 1134 default 42 if ARM64_VA_BITS_42 1135 default 47 if ARM64_VA_BITS_47 1136 default 48 if ARM64_VA_BITS_48 1137 default 52 if ARM64_VA_BITS_52 1138 1139choice 1140 prompt "Physical address space size" 1141 default ARM64_PA_BITS_48 1142 help 1143 Choose the maximum physical address range that the kernel will 1144 support. 1145 1146config ARM64_PA_BITS_48 1147 bool "48-bit" 1148 1149config ARM64_PA_BITS_52 1150 bool "52-bit (ARMv8.2)" 1151 depends on ARM64_64K_PAGES 1152 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1153 help 1154 Enable support for a 52-bit physical address space, introduced as 1155 part of the ARMv8.2-LPA extension. 1156 1157 With this enabled, the kernel will also continue to work on CPUs that 1158 do not support ARMv8.2-LPA, but with some added memory overhead (and 1159 minor performance overhead). 1160 1161endchoice 1162 1163config ARM64_PA_BITS 1164 int 1165 default 48 if ARM64_PA_BITS_48 1166 default 52 if ARM64_PA_BITS_52 1167 1168choice 1169 prompt "Endianness" 1170 default CPU_LITTLE_ENDIAN 1171 help 1172 Select the endianness of data accesses performed by the CPU. Userspace 1173 applications will need to be compiled and linked for the endianness 1174 that is selected here. 1175 1176config CPU_BIG_ENDIAN 1177 bool "Build big-endian kernel" 1178 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1179 help 1180 Say Y if you plan on running a kernel with a big-endian userspace. 1181 1182config CPU_LITTLE_ENDIAN 1183 bool "Build little-endian kernel" 1184 help 1185 Say Y if you plan on running a kernel with a little-endian userspace. 1186 This is usually the case for distributions targeting arm64. 1187 1188endchoice 1189 1190config SCHED_MC 1191 bool "Multi-core scheduler support" 1192 help 1193 Multi-core scheduler support improves the CPU scheduler's decision 1194 making when dealing with multi-core CPU chips at a cost of slightly 1195 increased overhead in some places. If unsure say N here. 1196 1197config SCHED_CLUSTER 1198 bool "Cluster scheduler support" 1199 help 1200 Cluster scheduler support improves the CPU scheduler's decision 1201 making when dealing with machines that have clusters of CPUs. 1202 Cluster usually means a couple of CPUs which are placed closely 1203 by sharing mid-level caches, last-level cache tags or internal 1204 busses. 1205 1206config SCHED_SMT 1207 bool "SMT scheduler support" 1208 help 1209 Improves the CPU scheduler's decision making when dealing with 1210 MultiThreading at a cost of slightly increased overhead in some 1211 places. If unsure say N here. 1212 1213config NR_CPUS 1214 int "Maximum number of CPUs (2-4096)" 1215 range 2 4096 1216 default "256" 1217 1218config HOTPLUG_CPU 1219 bool "Support for hot-pluggable CPUs" 1220 select GENERIC_IRQ_MIGRATION 1221 help 1222 Say Y here to experiment with turning CPUs off and on. CPUs 1223 can be controlled through /sys/devices/system/cpu. 1224 1225# Common NUMA Features 1226config NUMA 1227 bool "NUMA Memory Allocation and Scheduler Support" 1228 select GENERIC_ARCH_NUMA 1229 select ACPI_NUMA if ACPI 1230 select OF_NUMA 1231 select HAVE_SETUP_PER_CPU_AREA 1232 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1233 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1234 select USE_PERCPU_NUMA_NODE_ID 1235 help 1236 Enable NUMA (Non-Uniform Memory Access) support. 1237 1238 The kernel will try to allocate memory used by a CPU on the 1239 local memory of the CPU and add some more 1240 NUMA awareness to the kernel. 1241 1242config NODES_SHIFT 1243 int "Maximum NUMA Nodes (as a power of 2)" 1244 range 1 10 1245 default "4" 1246 depends on NUMA 1247 help 1248 Specify the maximum number of NUMA Nodes available on the target 1249 system. Increases memory reserved to accommodate various tables. 1250 1251source "kernel/Kconfig.hz" 1252 1253config ARCH_SPARSEMEM_ENABLE 1254 def_bool y 1255 select SPARSEMEM_VMEMMAP_ENABLE 1256 select SPARSEMEM_VMEMMAP 1257 1258config HW_PERF_EVENTS 1259 def_bool y 1260 depends on ARM_PMU 1261 1262# Supported by clang >= 7.0 or GCC >= 12.0.0 1263config CC_HAVE_SHADOW_CALL_STACK 1264 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1265 1266config PARAVIRT 1267 bool "Enable paravirtualization code" 1268 help 1269 This changes the kernel so it can modify itself when it is run 1270 under a hypervisor, potentially improving performance significantly 1271 over full virtualization. 1272 1273config PARAVIRT_TIME_ACCOUNTING 1274 bool "Paravirtual steal time accounting" 1275 select PARAVIRT 1276 help 1277 Select this option to enable fine granularity task steal time 1278 accounting. Time spent executing other tasks in parallel with 1279 the current vCPU is discounted from the vCPU power. To account for 1280 that, there can be a small performance impact. 1281 1282 If in doubt, say N here. 1283 1284config KEXEC 1285 depends on PM_SLEEP_SMP 1286 select KEXEC_CORE 1287 bool "kexec system call" 1288 help 1289 kexec is a system call that implements the ability to shutdown your 1290 current kernel, and to start another kernel. It is like a reboot 1291 but it is independent of the system firmware. And like a reboot 1292 you can start any kernel with it, not just Linux. 1293 1294config KEXEC_FILE 1295 bool "kexec file based system call" 1296 select KEXEC_CORE 1297 select HAVE_IMA_KEXEC if IMA 1298 help 1299 This is new version of kexec system call. This system call is 1300 file based and takes file descriptors as system call argument 1301 for kernel and initramfs as opposed to list of segments as 1302 accepted by previous system call. 1303 1304config KEXEC_SIG 1305 bool "Verify kernel signature during kexec_file_load() syscall" 1306 depends on KEXEC_FILE 1307 help 1308 Select this option to verify a signature with loaded kernel 1309 image. If configured, any attempt of loading a image without 1310 valid signature will fail. 1311 1312 In addition to that option, you need to enable signature 1313 verification for the corresponding kernel image type being 1314 loaded in order for this to work. 1315 1316config KEXEC_IMAGE_VERIFY_SIG 1317 bool "Enable Image signature verification support" 1318 default y 1319 depends on KEXEC_SIG 1320 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1321 help 1322 Enable Image signature verification support. 1323 1324comment "Support for PE file signature verification disabled" 1325 depends on KEXEC_SIG 1326 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1327 1328config CRASH_DUMP 1329 bool "Build kdump crash kernel" 1330 help 1331 Generate crash dump after being started by kexec. This should 1332 be normally only set in special crash dump kernels which are 1333 loaded in the main kernel with kexec-tools into a specially 1334 reserved region and then later executed after a crash by 1335 kdump/kexec. 1336 1337 For more details see Documentation/admin-guide/kdump/kdump.rst 1338 1339config TRANS_TABLE 1340 def_bool y 1341 depends on HIBERNATION || KEXEC_CORE 1342 1343config XEN_DOM0 1344 def_bool y 1345 depends on XEN 1346 1347config XEN 1348 bool "Xen guest support on ARM64" 1349 depends on ARM64 && OF 1350 select SWIOTLB_XEN 1351 select PARAVIRT 1352 help 1353 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1354 1355config FORCE_MAX_ZONEORDER 1356 int 1357 default "14" if ARM64_64K_PAGES 1358 default "12" if ARM64_16K_PAGES 1359 default "11" 1360 help 1361 The kernel memory allocator divides physically contiguous memory 1362 blocks into "zones", where each zone is a power of two number of 1363 pages. This option selects the largest power of two that the kernel 1364 keeps in the memory allocator. If you need to allocate very large 1365 blocks of physically contiguous memory, then you may need to 1366 increase this value. 1367 1368 This config option is actually maximum order plus one. For example, 1369 a value of 11 means that the largest free memory block is 2^10 pages. 1370 1371 We make sure that we can allocate upto a HugePage size for each configuration. 1372 Hence we have : 1373 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1374 1375 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1376 4M allocations matching the default size used by generic code. 1377 1378config UNMAP_KERNEL_AT_EL0 1379 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1380 default y 1381 help 1382 Speculation attacks against some high-performance processors can 1383 be used to bypass MMU permission checks and leak kernel data to 1384 userspace. This can be defended against by unmapping the kernel 1385 when running in userspace, mapping it back in on exception entry 1386 via a trampoline page in the vector table. 1387 1388 If unsure, say Y. 1389 1390config MITIGATE_SPECTRE_BRANCH_HISTORY 1391 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1392 default y 1393 help 1394 Speculation attacks against some high-performance processors can 1395 make use of branch history to influence future speculation. 1396 When taking an exception from user-space, a sequence of branches 1397 or a firmware call overwrites the branch history. 1398 1399config RODATA_FULL_DEFAULT_ENABLED 1400 bool "Apply r/o permissions of VM areas also to their linear aliases" 1401 default y 1402 help 1403 Apply read-only attributes of VM areas to the linear alias of 1404 the backing pages as well. This prevents code or read-only data 1405 from being modified (inadvertently or intentionally) via another 1406 mapping of the same memory page. This additional enhancement can 1407 be turned off at runtime by passing rodata=[off|on] (and turned on 1408 with rodata=full if this option is set to 'n') 1409 1410 This requires the linear region to be mapped down to pages, 1411 which may adversely affect performance in some cases. 1412 1413config ARM64_SW_TTBR0_PAN 1414 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1415 help 1416 Enabling this option prevents the kernel from accessing 1417 user-space memory directly by pointing TTBR0_EL1 to a reserved 1418 zeroed area and reserved ASID. The user access routines 1419 restore the valid TTBR0_EL1 temporarily. 1420 1421config ARM64_TAGGED_ADDR_ABI 1422 bool "Enable the tagged user addresses syscall ABI" 1423 default y 1424 help 1425 When this option is enabled, user applications can opt in to a 1426 relaxed ABI via prctl() allowing tagged addresses to be passed 1427 to system calls as pointer arguments. For details, see 1428 Documentation/arm64/tagged-address-abi.rst. 1429 1430menuconfig COMPAT 1431 bool "Kernel support for 32-bit EL0" 1432 depends on ARM64_4K_PAGES || EXPERT 1433 select HAVE_UID16 1434 select OLD_SIGSUSPEND3 1435 select COMPAT_OLD_SIGACTION 1436 help 1437 This option enables support for a 32-bit EL0 running under a 64-bit 1438 kernel at EL1. AArch32-specific components such as system calls, 1439 the user helper functions, VFP support and the ptrace interface are 1440 handled appropriately by the kernel. 1441 1442 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1443 that you will only be able to execute AArch32 binaries that were compiled 1444 with page size aligned segments. 1445 1446 If you want to execute 32-bit userspace applications, say Y. 1447 1448if COMPAT 1449 1450config KUSER_HELPERS 1451 bool "Enable kuser helpers page for 32-bit applications" 1452 default y 1453 help 1454 Warning: disabling this option may break 32-bit user programs. 1455 1456 Provide kuser helpers to compat tasks. The kernel provides 1457 helper code to userspace in read only form at a fixed location 1458 to allow userspace to be independent of the CPU type fitted to 1459 the system. This permits binaries to be run on ARMv4 through 1460 to ARMv8 without modification. 1461 1462 See Documentation/arm/kernel_user_helpers.rst for details. 1463 1464 However, the fixed address nature of these helpers can be used 1465 by ROP (return orientated programming) authors when creating 1466 exploits. 1467 1468 If all of the binaries and libraries which run on your platform 1469 are built specifically for your platform, and make no use of 1470 these helpers, then you can turn this option off to hinder 1471 such exploits. However, in that case, if a binary or library 1472 relying on those helpers is run, it will not function correctly. 1473 1474 Say N here only if you are absolutely certain that you do not 1475 need these helpers; otherwise, the safe option is to say Y. 1476 1477config COMPAT_VDSO 1478 bool "Enable vDSO for 32-bit applications" 1479 depends on !CPU_BIG_ENDIAN 1480 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1481 select GENERIC_COMPAT_VDSO 1482 default y 1483 help 1484 Place in the process address space of 32-bit applications an 1485 ELF shared object providing fast implementations of gettimeofday 1486 and clock_gettime. 1487 1488 You must have a 32-bit build of glibc 2.22 or later for programs 1489 to seamlessly take advantage of this. 1490 1491config THUMB2_COMPAT_VDSO 1492 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1493 depends on COMPAT_VDSO 1494 default y 1495 help 1496 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1497 otherwise with '-marm'. 1498 1499menuconfig ARMV8_DEPRECATED 1500 bool "Emulate deprecated/obsolete ARMv8 instructions" 1501 depends on SYSCTL 1502 help 1503 Legacy software support may require certain instructions 1504 that have been deprecated or obsoleted in the architecture. 1505 1506 Enable this config to enable selective emulation of these 1507 features. 1508 1509 If unsure, say Y 1510 1511if ARMV8_DEPRECATED 1512 1513config SWP_EMULATION 1514 bool "Emulate SWP/SWPB instructions" 1515 help 1516 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1517 they are always undefined. Say Y here to enable software 1518 emulation of these instructions for userspace using LDXR/STXR. 1519 This feature can be controlled at runtime with the abi.swp 1520 sysctl which is disabled by default. 1521 1522 In some older versions of glibc [<=2.8] SWP is used during futex 1523 trylock() operations with the assumption that the code will not 1524 be preempted. This invalid assumption may be more likely to fail 1525 with SWP emulation enabled, leading to deadlock of the user 1526 application. 1527 1528 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1529 on an external transaction monitoring block called a global 1530 monitor to maintain update atomicity. If your system does not 1531 implement a global monitor, this option can cause programs that 1532 perform SWP operations to uncached memory to deadlock. 1533 1534 If unsure, say Y 1535 1536config CP15_BARRIER_EMULATION 1537 bool "Emulate CP15 Barrier instructions" 1538 help 1539 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1540 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1541 strongly recommended to use the ISB, DSB, and DMB 1542 instructions instead. 1543 1544 Say Y here to enable software emulation of these 1545 instructions for AArch32 userspace code. When this option is 1546 enabled, CP15 barrier usage is traced which can help 1547 identify software that needs updating. This feature can be 1548 controlled at runtime with the abi.cp15_barrier sysctl. 1549 1550 If unsure, say Y 1551 1552config SETEND_EMULATION 1553 bool "Emulate SETEND instruction" 1554 help 1555 The SETEND instruction alters the data-endianness of the 1556 AArch32 EL0, and is deprecated in ARMv8. 1557 1558 Say Y here to enable software emulation of the instruction 1559 for AArch32 userspace code. This feature can be controlled 1560 at runtime with the abi.setend sysctl. 1561 1562 Note: All the cpus on the system must have mixed endian support at EL0 1563 for this feature to be enabled. If a new CPU - which doesn't support mixed 1564 endian - is hotplugged in after this feature has been enabled, there could 1565 be unexpected results in the applications. 1566 1567 If unsure, say Y 1568endif 1569 1570endif 1571 1572menu "ARMv8.1 architectural features" 1573 1574config ARM64_HW_AFDBM 1575 bool "Support for hardware updates of the Access and Dirty page flags" 1576 default y 1577 help 1578 The ARMv8.1 architecture extensions introduce support for 1579 hardware updates of the access and dirty information in page 1580 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1581 capable processors, accesses to pages with PTE_AF cleared will 1582 set this bit instead of raising an access flag fault. 1583 Similarly, writes to read-only pages with the DBM bit set will 1584 clear the read-only bit (AP[2]) instead of raising a 1585 permission fault. 1586 1587 Kernels built with this configuration option enabled continue 1588 to work on pre-ARMv8.1 hardware and the performance impact is 1589 minimal. If unsure, say Y. 1590 1591config ARM64_PAN 1592 bool "Enable support for Privileged Access Never (PAN)" 1593 default y 1594 help 1595 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1596 prevents the kernel or hypervisor from accessing user-space (EL0) 1597 memory directly. 1598 1599 Choosing this option will cause any unprotected (not using 1600 copy_to_user et al) memory access to fail with a permission fault. 1601 1602 The feature is detected at runtime, and will remain as a 'nop' 1603 instruction if the cpu does not implement the feature. 1604 1605config AS_HAS_LDAPR 1606 def_bool $(as-instr,.arch_extension rcpc) 1607 1608config AS_HAS_LSE_ATOMICS 1609 def_bool $(as-instr,.arch_extension lse) 1610 1611config ARM64_LSE_ATOMICS 1612 bool 1613 default ARM64_USE_LSE_ATOMICS 1614 depends on AS_HAS_LSE_ATOMICS 1615 1616config ARM64_USE_LSE_ATOMICS 1617 bool "Atomic instructions" 1618 depends on JUMP_LABEL 1619 default y 1620 help 1621 As part of the Large System Extensions, ARMv8.1 introduces new 1622 atomic instructions that are designed specifically to scale in 1623 very large systems. 1624 1625 Say Y here to make use of these instructions for the in-kernel 1626 atomic routines. This incurs a small overhead on CPUs that do 1627 not support these instructions and requires the kernel to be 1628 built with binutils >= 2.25 in order for the new instructions 1629 to be used. 1630 1631endmenu 1632 1633menu "ARMv8.2 architectural features" 1634 1635config AS_HAS_ARMV8_2 1636 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1637 1638config AS_HAS_SHA3 1639 def_bool $(as-instr,.arch armv8.2-a+sha3) 1640 1641config ARM64_PMEM 1642 bool "Enable support for persistent memory" 1643 select ARCH_HAS_PMEM_API 1644 select ARCH_HAS_UACCESS_FLUSHCACHE 1645 help 1646 Say Y to enable support for the persistent memory API based on the 1647 ARMv8.2 DCPoP feature. 1648 1649 The feature is detected at runtime, and the kernel will use DC CVAC 1650 operations if DC CVAP is not supported (following the behaviour of 1651 DC CVAP itself if the system does not define a point of persistence). 1652 1653config ARM64_RAS_EXTN 1654 bool "Enable support for RAS CPU Extensions" 1655 default y 1656 help 1657 CPUs that support the Reliability, Availability and Serviceability 1658 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1659 errors, classify them and report them to software. 1660 1661 On CPUs with these extensions system software can use additional 1662 barriers to determine if faults are pending and read the 1663 classification from a new set of registers. 1664 1665 Selecting this feature will allow the kernel to use these barriers 1666 and access the new registers if the system supports the extension. 1667 Platform RAS features may additionally depend on firmware support. 1668 1669config ARM64_CNP 1670 bool "Enable support for Common Not Private (CNP) translations" 1671 default y 1672 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1673 help 1674 Common Not Private (CNP) allows translation table entries to 1675 be shared between different PEs in the same inner shareable 1676 domain, so the hardware can use this fact to optimise the 1677 caching of such entries in the TLB. 1678 1679 Selecting this option allows the CNP feature to be detected 1680 at runtime, and does not affect PEs that do not implement 1681 this feature. 1682 1683endmenu 1684 1685menu "ARMv8.3 architectural features" 1686 1687config ARM64_PTR_AUTH 1688 bool "Enable support for pointer authentication" 1689 default y 1690 help 1691 Pointer authentication (part of the ARMv8.3 Extensions) provides 1692 instructions for signing and authenticating pointers against secret 1693 keys, which can be used to mitigate Return Oriented Programming (ROP) 1694 and other attacks. 1695 1696 This option enables these instructions at EL0 (i.e. for userspace). 1697 Choosing this option will cause the kernel to initialise secret keys 1698 for each process at exec() time, with these keys being 1699 context-switched along with the process. 1700 1701 The feature is detected at runtime. If the feature is not present in 1702 hardware it will not be advertised to userspace/KVM guest nor will it 1703 be enabled. 1704 1705 If the feature is present on the boot CPU but not on a late CPU, then 1706 the late CPU will be parked. Also, if the boot CPU does not have 1707 address auth and the late CPU has then the late CPU will still boot 1708 but with the feature disabled. On such a system, this option should 1709 not be selected. 1710 1711config ARM64_PTR_AUTH_KERNEL 1712 bool "Use pointer authentication for kernel" 1713 default y 1714 depends on ARM64_PTR_AUTH 1715 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1716 # Modern compilers insert a .note.gnu.property section note for PAC 1717 # which is only understood by binutils starting with version 2.33.1. 1718 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1719 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1720 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1721 help 1722 If the compiler supports the -mbranch-protection or 1723 -msign-return-address flag (e.g. GCC 7 or later), then this option 1724 will cause the kernel itself to be compiled with return address 1725 protection. In this case, and if the target hardware is known to 1726 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1727 disabled with minimal loss of protection. 1728 1729 This feature works with FUNCTION_GRAPH_TRACER option only if 1730 DYNAMIC_FTRACE_WITH_REGS is enabled. 1731 1732config CC_HAS_BRANCH_PROT_PAC_RET 1733 # GCC 9 or later, clang 8 or later 1734 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1735 1736config CC_HAS_SIGN_RETURN_ADDRESS 1737 # GCC 7, 8 1738 def_bool $(cc-option,-msign-return-address=all) 1739 1740config AS_HAS_PAC 1741 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1742 1743config AS_HAS_CFI_NEGATE_RA_STATE 1744 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1745 1746endmenu 1747 1748menu "ARMv8.4 architectural features" 1749 1750config ARM64_AMU_EXTN 1751 bool "Enable support for the Activity Monitors Unit CPU extension" 1752 default y 1753 help 1754 The activity monitors extension is an optional extension introduced 1755 by the ARMv8.4 CPU architecture. This enables support for version 1 1756 of the activity monitors architecture, AMUv1. 1757 1758 To enable the use of this extension on CPUs that implement it, say Y. 1759 1760 Note that for architectural reasons, firmware _must_ implement AMU 1761 support when running on CPUs that present the activity monitors 1762 extension. The required support is present in: 1763 * Version 1.5 and later of the ARM Trusted Firmware 1764 1765 For kernels that have this configuration enabled but boot with broken 1766 firmware, you may need to say N here until the firmware is fixed. 1767 Otherwise you may experience firmware panics or lockups when 1768 accessing the counter registers. Even if you are not observing these 1769 symptoms, the values returned by the register reads might not 1770 correctly reflect reality. Most commonly, the value read will be 0, 1771 indicating that the counter is not enabled. 1772 1773config AS_HAS_ARMV8_4 1774 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1775 1776config ARM64_TLB_RANGE 1777 bool "Enable support for tlbi range feature" 1778 default y 1779 depends on AS_HAS_ARMV8_4 1780 help 1781 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1782 range of input addresses. 1783 1784 The feature introduces new assembly instructions, and they were 1785 support when binutils >= 2.30. 1786 1787endmenu 1788 1789menu "ARMv8.5 architectural features" 1790 1791config AS_HAS_ARMV8_5 1792 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1793 1794config ARM64_BTI 1795 bool "Branch Target Identification support" 1796 default y 1797 help 1798 Branch Target Identification (part of the ARMv8.5 Extensions) 1799 provides a mechanism to limit the set of locations to which computed 1800 branch instructions such as BR or BLR can jump. 1801 1802 To make use of BTI on CPUs that support it, say Y. 1803 1804 BTI is intended to provide complementary protection to other control 1805 flow integrity protection mechanisms, such as the Pointer 1806 authentication mechanism provided as part of the ARMv8.3 Extensions. 1807 For this reason, it does not make sense to enable this option without 1808 also enabling support for pointer authentication. Thus, when 1809 enabling this option you should also select ARM64_PTR_AUTH=y. 1810 1811 Userspace binaries must also be specifically compiled to make use of 1812 this mechanism. If you say N here or the hardware does not support 1813 BTI, such binaries can still run, but you get no additional 1814 enforcement of branch destinations. 1815 1816config ARM64_BTI_KERNEL 1817 bool "Use Branch Target Identification for kernel" 1818 default y 1819 depends on ARM64_BTI 1820 depends on ARM64_PTR_AUTH_KERNEL 1821 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1822 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1823 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1824 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1825 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1826 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1827 help 1828 Build the kernel with Branch Target Identification annotations 1829 and enable enforcement of this for kernel code. When this option 1830 is enabled and the system supports BTI all kernel code including 1831 modular code must have BTI enabled. 1832 1833config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1834 # GCC 9 or later, clang 8 or later 1835 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1836 1837config ARM64_E0PD 1838 bool "Enable support for E0PD" 1839 default y 1840 help 1841 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1842 that EL0 accesses made via TTBR1 always fault in constant time, 1843 providing similar benefits to KASLR as those provided by KPTI, but 1844 with lower overhead and without disrupting legitimate access to 1845 kernel memory such as SPE. 1846 1847 This option enables E0PD for TTBR1 where available. 1848 1849config ARCH_RANDOM 1850 bool "Enable support for random number generation" 1851 default y 1852 help 1853 Random number generation (part of the ARMv8.5 Extensions) 1854 provides a high bandwidth, cryptographically secure 1855 hardware random number generator. 1856 1857config ARM64_AS_HAS_MTE 1858 # Initial support for MTE went in binutils 2.32.0, checked with 1859 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1860 # as a late addition to the final architecture spec (LDGM/STGM) 1861 # is only supported in the newer 2.32.x and 2.33 binutils 1862 # versions, hence the extra "stgm" instruction check below. 1863 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1864 1865config ARM64_MTE 1866 bool "Memory Tagging Extension support" 1867 default y 1868 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1869 depends on AS_HAS_ARMV8_5 1870 depends on AS_HAS_LSE_ATOMICS 1871 # Required for tag checking in the uaccess routines 1872 depends on ARM64_PAN 1873 select ARCH_USES_HIGH_VMA_FLAGS 1874 help 1875 Memory Tagging (part of the ARMv8.5 Extensions) provides 1876 architectural support for run-time, always-on detection of 1877 various classes of memory error to aid with software debugging 1878 to eliminate vulnerabilities arising from memory-unsafe 1879 languages. 1880 1881 This option enables the support for the Memory Tagging 1882 Extension at EL0 (i.e. for userspace). 1883 1884 Selecting this option allows the feature to be detected at 1885 runtime. Any secondary CPU not implementing this feature will 1886 not be allowed a late bring-up. 1887 1888 Userspace binaries that want to use this feature must 1889 explicitly opt in. The mechanism for the userspace is 1890 described in: 1891 1892 Documentation/arm64/memory-tagging-extension.rst. 1893 1894endmenu 1895 1896menu "ARMv8.7 architectural features" 1897 1898config ARM64_EPAN 1899 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1900 default y 1901 depends on ARM64_PAN 1902 help 1903 Enhanced Privileged Access Never (EPAN) allows Privileged 1904 Access Never to be used with Execute-only mappings. 1905 1906 The feature is detected at runtime, and will remain disabled 1907 if the cpu does not implement the feature. 1908endmenu 1909 1910config ARM64_SVE 1911 bool "ARM Scalable Vector Extension support" 1912 default y 1913 help 1914 The Scalable Vector Extension (SVE) is an extension to the AArch64 1915 execution state which complements and extends the SIMD functionality 1916 of the base architecture to support much larger vectors and to enable 1917 additional vectorisation opportunities. 1918 1919 To enable use of this extension on CPUs that implement it, say Y. 1920 1921 On CPUs that support the SVE2 extensions, this option will enable 1922 those too. 1923 1924 Note that for architectural reasons, firmware _must_ implement SVE 1925 support when running on SVE capable hardware. The required support 1926 is present in: 1927 1928 * version 1.5 and later of the ARM Trusted Firmware 1929 * the AArch64 boot wrapper since commit 5e1261e08abf 1930 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1931 1932 For other firmware implementations, consult the firmware documentation 1933 or vendor. 1934 1935 If you need the kernel to boot on SVE-capable hardware with broken 1936 firmware, you may need to say N here until you get your firmware 1937 fixed. Otherwise, you may experience firmware panics or lockups when 1938 booting the kernel. If unsure and you are not observing these 1939 symptoms, you should assume that it is safe to say Y. 1940 1941config ARM64_MODULE_PLTS 1942 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1943 depends on MODULES 1944 select HAVE_MOD_ARCH_SPECIFIC 1945 help 1946 Allocate PLTs when loading modules so that jumps and calls whose 1947 targets are too far away for their relative offsets to be encoded 1948 in the instructions themselves can be bounced via veneers in the 1949 module's PLT. This allows modules to be allocated in the generic 1950 vmalloc area after the dedicated module memory area has been 1951 exhausted. 1952 1953 When running with address space randomization (KASLR), the module 1954 region itself may be too far away for ordinary relative jumps and 1955 calls, and so in that case, module PLTs are required and cannot be 1956 disabled. 1957 1958 Specific errata workaround(s) might also force module PLTs to be 1959 enabled (ARM64_ERRATUM_843419). 1960 1961config ARM64_PSEUDO_NMI 1962 bool "Support for NMI-like interrupts" 1963 select ARM_GIC_V3 1964 help 1965 Adds support for mimicking Non-Maskable Interrupts through the use of 1966 GIC interrupt priority. This support requires version 3 or later of 1967 ARM GIC. 1968 1969 This high priority configuration for interrupts needs to be 1970 explicitly enabled by setting the kernel parameter 1971 "irqchip.gicv3_pseudo_nmi" to 1. 1972 1973 If unsure, say N 1974 1975if ARM64_PSEUDO_NMI 1976config ARM64_DEBUG_PRIORITY_MASKING 1977 bool "Debug interrupt priority masking" 1978 help 1979 This adds runtime checks to functions enabling/disabling 1980 interrupts when using priority masking. The additional checks verify 1981 the validity of ICC_PMR_EL1 when calling concerned functions. 1982 1983 If unsure, say N 1984endif 1985 1986config RELOCATABLE 1987 bool "Build a relocatable kernel image" if EXPERT 1988 select ARCH_HAS_RELR 1989 default y 1990 help 1991 This builds the kernel as a Position Independent Executable (PIE), 1992 which retains all relocation metadata required to relocate the 1993 kernel binary at runtime to a different virtual address than the 1994 address it was linked at. 1995 Since AArch64 uses the RELA relocation format, this requires a 1996 relocation pass at runtime even if the kernel is loaded at the 1997 same address it was linked at. 1998 1999config RANDOMIZE_BASE 2000 bool "Randomize the address of the kernel image" 2001 select ARM64_MODULE_PLTS if MODULES 2002 select RELOCATABLE 2003 help 2004 Randomizes the virtual address at which the kernel image is 2005 loaded, as a security feature that deters exploit attempts 2006 relying on knowledge of the location of kernel internals. 2007 2008 It is the bootloader's job to provide entropy, by passing a 2009 random u64 value in /chosen/kaslr-seed at kernel entry. 2010 2011 When booting via the UEFI stub, it will invoke the firmware's 2012 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2013 to the kernel proper. In addition, it will randomise the physical 2014 location of the kernel Image as well. 2015 2016 If unsure, say N. 2017 2018config RANDOMIZE_MODULE_REGION_FULL 2019 bool "Randomize the module region over a 2 GB range" 2020 depends on RANDOMIZE_BASE 2021 default y 2022 help 2023 Randomizes the location of the module region inside a 2 GB window 2024 covering the core kernel. This way, it is less likely for modules 2025 to leak information about the location of core kernel data structures 2026 but it does imply that function calls between modules and the core 2027 kernel will need to be resolved via veneers in the module PLT. 2028 2029 When this option is not set, the module region will be randomized over 2030 a limited range that contains the [_stext, _etext] interval of the 2031 core kernel, so branch relocations are almost always in range unless 2032 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2033 particular case of region exhaustion, modules might be able to fall 2034 back to a larger 2GB area. 2035 2036config CC_HAVE_STACKPROTECTOR_SYSREG 2037 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2038 2039config STACKPROTECTOR_PER_TASK 2040 def_bool y 2041 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2042 2043endmenu 2044 2045menu "Boot options" 2046 2047config ARM64_ACPI_PARKING_PROTOCOL 2048 bool "Enable support for the ARM64 ACPI parking protocol" 2049 depends on ACPI 2050 help 2051 Enable support for the ARM64 ACPI parking protocol. If disabled 2052 the kernel will not allow booting through the ARM64 ACPI parking 2053 protocol even if the corresponding data is present in the ACPI 2054 MADT table. 2055 2056config CMDLINE 2057 string "Default kernel command string" 2058 default "" 2059 help 2060 Provide a set of default command-line options at build time by 2061 entering them here. As a minimum, you should specify the the 2062 root device (e.g. root=/dev/nfs). 2063 2064choice 2065 prompt "Kernel command line type" if CMDLINE != "" 2066 default CMDLINE_FROM_BOOTLOADER 2067 help 2068 Choose how the kernel will handle the provided default kernel 2069 command line string. 2070 2071config CMDLINE_FROM_BOOTLOADER 2072 bool "Use bootloader kernel arguments if available" 2073 help 2074 Uses the command-line options passed by the boot loader. If 2075 the boot loader doesn't provide any, the default kernel command 2076 string provided in CMDLINE will be used. 2077 2078config CMDLINE_FORCE 2079 bool "Always use the default kernel command string" 2080 help 2081 Always use the default kernel command string, even if the boot 2082 loader passes other arguments to the kernel. 2083 This is useful if you cannot or don't want to change the 2084 command-line options your boot loader passes to the kernel. 2085 2086endchoice 2087 2088config EFI_STUB 2089 bool 2090 2091config EFI 2092 bool "UEFI runtime support" 2093 depends on OF && !CPU_BIG_ENDIAN 2094 depends on KERNEL_MODE_NEON 2095 select ARCH_SUPPORTS_ACPI 2096 select LIBFDT 2097 select UCS2_STRING 2098 select EFI_PARAMS_FROM_FDT 2099 select EFI_RUNTIME_WRAPPERS 2100 select EFI_STUB 2101 select EFI_GENERIC_STUB 2102 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2103 default y 2104 help 2105 This option provides support for runtime services provided 2106 by UEFI firmware (such as non-volatile variables, realtime 2107 clock, and platform reset). A UEFI stub is also provided to 2108 allow the kernel to be booted as an EFI application. This 2109 is only useful on systems that have UEFI firmware. 2110 2111config DMI 2112 bool "Enable support for SMBIOS (DMI) tables" 2113 depends on EFI 2114 default y 2115 help 2116 This enables SMBIOS/DMI feature for systems. 2117 2118 This option is only useful on systems that have UEFI firmware. 2119 However, even with this option, the resultant kernel should 2120 continue to boot on existing non-UEFI platforms. 2121 2122endmenu 2123 2124config SYSVIPC_COMPAT 2125 def_bool y 2126 depends on COMPAT && SYSVIPC 2127 2128menu "Power management options" 2129 2130source "kernel/power/Kconfig" 2131 2132config ARCH_HIBERNATION_POSSIBLE 2133 def_bool y 2134 depends on CPU_PM 2135 2136config ARCH_HIBERNATION_HEADER 2137 def_bool y 2138 depends on HIBERNATION 2139 2140config ARCH_SUSPEND_POSSIBLE 2141 def_bool y 2142 2143endmenu 2144 2145menu "CPU Power Management" 2146 2147source "drivers/cpuidle/Kconfig" 2148 2149source "drivers/cpufreq/Kconfig" 2150 2151endmenu 2152 2153source "drivers/acpi/Kconfig" 2154 2155source "arch/arm64/kvm/Kconfig" 2156 2157if CRYPTO 2158source "arch/arm64/crypto/Kconfig" 2159endif 2160