xref: /linux/arch/arm64/Kconfig (revision b85d45947951d23cb22d90caecf4c1eb81342c96)
1config ARM64
2	def_bool y
3	select ACPI_CCA_REQUIRED if ACPI
4	select ACPI_GENERIC_GSI if ACPI
5	select ACPI_REDUCED_HARDWARE_ONLY if ACPI
6	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
7	select ARCH_HAS_ELF_RANDOMIZE
8	select ARCH_HAS_GCOV_PROFILE_ALL
9	select ARCH_HAS_SG_CHAIN
10	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
11	select ARCH_USE_CMPXCHG_LOCKREF
12	select ARCH_SUPPORTS_ATOMIC_RMW
13	select ARCH_WANT_OPTIONAL_GPIOLIB
14	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
15	select ARCH_WANT_FRAME_POINTERS
16	select ARM_AMBA
17	select ARM_ARCH_TIMER
18	select ARM_GIC
19	select AUDIT_ARCH_COMPAT_GENERIC
20	select ARM_GIC_V2M if PCI_MSI
21	select ARM_GIC_V3
22	select ARM_GIC_V3_ITS if PCI_MSI
23	select ARM_PSCI_FW
24	select BUILDTIME_EXTABLE_SORT
25	select CLONE_BACKWARDS
26	select COMMON_CLK
27	select CPU_PM if (SUSPEND || CPU_IDLE)
28	select DCACHE_WORD_ACCESS
29	select EDAC_SUPPORT
30	select GENERIC_ALLOCATOR
31	select GENERIC_CLOCKEVENTS
32	select GENERIC_CLOCKEVENTS_BROADCAST
33	select GENERIC_CPU_AUTOPROBE
34	select GENERIC_EARLY_IOREMAP
35	select GENERIC_IDLE_POLL_SETUP
36	select GENERIC_IRQ_PROBE
37	select GENERIC_IRQ_SHOW
38	select GENERIC_IRQ_SHOW_LEVEL
39	select GENERIC_PCI_IOMAP
40	select GENERIC_SCHED_CLOCK
41	select GENERIC_SMP_IDLE_THREAD
42	select GENERIC_STRNCPY_FROM_USER
43	select GENERIC_STRNLEN_USER
44	select GENERIC_TIME_VSYSCALL
45	select HANDLE_DOMAIN_IRQ
46	select HARDIRQS_SW_RESEND
47	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
48	select HAVE_ARCH_AUDITSYSCALL
49	select HAVE_ARCH_BITREVERSE
50	select HAVE_ARCH_JUMP_LABEL
51	select HAVE_ARCH_KGDB
52	select HAVE_ARCH_SECCOMP_FILTER
53	select HAVE_ARCH_TRACEHOOK
54	select HAVE_BPF_JIT
55	select HAVE_C_RECORDMCOUNT
56	select HAVE_CC_STACKPROTECTOR
57	select HAVE_CMPXCHG_DOUBLE
58	select HAVE_CMPXCHG_LOCAL
59	select HAVE_DEBUG_BUGVERBOSE
60	select HAVE_DEBUG_KMEMLEAK
61	select HAVE_DMA_API_DEBUG
62	select HAVE_DMA_ATTRS
63	select HAVE_DMA_CONTIGUOUS
64	select HAVE_DYNAMIC_FTRACE
65	select HAVE_EFFICIENT_UNALIGNED_ACCESS
66	select HAVE_FTRACE_MCOUNT_RECORD
67	select HAVE_FUNCTION_TRACER
68	select HAVE_FUNCTION_GRAPH_TRACER
69	select HAVE_GENERIC_DMA_COHERENT
70	select HAVE_HW_BREAKPOINT if PERF_EVENTS
71	select HAVE_MEMBLOCK
72	select HAVE_PATA_PLATFORM
73	select HAVE_PERF_EVENTS
74	select HAVE_PERF_REGS
75	select HAVE_PERF_USER_STACK_DUMP
76	select HAVE_RCU_TABLE_FREE
77	select HAVE_SYSCALL_TRACEPOINTS
78	select IRQ_DOMAIN
79	select IRQ_FORCED_THREADING
80	select MODULES_USE_ELF_RELA
81	select NO_BOOTMEM
82	select OF
83	select OF_EARLY_FLATTREE
84	select OF_RESERVED_MEM
85	select PERF_USE_VMALLOC
86	select POWER_RESET
87	select POWER_SUPPLY
88	select RTC_LIB
89	select SPARSE_IRQ
90	select SYSCTL_EXCEPTION_TRACE
91	select HAVE_CONTEXT_TRACKING
92	help
93	  ARM 64-bit (AArch64) Linux support.
94
95config 64BIT
96	def_bool y
97
98config ARCH_PHYS_ADDR_T_64BIT
99	def_bool y
100
101config MMU
102	def_bool y
103
104config NO_IOPORT_MAP
105	def_bool y if !PCI
106
107config STACKTRACE_SUPPORT
108	def_bool y
109
110config ILLEGAL_POINTER_VALUE
111	hex
112	default 0xdead000000000000
113
114config LOCKDEP_SUPPORT
115	def_bool y
116
117config TRACE_IRQFLAGS_SUPPORT
118	def_bool y
119
120config RWSEM_XCHGADD_ALGORITHM
121	def_bool y
122
123config GENERIC_BUG
124	def_bool y
125	depends on BUG
126
127config GENERIC_BUG_RELATIVE_POINTERS
128	def_bool y
129	depends on GENERIC_BUG
130
131config GENERIC_HWEIGHT
132	def_bool y
133
134config GENERIC_CSUM
135        def_bool y
136
137config GENERIC_CALIBRATE_DELAY
138	def_bool y
139
140config ZONE_DMA
141	def_bool y
142
143config HAVE_GENERIC_RCU_GUP
144	def_bool y
145
146config ARCH_DMA_ADDR_T_64BIT
147	def_bool y
148
149config NEED_DMA_MAP_STATE
150	def_bool y
151
152config NEED_SG_DMA_LENGTH
153	def_bool y
154
155config SMP
156	def_bool y
157
158config SWIOTLB
159	def_bool y
160
161config IOMMU_HELPER
162	def_bool SWIOTLB
163
164config KERNEL_MODE_NEON
165	def_bool y
166
167config FIX_EARLYCON_MEM
168	def_bool y
169
170config PGTABLE_LEVELS
171	int
172	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
173	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
174	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
175	default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
176
177source "init/Kconfig"
178
179source "kernel/Kconfig.freezer"
180
181source "arch/arm64/Kconfig.platforms"
182
183menu "Bus support"
184
185config PCI
186	bool "PCI support"
187	help
188	  This feature enables support for PCI bus system. If you say Y
189	  here, the kernel will include drivers and infrastructure code
190	  to support PCI bus devices.
191
192config PCI_DOMAINS
193	def_bool PCI
194
195config PCI_DOMAINS_GENERIC
196	def_bool PCI
197
198config PCI_SYSCALL
199	def_bool PCI
200
201source "drivers/pci/Kconfig"
202source "drivers/pci/pcie/Kconfig"
203source "drivers/pci/hotplug/Kconfig"
204
205endmenu
206
207menu "Kernel Features"
208
209menu "ARM errata workarounds via the alternatives framework"
210
211config ARM64_ERRATUM_826319
212	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
213	default y
214	help
215	  This option adds an alternative code sequence to work around ARM
216	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
217	  AXI master interface and an L2 cache.
218
219	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
220	  and is unable to accept a certain write via this interface, it will
221	  not progress on read data presented on the read data channel and the
222	  system can deadlock.
223
224	  The workaround promotes data cache clean instructions to
225	  data cache clean-and-invalidate.
226	  Please note that this does not necessarily enable the workaround,
227	  as it depends on the alternative framework, which will only patch
228	  the kernel if an affected CPU is detected.
229
230	  If unsure, say Y.
231
232config ARM64_ERRATUM_827319
233	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
234	default y
235	help
236	  This option adds an alternative code sequence to work around ARM
237	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
238	  master interface and an L2 cache.
239
240	  Under certain conditions this erratum can cause a clean line eviction
241	  to occur at the same time as another transaction to the same address
242	  on the AMBA 5 CHI interface, which can cause data corruption if the
243	  interconnect reorders the two transactions.
244
245	  The workaround promotes data cache clean instructions to
246	  data cache clean-and-invalidate.
247	  Please note that this does not necessarily enable the workaround,
248	  as it depends on the alternative framework, which will only patch
249	  the kernel if an affected CPU is detected.
250
251	  If unsure, say Y.
252
253config ARM64_ERRATUM_824069
254	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
255	default y
256	help
257	  This option adds an alternative code sequence to work around ARM
258	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
259	  to a coherent interconnect.
260
261	  If a Cortex-A53 processor is executing a store or prefetch for
262	  write instruction at the same time as a processor in another
263	  cluster is executing a cache maintenance operation to the same
264	  address, then this erratum might cause a clean cache line to be
265	  incorrectly marked as dirty.
266
267	  The workaround promotes data cache clean instructions to
268	  data cache clean-and-invalidate.
269	  Please note that this option does not necessarily enable the
270	  workaround, as it depends on the alternative framework, which will
271	  only patch the kernel if an affected CPU is detected.
272
273	  If unsure, say Y.
274
275config ARM64_ERRATUM_819472
276	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
277	default y
278	help
279	  This option adds an alternative code sequence to work around ARM
280	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
281	  present when it is connected to a coherent interconnect.
282
283	  If the processor is executing a load and store exclusive sequence at
284	  the same time as a processor in another cluster is executing a cache
285	  maintenance operation to the same address, then this erratum might
286	  cause data corruption.
287
288	  The workaround promotes data cache clean instructions to
289	  data cache clean-and-invalidate.
290	  Please note that this does not necessarily enable the workaround,
291	  as it depends on the alternative framework, which will only patch
292	  the kernel if an affected CPU is detected.
293
294	  If unsure, say Y.
295
296config ARM64_ERRATUM_832075
297	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
298	default y
299	help
300	  This option adds an alternative code sequence to work around ARM
301	  erratum 832075 on Cortex-A57 parts up to r1p2.
302
303	  Affected Cortex-A57 parts might deadlock when exclusive load/store
304	  instructions to Write-Back memory are mixed with Device loads.
305
306	  The workaround is to promote device loads to use Load-Acquire
307	  semantics.
308	  Please note that this does not necessarily enable the workaround,
309	  as it depends on the alternative framework, which will only patch
310	  the kernel if an affected CPU is detected.
311
312	  If unsure, say Y.
313
314config ARM64_ERRATUM_845719
315	bool "Cortex-A53: 845719: a load might read incorrect data"
316	depends on COMPAT
317	default y
318	help
319	  This option adds an alternative code sequence to work around ARM
320	  erratum 845719 on Cortex-A53 parts up to r0p4.
321
322	  When running a compat (AArch32) userspace on an affected Cortex-A53
323	  part, a load at EL0 from a virtual address that matches the bottom 32
324	  bits of the virtual address used by a recent load at (AArch64) EL1
325	  might return incorrect data.
326
327	  The workaround is to write the contextidr_el1 register on exception
328	  return to a 32-bit task.
329	  Please note that this does not necessarily enable the workaround,
330	  as it depends on the alternative framework, which will only patch
331	  the kernel if an affected CPU is detected.
332
333	  If unsure, say Y.
334
335config ARM64_ERRATUM_843419
336	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
337	depends on MODULES
338	default y
339	help
340	  This option builds kernel modules using the large memory model in
341	  order to avoid the use of the ADRP instruction, which can cause
342	  a subsequent memory access to use an incorrect address on Cortex-A53
343	  parts up to r0p4.
344
345	  Note that the kernel itself must be linked with a version of ld
346	  which fixes potentially affected ADRP instructions through the
347	  use of veneers.
348
349	  If unsure, say Y.
350
351endmenu
352
353
354choice
355	prompt "Page size"
356	default ARM64_4K_PAGES
357	help
358	  Page size (translation granule) configuration.
359
360config ARM64_4K_PAGES
361	bool "4KB"
362	help
363	  This feature enables 4KB pages support.
364
365config ARM64_64K_PAGES
366	bool "64KB"
367	help
368	  This feature enables 64KB pages support (4KB by default)
369	  allowing only two levels of page tables and faster TLB
370	  look-up. AArch32 emulation is not available when this feature
371	  is enabled.
372
373endchoice
374
375choice
376	prompt "Virtual address space size"
377	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
378	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
379	help
380	  Allows choosing one of multiple possible virtual address
381	  space sizes. The level of translation table is determined by
382	  a combination of page size and virtual address space size.
383
384config ARM64_VA_BITS_39
385	bool "39-bit"
386	depends on ARM64_4K_PAGES
387
388config ARM64_VA_BITS_42
389	bool "42-bit"
390	depends on ARM64_64K_PAGES
391
392config ARM64_VA_BITS_48
393	bool "48-bit"
394
395endchoice
396
397config ARM64_VA_BITS
398	int
399	default 39 if ARM64_VA_BITS_39
400	default 42 if ARM64_VA_BITS_42
401	default 48 if ARM64_VA_BITS_48
402
403config CPU_BIG_ENDIAN
404       bool "Build big-endian kernel"
405       help
406         Say Y if you plan on running a kernel in big-endian mode.
407
408config SCHED_MC
409	bool "Multi-core scheduler support"
410	help
411	  Multi-core scheduler support improves the CPU scheduler's decision
412	  making when dealing with multi-core CPU chips at a cost of slightly
413	  increased overhead in some places. If unsure say N here.
414
415config SCHED_SMT
416	bool "SMT scheduler support"
417	help
418	  Improves the CPU scheduler's decision making when dealing with
419	  MultiThreading at a cost of slightly increased overhead in some
420	  places. If unsure say N here.
421
422config NR_CPUS
423	int "Maximum number of CPUs (2-4096)"
424	range 2 4096
425	# These have to remain sorted largest to smallest
426	default "64"
427
428config HOTPLUG_CPU
429	bool "Support for hot-pluggable CPUs"
430	help
431	  Say Y here to experiment with turning CPUs off and on.  CPUs
432	  can be controlled through /sys/devices/system/cpu.
433
434source kernel/Kconfig.preempt
435
436config HZ
437	int
438	default 100
439
440config ARCH_HAS_HOLES_MEMORYMODEL
441	def_bool y if SPARSEMEM
442
443config ARCH_SPARSEMEM_ENABLE
444	def_bool y
445	select SPARSEMEM_VMEMMAP_ENABLE
446
447config ARCH_SPARSEMEM_DEFAULT
448	def_bool ARCH_SPARSEMEM_ENABLE
449
450config ARCH_SELECT_MEMORY_MODEL
451	def_bool ARCH_SPARSEMEM_ENABLE
452
453config HAVE_ARCH_PFN_VALID
454	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
455
456config HW_PERF_EVENTS
457	bool "Enable hardware performance counter support for perf events"
458	depends on PERF_EVENTS
459	default y
460	help
461	  Enable hardware performance counter support for perf events. If
462	  disabled, perf events will use software events only.
463
464config SYS_SUPPORTS_HUGETLBFS
465	def_bool y
466
467config ARCH_WANT_GENERAL_HUGETLB
468	def_bool y
469
470config ARCH_WANT_HUGE_PMD_SHARE
471	def_bool y if !ARM64_64K_PAGES
472
473config HAVE_ARCH_TRANSPARENT_HUGEPAGE
474	def_bool y
475
476config ARCH_HAS_CACHE_LINE_SIZE
477	def_bool y
478
479source "mm/Kconfig"
480
481config SECCOMP
482	bool "Enable seccomp to safely compute untrusted bytecode"
483	---help---
484	  This kernel feature is useful for number crunching applications
485	  that may need to compute untrusted bytecode during their
486	  execution. By using pipes or other transports made available to
487	  the process as file descriptors supporting the read/write
488	  syscalls, it's possible to isolate those applications in
489	  their own address space using seccomp. Once seccomp is
490	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
491	  and the task is only allowed to execute a few safe syscalls
492	  defined by each seccomp mode.
493
494config XEN_DOM0
495	def_bool y
496	depends on XEN
497
498config XEN
499	bool "Xen guest support on ARM64"
500	depends on ARM64 && OF
501	select SWIOTLB_XEN
502	help
503	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
504
505config FORCE_MAX_ZONEORDER
506	int
507	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
508	default "11"
509
510menuconfig ARMV8_DEPRECATED
511	bool "Emulate deprecated/obsolete ARMv8 instructions"
512	depends on COMPAT
513	help
514	  Legacy software support may require certain instructions
515	  that have been deprecated or obsoleted in the architecture.
516
517	  Enable this config to enable selective emulation of these
518	  features.
519
520	  If unsure, say Y
521
522if ARMV8_DEPRECATED
523
524config SWP_EMULATION
525	bool "Emulate SWP/SWPB instructions"
526	help
527	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
528	  they are always undefined. Say Y here to enable software
529	  emulation of these instructions for userspace using LDXR/STXR.
530
531	  In some older versions of glibc [<=2.8] SWP is used during futex
532	  trylock() operations with the assumption that the code will not
533	  be preempted. This invalid assumption may be more likely to fail
534	  with SWP emulation enabled, leading to deadlock of the user
535	  application.
536
537	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
538	  on an external transaction monitoring block called a global
539	  monitor to maintain update atomicity. If your system does not
540	  implement a global monitor, this option can cause programs that
541	  perform SWP operations to uncached memory to deadlock.
542
543	  If unsure, say Y
544
545config CP15_BARRIER_EMULATION
546	bool "Emulate CP15 Barrier instructions"
547	help
548	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
549	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
550	  strongly recommended to use the ISB, DSB, and DMB
551	  instructions instead.
552
553	  Say Y here to enable software emulation of these
554	  instructions for AArch32 userspace code. When this option is
555	  enabled, CP15 barrier usage is traced which can help
556	  identify software that needs updating.
557
558	  If unsure, say Y
559
560config SETEND_EMULATION
561	bool "Emulate SETEND instruction"
562	help
563	  The SETEND instruction alters the data-endianness of the
564	  AArch32 EL0, and is deprecated in ARMv8.
565
566	  Say Y here to enable software emulation of the instruction
567	  for AArch32 userspace code.
568
569	  Note: All the cpus on the system must have mixed endian support at EL0
570	  for this feature to be enabled. If a new CPU - which doesn't support mixed
571	  endian - is hotplugged in after this feature has been enabled, there could
572	  be unexpected results in the applications.
573
574	  If unsure, say Y
575endif
576
577menu "ARMv8.1 architectural features"
578
579config ARM64_HW_AFDBM
580	bool "Support for hardware updates of the Access and Dirty page flags"
581	default y
582	help
583	  The ARMv8.1 architecture extensions introduce support for
584	  hardware updates of the access and dirty information in page
585	  table entries. When enabled in TCR_EL1 (HA and HD bits) on
586	  capable processors, accesses to pages with PTE_AF cleared will
587	  set this bit instead of raising an access flag fault.
588	  Similarly, writes to read-only pages with the DBM bit set will
589	  clear the read-only bit (AP[2]) instead of raising a
590	  permission fault.
591
592	  Kernels built with this configuration option enabled continue
593	  to work on pre-ARMv8.1 hardware and the performance impact is
594	  minimal. If unsure, say Y.
595
596config ARM64_PAN
597	bool "Enable support for Privileged Access Never (PAN)"
598	default y
599	help
600	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
601	 prevents the kernel or hypervisor from accessing user-space (EL0)
602	 memory directly.
603
604	 Choosing this option will cause any unprotected (not using
605	 copy_to_user et al) memory access to fail with a permission fault.
606
607	 The feature is detected at runtime, and will remain as a 'nop'
608	 instruction if the cpu does not implement the feature.
609
610config ARM64_LSE_ATOMICS
611	bool "Atomic instructions"
612	help
613	  As part of the Large System Extensions, ARMv8.1 introduces new
614	  atomic instructions that are designed specifically to scale in
615	  very large systems.
616
617	  Say Y here to make use of these instructions for the in-kernel
618	  atomic routines. This incurs a small overhead on CPUs that do
619	  not support these instructions and requires the kernel to be
620	  built with binutils >= 2.25.
621
622endmenu
623
624endmenu
625
626menu "Boot options"
627
628config CMDLINE
629	string "Default kernel command string"
630	default ""
631	help
632	  Provide a set of default command-line options at build time by
633	  entering them here. As a minimum, you should specify the the
634	  root device (e.g. root=/dev/nfs).
635
636config CMDLINE_FORCE
637	bool "Always use the default kernel command string"
638	help
639	  Always use the default kernel command string, even if the boot
640	  loader passes other arguments to the kernel.
641	  This is useful if you cannot or don't want to change the
642	  command-line options your boot loader passes to the kernel.
643
644config EFI_STUB
645	bool
646
647config EFI
648	bool "UEFI runtime support"
649	depends on OF && !CPU_BIG_ENDIAN
650	select LIBFDT
651	select UCS2_STRING
652	select EFI_PARAMS_FROM_FDT
653	select EFI_RUNTIME_WRAPPERS
654	select EFI_STUB
655	select EFI_ARMSTUB
656	default y
657	help
658	  This option provides support for runtime services provided
659	  by UEFI firmware (such as non-volatile variables, realtime
660          clock, and platform reset). A UEFI stub is also provided to
661	  allow the kernel to be booted as an EFI application. This
662	  is only useful on systems that have UEFI firmware.
663
664config DMI
665	bool "Enable support for SMBIOS (DMI) tables"
666	depends on EFI
667	default y
668	help
669	  This enables SMBIOS/DMI feature for systems.
670
671	  This option is only useful on systems that have UEFI firmware.
672	  However, even with this option, the resultant kernel should
673	  continue to boot on existing non-UEFI platforms.
674
675endmenu
676
677menu "Userspace binary formats"
678
679source "fs/Kconfig.binfmt"
680
681config COMPAT
682	bool "Kernel support for 32-bit EL0"
683	depends on !ARM64_64K_PAGES || EXPERT
684	select COMPAT_BINFMT_ELF
685	select HAVE_UID16
686	select OLD_SIGSUSPEND3
687	select COMPAT_OLD_SIGACTION
688	help
689	  This option enables support for a 32-bit EL0 running under a 64-bit
690	  kernel at EL1. AArch32-specific components such as system calls,
691	  the user helper functions, VFP support and the ptrace interface are
692	  handled appropriately by the kernel.
693
694	  If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
695	  will only be able to execute AArch32 binaries that were compiled with
696	  64k aligned segments.
697
698	  If you want to execute 32-bit userspace applications, say Y.
699
700config SYSVIPC_COMPAT
701	def_bool y
702	depends on COMPAT && SYSVIPC
703
704endmenu
705
706menu "Power management options"
707
708source "kernel/power/Kconfig"
709
710config ARCH_SUSPEND_POSSIBLE
711	def_bool y
712
713endmenu
714
715menu "CPU Power Management"
716
717source "drivers/cpuidle/Kconfig"
718
719source "drivers/cpufreq/Kconfig"
720
721endmenu
722
723source "net/Kconfig"
724
725source "drivers/Kconfig"
726
727source "drivers/firmware/Kconfig"
728
729source "drivers/acpi/Kconfig"
730
731source "fs/Kconfig"
732
733source "arch/arm64/kvm/Kconfig"
734
735source "arch/arm64/Kconfig.debug"
736
737source "security/Kconfig"
738
739source "crypto/Kconfig"
740if CRYPTO
741source "arch/arm64/crypto/Kconfig"
742endif
743
744source "lib/Kconfig"
745