1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 18 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 19 select ARCH_ENABLE_MEMORY_HOTPLUG 20 select ARCH_ENABLE_MEMORY_HOTREMOVE 21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 22 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 23 select ARCH_HAS_CACHE_LINE_SIZE 24 select ARCH_HAS_CC_PLATFORM 25 select ARCH_HAS_CURRENT_STACK_POINTER 26 select ARCH_HAS_DEBUG_VIRTUAL 27 select ARCH_HAS_DEBUG_VM_PGTABLE 28 select ARCH_HAS_DMA_OPS if XEN 29 select ARCH_HAS_DMA_PREP_COHERENT 30 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 31 select ARCH_HAS_FAST_MULTIPLIER 32 select ARCH_HAS_FORTIFY_SOURCE 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_HAS_GIGANTIC_PAGE 35 select ARCH_HAS_KCOV 36 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 37 select ARCH_HAS_KEEPINITRD 38 select ARCH_HAS_MEMBARRIER_SYNC_CORE 39 select ARCH_HAS_MEM_ENCRYPT 40 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 41 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 42 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 43 select ARCH_HAS_PTE_DEVMAP 44 select ARCH_HAS_PTE_SPECIAL 45 select ARCH_HAS_HW_PTE_YOUNG 46 select ARCH_HAS_SETUP_DMA_OPS 47 select ARCH_HAS_SET_DIRECT_MAP 48 select ARCH_HAS_SET_MEMORY 49 select ARCH_HAS_MEM_ENCRYPT 50 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 51 select ARCH_STACKWALK 52 select ARCH_HAS_STRICT_KERNEL_RWX 53 select ARCH_HAS_STRICT_MODULE_RWX 54 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 55 select ARCH_HAS_SYNC_DMA_FOR_CPU 56 select ARCH_HAS_SYSCALL_WRAPPER 57 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 58 select ARCH_HAS_ZONE_DMA_SET if EXPERT 59 select ARCH_HAVE_ELF_PROT 60 select ARCH_HAVE_NMI_SAFE_CMPXCHG 61 select ARCH_HAVE_TRACE_MMIO_ACCESS 62 select ARCH_INLINE_READ_LOCK if !PREEMPTION 63 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 66 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 70 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 80 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 84 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 88 select ARCH_KEEP_MEMBLOCK 89 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 90 select ARCH_USE_CMPXCHG_LOCKREF 91 select ARCH_USE_GNU_PROPERTY 92 select ARCH_USE_MEMTEST 93 select ARCH_USE_QUEUED_RWLOCKS 94 select ARCH_USE_QUEUED_SPINLOCKS 95 select ARCH_USE_SYM_ANNOTATIONS 96 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 97 select ARCH_SUPPORTS_HUGETLBFS 98 select ARCH_SUPPORTS_MEMORY_FAILURE 99 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 100 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 101 select ARCH_SUPPORTS_LTO_CLANG_THIN 102 select ARCH_SUPPORTS_CFI_CLANG 103 select ARCH_SUPPORTS_ATOMIC_RMW 104 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 105 select ARCH_SUPPORTS_NUMA_BALANCING 106 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 107 select ARCH_SUPPORTS_PER_VMA_LOCK 108 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 109 select ARCH_SUPPORTS_RT 110 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 111 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 112 select ARCH_WANT_DEFAULT_BPF_JIT 113 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 114 select ARCH_WANT_FRAME_POINTERS 115 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 116 select ARCH_WANT_LD_ORPHAN_WARN 117 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 118 select ARCH_WANTS_NO_INSTR 119 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 120 select ARCH_HAS_UBSAN 121 select ARM_AMBA 122 select ARM_ARCH_TIMER 123 select ARM_GIC 124 select AUDIT_ARCH_COMPAT_GENERIC 125 select ARM_GIC_V2M if PCI 126 select ARM_GIC_V3 127 select ARM_GIC_V3_ITS if PCI 128 select ARM_PSCI_FW 129 select BUILDTIME_TABLE_SORT 130 select CLONE_BACKWARDS 131 select COMMON_CLK 132 select CPU_PM if (SUSPEND || CPU_IDLE) 133 select CPUMASK_OFFSTACK if NR_CPUS > 256 134 select CRC32 135 select DCACHE_WORD_ACCESS 136 select DYNAMIC_FTRACE if FUNCTION_TRACER 137 select DMA_BOUNCE_UNALIGNED_KMALLOC 138 select DMA_DIRECT_REMAP 139 select EDAC_SUPPORT 140 select FRAME_POINTER 141 select FUNCTION_ALIGNMENT_4B 142 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 143 select GENERIC_ALLOCATOR 144 select GENERIC_ARCH_TOPOLOGY 145 select GENERIC_CLOCKEVENTS_BROADCAST 146 select GENERIC_CPU_AUTOPROBE 147 select GENERIC_CPU_DEVICES 148 select GENERIC_CPU_VULNERABILITIES 149 select GENERIC_EARLY_IOREMAP 150 select GENERIC_IDLE_POLL_SETUP 151 select GENERIC_IOREMAP 152 select GENERIC_IRQ_IPI 153 select GENERIC_IRQ_PROBE 154 select GENERIC_IRQ_SHOW 155 select GENERIC_IRQ_SHOW_LEVEL 156 select GENERIC_LIB_DEVMEM_IS_ALLOWED 157 select GENERIC_PCI_IOMAP 158 select GENERIC_PTDUMP 159 select GENERIC_SCHED_CLOCK 160 select GENERIC_SMP_IDLE_THREAD 161 select GENERIC_TIME_VSYSCALL 162 select GENERIC_GETTIMEOFDAY 163 select GENERIC_VDSO_TIME_NS 164 select HARDIRQS_SW_RESEND 165 select HAS_IOPORT 166 select HAVE_MOVE_PMD 167 select HAVE_MOVE_PUD 168 select HAVE_PCI 169 select HAVE_ACPI_APEI if (ACPI && EFI) 170 select HAVE_ALIGNED_STRUCT_PAGE 171 select HAVE_ARCH_AUDITSYSCALL 172 select HAVE_ARCH_BITREVERSE 173 select HAVE_ARCH_COMPILER_H 174 select HAVE_ARCH_HUGE_VMALLOC 175 select HAVE_ARCH_HUGE_VMAP 176 select HAVE_ARCH_JUMP_LABEL 177 select HAVE_ARCH_JUMP_LABEL_RELATIVE 178 select HAVE_ARCH_KASAN 179 select HAVE_ARCH_KASAN_VMALLOC 180 select HAVE_ARCH_KASAN_SW_TAGS 181 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 182 # Some instrumentation may be unsound, hence EXPERT 183 select HAVE_ARCH_KCSAN if EXPERT 184 select HAVE_ARCH_KFENCE 185 select HAVE_ARCH_KGDB 186 select HAVE_ARCH_MMAP_RND_BITS 187 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 188 select HAVE_ARCH_PREL32_RELOCATIONS 189 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 190 select HAVE_ARCH_SECCOMP_FILTER 191 select HAVE_ARCH_STACKLEAK 192 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 193 select HAVE_ARCH_TRACEHOOK 194 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 195 select HAVE_ARCH_VMAP_STACK 196 select HAVE_ARM_SMCCC 197 select HAVE_ASM_MODVERSIONS 198 select HAVE_EBPF_JIT 199 select HAVE_C_RECORDMCOUNT 200 select HAVE_CMPXCHG_DOUBLE 201 select HAVE_CMPXCHG_LOCAL 202 select HAVE_CONTEXT_TRACKING_USER 203 select HAVE_DEBUG_KMEMLEAK 204 select HAVE_DMA_CONTIGUOUS 205 select HAVE_DYNAMIC_FTRACE 206 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 207 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 208 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 209 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 210 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 211 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 212 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 213 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 214 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 215 if DYNAMIC_FTRACE_WITH_ARGS 216 select HAVE_SAMPLE_FTRACE_DIRECT 217 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 218 select HAVE_EFFICIENT_UNALIGNED_ACCESS 219 select HAVE_GUP_FAST 220 select HAVE_FTRACE_MCOUNT_RECORD 221 select HAVE_FUNCTION_TRACER 222 select HAVE_FUNCTION_ERROR_INJECTION 223 select HAVE_FUNCTION_GRAPH_TRACER 224 select HAVE_FUNCTION_GRAPH_RETVAL 225 select HAVE_GCC_PLUGINS 226 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 227 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 228 select HAVE_HW_BREAKPOINT if PERF_EVENTS 229 select HAVE_IOREMAP_PROT 230 select HAVE_IRQ_TIME_ACCOUNTING 231 select HAVE_MOD_ARCH_SPECIFIC 232 select HAVE_NMI 233 select HAVE_PERF_EVENTS 234 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 235 select HAVE_PERF_REGS 236 select HAVE_PERF_USER_STACK_DUMP 237 select HAVE_PREEMPT_DYNAMIC_KEY 238 select HAVE_REGS_AND_STACK_ACCESS_API 239 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 240 select HAVE_FUNCTION_ARG_ACCESS_API 241 select MMU_GATHER_RCU_TABLE_FREE 242 select HAVE_RSEQ 243 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 244 select HAVE_STACKPROTECTOR 245 select HAVE_SYSCALL_TRACEPOINTS 246 select HAVE_KPROBES 247 select HAVE_KRETPROBES 248 select HAVE_GENERIC_VDSO 249 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 250 select IRQ_DOMAIN 251 select IRQ_FORCED_THREADING 252 select KASAN_VMALLOC if KASAN 253 select LOCK_MM_AND_FIND_VMA 254 select MODULES_USE_ELF_RELA 255 select NEED_DMA_MAP_STATE 256 select NEED_SG_DMA_LENGTH 257 select OF 258 select OF_EARLY_FLATTREE 259 select PCI_DOMAINS_GENERIC if PCI 260 select PCI_ECAM if (ACPI && PCI) 261 select PCI_SYSCALL if PCI 262 select POWER_RESET 263 select POWER_SUPPLY 264 select SPARSE_IRQ 265 select SWIOTLB 266 select SYSCTL_EXCEPTION_TRACE 267 select THREAD_INFO_IN_TASK 268 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 269 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 270 select TRACE_IRQFLAGS_SUPPORT 271 select TRACE_IRQFLAGS_NMI_SUPPORT 272 select HAVE_SOFTIRQ_ON_OWN_STACK 273 select USER_STACKTRACE_SUPPORT 274 select VDSO_GETRANDOM 275 help 276 ARM 64-bit (AArch64) Linux support. 277 278config RUSTC_SUPPORTS_ARM64 279 def_bool y 280 depends on CPU_LITTLE_ENDIAN 281 # Shadow call stack is only supported on certain rustc versions. 282 # 283 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 284 # required due to use of the -Zfixed-x18 flag. 285 # 286 # Otherwise, rustc version 1.82+ is required due to use of the 287 # -Zsanitizer=shadow-call-stack flag. 288 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 289 290config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 291 def_bool CC_IS_CLANG 292 # https://github.com/ClangBuiltLinux/linux/issues/1507 293 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 294 295config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 296 def_bool CC_IS_GCC 297 depends on $(cc-option,-fpatchable-function-entry=2) 298 299config 64BIT 300 def_bool y 301 302config MMU 303 def_bool y 304 305config ARM64_CONT_PTE_SHIFT 306 int 307 default 5 if PAGE_SIZE_64KB 308 default 7 if PAGE_SIZE_16KB 309 default 4 310 311config ARM64_CONT_PMD_SHIFT 312 int 313 default 5 if PAGE_SIZE_64KB 314 default 5 if PAGE_SIZE_16KB 315 default 4 316 317config ARCH_MMAP_RND_BITS_MIN 318 default 14 if PAGE_SIZE_64KB 319 default 16 if PAGE_SIZE_16KB 320 default 18 321 322# max bits determined by the following formula: 323# VA_BITS - PAGE_SHIFT - 3 324config ARCH_MMAP_RND_BITS_MAX 325 default 19 if ARM64_VA_BITS=36 326 default 24 if ARM64_VA_BITS=39 327 default 27 if ARM64_VA_BITS=42 328 default 30 if ARM64_VA_BITS=47 329 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 330 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 331 default 33 if ARM64_VA_BITS=48 332 default 14 if ARM64_64K_PAGES 333 default 16 if ARM64_16K_PAGES 334 default 18 335 336config ARCH_MMAP_RND_COMPAT_BITS_MIN 337 default 7 if ARM64_64K_PAGES 338 default 9 if ARM64_16K_PAGES 339 default 11 340 341config ARCH_MMAP_RND_COMPAT_BITS_MAX 342 default 16 343 344config NO_IOPORT_MAP 345 def_bool y if !PCI 346 347config STACKTRACE_SUPPORT 348 def_bool y 349 350config ILLEGAL_POINTER_VALUE 351 hex 352 default 0xdead000000000000 353 354config LOCKDEP_SUPPORT 355 def_bool y 356 357config GENERIC_BUG 358 def_bool y 359 depends on BUG 360 361config GENERIC_BUG_RELATIVE_POINTERS 362 def_bool y 363 depends on GENERIC_BUG 364 365config GENERIC_HWEIGHT 366 def_bool y 367 368config GENERIC_CSUM 369 def_bool y 370 371config GENERIC_CALIBRATE_DELAY 372 def_bool y 373 374config SMP 375 def_bool y 376 377config KERNEL_MODE_NEON 378 def_bool y 379 380config FIX_EARLYCON_MEM 381 def_bool y 382 383config PGTABLE_LEVELS 384 int 385 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 386 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 387 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 388 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 389 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 390 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 391 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 392 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 393 394config ARCH_SUPPORTS_UPROBES 395 def_bool y 396 397config ARCH_PROC_KCORE_TEXT 398 def_bool y 399 400config BROKEN_GAS_INST 401 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 402 403config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 404 bool 405 # Clang's __builtin_return_address() strips the PAC since 12.0.0 406 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 407 default y if CC_IS_CLANG 408 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 409 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 410 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 411 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 412 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 413 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 414 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 415 default n 416 417config KASAN_SHADOW_OFFSET 418 hex 419 depends on KASAN_GENERIC || KASAN_SW_TAGS 420 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 421 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 422 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 423 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 424 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 425 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 426 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 427 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 428 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 429 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 430 default 0xffffffffffffffff 431 432config UNWIND_TABLES 433 bool 434 435source "arch/arm64/Kconfig.platforms" 436 437menu "Kernel Features" 438 439menu "ARM errata workarounds via the alternatives framework" 440 441config AMPERE_ERRATUM_AC03_CPU_38 442 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 443 default y 444 help 445 This option adds an alternative code sequence to work around Ampere 446 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 447 448 The affected design reports FEAT_HAFDBS as not implemented in 449 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 450 as required by the architecture. The unadvertised HAFDBS 451 implementation suffers from an additional erratum where hardware 452 A/D updates can occur after a PTE has been marked invalid. 453 454 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 455 which avoids enabling unadvertised hardware Access Flag management 456 at stage-2. 457 458 If unsure, say Y. 459 460config ARM64_WORKAROUND_CLEAN_CACHE 461 bool 462 463config ARM64_ERRATUM_826319 464 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 465 default y 466 select ARM64_WORKAROUND_CLEAN_CACHE 467 help 468 This option adds an alternative code sequence to work around ARM 469 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 470 AXI master interface and an L2 cache. 471 472 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 473 and is unable to accept a certain write via this interface, it will 474 not progress on read data presented on the read data channel and the 475 system can deadlock. 476 477 The workaround promotes data cache clean instructions to 478 data cache clean-and-invalidate. 479 Please note that this does not necessarily enable the workaround, 480 as it depends on the alternative framework, which will only patch 481 the kernel if an affected CPU is detected. 482 483 If unsure, say Y. 484 485config ARM64_ERRATUM_827319 486 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 487 default y 488 select ARM64_WORKAROUND_CLEAN_CACHE 489 help 490 This option adds an alternative code sequence to work around ARM 491 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 492 master interface and an L2 cache. 493 494 Under certain conditions this erratum can cause a clean line eviction 495 to occur at the same time as another transaction to the same address 496 on the AMBA 5 CHI interface, which can cause data corruption if the 497 interconnect reorders the two transactions. 498 499 The workaround promotes data cache clean instructions to 500 data cache clean-and-invalidate. 501 Please note that this does not necessarily enable the workaround, 502 as it depends on the alternative framework, which will only patch 503 the kernel if an affected CPU is detected. 504 505 If unsure, say Y. 506 507config ARM64_ERRATUM_824069 508 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 509 default y 510 select ARM64_WORKAROUND_CLEAN_CACHE 511 help 512 This option adds an alternative code sequence to work around ARM 513 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 514 to a coherent interconnect. 515 516 If a Cortex-A53 processor is executing a store or prefetch for 517 write instruction at the same time as a processor in another 518 cluster is executing a cache maintenance operation to the same 519 address, then this erratum might cause a clean cache line to be 520 incorrectly marked as dirty. 521 522 The workaround promotes data cache clean instructions to 523 data cache clean-and-invalidate. 524 Please note that this option does not necessarily enable the 525 workaround, as it depends on the alternative framework, which will 526 only patch the kernel if an affected CPU is detected. 527 528 If unsure, say Y. 529 530config ARM64_ERRATUM_819472 531 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 532 default y 533 select ARM64_WORKAROUND_CLEAN_CACHE 534 help 535 This option adds an alternative code sequence to work around ARM 536 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 537 present when it is connected to a coherent interconnect. 538 539 If the processor is executing a load and store exclusive sequence at 540 the same time as a processor in another cluster is executing a cache 541 maintenance operation to the same address, then this erratum might 542 cause data corruption. 543 544 The workaround promotes data cache clean instructions to 545 data cache clean-and-invalidate. 546 Please note that this does not necessarily enable the workaround, 547 as it depends on the alternative framework, which will only patch 548 the kernel if an affected CPU is detected. 549 550 If unsure, say Y. 551 552config ARM64_ERRATUM_832075 553 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 554 default y 555 help 556 This option adds an alternative code sequence to work around ARM 557 erratum 832075 on Cortex-A57 parts up to r1p2. 558 559 Affected Cortex-A57 parts might deadlock when exclusive load/store 560 instructions to Write-Back memory are mixed with Device loads. 561 562 The workaround is to promote device loads to use Load-Acquire 563 semantics. 564 Please note that this does not necessarily enable the workaround, 565 as it depends on the alternative framework, which will only patch 566 the kernel if an affected CPU is detected. 567 568 If unsure, say Y. 569 570config ARM64_ERRATUM_834220 571 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 572 depends on KVM 573 help 574 This option adds an alternative code sequence to work around ARM 575 erratum 834220 on Cortex-A57 parts up to r1p2. 576 577 Affected Cortex-A57 parts might report a Stage 2 translation 578 fault as the result of a Stage 1 fault for load crossing a 579 page boundary when there is a permission or device memory 580 alignment fault at Stage 1 and a translation fault at Stage 2. 581 582 The workaround is to verify that the Stage 1 translation 583 doesn't generate a fault before handling the Stage 2 fault. 584 Please note that this does not necessarily enable the workaround, 585 as it depends on the alternative framework, which will only patch 586 the kernel if an affected CPU is detected. 587 588 If unsure, say N. 589 590config ARM64_ERRATUM_1742098 591 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 592 depends on COMPAT 593 default y 594 help 595 This option removes the AES hwcap for aarch32 user-space to 596 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 597 598 Affected parts may corrupt the AES state if an interrupt is 599 taken between a pair of AES instructions. These instructions 600 are only present if the cryptography extensions are present. 601 All software should have a fallback implementation for CPUs 602 that don't implement the cryptography extensions. 603 604 If unsure, say Y. 605 606config ARM64_ERRATUM_845719 607 bool "Cortex-A53: 845719: a load might read incorrect data" 608 depends on COMPAT 609 default y 610 help 611 This option adds an alternative code sequence to work around ARM 612 erratum 845719 on Cortex-A53 parts up to r0p4. 613 614 When running a compat (AArch32) userspace on an affected Cortex-A53 615 part, a load at EL0 from a virtual address that matches the bottom 32 616 bits of the virtual address used by a recent load at (AArch64) EL1 617 might return incorrect data. 618 619 The workaround is to write the contextidr_el1 register on exception 620 return to a 32-bit task. 621 Please note that this does not necessarily enable the workaround, 622 as it depends on the alternative framework, which will only patch 623 the kernel if an affected CPU is detected. 624 625 If unsure, say Y. 626 627config ARM64_ERRATUM_843419 628 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 629 default y 630 help 631 This option links the kernel with '--fix-cortex-a53-843419' and 632 enables PLT support to replace certain ADRP instructions, which can 633 cause subsequent memory accesses to use an incorrect address on 634 Cortex-A53 parts up to r0p4. 635 636 If unsure, say Y. 637 638config ARM64_LD_HAS_FIX_ERRATUM_843419 639 def_bool $(ld-option,--fix-cortex-a53-843419) 640 641config ARM64_ERRATUM_1024718 642 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 643 default y 644 help 645 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 646 647 Affected Cortex-A55 cores (all revisions) could cause incorrect 648 update of the hardware dirty bit when the DBM/AP bits are updated 649 without a break-before-make. The workaround is to disable the usage 650 of hardware DBM locally on the affected cores. CPUs not affected by 651 this erratum will continue to use the feature. 652 653 If unsure, say Y. 654 655config ARM64_ERRATUM_1418040 656 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 657 default y 658 depends on COMPAT 659 help 660 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 661 errata 1188873 and 1418040. 662 663 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 664 cause register corruption when accessing the timer registers 665 from AArch32 userspace. 666 667 If unsure, say Y. 668 669config ARM64_WORKAROUND_SPECULATIVE_AT 670 bool 671 672config ARM64_ERRATUM_1165522 673 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 674 default y 675 select ARM64_WORKAROUND_SPECULATIVE_AT 676 help 677 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 678 679 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 680 corrupted TLBs by speculating an AT instruction during a guest 681 context switch. 682 683 If unsure, say Y. 684 685config ARM64_ERRATUM_1319367 686 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 687 default y 688 select ARM64_WORKAROUND_SPECULATIVE_AT 689 help 690 This option adds work arounds for ARM Cortex-A57 erratum 1319537 691 and A72 erratum 1319367 692 693 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 694 speculating an AT instruction during a guest context switch. 695 696 If unsure, say Y. 697 698config ARM64_ERRATUM_1530923 699 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 700 default y 701 select ARM64_WORKAROUND_SPECULATIVE_AT 702 help 703 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 704 705 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 706 corrupted TLBs by speculating an AT instruction during a guest 707 context switch. 708 709 If unsure, say Y. 710 711config ARM64_WORKAROUND_REPEAT_TLBI 712 bool 713 714config ARM64_ERRATUM_2441007 715 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 716 select ARM64_WORKAROUND_REPEAT_TLBI 717 help 718 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 719 720 Under very rare circumstances, affected Cortex-A55 CPUs 721 may not handle a race between a break-before-make sequence on one 722 CPU, and another CPU accessing the same page. This could allow a 723 store to a page that has been unmapped. 724 725 Work around this by adding the affected CPUs to the list that needs 726 TLB sequences to be done twice. 727 728 If unsure, say N. 729 730config ARM64_ERRATUM_1286807 731 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 732 select ARM64_WORKAROUND_REPEAT_TLBI 733 help 734 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 735 736 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 737 address for a cacheable mapping of a location is being 738 accessed by a core while another core is remapping the virtual 739 address to a new physical page using the recommended 740 break-before-make sequence, then under very rare circumstances 741 TLBI+DSB completes before a read using the translation being 742 invalidated has been observed by other observers. The 743 workaround repeats the TLBI+DSB operation. 744 745 If unsure, say N. 746 747config ARM64_ERRATUM_1463225 748 bool "Cortex-A76: Software Step might prevent interrupt recognition" 749 default y 750 help 751 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 752 753 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 754 of a system call instruction (SVC) can prevent recognition of 755 subsequent interrupts when software stepping is disabled in the 756 exception handler of the system call and either kernel debugging 757 is enabled or VHE is in use. 758 759 Work around the erratum by triggering a dummy step exception 760 when handling a system call from a task that is being stepped 761 in a VHE configuration of the kernel. 762 763 If unsure, say Y. 764 765config ARM64_ERRATUM_1542419 766 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 767 help 768 This option adds a workaround for ARM Neoverse-N1 erratum 769 1542419. 770 771 Affected Neoverse-N1 cores could execute a stale instruction when 772 modified by another CPU. The workaround depends on a firmware 773 counterpart. 774 775 Workaround the issue by hiding the DIC feature from EL0. This 776 forces user-space to perform cache maintenance. 777 778 If unsure, say N. 779 780config ARM64_ERRATUM_1508412 781 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 782 default y 783 help 784 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 785 786 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 787 of a store-exclusive or read of PAR_EL1 and a load with device or 788 non-cacheable memory attributes. The workaround depends on a firmware 789 counterpart. 790 791 KVM guests must also have the workaround implemented or they can 792 deadlock the system. 793 794 Work around the issue by inserting DMB SY barriers around PAR_EL1 795 register reads and warning KVM users. The DMB barrier is sufficient 796 to prevent a speculative PAR_EL1 read. 797 798 If unsure, say Y. 799 800config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 801 bool 802 803config ARM64_ERRATUM_2051678 804 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 805 default y 806 help 807 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 808 Affected Cortex-A510 might not respect the ordering rules for 809 hardware update of the page table's dirty bit. The workaround 810 is to not enable the feature on affected CPUs. 811 812 If unsure, say Y. 813 814config ARM64_ERRATUM_2077057 815 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 816 default y 817 help 818 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 819 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 820 expected, but a Pointer Authentication trap is taken instead. The 821 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 822 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 823 824 This can only happen when EL2 is stepping EL1. 825 826 When these conditions occur, the SPSR_EL2 value is unchanged from the 827 previous guest entry, and can be restored from the in-memory copy. 828 829 If unsure, say Y. 830 831config ARM64_ERRATUM_2658417 832 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 833 default y 834 help 835 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 836 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 837 BFMMLA or VMMLA instructions in rare circumstances when a pair of 838 A510 CPUs are using shared neon hardware. As the sharing is not 839 discoverable by the kernel, hide the BF16 HWCAP to indicate that 840 user-space should not be using these instructions. 841 842 If unsure, say Y. 843 844config ARM64_ERRATUM_2119858 845 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 846 default y 847 depends on CORESIGHT_TRBE 848 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 849 help 850 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 851 852 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 853 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 854 the event of a WRAP event. 855 856 Work around the issue by always making sure we move the TRBPTR_EL1 by 857 256 bytes before enabling the buffer and filling the first 256 bytes of 858 the buffer with ETM ignore packets upon disabling. 859 860 If unsure, say Y. 861 862config ARM64_ERRATUM_2139208 863 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 864 default y 865 depends on CORESIGHT_TRBE 866 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 867 help 868 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 869 870 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 871 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 872 the event of a WRAP event. 873 874 Work around the issue by always making sure we move the TRBPTR_EL1 by 875 256 bytes before enabling the buffer and filling the first 256 bytes of 876 the buffer with ETM ignore packets upon disabling. 877 878 If unsure, say Y. 879 880config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 881 bool 882 883config ARM64_ERRATUM_2054223 884 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 885 default y 886 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 887 help 888 Enable workaround for ARM Cortex-A710 erratum 2054223 889 890 Affected cores may fail to flush the trace data on a TSB instruction, when 891 the PE is in trace prohibited state. This will cause losing a few bytes 892 of the trace cached. 893 894 Workaround is to issue two TSB consecutively on affected cores. 895 896 If unsure, say Y. 897 898config ARM64_ERRATUM_2067961 899 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 900 default y 901 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 902 help 903 Enable workaround for ARM Neoverse-N2 erratum 2067961 904 905 Affected cores may fail to flush the trace data on a TSB instruction, when 906 the PE is in trace prohibited state. This will cause losing a few bytes 907 of the trace cached. 908 909 Workaround is to issue two TSB consecutively on affected cores. 910 911 If unsure, say Y. 912 913config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 914 bool 915 916config ARM64_ERRATUM_2253138 917 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 918 depends on CORESIGHT_TRBE 919 default y 920 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 921 help 922 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 923 924 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 925 for TRBE. Under some conditions, the TRBE might generate a write to the next 926 virtually addressed page following the last page of the TRBE address space 927 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 928 929 Work around this in the driver by always making sure that there is a 930 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 931 932 If unsure, say Y. 933 934config ARM64_ERRATUM_2224489 935 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 936 depends on CORESIGHT_TRBE 937 default y 938 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 939 help 940 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 941 942 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 943 for TRBE. Under some conditions, the TRBE might generate a write to the next 944 virtually addressed page following the last page of the TRBE address space 945 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 946 947 Work around this in the driver by always making sure that there is a 948 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 949 950 If unsure, say Y. 951 952config ARM64_ERRATUM_2441009 953 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 954 select ARM64_WORKAROUND_REPEAT_TLBI 955 help 956 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 957 958 Under very rare circumstances, affected Cortex-A510 CPUs 959 may not handle a race between a break-before-make sequence on one 960 CPU, and another CPU accessing the same page. This could allow a 961 store to a page that has been unmapped. 962 963 Work around this by adding the affected CPUs to the list that needs 964 TLB sequences to be done twice. 965 966 If unsure, say N. 967 968config ARM64_ERRATUM_2064142 969 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 970 depends on CORESIGHT_TRBE 971 default y 972 help 973 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 974 975 Affected Cortex-A510 core might fail to write into system registers after the 976 TRBE has been disabled. Under some conditions after the TRBE has been disabled 977 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 978 and TRBTRG_EL1 will be ignored and will not be effected. 979 980 Work around this in the driver by executing TSB CSYNC and DSB after collection 981 is stopped and before performing a system register write to one of the affected 982 registers. 983 984 If unsure, say Y. 985 986config ARM64_ERRATUM_2038923 987 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 988 depends on CORESIGHT_TRBE 989 default y 990 help 991 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 992 993 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 994 prohibited within the CPU. As a result, the trace buffer or trace buffer state 995 might be corrupted. This happens after TRBE buffer has been enabled by setting 996 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 997 execution changes from a context, in which trace is prohibited to one where it 998 isn't, or vice versa. In these mentioned conditions, the view of whether trace 999 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1000 the trace buffer state might be corrupted. 1001 1002 Work around this in the driver by preventing an inconsistent view of whether the 1003 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1004 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1005 two ISB instructions if no ERET is to take place. 1006 1007 If unsure, say Y. 1008 1009config ARM64_ERRATUM_1902691 1010 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1011 depends on CORESIGHT_TRBE 1012 default y 1013 help 1014 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1015 1016 Affected Cortex-A510 core might cause trace data corruption, when being written 1017 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1018 trace data. 1019 1020 Work around this problem in the driver by just preventing TRBE initialization on 1021 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1022 on such implementations. This will cover the kernel for any firmware that doesn't 1023 do this already. 1024 1025 If unsure, say Y. 1026 1027config ARM64_ERRATUM_2457168 1028 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1029 depends on ARM64_AMU_EXTN 1030 default y 1031 help 1032 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1033 1034 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1035 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1036 incorrectly giving a significantly higher output value. 1037 1038 Work around this problem by returning 0 when reading the affected counter in 1039 key locations that results in disabling all users of this counter. This effect 1040 is the same to firmware disabling affected counters. 1041 1042 If unsure, say Y. 1043 1044config ARM64_ERRATUM_2645198 1045 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1046 default y 1047 help 1048 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1049 1050 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1051 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1052 next instruction abort caused by permission fault. 1053 1054 Only user-space does executable to non-executable permission transition via 1055 mprotect() system call. Workaround the problem by doing a break-before-make 1056 TLB invalidation, for all changes to executable user space mappings. 1057 1058 If unsure, say Y. 1059 1060config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1061 bool 1062 1063config ARM64_ERRATUM_2966298 1064 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1065 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1066 default y 1067 help 1068 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1069 1070 On an affected Cortex-A520 core, a speculatively executed unprivileged 1071 load might leak data from a privileged level via a cache side channel. 1072 1073 Work around this problem by executing a TLBI before returning to EL0. 1074 1075 If unsure, say Y. 1076 1077config ARM64_ERRATUM_3117295 1078 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1079 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1080 default y 1081 help 1082 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1083 1084 On an affected Cortex-A510 core, a speculatively executed unprivileged 1085 load might leak data from a privileged level via a cache side channel. 1086 1087 Work around this problem by executing a TLBI before returning to EL0. 1088 1089 If unsure, say Y. 1090 1091config ARM64_ERRATUM_3194386 1092 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1093 default y 1094 help 1095 This option adds the workaround for the following errata: 1096 1097 * ARM Cortex-A76 erratum 3324349 1098 * ARM Cortex-A77 erratum 3324348 1099 * ARM Cortex-A78 erratum 3324344 1100 * ARM Cortex-A78C erratum 3324346 1101 * ARM Cortex-A78C erratum 3324347 1102 * ARM Cortex-A710 erratam 3324338 1103 * ARM Cortex-A715 errartum 3456084 1104 * ARM Cortex-A720 erratum 3456091 1105 * ARM Cortex-A725 erratum 3456106 1106 * ARM Cortex-X1 erratum 3324344 1107 * ARM Cortex-X1C erratum 3324346 1108 * ARM Cortex-X2 erratum 3324338 1109 * ARM Cortex-X3 erratum 3324335 1110 * ARM Cortex-X4 erratum 3194386 1111 * ARM Cortex-X925 erratum 3324334 1112 * ARM Neoverse-N1 erratum 3324349 1113 * ARM Neoverse N2 erratum 3324339 1114 * ARM Neoverse-N3 erratum 3456111 1115 * ARM Neoverse-V1 erratum 3324341 1116 * ARM Neoverse V2 erratum 3324336 1117 * ARM Neoverse-V3 erratum 3312417 1118 1119 On affected cores "MSR SSBS, #0" instructions may not affect 1120 subsequent speculative instructions, which may permit unexepected 1121 speculative store bypassing. 1122 1123 Work around this problem by placing a Speculation Barrier (SB) or 1124 Instruction Synchronization Barrier (ISB) after kernel changes to 1125 SSBS. The presence of the SSBS special-purpose register is hidden 1126 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1127 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1128 1129 If unsure, say Y. 1130 1131config CAVIUM_ERRATUM_22375 1132 bool "Cavium erratum 22375, 24313" 1133 default y 1134 help 1135 Enable workaround for errata 22375 and 24313. 1136 1137 This implements two gicv3-its errata workarounds for ThunderX. Both 1138 with a small impact affecting only ITS table allocation. 1139 1140 erratum 22375: only alloc 8MB table size 1141 erratum 24313: ignore memory access type 1142 1143 The fixes are in ITS initialization and basically ignore memory access 1144 type and table size provided by the TYPER and BASER registers. 1145 1146 If unsure, say Y. 1147 1148config CAVIUM_ERRATUM_23144 1149 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1150 depends on NUMA 1151 default y 1152 help 1153 ITS SYNC command hang for cross node io and collections/cpu mapping. 1154 1155 If unsure, say Y. 1156 1157config CAVIUM_ERRATUM_23154 1158 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1159 default y 1160 help 1161 The ThunderX GICv3 implementation requires a modified version for 1162 reading the IAR status to ensure data synchronization 1163 (access to icc_iar1_el1 is not sync'ed before and after). 1164 1165 It also suffers from erratum 38545 (also present on Marvell's 1166 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1167 spuriously presented to the CPU interface. 1168 1169 If unsure, say Y. 1170 1171config CAVIUM_ERRATUM_27456 1172 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1173 default y 1174 help 1175 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1176 instructions may cause the icache to become corrupted if it 1177 contains data for a non-current ASID. The fix is to 1178 invalidate the icache when changing the mm context. 1179 1180 If unsure, say Y. 1181 1182config CAVIUM_ERRATUM_30115 1183 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1184 default y 1185 help 1186 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1187 1.2, and T83 Pass 1.0, KVM guest execution may disable 1188 interrupts in host. Trapping both GICv3 group-0 and group-1 1189 accesses sidesteps the issue. 1190 1191 If unsure, say Y. 1192 1193config CAVIUM_TX2_ERRATUM_219 1194 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1195 default y 1196 help 1197 On Cavium ThunderX2, a load, store or prefetch instruction between a 1198 TTBR update and the corresponding context synchronizing operation can 1199 cause a spurious Data Abort to be delivered to any hardware thread in 1200 the CPU core. 1201 1202 Work around the issue by avoiding the problematic code sequence and 1203 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1204 trap handler performs the corresponding register access, skips the 1205 instruction and ensures context synchronization by virtue of the 1206 exception return. 1207 1208 If unsure, say Y. 1209 1210config FUJITSU_ERRATUM_010001 1211 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1212 default y 1213 help 1214 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1215 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1216 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1217 This fault occurs under a specific hardware condition when a 1218 load/store instruction performs an address translation using: 1219 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1220 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1221 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1222 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1223 1224 The workaround is to ensure these bits are clear in TCR_ELx. 1225 The workaround only affects the Fujitsu-A64FX. 1226 1227 If unsure, say Y. 1228 1229config HISILICON_ERRATUM_161600802 1230 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1231 default y 1232 help 1233 The HiSilicon Hip07 SoC uses the wrong redistributor base 1234 when issued ITS commands such as VMOVP and VMAPP, and requires 1235 a 128kB offset to be applied to the target address in this commands. 1236 1237 If unsure, say Y. 1238 1239config QCOM_FALKOR_ERRATUM_1003 1240 bool "Falkor E1003: Incorrect translation due to ASID change" 1241 default y 1242 help 1243 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1244 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1245 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1246 then only for entries in the walk cache, since the leaf translation 1247 is unchanged. Work around the erratum by invalidating the walk cache 1248 entries for the trampoline before entering the kernel proper. 1249 1250config QCOM_FALKOR_ERRATUM_1009 1251 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1252 default y 1253 select ARM64_WORKAROUND_REPEAT_TLBI 1254 help 1255 On Falkor v1, the CPU may prematurely complete a DSB following a 1256 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1257 one more time to fix the issue. 1258 1259 If unsure, say Y. 1260 1261config QCOM_QDF2400_ERRATUM_0065 1262 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1263 default y 1264 help 1265 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1266 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1267 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1268 1269 If unsure, say Y. 1270 1271config QCOM_FALKOR_ERRATUM_E1041 1272 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1273 default y 1274 help 1275 Falkor CPU may speculatively fetch instructions from an improper 1276 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1277 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1278 1279 If unsure, say Y. 1280 1281config NVIDIA_CARMEL_CNP_ERRATUM 1282 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1283 default y 1284 help 1285 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1286 invalidate shared TLB entries installed by a different core, as it would 1287 on standard ARM cores. 1288 1289 If unsure, say Y. 1290 1291config ROCKCHIP_ERRATUM_3588001 1292 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1293 default y 1294 help 1295 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1296 This means, that its sharability feature may not be used, even though it 1297 is supported by the IP itself. 1298 1299 If unsure, say Y. 1300 1301config SOCIONEXT_SYNQUACER_PREITS 1302 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1303 default y 1304 help 1305 Socionext Synquacer SoCs implement a separate h/w block to generate 1306 MSI doorbell writes with non-zero values for the device ID. 1307 1308 If unsure, say Y. 1309 1310endmenu # "ARM errata workarounds via the alternatives framework" 1311 1312choice 1313 prompt "Page size" 1314 default ARM64_4K_PAGES 1315 help 1316 Page size (translation granule) configuration. 1317 1318config ARM64_4K_PAGES 1319 bool "4KB" 1320 select HAVE_PAGE_SIZE_4KB 1321 help 1322 This feature enables 4KB pages support. 1323 1324config ARM64_16K_PAGES 1325 bool "16KB" 1326 select HAVE_PAGE_SIZE_16KB 1327 help 1328 The system will use 16KB pages support. AArch32 emulation 1329 requires applications compiled with 16K (or a multiple of 16K) 1330 aligned segments. 1331 1332config ARM64_64K_PAGES 1333 bool "64KB" 1334 select HAVE_PAGE_SIZE_64KB 1335 help 1336 This feature enables 64KB pages support (4KB by default) 1337 allowing only two levels of page tables and faster TLB 1338 look-up. AArch32 emulation requires applications compiled 1339 with 64K aligned segments. 1340 1341endchoice 1342 1343choice 1344 prompt "Virtual address space size" 1345 default ARM64_VA_BITS_52 1346 help 1347 Allows choosing one of multiple possible virtual address 1348 space sizes. The level of translation table is determined by 1349 a combination of page size and virtual address space size. 1350 1351config ARM64_VA_BITS_36 1352 bool "36-bit" if EXPERT 1353 depends on PAGE_SIZE_16KB 1354 1355config ARM64_VA_BITS_39 1356 bool "39-bit" 1357 depends on PAGE_SIZE_4KB 1358 1359config ARM64_VA_BITS_42 1360 bool "42-bit" 1361 depends on PAGE_SIZE_64KB 1362 1363config ARM64_VA_BITS_47 1364 bool "47-bit" 1365 depends on PAGE_SIZE_16KB 1366 1367config ARM64_VA_BITS_48 1368 bool "48-bit" 1369 1370config ARM64_VA_BITS_52 1371 bool "52-bit" 1372 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1373 help 1374 Enable 52-bit virtual addressing for userspace when explicitly 1375 requested via a hint to mmap(). The kernel will also use 52-bit 1376 virtual addresses for its own mappings (provided HW support for 1377 this feature is available, otherwise it reverts to 48-bit). 1378 1379 NOTE: Enabling 52-bit virtual addressing in conjunction with 1380 ARMv8.3 Pointer Authentication will result in the PAC being 1381 reduced from 7 bits to 3 bits, which may have a significant 1382 impact on its susceptibility to brute-force attacks. 1383 1384 If unsure, select 48-bit virtual addressing instead. 1385 1386endchoice 1387 1388config ARM64_FORCE_52BIT 1389 bool "Force 52-bit virtual addresses for userspace" 1390 depends on ARM64_VA_BITS_52 && EXPERT 1391 help 1392 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1393 to maintain compatibility with older software by providing 48-bit VAs 1394 unless a hint is supplied to mmap. 1395 1396 This configuration option disables the 48-bit compatibility logic, and 1397 forces all userspace addresses to be 52-bit on HW that supports it. One 1398 should only enable this configuration option for stress testing userspace 1399 memory management code. If unsure say N here. 1400 1401config ARM64_VA_BITS 1402 int 1403 default 36 if ARM64_VA_BITS_36 1404 default 39 if ARM64_VA_BITS_39 1405 default 42 if ARM64_VA_BITS_42 1406 default 47 if ARM64_VA_BITS_47 1407 default 48 if ARM64_VA_BITS_48 1408 default 52 if ARM64_VA_BITS_52 1409 1410choice 1411 prompt "Physical address space size" 1412 default ARM64_PA_BITS_48 1413 help 1414 Choose the maximum physical address range that the kernel will 1415 support. 1416 1417config ARM64_PA_BITS_48 1418 bool "48-bit" 1419 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1420 1421config ARM64_PA_BITS_52 1422 bool "52-bit" 1423 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1424 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1425 help 1426 Enable support for a 52-bit physical address space, introduced as 1427 part of the ARMv8.2-LPA extension. 1428 1429 With this enabled, the kernel will also continue to work on CPUs that 1430 do not support ARMv8.2-LPA, but with some added memory overhead (and 1431 minor performance overhead). 1432 1433endchoice 1434 1435config ARM64_PA_BITS 1436 int 1437 default 48 if ARM64_PA_BITS_48 1438 default 52 if ARM64_PA_BITS_52 1439 1440config ARM64_LPA2 1441 def_bool y 1442 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1443 1444choice 1445 prompt "Endianness" 1446 default CPU_LITTLE_ENDIAN 1447 help 1448 Select the endianness of data accesses performed by the CPU. Userspace 1449 applications will need to be compiled and linked for the endianness 1450 that is selected here. 1451 1452config CPU_BIG_ENDIAN 1453 bool "Build big-endian kernel" 1454 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1455 depends on AS_IS_GNU || AS_VERSION >= 150000 1456 help 1457 Say Y if you plan on running a kernel with a big-endian userspace. 1458 1459config CPU_LITTLE_ENDIAN 1460 bool "Build little-endian kernel" 1461 help 1462 Say Y if you plan on running a kernel with a little-endian userspace. 1463 This is usually the case for distributions targeting arm64. 1464 1465endchoice 1466 1467config SCHED_MC 1468 bool "Multi-core scheduler support" 1469 help 1470 Multi-core scheduler support improves the CPU scheduler's decision 1471 making when dealing with multi-core CPU chips at a cost of slightly 1472 increased overhead in some places. If unsure say N here. 1473 1474config SCHED_CLUSTER 1475 bool "Cluster scheduler support" 1476 help 1477 Cluster scheduler support improves the CPU scheduler's decision 1478 making when dealing with machines that have clusters of CPUs. 1479 Cluster usually means a couple of CPUs which are placed closely 1480 by sharing mid-level caches, last-level cache tags or internal 1481 busses. 1482 1483config SCHED_SMT 1484 bool "SMT scheduler support" 1485 help 1486 Improves the CPU scheduler's decision making when dealing with 1487 MultiThreading at a cost of slightly increased overhead in some 1488 places. If unsure say N here. 1489 1490config NR_CPUS 1491 int "Maximum number of CPUs (2-4096)" 1492 range 2 4096 1493 default "512" 1494 1495config HOTPLUG_CPU 1496 bool "Support for hot-pluggable CPUs" 1497 select GENERIC_IRQ_MIGRATION 1498 help 1499 Say Y here to experiment with turning CPUs off and on. CPUs 1500 can be controlled through /sys/devices/system/cpu. 1501 1502# Common NUMA Features 1503config NUMA 1504 bool "NUMA Memory Allocation and Scheduler Support" 1505 select GENERIC_ARCH_NUMA 1506 select OF_NUMA 1507 select HAVE_SETUP_PER_CPU_AREA 1508 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1509 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1510 select USE_PERCPU_NUMA_NODE_ID 1511 help 1512 Enable NUMA (Non-Uniform Memory Access) support. 1513 1514 The kernel will try to allocate memory used by a CPU on the 1515 local memory of the CPU and add some more 1516 NUMA awareness to the kernel. 1517 1518config NODES_SHIFT 1519 int "Maximum NUMA Nodes (as a power of 2)" 1520 range 1 10 1521 default "4" 1522 depends on NUMA 1523 help 1524 Specify the maximum number of NUMA Nodes available on the target 1525 system. Increases memory reserved to accommodate various tables. 1526 1527source "kernel/Kconfig.hz" 1528 1529config ARCH_SPARSEMEM_ENABLE 1530 def_bool y 1531 select SPARSEMEM_VMEMMAP_ENABLE 1532 select SPARSEMEM_VMEMMAP 1533 1534config HW_PERF_EVENTS 1535 def_bool y 1536 depends on ARM_PMU 1537 1538# Supported by clang >= 7.0 or GCC >= 12.0.0 1539config CC_HAVE_SHADOW_CALL_STACK 1540 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1541 1542config PARAVIRT 1543 bool "Enable paravirtualization code" 1544 help 1545 This changes the kernel so it can modify itself when it is run 1546 under a hypervisor, potentially improving performance significantly 1547 over full virtualization. 1548 1549config PARAVIRT_TIME_ACCOUNTING 1550 bool "Paravirtual steal time accounting" 1551 select PARAVIRT 1552 help 1553 Select this option to enable fine granularity task steal time 1554 accounting. Time spent executing other tasks in parallel with 1555 the current vCPU is discounted from the vCPU power. To account for 1556 that, there can be a small performance impact. 1557 1558 If in doubt, say N here. 1559 1560config ARCH_SUPPORTS_KEXEC 1561 def_bool PM_SLEEP_SMP 1562 1563config ARCH_SUPPORTS_KEXEC_FILE 1564 def_bool y 1565 1566config ARCH_SELECTS_KEXEC_FILE 1567 def_bool y 1568 depends on KEXEC_FILE 1569 select HAVE_IMA_KEXEC if IMA 1570 1571config ARCH_SUPPORTS_KEXEC_SIG 1572 def_bool y 1573 1574config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1575 def_bool y 1576 1577config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1578 def_bool y 1579 1580config ARCH_SUPPORTS_CRASH_DUMP 1581 def_bool y 1582 1583config ARCH_DEFAULT_CRASH_DUMP 1584 def_bool y 1585 1586config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1587 def_bool CRASH_RESERVE 1588 1589config TRANS_TABLE 1590 def_bool y 1591 depends on HIBERNATION || KEXEC_CORE 1592 1593config XEN_DOM0 1594 def_bool y 1595 depends on XEN 1596 1597config XEN 1598 bool "Xen guest support on ARM64" 1599 depends on ARM64 && OF 1600 select SWIOTLB_XEN 1601 select PARAVIRT 1602 help 1603 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1604 1605# include/linux/mmzone.h requires the following to be true: 1606# 1607# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1608# 1609# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1610# 1611# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1612# ----+-------------------+--------------+----------------------+-------------------------+ 1613# 4K | 27 | 12 | 15 | 10 | 1614# 16K | 27 | 14 | 13 | 11 | 1615# 64K | 29 | 16 | 13 | 13 | 1616config ARCH_FORCE_MAX_ORDER 1617 int 1618 default "13" if ARM64_64K_PAGES 1619 default "11" if ARM64_16K_PAGES 1620 default "10" 1621 help 1622 The kernel page allocator limits the size of maximal physically 1623 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1624 defines the maximal power of two of number of pages that can be 1625 allocated as a single contiguous block. This option allows 1626 overriding the default setting when ability to allocate very 1627 large blocks of physically contiguous memory is required. 1628 1629 The maximal size of allocation cannot exceed the size of the 1630 section, so the value of MAX_PAGE_ORDER should satisfy 1631 1632 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1633 1634 Don't change if unsure. 1635 1636config UNMAP_KERNEL_AT_EL0 1637 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1638 default y 1639 help 1640 Speculation attacks against some high-performance processors can 1641 be used to bypass MMU permission checks and leak kernel data to 1642 userspace. This can be defended against by unmapping the kernel 1643 when running in userspace, mapping it back in on exception entry 1644 via a trampoline page in the vector table. 1645 1646 If unsure, say Y. 1647 1648config MITIGATE_SPECTRE_BRANCH_HISTORY 1649 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1650 default y 1651 help 1652 Speculation attacks against some high-performance processors can 1653 make use of branch history to influence future speculation. 1654 When taking an exception from user-space, a sequence of branches 1655 or a firmware call overwrites the branch history. 1656 1657config RODATA_FULL_DEFAULT_ENABLED 1658 bool "Apply r/o permissions of VM areas also to their linear aliases" 1659 default y 1660 help 1661 Apply read-only attributes of VM areas to the linear alias of 1662 the backing pages as well. This prevents code or read-only data 1663 from being modified (inadvertently or intentionally) via another 1664 mapping of the same memory page. This additional enhancement can 1665 be turned off at runtime by passing rodata=[off|on] (and turned on 1666 with rodata=full if this option is set to 'n') 1667 1668 This requires the linear region to be mapped down to pages, 1669 which may adversely affect performance in some cases. 1670 1671config ARM64_SW_TTBR0_PAN 1672 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1673 depends on !KCSAN 1674 help 1675 Enabling this option prevents the kernel from accessing 1676 user-space memory directly by pointing TTBR0_EL1 to a reserved 1677 zeroed area and reserved ASID. The user access routines 1678 restore the valid TTBR0_EL1 temporarily. 1679 1680config ARM64_TAGGED_ADDR_ABI 1681 bool "Enable the tagged user addresses syscall ABI" 1682 default y 1683 help 1684 When this option is enabled, user applications can opt in to a 1685 relaxed ABI via prctl() allowing tagged addresses to be passed 1686 to system calls as pointer arguments. For details, see 1687 Documentation/arch/arm64/tagged-address-abi.rst. 1688 1689menuconfig COMPAT 1690 bool "Kernel support for 32-bit EL0" 1691 depends on ARM64_4K_PAGES || EXPERT 1692 select HAVE_UID16 1693 select OLD_SIGSUSPEND3 1694 select COMPAT_OLD_SIGACTION 1695 help 1696 This option enables support for a 32-bit EL0 running under a 64-bit 1697 kernel at EL1. AArch32-specific components such as system calls, 1698 the user helper functions, VFP support and the ptrace interface are 1699 handled appropriately by the kernel. 1700 1701 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1702 that you will only be able to execute AArch32 binaries that were compiled 1703 with page size aligned segments. 1704 1705 If you want to execute 32-bit userspace applications, say Y. 1706 1707if COMPAT 1708 1709config KUSER_HELPERS 1710 bool "Enable kuser helpers page for 32-bit applications" 1711 default y 1712 help 1713 Warning: disabling this option may break 32-bit user programs. 1714 1715 Provide kuser helpers to compat tasks. The kernel provides 1716 helper code to userspace in read only form at a fixed location 1717 to allow userspace to be independent of the CPU type fitted to 1718 the system. This permits binaries to be run on ARMv4 through 1719 to ARMv8 without modification. 1720 1721 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1722 1723 However, the fixed address nature of these helpers can be used 1724 by ROP (return orientated programming) authors when creating 1725 exploits. 1726 1727 If all of the binaries and libraries which run on your platform 1728 are built specifically for your platform, and make no use of 1729 these helpers, then you can turn this option off to hinder 1730 such exploits. However, in that case, if a binary or library 1731 relying on those helpers is run, it will not function correctly. 1732 1733 Say N here only if you are absolutely certain that you do not 1734 need these helpers; otherwise, the safe option is to say Y. 1735 1736config COMPAT_VDSO 1737 bool "Enable vDSO for 32-bit applications" 1738 depends on !CPU_BIG_ENDIAN 1739 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1740 select GENERIC_COMPAT_VDSO 1741 default y 1742 help 1743 Place in the process address space of 32-bit applications an 1744 ELF shared object providing fast implementations of gettimeofday 1745 and clock_gettime. 1746 1747 You must have a 32-bit build of glibc 2.22 or later for programs 1748 to seamlessly take advantage of this. 1749 1750config THUMB2_COMPAT_VDSO 1751 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1752 depends on COMPAT_VDSO 1753 default y 1754 help 1755 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1756 otherwise with '-marm'. 1757 1758config COMPAT_ALIGNMENT_FIXUPS 1759 bool "Fix up misaligned multi-word loads and stores in user space" 1760 1761menuconfig ARMV8_DEPRECATED 1762 bool "Emulate deprecated/obsolete ARMv8 instructions" 1763 depends on SYSCTL 1764 help 1765 Legacy software support may require certain instructions 1766 that have been deprecated or obsoleted in the architecture. 1767 1768 Enable this config to enable selective emulation of these 1769 features. 1770 1771 If unsure, say Y 1772 1773if ARMV8_DEPRECATED 1774 1775config SWP_EMULATION 1776 bool "Emulate SWP/SWPB instructions" 1777 help 1778 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1779 they are always undefined. Say Y here to enable software 1780 emulation of these instructions for userspace using LDXR/STXR. 1781 This feature can be controlled at runtime with the abi.swp 1782 sysctl which is disabled by default. 1783 1784 In some older versions of glibc [<=2.8] SWP is used during futex 1785 trylock() operations with the assumption that the code will not 1786 be preempted. This invalid assumption may be more likely to fail 1787 with SWP emulation enabled, leading to deadlock of the user 1788 application. 1789 1790 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1791 on an external transaction monitoring block called a global 1792 monitor to maintain update atomicity. If your system does not 1793 implement a global monitor, this option can cause programs that 1794 perform SWP operations to uncached memory to deadlock. 1795 1796 If unsure, say Y 1797 1798config CP15_BARRIER_EMULATION 1799 bool "Emulate CP15 Barrier instructions" 1800 help 1801 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1802 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1803 strongly recommended to use the ISB, DSB, and DMB 1804 instructions instead. 1805 1806 Say Y here to enable software emulation of these 1807 instructions for AArch32 userspace code. When this option is 1808 enabled, CP15 barrier usage is traced which can help 1809 identify software that needs updating. This feature can be 1810 controlled at runtime with the abi.cp15_barrier sysctl. 1811 1812 If unsure, say Y 1813 1814config SETEND_EMULATION 1815 bool "Emulate SETEND instruction" 1816 help 1817 The SETEND instruction alters the data-endianness of the 1818 AArch32 EL0, and is deprecated in ARMv8. 1819 1820 Say Y here to enable software emulation of the instruction 1821 for AArch32 userspace code. This feature can be controlled 1822 at runtime with the abi.setend sysctl. 1823 1824 Note: All the cpus on the system must have mixed endian support at EL0 1825 for this feature to be enabled. If a new CPU - which doesn't support mixed 1826 endian - is hotplugged in after this feature has been enabled, there could 1827 be unexpected results in the applications. 1828 1829 If unsure, say Y 1830endif # ARMV8_DEPRECATED 1831 1832endif # COMPAT 1833 1834menu "ARMv8.1 architectural features" 1835 1836config ARM64_HW_AFDBM 1837 bool "Support for hardware updates of the Access and Dirty page flags" 1838 default y 1839 help 1840 The ARMv8.1 architecture extensions introduce support for 1841 hardware updates of the access and dirty information in page 1842 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1843 capable processors, accesses to pages with PTE_AF cleared will 1844 set this bit instead of raising an access flag fault. 1845 Similarly, writes to read-only pages with the DBM bit set will 1846 clear the read-only bit (AP[2]) instead of raising a 1847 permission fault. 1848 1849 Kernels built with this configuration option enabled continue 1850 to work on pre-ARMv8.1 hardware and the performance impact is 1851 minimal. If unsure, say Y. 1852 1853config ARM64_PAN 1854 bool "Enable support for Privileged Access Never (PAN)" 1855 default y 1856 help 1857 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1858 prevents the kernel or hypervisor from accessing user-space (EL0) 1859 memory directly. 1860 1861 Choosing this option will cause any unprotected (not using 1862 copy_to_user et al) memory access to fail with a permission fault. 1863 1864 The feature is detected at runtime, and will remain as a 'nop' 1865 instruction if the cpu does not implement the feature. 1866 1867config AS_HAS_LSE_ATOMICS 1868 def_bool $(as-instr,.arch_extension lse) 1869 1870config ARM64_LSE_ATOMICS 1871 bool 1872 default ARM64_USE_LSE_ATOMICS 1873 depends on AS_HAS_LSE_ATOMICS 1874 1875config ARM64_USE_LSE_ATOMICS 1876 bool "Atomic instructions" 1877 default y 1878 help 1879 As part of the Large System Extensions, ARMv8.1 introduces new 1880 atomic instructions that are designed specifically to scale in 1881 very large systems. 1882 1883 Say Y here to make use of these instructions for the in-kernel 1884 atomic routines. This incurs a small overhead on CPUs that do 1885 not support these instructions and requires the kernel to be 1886 built with binutils >= 2.25 in order for the new instructions 1887 to be used. 1888 1889endmenu # "ARMv8.1 architectural features" 1890 1891menu "ARMv8.2 architectural features" 1892 1893config AS_HAS_ARMV8_2 1894 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1895 1896config AS_HAS_SHA3 1897 def_bool $(as-instr,.arch armv8.2-a+sha3) 1898 1899config ARM64_PMEM 1900 bool "Enable support for persistent memory" 1901 select ARCH_HAS_PMEM_API 1902 select ARCH_HAS_UACCESS_FLUSHCACHE 1903 help 1904 Say Y to enable support for the persistent memory API based on the 1905 ARMv8.2 DCPoP feature. 1906 1907 The feature is detected at runtime, and the kernel will use DC CVAC 1908 operations if DC CVAP is not supported (following the behaviour of 1909 DC CVAP itself if the system does not define a point of persistence). 1910 1911config ARM64_RAS_EXTN 1912 bool "Enable support for RAS CPU Extensions" 1913 default y 1914 help 1915 CPUs that support the Reliability, Availability and Serviceability 1916 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1917 errors, classify them and report them to software. 1918 1919 On CPUs with these extensions system software can use additional 1920 barriers to determine if faults are pending and read the 1921 classification from a new set of registers. 1922 1923 Selecting this feature will allow the kernel to use these barriers 1924 and access the new registers if the system supports the extension. 1925 Platform RAS features may additionally depend on firmware support. 1926 1927config ARM64_CNP 1928 bool "Enable support for Common Not Private (CNP) translations" 1929 default y 1930 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1931 help 1932 Common Not Private (CNP) allows translation table entries to 1933 be shared between different PEs in the same inner shareable 1934 domain, so the hardware can use this fact to optimise the 1935 caching of such entries in the TLB. 1936 1937 Selecting this option allows the CNP feature to be detected 1938 at runtime, and does not affect PEs that do not implement 1939 this feature. 1940 1941endmenu # "ARMv8.2 architectural features" 1942 1943menu "ARMv8.3 architectural features" 1944 1945config ARM64_PTR_AUTH 1946 bool "Enable support for pointer authentication" 1947 default y 1948 help 1949 Pointer authentication (part of the ARMv8.3 Extensions) provides 1950 instructions for signing and authenticating pointers against secret 1951 keys, which can be used to mitigate Return Oriented Programming (ROP) 1952 and other attacks. 1953 1954 This option enables these instructions at EL0 (i.e. for userspace). 1955 Choosing this option will cause the kernel to initialise secret keys 1956 for each process at exec() time, with these keys being 1957 context-switched along with the process. 1958 1959 The feature is detected at runtime. If the feature is not present in 1960 hardware it will not be advertised to userspace/KVM guest nor will it 1961 be enabled. 1962 1963 If the feature is present on the boot CPU but not on a late CPU, then 1964 the late CPU will be parked. Also, if the boot CPU does not have 1965 address auth and the late CPU has then the late CPU will still boot 1966 but with the feature disabled. On such a system, this option should 1967 not be selected. 1968 1969config ARM64_PTR_AUTH_KERNEL 1970 bool "Use pointer authentication for kernel" 1971 default y 1972 depends on ARM64_PTR_AUTH 1973 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1974 # Modern compilers insert a .note.gnu.property section note for PAC 1975 # which is only understood by binutils starting with version 2.33.1. 1976 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1977 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1978 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1979 help 1980 If the compiler supports the -mbranch-protection or 1981 -msign-return-address flag (e.g. GCC 7 or later), then this option 1982 will cause the kernel itself to be compiled with return address 1983 protection. In this case, and if the target hardware is known to 1984 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1985 disabled with minimal loss of protection. 1986 1987 This feature works with FUNCTION_GRAPH_TRACER option only if 1988 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1989 1990config CC_HAS_BRANCH_PROT_PAC_RET 1991 # GCC 9 or later, clang 8 or later 1992 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1993 1994config CC_HAS_SIGN_RETURN_ADDRESS 1995 # GCC 7, 8 1996 def_bool $(cc-option,-msign-return-address=all) 1997 1998config AS_HAS_ARMV8_3 1999 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 2000 2001config AS_HAS_CFI_NEGATE_RA_STATE 2002 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2003 2004config AS_HAS_LDAPR 2005 def_bool $(as-instr,.arch_extension rcpc) 2006 2007endmenu # "ARMv8.3 architectural features" 2008 2009menu "ARMv8.4 architectural features" 2010 2011config ARM64_AMU_EXTN 2012 bool "Enable support for the Activity Monitors Unit CPU extension" 2013 default y 2014 help 2015 The activity monitors extension is an optional extension introduced 2016 by the ARMv8.4 CPU architecture. This enables support for version 1 2017 of the activity monitors architecture, AMUv1. 2018 2019 To enable the use of this extension on CPUs that implement it, say Y. 2020 2021 Note that for architectural reasons, firmware _must_ implement AMU 2022 support when running on CPUs that present the activity monitors 2023 extension. The required support is present in: 2024 * Version 1.5 and later of the ARM Trusted Firmware 2025 2026 For kernels that have this configuration enabled but boot with broken 2027 firmware, you may need to say N here until the firmware is fixed. 2028 Otherwise you may experience firmware panics or lockups when 2029 accessing the counter registers. Even if you are not observing these 2030 symptoms, the values returned by the register reads might not 2031 correctly reflect reality. Most commonly, the value read will be 0, 2032 indicating that the counter is not enabled. 2033 2034config AS_HAS_ARMV8_4 2035 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2036 2037config ARM64_TLB_RANGE 2038 bool "Enable support for tlbi range feature" 2039 default y 2040 depends on AS_HAS_ARMV8_4 2041 help 2042 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2043 range of input addresses. 2044 2045 The feature introduces new assembly instructions, and they were 2046 support when binutils >= 2.30. 2047 2048endmenu # "ARMv8.4 architectural features" 2049 2050menu "ARMv8.5 architectural features" 2051 2052config AS_HAS_ARMV8_5 2053 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2054 2055config ARM64_BTI 2056 bool "Branch Target Identification support" 2057 default y 2058 help 2059 Branch Target Identification (part of the ARMv8.5 Extensions) 2060 provides a mechanism to limit the set of locations to which computed 2061 branch instructions such as BR or BLR can jump. 2062 2063 To make use of BTI on CPUs that support it, say Y. 2064 2065 BTI is intended to provide complementary protection to other control 2066 flow integrity protection mechanisms, such as the Pointer 2067 authentication mechanism provided as part of the ARMv8.3 Extensions. 2068 For this reason, it does not make sense to enable this option without 2069 also enabling support for pointer authentication. Thus, when 2070 enabling this option you should also select ARM64_PTR_AUTH=y. 2071 2072 Userspace binaries must also be specifically compiled to make use of 2073 this mechanism. If you say N here or the hardware does not support 2074 BTI, such binaries can still run, but you get no additional 2075 enforcement of branch destinations. 2076 2077config ARM64_BTI_KERNEL 2078 bool "Use Branch Target Identification for kernel" 2079 default y 2080 depends on ARM64_BTI 2081 depends on ARM64_PTR_AUTH_KERNEL 2082 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2083 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2084 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2085 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2086 depends on !CC_IS_GCC 2087 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2088 help 2089 Build the kernel with Branch Target Identification annotations 2090 and enable enforcement of this for kernel code. When this option 2091 is enabled and the system supports BTI all kernel code including 2092 modular code must have BTI enabled. 2093 2094config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2095 # GCC 9 or later, clang 8 or later 2096 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2097 2098config ARM64_E0PD 2099 bool "Enable support for E0PD" 2100 default y 2101 help 2102 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2103 that EL0 accesses made via TTBR1 always fault in constant time, 2104 providing similar benefits to KASLR as those provided by KPTI, but 2105 with lower overhead and without disrupting legitimate access to 2106 kernel memory such as SPE. 2107 2108 This option enables E0PD for TTBR1 where available. 2109 2110config ARM64_AS_HAS_MTE 2111 # Initial support for MTE went in binutils 2.32.0, checked with 2112 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2113 # as a late addition to the final architecture spec (LDGM/STGM) 2114 # is only supported in the newer 2.32.x and 2.33 binutils 2115 # versions, hence the extra "stgm" instruction check below. 2116 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2117 2118config ARM64_MTE 2119 bool "Memory Tagging Extension support" 2120 default y 2121 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2122 depends on AS_HAS_ARMV8_5 2123 depends on AS_HAS_LSE_ATOMICS 2124 # Required for tag checking in the uaccess routines 2125 depends on ARM64_PAN 2126 select ARCH_HAS_SUBPAGE_FAULTS 2127 select ARCH_USES_HIGH_VMA_FLAGS 2128 select ARCH_USES_PG_ARCH_2 2129 select ARCH_USES_PG_ARCH_3 2130 help 2131 Memory Tagging (part of the ARMv8.5 Extensions) provides 2132 architectural support for run-time, always-on detection of 2133 various classes of memory error to aid with software debugging 2134 to eliminate vulnerabilities arising from memory-unsafe 2135 languages. 2136 2137 This option enables the support for the Memory Tagging 2138 Extension at EL0 (i.e. for userspace). 2139 2140 Selecting this option allows the feature to be detected at 2141 runtime. Any secondary CPU not implementing this feature will 2142 not be allowed a late bring-up. 2143 2144 Userspace binaries that want to use this feature must 2145 explicitly opt in. The mechanism for the userspace is 2146 described in: 2147 2148 Documentation/arch/arm64/memory-tagging-extension.rst. 2149 2150endmenu # "ARMv8.5 architectural features" 2151 2152menu "ARMv8.7 architectural features" 2153 2154config ARM64_EPAN 2155 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2156 default y 2157 depends on ARM64_PAN 2158 help 2159 Enhanced Privileged Access Never (EPAN) allows Privileged 2160 Access Never to be used with Execute-only mappings. 2161 2162 The feature is detected at runtime, and will remain disabled 2163 if the cpu does not implement the feature. 2164endmenu # "ARMv8.7 architectural features" 2165 2166config AS_HAS_MOPS 2167 def_bool $(as-instr,.arch_extension mops) 2168 2169menu "ARMv8.9 architectural features" 2170 2171config ARM64_POE 2172 prompt "Permission Overlay Extension" 2173 def_bool y 2174 select ARCH_USES_HIGH_VMA_FLAGS 2175 select ARCH_HAS_PKEYS 2176 help 2177 The Permission Overlay Extension is used to implement Memory 2178 Protection Keys. Memory Protection Keys provides a mechanism for 2179 enforcing page-based protections, but without requiring modification 2180 of the page tables when an application changes protection domains. 2181 2182 For details, see Documentation/core-api/protection-keys.rst 2183 2184 If unsure, say y. 2185 2186config ARCH_PKEY_BITS 2187 int 2188 default 3 2189 2190config ARM64_HAFT 2191 bool "Support for Hardware managed Access Flag for Table Descriptors" 2192 depends on ARM64_HW_AFDBM 2193 default y 2194 help 2195 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2196 Flag for Table descriptors. When enabled an architectural executed 2197 memory access will update the Access Flag in each Table descriptor 2198 which is accessed during the translation table walk and for which 2199 the Access Flag is 0. The Access Flag of the Table descriptor use 2200 the same bit of PTE_AF. 2201 2202 The feature will only be enabled if all the CPUs in the system 2203 support this feature. If unsure, say Y. 2204 2205endmenu # "ARMv8.9 architectural features" 2206 2207menu "v9.4 architectural features" 2208 2209config ARM64_GCS 2210 bool "Enable support for Guarded Control Stack (GCS)" 2211 default y 2212 select ARCH_HAS_USER_SHADOW_STACK 2213 select ARCH_USES_HIGH_VMA_FLAGS 2214 depends on !UPROBES 2215 help 2216 Guarded Control Stack (GCS) provides support for a separate 2217 stack with restricted access which contains only return 2218 addresses. This can be used to harden against some attacks 2219 by comparing return address used by the program with what is 2220 stored in the GCS, and may also be used to efficiently obtain 2221 the call stack for applications such as profiling. 2222 2223 The feature is detected at runtime, and will remain disabled 2224 if the system does not implement the feature. 2225 2226endmenu # "v9.4 architectural features" 2227 2228config ARM64_SVE 2229 bool "ARM Scalable Vector Extension support" 2230 default y 2231 help 2232 The Scalable Vector Extension (SVE) is an extension to the AArch64 2233 execution state which complements and extends the SIMD functionality 2234 of the base architecture to support much larger vectors and to enable 2235 additional vectorisation opportunities. 2236 2237 To enable use of this extension on CPUs that implement it, say Y. 2238 2239 On CPUs that support the SVE2 extensions, this option will enable 2240 those too. 2241 2242 Note that for architectural reasons, firmware _must_ implement SVE 2243 support when running on SVE capable hardware. The required support 2244 is present in: 2245 2246 * version 1.5 and later of the ARM Trusted Firmware 2247 * the AArch64 boot wrapper since commit 5e1261e08abf 2248 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2249 2250 For other firmware implementations, consult the firmware documentation 2251 or vendor. 2252 2253 If you need the kernel to boot on SVE-capable hardware with broken 2254 firmware, you may need to say N here until you get your firmware 2255 fixed. Otherwise, you may experience firmware panics or lockups when 2256 booting the kernel. If unsure and you are not observing these 2257 symptoms, you should assume that it is safe to say Y. 2258 2259config ARM64_SME 2260 bool "ARM Scalable Matrix Extension support" 2261 default y 2262 depends on ARM64_SVE 2263 depends on BROKEN 2264 help 2265 The Scalable Matrix Extension (SME) is an extension to the AArch64 2266 execution state which utilises a substantial subset of the SVE 2267 instruction set, together with the addition of new architectural 2268 register state capable of holding two dimensional matrix tiles to 2269 enable various matrix operations. 2270 2271config ARM64_PSEUDO_NMI 2272 bool "Support for NMI-like interrupts" 2273 select ARM_GIC_V3 2274 help 2275 Adds support for mimicking Non-Maskable Interrupts through the use of 2276 GIC interrupt priority. This support requires version 3 or later of 2277 ARM GIC. 2278 2279 This high priority configuration for interrupts needs to be 2280 explicitly enabled by setting the kernel parameter 2281 "irqchip.gicv3_pseudo_nmi" to 1. 2282 2283 If unsure, say N 2284 2285if ARM64_PSEUDO_NMI 2286config ARM64_DEBUG_PRIORITY_MASKING 2287 bool "Debug interrupt priority masking" 2288 help 2289 This adds runtime checks to functions enabling/disabling 2290 interrupts when using priority masking. The additional checks verify 2291 the validity of ICC_PMR_EL1 when calling concerned functions. 2292 2293 If unsure, say N 2294endif # ARM64_PSEUDO_NMI 2295 2296config RELOCATABLE 2297 bool "Build a relocatable kernel image" if EXPERT 2298 select ARCH_HAS_RELR 2299 default y 2300 help 2301 This builds the kernel as a Position Independent Executable (PIE), 2302 which retains all relocation metadata required to relocate the 2303 kernel binary at runtime to a different virtual address than the 2304 address it was linked at. 2305 Since AArch64 uses the RELA relocation format, this requires a 2306 relocation pass at runtime even if the kernel is loaded at the 2307 same address it was linked at. 2308 2309config RANDOMIZE_BASE 2310 bool "Randomize the address of the kernel image" 2311 select RELOCATABLE 2312 help 2313 Randomizes the virtual address at which the kernel image is 2314 loaded, as a security feature that deters exploit attempts 2315 relying on knowledge of the location of kernel internals. 2316 2317 It is the bootloader's job to provide entropy, by passing a 2318 random u64 value in /chosen/kaslr-seed at kernel entry. 2319 2320 When booting via the UEFI stub, it will invoke the firmware's 2321 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2322 to the kernel proper. In addition, it will randomise the physical 2323 location of the kernel Image as well. 2324 2325 If unsure, say N. 2326 2327config RANDOMIZE_MODULE_REGION_FULL 2328 bool "Randomize the module region over a 2 GB range" 2329 depends on RANDOMIZE_BASE 2330 default y 2331 help 2332 Randomizes the location of the module region inside a 2 GB window 2333 covering the core kernel. This way, it is less likely for modules 2334 to leak information about the location of core kernel data structures 2335 but it does imply that function calls between modules and the core 2336 kernel will need to be resolved via veneers in the module PLT. 2337 2338 When this option is not set, the module region will be randomized over 2339 a limited range that contains the [_stext, _etext] interval of the 2340 core kernel, so branch relocations are almost always in range unless 2341 the region is exhausted. In this particular case of region 2342 exhaustion, modules might be able to fall back to a larger 2GB area. 2343 2344config CC_HAVE_STACKPROTECTOR_SYSREG 2345 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2346 2347config STACKPROTECTOR_PER_TASK 2348 def_bool y 2349 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2350 2351config UNWIND_PATCH_PAC_INTO_SCS 2352 bool "Enable shadow call stack dynamically using code patching" 2353 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2354 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2355 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2356 depends on SHADOW_CALL_STACK 2357 select UNWIND_TABLES 2358 select DYNAMIC_SCS 2359 2360config ARM64_CONTPTE 2361 bool "Contiguous PTE mappings for user memory" if EXPERT 2362 depends on TRANSPARENT_HUGEPAGE 2363 default y 2364 help 2365 When enabled, user mappings are configured using the PTE contiguous 2366 bit, for any mappings that meet the size and alignment requirements. 2367 This reduces TLB pressure and improves performance. 2368 2369endmenu # "Kernel Features" 2370 2371menu "Boot options" 2372 2373config ARM64_ACPI_PARKING_PROTOCOL 2374 bool "Enable support for the ARM64 ACPI parking protocol" 2375 depends on ACPI 2376 help 2377 Enable support for the ARM64 ACPI parking protocol. If disabled 2378 the kernel will not allow booting through the ARM64 ACPI parking 2379 protocol even if the corresponding data is present in the ACPI 2380 MADT table. 2381 2382config CMDLINE 2383 string "Default kernel command string" 2384 default "" 2385 help 2386 Provide a set of default command-line options at build time by 2387 entering them here. As a minimum, you should specify the the 2388 root device (e.g. root=/dev/nfs). 2389 2390choice 2391 prompt "Kernel command line type" 2392 depends on CMDLINE != "" 2393 default CMDLINE_FROM_BOOTLOADER 2394 help 2395 Choose how the kernel will handle the provided default kernel 2396 command line string. 2397 2398config CMDLINE_FROM_BOOTLOADER 2399 bool "Use bootloader kernel arguments if available" 2400 help 2401 Uses the command-line options passed by the boot loader. If 2402 the boot loader doesn't provide any, the default kernel command 2403 string provided in CMDLINE will be used. 2404 2405config CMDLINE_FORCE 2406 bool "Always use the default kernel command string" 2407 help 2408 Always use the default kernel command string, even if the boot 2409 loader passes other arguments to the kernel. 2410 This is useful if you cannot or don't want to change the 2411 command-line options your boot loader passes to the kernel. 2412 2413endchoice 2414 2415config EFI_STUB 2416 bool 2417 2418config EFI 2419 bool "UEFI runtime support" 2420 depends on OF && !CPU_BIG_ENDIAN 2421 depends on KERNEL_MODE_NEON 2422 select ARCH_SUPPORTS_ACPI 2423 select LIBFDT 2424 select UCS2_STRING 2425 select EFI_PARAMS_FROM_FDT 2426 select EFI_RUNTIME_WRAPPERS 2427 select EFI_STUB 2428 select EFI_GENERIC_STUB 2429 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2430 default y 2431 help 2432 This option provides support for runtime services provided 2433 by UEFI firmware (such as non-volatile variables, realtime 2434 clock, and platform reset). A UEFI stub is also provided to 2435 allow the kernel to be booted as an EFI application. This 2436 is only useful on systems that have UEFI firmware. 2437 2438config COMPRESSED_INSTALL 2439 bool "Install compressed image by default" 2440 help 2441 This makes the regular "make install" install the compressed 2442 image we built, not the legacy uncompressed one. 2443 2444 You can check that a compressed image works for you by doing 2445 "make zinstall" first, and verifying that everything is fine 2446 in your environment before making "make install" do this for 2447 you. 2448 2449config DMI 2450 bool "Enable support for SMBIOS (DMI) tables" 2451 depends on EFI 2452 default y 2453 help 2454 This enables SMBIOS/DMI feature for systems. 2455 2456 This option is only useful on systems that have UEFI firmware. 2457 However, even with this option, the resultant kernel should 2458 continue to boot on existing non-UEFI platforms. 2459 2460endmenu # "Boot options" 2461 2462menu "Power management options" 2463 2464source "kernel/power/Kconfig" 2465 2466config ARCH_HIBERNATION_POSSIBLE 2467 def_bool y 2468 depends on CPU_PM 2469 2470config ARCH_HIBERNATION_HEADER 2471 def_bool y 2472 depends on HIBERNATION 2473 2474config ARCH_SUSPEND_POSSIBLE 2475 def_bool y 2476 2477endmenu # "Power management options" 2478 2479menu "CPU Power Management" 2480 2481source "drivers/cpuidle/Kconfig" 2482 2483source "drivers/cpufreq/Kconfig" 2484 2485endmenu # "CPU Power Management" 2486 2487source "drivers/acpi/Kconfig" 2488 2489source "arch/arm64/kvm/Kconfig" 2490 2491