1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_GTDT if ACPI 6 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 7 select ACPI_MCFG if ACPI 8 select ACPI_SPCR_TABLE if ACPI 9 select ARCH_CLOCKSOURCE_DATA 10 select ARCH_HAS_DEBUG_VIRTUAL 11 select ARCH_HAS_DEVMEM_IS_ALLOWED 12 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 13 select ARCH_HAS_ELF_RANDOMIZE 14 select ARCH_HAS_GCOV_PROFILE_ALL 15 select ARCH_HAS_GIGANTIC_PAGE 16 select ARCH_HAS_KCOV 17 select ARCH_HAS_SET_MEMORY 18 select ARCH_HAS_SG_CHAIN 19 select ARCH_HAS_STRICT_KERNEL_RWX 20 select ARCH_HAS_STRICT_MODULE_RWX 21 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 22 select ARCH_USE_CMPXCHG_LOCKREF 23 select ARCH_SUPPORTS_ATOMIC_RMW 24 select ARCH_SUPPORTS_NUMA_BALANCING 25 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 26 select ARCH_WANT_FRAME_POINTERS 27 select ARCH_HAS_UBSAN_SANITIZE_ALL 28 select ARM_AMBA 29 select ARM_ARCH_TIMER 30 select ARM_GIC 31 select AUDIT_ARCH_COMPAT_GENERIC 32 select ARM_GIC_V2M if PCI 33 select ARM_GIC_V3 34 select ARM_GIC_V3_ITS if PCI 35 select ARM_PSCI_FW 36 select BUILDTIME_EXTABLE_SORT 37 select CLONE_BACKWARDS 38 select COMMON_CLK 39 select CPU_PM if (SUSPEND || CPU_IDLE) 40 select DCACHE_WORD_ACCESS 41 select EDAC_SUPPORT 42 select FRAME_POINTER 43 select GENERIC_ALLOCATOR 44 select GENERIC_CLOCKEVENTS 45 select GENERIC_CLOCKEVENTS_BROADCAST 46 select GENERIC_CPU_AUTOPROBE 47 select GENERIC_EARLY_IOREMAP 48 select GENERIC_IDLE_POLL_SETUP 49 select GENERIC_IRQ_PROBE 50 select GENERIC_IRQ_SHOW 51 select GENERIC_IRQ_SHOW_LEVEL 52 select GENERIC_PCI_IOMAP 53 select GENERIC_SCHED_CLOCK 54 select GENERIC_SMP_IDLE_THREAD 55 select GENERIC_STRNCPY_FROM_USER 56 select GENERIC_STRNLEN_USER 57 select GENERIC_TIME_VSYSCALL 58 select HANDLE_DOMAIN_IRQ 59 select HARDIRQS_SW_RESEND 60 select HAVE_ACPI_APEI if (ACPI && EFI) 61 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 62 select HAVE_ARCH_AUDITSYSCALL 63 select HAVE_ARCH_BITREVERSE 64 select HAVE_ARCH_HUGE_VMAP 65 select HAVE_ARCH_JUMP_LABEL 66 select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 67 select HAVE_ARCH_KGDB 68 select HAVE_ARCH_MMAP_RND_BITS 69 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 70 select HAVE_ARCH_SECCOMP_FILTER 71 select HAVE_ARCH_TRACEHOOK 72 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 73 select HAVE_ARM_SMCCC 74 select HAVE_EBPF_JIT 75 select HAVE_C_RECORDMCOUNT 76 select HAVE_CC_STACKPROTECTOR 77 select HAVE_CMPXCHG_DOUBLE 78 select HAVE_CMPXCHG_LOCAL 79 select HAVE_CONTEXT_TRACKING 80 select HAVE_DEBUG_BUGVERBOSE 81 select HAVE_DEBUG_KMEMLEAK 82 select HAVE_DMA_API_DEBUG 83 select HAVE_DMA_CONTIGUOUS 84 select HAVE_DYNAMIC_FTRACE 85 select HAVE_EFFICIENT_UNALIGNED_ACCESS 86 select HAVE_FTRACE_MCOUNT_RECORD 87 select HAVE_FUNCTION_TRACER 88 select HAVE_FUNCTION_GRAPH_TRACER 89 select HAVE_GCC_PLUGINS 90 select HAVE_GENERIC_DMA_COHERENT 91 select HAVE_HW_BREAKPOINT if PERF_EVENTS 92 select HAVE_IRQ_TIME_ACCOUNTING 93 select HAVE_MEMBLOCK 94 select HAVE_MEMBLOCK_NODE_MAP if NUMA 95 select HAVE_PATA_PLATFORM 96 select HAVE_PERF_EVENTS 97 select HAVE_PERF_REGS 98 select HAVE_PERF_USER_STACK_DUMP 99 select HAVE_REGS_AND_STACK_ACCESS_API 100 select HAVE_RCU_TABLE_FREE 101 select HAVE_SYSCALL_TRACEPOINTS 102 select HAVE_KPROBES 103 select HAVE_KRETPROBES 104 select IOMMU_DMA if IOMMU_SUPPORT 105 select IRQ_DOMAIN 106 select IRQ_FORCED_THREADING 107 select MODULES_USE_ELF_RELA 108 select NO_BOOTMEM 109 select OF 110 select OF_EARLY_FLATTREE 111 select OF_RESERVED_MEM 112 select PCI_ECAM if ACPI 113 select POWER_RESET 114 select POWER_SUPPLY 115 select SPARSE_IRQ 116 select SYSCTL_EXCEPTION_TRACE 117 select THREAD_INFO_IN_TASK 118 help 119 ARM 64-bit (AArch64) Linux support. 120 121config 64BIT 122 def_bool y 123 124config ARCH_PHYS_ADDR_T_64BIT 125 def_bool y 126 127config MMU 128 def_bool y 129 130config ARM64_PAGE_SHIFT 131 int 132 default 16 if ARM64_64K_PAGES 133 default 14 if ARM64_16K_PAGES 134 default 12 135 136config ARM64_CONT_SHIFT 137 int 138 default 5 if ARM64_64K_PAGES 139 default 7 if ARM64_16K_PAGES 140 default 4 141 142config ARCH_MMAP_RND_BITS_MIN 143 default 14 if ARM64_64K_PAGES 144 default 16 if ARM64_16K_PAGES 145 default 18 146 147# max bits determined by the following formula: 148# VA_BITS - PAGE_SHIFT - 3 149config ARCH_MMAP_RND_BITS_MAX 150 default 19 if ARM64_VA_BITS=36 151 default 24 if ARM64_VA_BITS=39 152 default 27 if ARM64_VA_BITS=42 153 default 30 if ARM64_VA_BITS=47 154 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 155 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 156 default 33 if ARM64_VA_BITS=48 157 default 14 if ARM64_64K_PAGES 158 default 16 if ARM64_16K_PAGES 159 default 18 160 161config ARCH_MMAP_RND_COMPAT_BITS_MIN 162 default 7 if ARM64_64K_PAGES 163 default 9 if ARM64_16K_PAGES 164 default 11 165 166config ARCH_MMAP_RND_COMPAT_BITS_MAX 167 default 16 168 169config NO_IOPORT_MAP 170 def_bool y if !PCI 171 172config STACKTRACE_SUPPORT 173 def_bool y 174 175config ILLEGAL_POINTER_VALUE 176 hex 177 default 0xdead000000000000 178 179config LOCKDEP_SUPPORT 180 def_bool y 181 182config TRACE_IRQFLAGS_SUPPORT 183 def_bool y 184 185config RWSEM_XCHGADD_ALGORITHM 186 def_bool y 187 188config GENERIC_BUG 189 def_bool y 190 depends on BUG 191 192config GENERIC_BUG_RELATIVE_POINTERS 193 def_bool y 194 depends on GENERIC_BUG 195 196config GENERIC_HWEIGHT 197 def_bool y 198 199config GENERIC_CSUM 200 def_bool y 201 202config GENERIC_CALIBRATE_DELAY 203 def_bool y 204 205config ZONE_DMA 206 def_bool y 207 208config HAVE_GENERIC_RCU_GUP 209 def_bool y 210 211config ARCH_DMA_ADDR_T_64BIT 212 def_bool y 213 214config NEED_DMA_MAP_STATE 215 def_bool y 216 217config NEED_SG_DMA_LENGTH 218 def_bool y 219 220config SMP 221 def_bool y 222 223config SWIOTLB 224 def_bool y 225 226config IOMMU_HELPER 227 def_bool SWIOTLB 228 229config KERNEL_MODE_NEON 230 def_bool y 231 232config FIX_EARLYCON_MEM 233 def_bool y 234 235config PGTABLE_LEVELS 236 int 237 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 238 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 239 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 240 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 241 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 242 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 243 244config ARCH_SUPPORTS_UPROBES 245 def_bool y 246 247source "init/Kconfig" 248 249source "kernel/Kconfig.freezer" 250 251source "arch/arm64/Kconfig.platforms" 252 253menu "Bus support" 254 255config PCI 256 bool "PCI support" 257 help 258 This feature enables support for PCI bus system. If you say Y 259 here, the kernel will include drivers and infrastructure code 260 to support PCI bus devices. 261 262config PCI_DOMAINS 263 def_bool PCI 264 265config PCI_DOMAINS_GENERIC 266 def_bool PCI 267 268config PCI_SYSCALL 269 def_bool PCI 270 271source "drivers/pci/Kconfig" 272 273endmenu 274 275menu "Kernel Features" 276 277menu "ARM errata workarounds via the alternatives framework" 278 279config ARM64_ERRATUM_826319 280 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 281 default y 282 help 283 This option adds an alternative code sequence to work around ARM 284 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 285 AXI master interface and an L2 cache. 286 287 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 288 and is unable to accept a certain write via this interface, it will 289 not progress on read data presented on the read data channel and the 290 system can deadlock. 291 292 The workaround promotes data cache clean instructions to 293 data cache clean-and-invalidate. 294 Please note that this does not necessarily enable the workaround, 295 as it depends on the alternative framework, which will only patch 296 the kernel if an affected CPU is detected. 297 298 If unsure, say Y. 299 300config ARM64_ERRATUM_827319 301 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 302 default y 303 help 304 This option adds an alternative code sequence to work around ARM 305 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 306 master interface and an L2 cache. 307 308 Under certain conditions this erratum can cause a clean line eviction 309 to occur at the same time as another transaction to the same address 310 on the AMBA 5 CHI interface, which can cause data corruption if the 311 interconnect reorders the two transactions. 312 313 The workaround promotes data cache clean instructions to 314 data cache clean-and-invalidate. 315 Please note that this does not necessarily enable the workaround, 316 as it depends on the alternative framework, which will only patch 317 the kernel if an affected CPU is detected. 318 319 If unsure, say Y. 320 321config ARM64_ERRATUM_824069 322 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 323 default y 324 help 325 This option adds an alternative code sequence to work around ARM 326 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 327 to a coherent interconnect. 328 329 If a Cortex-A53 processor is executing a store or prefetch for 330 write instruction at the same time as a processor in another 331 cluster is executing a cache maintenance operation to the same 332 address, then this erratum might cause a clean cache line to be 333 incorrectly marked as dirty. 334 335 The workaround promotes data cache clean instructions to 336 data cache clean-and-invalidate. 337 Please note that this option does not necessarily enable the 338 workaround, as it depends on the alternative framework, which will 339 only patch the kernel if an affected CPU is detected. 340 341 If unsure, say Y. 342 343config ARM64_ERRATUM_819472 344 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 345 default y 346 help 347 This option adds an alternative code sequence to work around ARM 348 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 349 present when it is connected to a coherent interconnect. 350 351 If the processor is executing a load and store exclusive sequence at 352 the same time as a processor in another cluster is executing a cache 353 maintenance operation to the same address, then this erratum might 354 cause data corruption. 355 356 The workaround promotes data cache clean instructions to 357 data cache clean-and-invalidate. 358 Please note that this does not necessarily enable the workaround, 359 as it depends on the alternative framework, which will only patch 360 the kernel if an affected CPU is detected. 361 362 If unsure, say Y. 363 364config ARM64_ERRATUM_832075 365 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 366 default y 367 help 368 This option adds an alternative code sequence to work around ARM 369 erratum 832075 on Cortex-A57 parts up to r1p2. 370 371 Affected Cortex-A57 parts might deadlock when exclusive load/store 372 instructions to Write-Back memory are mixed with Device loads. 373 374 The workaround is to promote device loads to use Load-Acquire 375 semantics. 376 Please note that this does not necessarily enable the workaround, 377 as it depends on the alternative framework, which will only patch 378 the kernel if an affected CPU is detected. 379 380 If unsure, say Y. 381 382config ARM64_ERRATUM_834220 383 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 384 depends on KVM 385 default y 386 help 387 This option adds an alternative code sequence to work around ARM 388 erratum 834220 on Cortex-A57 parts up to r1p2. 389 390 Affected Cortex-A57 parts might report a Stage 2 translation 391 fault as the result of a Stage 1 fault for load crossing a 392 page boundary when there is a permission or device memory 393 alignment fault at Stage 1 and a translation fault at Stage 2. 394 395 The workaround is to verify that the Stage 1 translation 396 doesn't generate a fault before handling the Stage 2 fault. 397 Please note that this does not necessarily enable the workaround, 398 as it depends on the alternative framework, which will only patch 399 the kernel if an affected CPU is detected. 400 401 If unsure, say Y. 402 403config ARM64_ERRATUM_845719 404 bool "Cortex-A53: 845719: a load might read incorrect data" 405 depends on COMPAT 406 default y 407 help 408 This option adds an alternative code sequence to work around ARM 409 erratum 845719 on Cortex-A53 parts up to r0p4. 410 411 When running a compat (AArch32) userspace on an affected Cortex-A53 412 part, a load at EL0 from a virtual address that matches the bottom 32 413 bits of the virtual address used by a recent load at (AArch64) EL1 414 might return incorrect data. 415 416 The workaround is to write the contextidr_el1 register on exception 417 return to a 32-bit task. 418 Please note that this does not necessarily enable the workaround, 419 as it depends on the alternative framework, which will only patch 420 the kernel if an affected CPU is detected. 421 422 If unsure, say Y. 423 424config ARM64_ERRATUM_843419 425 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 426 default y 427 select ARM64_MODULE_CMODEL_LARGE if MODULES 428 help 429 This option links the kernel with '--fix-cortex-a53-843419' and 430 builds modules using the large memory model in order to avoid the use 431 of the ADRP instruction, which can cause a subsequent memory access 432 to use an incorrect address on Cortex-A53 parts up to r0p4. 433 434 If unsure, say Y. 435 436config CAVIUM_ERRATUM_22375 437 bool "Cavium erratum 22375, 24313" 438 default y 439 help 440 Enable workaround for erratum 22375, 24313. 441 442 This implements two gicv3-its errata workarounds for ThunderX. Both 443 with small impact affecting only ITS table allocation. 444 445 erratum 22375: only alloc 8MB table size 446 erratum 24313: ignore memory access type 447 448 The fixes are in ITS initialization and basically ignore memory access 449 type and table size provided by the TYPER and BASER registers. 450 451 If unsure, say Y. 452 453config CAVIUM_ERRATUM_23144 454 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 455 depends on NUMA 456 default y 457 help 458 ITS SYNC command hang for cross node io and collections/cpu mapping. 459 460 If unsure, say Y. 461 462config CAVIUM_ERRATUM_23154 463 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 464 default y 465 help 466 The gicv3 of ThunderX requires a modified version for 467 reading the IAR status to ensure data synchronization 468 (access to icc_iar1_el1 is not sync'ed before and after). 469 470 If unsure, say Y. 471 472config CAVIUM_ERRATUM_27456 473 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 474 default y 475 help 476 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 477 instructions may cause the icache to become corrupted if it 478 contains data for a non-current ASID. The fix is to 479 invalidate the icache when changing the mm context. 480 481 If unsure, say Y. 482 483config QCOM_FALKOR_ERRATUM_1003 484 bool "Falkor E1003: Incorrect translation due to ASID change" 485 default y 486 select ARM64_PAN if ARM64_SW_TTBR0_PAN 487 help 488 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 489 and BADDR are changed together in TTBRx_EL1. The workaround for this 490 issue is to use a reserved ASID in cpu_do_switch_mm() before 491 switching to the new ASID. Saying Y here selects ARM64_PAN if 492 ARM64_SW_TTBR0_PAN is selected. This is done because implementing and 493 maintaining the E1003 workaround in the software PAN emulation code 494 would be an unnecessary complication. The affected Falkor v1 CPU 495 implements ARMv8.1 hardware PAN support and using hardware PAN 496 support versus software PAN emulation is mutually exclusive at 497 runtime. 498 499 If unsure, say Y. 500 501config QCOM_FALKOR_ERRATUM_1009 502 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 503 default y 504 help 505 On Falkor v1, the CPU may prematurely complete a DSB following a 506 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 507 one more time to fix the issue. 508 509 If unsure, say Y. 510 511config QCOM_QDF2400_ERRATUM_0065 512 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 513 default y 514 help 515 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 516 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 517 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 518 519 If unsure, say Y. 520 521endmenu 522 523 524choice 525 prompt "Page size" 526 default ARM64_4K_PAGES 527 help 528 Page size (translation granule) configuration. 529 530config ARM64_4K_PAGES 531 bool "4KB" 532 help 533 This feature enables 4KB pages support. 534 535config ARM64_16K_PAGES 536 bool "16KB" 537 help 538 The system will use 16KB pages support. AArch32 emulation 539 requires applications compiled with 16K (or a multiple of 16K) 540 aligned segments. 541 542config ARM64_64K_PAGES 543 bool "64KB" 544 help 545 This feature enables 64KB pages support (4KB by default) 546 allowing only two levels of page tables and faster TLB 547 look-up. AArch32 emulation requires applications compiled 548 with 64K aligned segments. 549 550endchoice 551 552choice 553 prompt "Virtual address space size" 554 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 555 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 556 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 557 help 558 Allows choosing one of multiple possible virtual address 559 space sizes. The level of translation table is determined by 560 a combination of page size and virtual address space size. 561 562config ARM64_VA_BITS_36 563 bool "36-bit" if EXPERT 564 depends on ARM64_16K_PAGES 565 566config ARM64_VA_BITS_39 567 bool "39-bit" 568 depends on ARM64_4K_PAGES 569 570config ARM64_VA_BITS_42 571 bool "42-bit" 572 depends on ARM64_64K_PAGES 573 574config ARM64_VA_BITS_47 575 bool "47-bit" 576 depends on ARM64_16K_PAGES 577 578config ARM64_VA_BITS_48 579 bool "48-bit" 580 581endchoice 582 583config ARM64_VA_BITS 584 int 585 default 36 if ARM64_VA_BITS_36 586 default 39 if ARM64_VA_BITS_39 587 default 42 if ARM64_VA_BITS_42 588 default 47 if ARM64_VA_BITS_47 589 default 48 if ARM64_VA_BITS_48 590 591config CPU_BIG_ENDIAN 592 bool "Build big-endian kernel" 593 help 594 Say Y if you plan on running a kernel in big-endian mode. 595 596config SCHED_MC 597 bool "Multi-core scheduler support" 598 help 599 Multi-core scheduler support improves the CPU scheduler's decision 600 making when dealing with multi-core CPU chips at a cost of slightly 601 increased overhead in some places. If unsure say N here. 602 603config SCHED_SMT 604 bool "SMT scheduler support" 605 help 606 Improves the CPU scheduler's decision making when dealing with 607 MultiThreading at a cost of slightly increased overhead in some 608 places. If unsure say N here. 609 610config NR_CPUS 611 int "Maximum number of CPUs (2-4096)" 612 range 2 4096 613 # These have to remain sorted largest to smallest 614 default "64" 615 616config HOTPLUG_CPU 617 bool "Support for hot-pluggable CPUs" 618 select GENERIC_IRQ_MIGRATION 619 help 620 Say Y here to experiment with turning CPUs off and on. CPUs 621 can be controlled through /sys/devices/system/cpu. 622 623# Common NUMA Features 624config NUMA 625 bool "Numa Memory Allocation and Scheduler Support" 626 select ACPI_NUMA if ACPI 627 select OF_NUMA 628 help 629 Enable NUMA (Non Uniform Memory Access) support. 630 631 The kernel will try to allocate memory used by a CPU on the 632 local memory of the CPU and add some more 633 NUMA awareness to the kernel. 634 635config NODES_SHIFT 636 int "Maximum NUMA Nodes (as a power of 2)" 637 range 1 10 638 default "2" 639 depends on NEED_MULTIPLE_NODES 640 help 641 Specify the maximum number of NUMA Nodes available on the target 642 system. Increases memory reserved to accommodate various tables. 643 644config USE_PERCPU_NUMA_NODE_ID 645 def_bool y 646 depends on NUMA 647 648config HAVE_SETUP_PER_CPU_AREA 649 def_bool y 650 depends on NUMA 651 652config NEED_PER_CPU_EMBED_FIRST_CHUNK 653 def_bool y 654 depends on NUMA 655 656config HOLES_IN_ZONE 657 def_bool y 658 depends on NUMA 659 660source kernel/Kconfig.preempt 661source kernel/Kconfig.hz 662 663config ARCH_SUPPORTS_DEBUG_PAGEALLOC 664 def_bool y 665 666config ARCH_HAS_HOLES_MEMORYMODEL 667 def_bool y if SPARSEMEM 668 669config ARCH_SPARSEMEM_ENABLE 670 def_bool y 671 select SPARSEMEM_VMEMMAP_ENABLE 672 673config ARCH_SPARSEMEM_DEFAULT 674 def_bool ARCH_SPARSEMEM_ENABLE 675 676config ARCH_SELECT_MEMORY_MODEL 677 def_bool ARCH_SPARSEMEM_ENABLE 678 679config HAVE_ARCH_PFN_VALID 680 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 681 682config HW_PERF_EVENTS 683 def_bool y 684 depends on ARM_PMU 685 686config SYS_SUPPORTS_HUGETLBFS 687 def_bool y 688 689config ARCH_WANT_HUGE_PMD_SHARE 690 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 691 692config ARCH_HAS_CACHE_LINE_SIZE 693 def_bool y 694 695source "mm/Kconfig" 696 697config SECCOMP 698 bool "Enable seccomp to safely compute untrusted bytecode" 699 ---help--- 700 This kernel feature is useful for number crunching applications 701 that may need to compute untrusted bytecode during their 702 execution. By using pipes or other transports made available to 703 the process as file descriptors supporting the read/write 704 syscalls, it's possible to isolate those applications in 705 their own address space using seccomp. Once seccomp is 706 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 707 and the task is only allowed to execute a few safe syscalls 708 defined by each seccomp mode. 709 710config PARAVIRT 711 bool "Enable paravirtualization code" 712 help 713 This changes the kernel so it can modify itself when it is run 714 under a hypervisor, potentially improving performance significantly 715 over full virtualization. 716 717config PARAVIRT_TIME_ACCOUNTING 718 bool "Paravirtual steal time accounting" 719 select PARAVIRT 720 default n 721 help 722 Select this option to enable fine granularity task steal time 723 accounting. Time spent executing other tasks in parallel with 724 the current vCPU is discounted from the vCPU power. To account for 725 that, there can be a small performance impact. 726 727 If in doubt, say N here. 728 729config KEXEC 730 depends on PM_SLEEP_SMP 731 select KEXEC_CORE 732 bool "kexec system call" 733 ---help--- 734 kexec is a system call that implements the ability to shutdown your 735 current kernel, and to start another kernel. It is like a reboot 736 but it is independent of the system firmware. And like a reboot 737 you can start any kernel with it, not just Linux. 738 739config CRASH_DUMP 740 bool "Build kdump crash kernel" 741 help 742 Generate crash dump after being started by kexec. This should 743 be normally only set in special crash dump kernels which are 744 loaded in the main kernel with kexec-tools into a specially 745 reserved region and then later executed after a crash by 746 kdump/kexec. 747 748 For more details see Documentation/kdump/kdump.txt 749 750config XEN_DOM0 751 def_bool y 752 depends on XEN 753 754config XEN 755 bool "Xen guest support on ARM64" 756 depends on ARM64 && OF 757 select SWIOTLB_XEN 758 select PARAVIRT 759 help 760 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 761 762config FORCE_MAX_ZONEORDER 763 int 764 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 765 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 766 default "11" 767 help 768 The kernel memory allocator divides physically contiguous memory 769 blocks into "zones", where each zone is a power of two number of 770 pages. This option selects the largest power of two that the kernel 771 keeps in the memory allocator. If you need to allocate very large 772 blocks of physically contiguous memory, then you may need to 773 increase this value. 774 775 This config option is actually maximum order plus one. For example, 776 a value of 11 means that the largest free memory block is 2^10 pages. 777 778 We make sure that we can allocate upto a HugePage size for each configuration. 779 Hence we have : 780 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 781 782 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 783 4M allocations matching the default size used by generic code. 784 785menuconfig ARMV8_DEPRECATED 786 bool "Emulate deprecated/obsolete ARMv8 instructions" 787 depends on COMPAT 788 help 789 Legacy software support may require certain instructions 790 that have been deprecated or obsoleted in the architecture. 791 792 Enable this config to enable selective emulation of these 793 features. 794 795 If unsure, say Y 796 797if ARMV8_DEPRECATED 798 799config SWP_EMULATION 800 bool "Emulate SWP/SWPB instructions" 801 help 802 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 803 they are always undefined. Say Y here to enable software 804 emulation of these instructions for userspace using LDXR/STXR. 805 806 In some older versions of glibc [<=2.8] SWP is used during futex 807 trylock() operations with the assumption that the code will not 808 be preempted. This invalid assumption may be more likely to fail 809 with SWP emulation enabled, leading to deadlock of the user 810 application. 811 812 NOTE: when accessing uncached shared regions, LDXR/STXR rely 813 on an external transaction monitoring block called a global 814 monitor to maintain update atomicity. If your system does not 815 implement a global monitor, this option can cause programs that 816 perform SWP operations to uncached memory to deadlock. 817 818 If unsure, say Y 819 820config CP15_BARRIER_EMULATION 821 bool "Emulate CP15 Barrier instructions" 822 help 823 The CP15 barrier instructions - CP15ISB, CP15DSB, and 824 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 825 strongly recommended to use the ISB, DSB, and DMB 826 instructions instead. 827 828 Say Y here to enable software emulation of these 829 instructions for AArch32 userspace code. When this option is 830 enabled, CP15 barrier usage is traced which can help 831 identify software that needs updating. 832 833 If unsure, say Y 834 835config SETEND_EMULATION 836 bool "Emulate SETEND instruction" 837 help 838 The SETEND instruction alters the data-endianness of the 839 AArch32 EL0, and is deprecated in ARMv8. 840 841 Say Y here to enable software emulation of the instruction 842 for AArch32 userspace code. 843 844 Note: All the cpus on the system must have mixed endian support at EL0 845 for this feature to be enabled. If a new CPU - which doesn't support mixed 846 endian - is hotplugged in after this feature has been enabled, there could 847 be unexpected results in the applications. 848 849 If unsure, say Y 850endif 851 852config ARM64_SW_TTBR0_PAN 853 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 854 help 855 Enabling this option prevents the kernel from accessing 856 user-space memory directly by pointing TTBR0_EL1 to a reserved 857 zeroed area and reserved ASID. The user access routines 858 restore the valid TTBR0_EL1 temporarily. 859 860menu "ARMv8.1 architectural features" 861 862config ARM64_HW_AFDBM 863 bool "Support for hardware updates of the Access and Dirty page flags" 864 default y 865 help 866 The ARMv8.1 architecture extensions introduce support for 867 hardware updates of the access and dirty information in page 868 table entries. When enabled in TCR_EL1 (HA and HD bits) on 869 capable processors, accesses to pages with PTE_AF cleared will 870 set this bit instead of raising an access flag fault. 871 Similarly, writes to read-only pages with the DBM bit set will 872 clear the read-only bit (AP[2]) instead of raising a 873 permission fault. 874 875 Kernels built with this configuration option enabled continue 876 to work on pre-ARMv8.1 hardware and the performance impact is 877 minimal. If unsure, say Y. 878 879config ARM64_PAN 880 bool "Enable support for Privileged Access Never (PAN)" 881 default y 882 help 883 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 884 prevents the kernel or hypervisor from accessing user-space (EL0) 885 memory directly. 886 887 Choosing this option will cause any unprotected (not using 888 copy_to_user et al) memory access to fail with a permission fault. 889 890 The feature is detected at runtime, and will remain as a 'nop' 891 instruction if the cpu does not implement the feature. 892 893config ARM64_LSE_ATOMICS 894 bool "Atomic instructions" 895 help 896 As part of the Large System Extensions, ARMv8.1 introduces new 897 atomic instructions that are designed specifically to scale in 898 very large systems. 899 900 Say Y here to make use of these instructions for the in-kernel 901 atomic routines. This incurs a small overhead on CPUs that do 902 not support these instructions and requires the kernel to be 903 built with binutils >= 2.25. 904 905config ARM64_VHE 906 bool "Enable support for Virtualization Host Extensions (VHE)" 907 default y 908 help 909 Virtualization Host Extensions (VHE) allow the kernel to run 910 directly at EL2 (instead of EL1) on processors that support 911 it. This leads to better performance for KVM, as they reduce 912 the cost of the world switch. 913 914 Selecting this option allows the VHE feature to be detected 915 at runtime, and does not affect processors that do not 916 implement this feature. 917 918endmenu 919 920menu "ARMv8.2 architectural features" 921 922config ARM64_UAO 923 bool "Enable support for User Access Override (UAO)" 924 default y 925 help 926 User Access Override (UAO; part of the ARMv8.2 Extensions) 927 causes the 'unprivileged' variant of the load/store instructions to 928 be overriden to be privileged. 929 930 This option changes get_user() and friends to use the 'unprivileged' 931 variant of the load/store instructions. This ensures that user-space 932 really did have access to the supplied memory. When addr_limit is 933 set to kernel memory the UAO bit will be set, allowing privileged 934 access to kernel memory. 935 936 Choosing this option will cause copy_to_user() et al to use user-space 937 memory permissions. 938 939 The feature is detected at runtime, the kernel will use the 940 regular load/store instructions if the cpu does not implement the 941 feature. 942 943endmenu 944 945config ARM64_MODULE_CMODEL_LARGE 946 bool 947 948config ARM64_MODULE_PLTS 949 bool 950 select ARM64_MODULE_CMODEL_LARGE 951 select HAVE_MOD_ARCH_SPECIFIC 952 953config RELOCATABLE 954 bool 955 help 956 This builds the kernel as a Position Independent Executable (PIE), 957 which retains all relocation metadata required to relocate the 958 kernel binary at runtime to a different virtual address than the 959 address it was linked at. 960 Since AArch64 uses the RELA relocation format, this requires a 961 relocation pass at runtime even if the kernel is loaded at the 962 same address it was linked at. 963 964config RANDOMIZE_BASE 965 bool "Randomize the address of the kernel image" 966 select ARM64_MODULE_PLTS if MODULES 967 select RELOCATABLE 968 help 969 Randomizes the virtual address at which the kernel image is 970 loaded, as a security feature that deters exploit attempts 971 relying on knowledge of the location of kernel internals. 972 973 It is the bootloader's job to provide entropy, by passing a 974 random u64 value in /chosen/kaslr-seed at kernel entry. 975 976 When booting via the UEFI stub, it will invoke the firmware's 977 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 978 to the kernel proper. In addition, it will randomise the physical 979 location of the kernel Image as well. 980 981 If unsure, say N. 982 983config RANDOMIZE_MODULE_REGION_FULL 984 bool "Randomize the module region independently from the core kernel" 985 depends on RANDOMIZE_BASE && !DYNAMIC_FTRACE 986 default y 987 help 988 Randomizes the location of the module region without considering the 989 location of the core kernel. This way, it is impossible for modules 990 to leak information about the location of core kernel data structures 991 but it does imply that function calls between modules and the core 992 kernel will need to be resolved via veneers in the module PLT. 993 994 When this option is not set, the module region will be randomized over 995 a limited range that contains the [_stext, _etext] interval of the 996 core kernel, so branch relocations are always in range. 997 998endmenu 999 1000menu "Boot options" 1001 1002config ARM64_ACPI_PARKING_PROTOCOL 1003 bool "Enable support for the ARM64 ACPI parking protocol" 1004 depends on ACPI 1005 help 1006 Enable support for the ARM64 ACPI parking protocol. If disabled 1007 the kernel will not allow booting through the ARM64 ACPI parking 1008 protocol even if the corresponding data is present in the ACPI 1009 MADT table. 1010 1011config CMDLINE 1012 string "Default kernel command string" 1013 default "" 1014 help 1015 Provide a set of default command-line options at build time by 1016 entering them here. As a minimum, you should specify the the 1017 root device (e.g. root=/dev/nfs). 1018 1019config CMDLINE_FORCE 1020 bool "Always use the default kernel command string" 1021 help 1022 Always use the default kernel command string, even if the boot 1023 loader passes other arguments to the kernel. 1024 This is useful if you cannot or don't want to change the 1025 command-line options your boot loader passes to the kernel. 1026 1027config EFI_STUB 1028 bool 1029 1030config EFI 1031 bool "UEFI runtime support" 1032 depends on OF && !CPU_BIG_ENDIAN 1033 select LIBFDT 1034 select UCS2_STRING 1035 select EFI_PARAMS_FROM_FDT 1036 select EFI_RUNTIME_WRAPPERS 1037 select EFI_STUB 1038 select EFI_ARMSTUB 1039 default y 1040 help 1041 This option provides support for runtime services provided 1042 by UEFI firmware (such as non-volatile variables, realtime 1043 clock, and platform reset). A UEFI stub is also provided to 1044 allow the kernel to be booted as an EFI application. This 1045 is only useful on systems that have UEFI firmware. 1046 1047config DMI 1048 bool "Enable support for SMBIOS (DMI) tables" 1049 depends on EFI 1050 default y 1051 help 1052 This enables SMBIOS/DMI feature for systems. 1053 1054 This option is only useful on systems that have UEFI firmware. 1055 However, even with this option, the resultant kernel should 1056 continue to boot on existing non-UEFI platforms. 1057 1058endmenu 1059 1060menu "Userspace binary formats" 1061 1062source "fs/Kconfig.binfmt" 1063 1064config COMPAT 1065 bool "Kernel support for 32-bit EL0" 1066 depends on ARM64_4K_PAGES || EXPERT 1067 select COMPAT_BINFMT_ELF if BINFMT_ELF 1068 select HAVE_UID16 1069 select OLD_SIGSUSPEND3 1070 select COMPAT_OLD_SIGACTION 1071 help 1072 This option enables support for a 32-bit EL0 running under a 64-bit 1073 kernel at EL1. AArch32-specific components such as system calls, 1074 the user helper functions, VFP support and the ptrace interface are 1075 handled appropriately by the kernel. 1076 1077 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1078 that you will only be able to execute AArch32 binaries that were compiled 1079 with page size aligned segments. 1080 1081 If you want to execute 32-bit userspace applications, say Y. 1082 1083config SYSVIPC_COMPAT 1084 def_bool y 1085 depends on COMPAT && SYSVIPC 1086 1087config KEYS_COMPAT 1088 def_bool y 1089 depends on COMPAT && KEYS 1090 1091endmenu 1092 1093menu "Power management options" 1094 1095source "kernel/power/Kconfig" 1096 1097config ARCH_HIBERNATION_POSSIBLE 1098 def_bool y 1099 depends on CPU_PM 1100 1101config ARCH_HIBERNATION_HEADER 1102 def_bool y 1103 depends on HIBERNATION 1104 1105config ARCH_SUSPEND_POSSIBLE 1106 def_bool y 1107 1108endmenu 1109 1110menu "CPU Power Management" 1111 1112source "drivers/cpuidle/Kconfig" 1113 1114source "drivers/cpufreq/Kconfig" 1115 1116endmenu 1117 1118source "net/Kconfig" 1119 1120source "drivers/Kconfig" 1121 1122source "drivers/firmware/Kconfig" 1123 1124source "drivers/acpi/Kconfig" 1125 1126source "fs/Kconfig" 1127 1128source "arch/arm64/kvm/Kconfig" 1129 1130source "arch/arm64/Kconfig.debug" 1131 1132source "security/Kconfig" 1133 1134source "crypto/Kconfig" 1135if CRYPTO 1136source "arch/arm64/crypto/Kconfig" 1137endif 1138 1139source "lib/Kconfig" 1140