1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION 25 select ARCH_HAS_CURRENT_STACK_POINTER 26 select ARCH_HAS_DEBUG_VIRTUAL 27 select ARCH_HAS_DEBUG_VM_PGTABLE 28 select ARCH_HAS_DMA_OPS if XEN 29 select ARCH_HAS_DMA_PREP_COHERENT 30 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 31 select ARCH_HAS_FAST_MULTIPLIER 32 select ARCH_HAS_FORTIFY_SOURCE 33 select ARCH_HAS_GCOV_PROFILE_ALL 34 select ARCH_HAS_GIGANTIC_PAGE 35 select ARCH_HAS_KCOV 36 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 37 select ARCH_HAS_KEEPINITRD 38 select ARCH_HAS_LAZY_MMU_MODE 39 select ARCH_HAS_MEMBARRIER_SYNC_CORE 40 select ARCH_HAS_MEM_ENCRYPT 41 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 42 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 43 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 44 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 45 select ARCH_HAS_PREEMPT_LAZY 46 select ARCH_HAS_PTDUMP 47 select ARCH_HAS_PTE_SPECIAL 48 select ARCH_HAS_HW_PTE_YOUNG 49 select ARCH_HAS_SETUP_DMA_OPS 50 select ARCH_HAS_SET_DIRECT_MAP 51 select ARCH_HAS_SET_MEMORY 52 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 53 select ARCH_STACKWALK 54 select ARCH_HAS_STRICT_KERNEL_RWX 55 select ARCH_HAS_STRICT_MODULE_RWX 56 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 57 select ARCH_HAS_SYNC_DMA_FOR_CPU 58 select ARCH_HAS_SYSCALL_WRAPPER 59 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 60 select ARCH_HAS_ZONE_DMA_SET if EXPERT 61 select ARCH_HAVE_ELF_PROT 62 select ARCH_HAVE_NMI_SAFE_CMPXCHG 63 select ARCH_HAVE_TRACE_MMIO_ACCESS 64 select ARCH_KEEP_MEMBLOCK 65 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 66 select ARCH_USE_CMPXCHG_LOCKREF 67 select ARCH_USE_GNU_PROPERTY 68 select ARCH_USE_MEMTEST 69 select ARCH_USE_QUEUED_RWLOCKS 70 select ARCH_USE_QUEUED_SPINLOCKS 71 select ARCH_USE_SYM_ANNOTATIONS 72 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 73 select ARCH_SUPPORTS_HUGETLBFS 74 select ARCH_SUPPORTS_MEMORY_FAILURE 75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 77 select ARCH_SUPPORTS_LTO_CLANG_THIN 78 select ARCH_SUPPORTS_CFI 79 select ARCH_SUPPORTS_ATOMIC_RMW 80 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 81 select ARCH_SUPPORTS_NUMA_BALANCING 82 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 83 select ARCH_SUPPORTS_PER_VMA_LOCK 84 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 85 select ARCH_SUPPORTS_RT 86 select ARCH_SUPPORTS_SCHED_SMT 87 select ARCH_SUPPORTS_SCHED_CLUSTER 88 select ARCH_SUPPORTS_SCHED_MC 89 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 90 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 91 select ARCH_WANT_DEFAULT_BPF_JIT 92 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 93 select ARCH_WANT_FRAME_POINTERS 94 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 95 select ARCH_WANT_LD_ORPHAN_WARN 96 select ARCH_WANTS_EXECMEM_LATE 97 select ARCH_WANTS_NO_INSTR 98 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 99 select ARCH_HAS_UBSAN 100 select ARM_AMBA 101 select ARM_ARCH_TIMER 102 select ARM_GIC 103 select AUDIT_ARCH_COMPAT_GENERIC 104 select ARM_GIC_V2M if PCI 105 select ARM_GIC_V3 106 select ARM_GIC_V3_ITS if PCI 107 select ARM_GIC_V5 108 select ARM_PSCI_FW 109 select BUILDTIME_TABLE_SORT 110 select CLONE_BACKWARDS 111 select COMMON_CLK 112 select CPU_PM if (SUSPEND || CPU_IDLE) 113 select CPUMASK_OFFSTACK if NR_CPUS > 256 114 select DCACHE_WORD_ACCESS 115 select HAVE_EXTRA_IPI_TRACEPOINTS 116 select DYNAMIC_FTRACE if FUNCTION_TRACER 117 select DMA_BOUNCE_UNALIGNED_KMALLOC 118 select DMA_DIRECT_REMAP 119 select EDAC_SUPPORT 120 select FRAME_POINTER 121 select FUNCTION_ALIGNMENT_4B 122 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 123 select GENERIC_ALLOCATOR 124 select GENERIC_ARCH_TOPOLOGY 125 select GENERIC_CLOCKEVENTS_BROADCAST 126 select GENERIC_CPU_AUTOPROBE 127 select GENERIC_CPU_CACHE_MAINTENANCE 128 select GENERIC_CPU_DEVICES 129 select GENERIC_CPU_VULNERABILITIES 130 select GENERIC_EARLY_IOREMAP 131 select GENERIC_IDLE_POLL_SETUP 132 select GENERIC_IOREMAP 133 select GENERIC_IRQ_ENTRY 134 select GENERIC_IRQ_IPI 135 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 136 select GENERIC_IRQ_PROBE 137 select GENERIC_IRQ_SHOW 138 select GENERIC_IRQ_SHOW_LEVEL 139 select GENERIC_LIB_DEVMEM_IS_ALLOWED 140 select GENERIC_PCI_IOMAP 141 select GENERIC_SCHED_CLOCK 142 select GENERIC_SMP_IDLE_THREAD 143 select GENERIC_TIME_VSYSCALL 144 select GENERIC_GETTIMEOFDAY 145 select HARDIRQS_SW_RESEND 146 select HAS_IOPORT 147 select HAVE_MOVE_PMD 148 select HAVE_MOVE_PUD 149 select HAVE_PCI 150 select HAVE_ACPI_APEI if (ACPI && EFI) 151 select HAVE_ALIGNED_STRUCT_PAGE 152 select HAVE_ARCH_AUDITSYSCALL 153 select HAVE_ARCH_BITREVERSE 154 select HAVE_ARCH_COMPILER_H 155 select HAVE_ARCH_HUGE_VMALLOC 156 select HAVE_ARCH_HUGE_VMAP 157 select HAVE_ARCH_JUMP_LABEL 158 select HAVE_ARCH_JUMP_LABEL_RELATIVE 159 select HAVE_ARCH_KASAN 160 select HAVE_ARCH_KASAN_VMALLOC 161 select HAVE_ARCH_KASAN_SW_TAGS 162 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 163 # Some instrumentation may be unsound, hence EXPERT 164 select HAVE_ARCH_KCSAN if EXPERT 165 select HAVE_ARCH_KFENCE 166 select HAVE_ARCH_KGDB 167 select HAVE_ARCH_KSTACK_ERASE 168 select HAVE_ARCH_MMAP_RND_BITS 169 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 170 select HAVE_ARCH_PREL32_RELOCATIONS 171 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 172 select HAVE_ARCH_SECCOMP_FILTER 173 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 174 select HAVE_ARCH_TRACEHOOK 175 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 176 select HAVE_ARCH_VMAP_STACK 177 select HAVE_ARM_SMCCC 178 select HAVE_ASM_MODVERSIONS 179 select HAVE_EBPF_JIT 180 select HAVE_C_RECORDMCOUNT 181 select HAVE_CMPXCHG_DOUBLE 182 select HAVE_CMPXCHG_LOCAL 183 select HAVE_CONTEXT_TRACKING_USER 184 select HAVE_DEBUG_KMEMLEAK 185 select HAVE_DMA_CONTIGUOUS 186 select HAVE_DYNAMIC_FTRACE 187 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 188 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 189 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 190 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 191 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 192 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 193 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 194 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 195 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 196 if DYNAMIC_FTRACE_WITH_ARGS 197 select HAVE_SAMPLE_FTRACE_DIRECT 198 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 199 select HAVE_BUILDTIME_MCOUNT_SORT 200 select HAVE_EFFICIENT_UNALIGNED_ACCESS 201 select HAVE_GUP_FAST 202 select HAVE_FTRACE_GRAPH_FUNC 203 select HAVE_FUNCTION_TRACER 204 select HAVE_FUNCTION_ERROR_INJECTION 205 select HAVE_FUNCTION_GRAPH_FREGS 206 select HAVE_FUNCTION_GRAPH_TRACER 207 select HAVE_GCC_PLUGINS 208 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 209 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 210 select HAVE_HW_BREAKPOINT if PERF_EVENTS 211 select HAVE_IOREMAP_PROT 212 select HAVE_IRQ_TIME_ACCOUNTING 213 select HAVE_LIVEPATCH 214 select HAVE_MOD_ARCH_SPECIFIC 215 select HAVE_NMI 216 select HAVE_PERF_EVENTS 217 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 218 select HAVE_PERF_REGS 219 select HAVE_PERF_USER_STACK_DUMP 220 select HAVE_PREEMPT_DYNAMIC_KEY 221 select HAVE_REGS_AND_STACK_ACCESS_API 222 select HAVE_RELIABLE_STACKTRACE 223 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 224 select HAVE_FUNCTION_ARG_ACCESS_API 225 select MMU_GATHER_RCU_TABLE_FREE 226 select HAVE_RSEQ 227 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 228 select HAVE_STACKPROTECTOR 229 select HAVE_SYSCALL_TRACEPOINTS 230 select HAVE_KPROBES 231 select HAVE_KRETPROBES 232 select HAVE_GENERIC_VDSO 233 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 234 select HOTPLUG_SMT if HOTPLUG_CPU 235 select IRQ_DOMAIN 236 select IRQ_FORCED_THREADING 237 select JUMP_LABEL 238 select KASAN_VMALLOC if KASAN 239 select LOCK_MM_AND_FIND_VMA 240 select MODULES_USE_ELF_RELA 241 select NEED_DMA_MAP_STATE 242 select NEED_SG_DMA_LENGTH 243 select OF 244 select OF_EARLY_FLATTREE 245 select PCI_DOMAINS_GENERIC if PCI 246 select PCI_ECAM if (ACPI && PCI) 247 select PCI_SYSCALL if PCI 248 select POWER_RESET 249 select POWER_SUPPLY 250 select SPARSE_IRQ 251 select SWIOTLB 252 select SYSCTL_EXCEPTION_TRACE 253 select THREAD_INFO_IN_TASK 254 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 255 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 256 select TRACE_IRQFLAGS_SUPPORT 257 select TRACE_IRQFLAGS_NMI_SUPPORT 258 select HAVE_SOFTIRQ_ON_OWN_STACK 259 select USER_STACKTRACE_SUPPORT 260 select VDSO_GETRANDOM 261 select VMAP_STACK 262 help 263 ARM 64-bit (AArch64) Linux support. 264 265config RUSTC_SUPPORTS_ARM64 266 def_bool y 267 depends on CPU_LITTLE_ENDIAN 268 # Shadow call stack is only supported on certain rustc versions. 269 # 270 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 271 # required due to use of the -Zfixed-x18 flag. 272 # 273 # Otherwise, rustc version 1.82+ is required due to use of the 274 # -Zsanitizer=shadow-call-stack flag. 275 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 276 277config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 278 def_bool CC_IS_CLANG 279 # https://github.com/ClangBuiltLinux/linux/issues/1507 280 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 281 282config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 283 def_bool CC_IS_GCC 284 depends on $(cc-option,-fpatchable-function-entry=2) 285 286config 64BIT 287 def_bool y 288 289config MMU 290 def_bool y 291 292config ARM64_CONT_PTE_SHIFT 293 int 294 default 5 if PAGE_SIZE_64KB 295 default 7 if PAGE_SIZE_16KB 296 default 4 297 298config ARM64_CONT_PMD_SHIFT 299 int 300 default 5 if PAGE_SIZE_64KB 301 default 5 if PAGE_SIZE_16KB 302 default 4 303 304config ARCH_MMAP_RND_BITS_MIN 305 default 14 if PAGE_SIZE_64KB 306 default 16 if PAGE_SIZE_16KB 307 default 18 308 309# max bits determined by the following formula: 310# VA_BITS - PTDESC_TABLE_SHIFT 311config ARCH_MMAP_RND_BITS_MAX 312 default 19 if ARM64_VA_BITS=36 313 default 24 if ARM64_VA_BITS=39 314 default 27 if ARM64_VA_BITS=42 315 default 30 if ARM64_VA_BITS=47 316 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 317 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 318 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 319 default 14 if ARM64_64K_PAGES 320 default 16 if ARM64_16K_PAGES 321 default 18 322 323config ARCH_MMAP_RND_COMPAT_BITS_MIN 324 default 7 if ARM64_64K_PAGES 325 default 9 if ARM64_16K_PAGES 326 default 11 327 328config ARCH_MMAP_RND_COMPAT_BITS_MAX 329 default 16 330 331config NO_IOPORT_MAP 332 def_bool y if !PCI 333 334config STACKTRACE_SUPPORT 335 def_bool y 336 337config ILLEGAL_POINTER_VALUE 338 hex 339 default 0xdead000000000000 340 341config LOCKDEP_SUPPORT 342 def_bool y 343 344config GENERIC_BUG 345 def_bool y 346 depends on BUG 347 348config GENERIC_BUG_RELATIVE_POINTERS 349 def_bool y 350 depends on GENERIC_BUG 351 352config GENERIC_HWEIGHT 353 def_bool y 354 355config GENERIC_CSUM 356 def_bool y 357 358config GENERIC_CALIBRATE_DELAY 359 def_bool y 360 361config SMP 362 def_bool y 363 364config KERNEL_MODE_NEON 365 def_bool y 366 367config FIX_EARLYCON_MEM 368 def_bool y 369 370config PGTABLE_LEVELS 371 int 372 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 373 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 374 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 375 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 376 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 377 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 378 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 379 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 380 381config ARCH_SUPPORTS_UPROBES 382 def_bool y 383 384config ARCH_PROC_KCORE_TEXT 385 def_bool y 386 387config BROKEN_GAS_INST 388 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 389 390config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 391 bool 392 # Clang's __builtin_return_address() strips the PAC since 12.0.0 393 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 394 default y if CC_IS_CLANG 395 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 396 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 397 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 398 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 399 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 400 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 401 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 402 default n 403 404config KASAN_SHADOW_OFFSET 405 hex 406 depends on KASAN_GENERIC || KASAN_SW_TAGS 407 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 408 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 409 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 410 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 411 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 412 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 413 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 414 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 415 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 416 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 417 default 0xffffffffffffffff 418 419config UNWIND_TABLES 420 bool 421 422source "arch/arm64/Kconfig.platforms" 423 424menu "Kernel Features" 425 426menu "ARM errata workarounds via the alternatives framework" 427 428config AMPERE_ERRATUM_AC03_CPU_38 429 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 430 default y 431 help 432 This option adds an alternative code sequence to work around Ampere 433 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 434 435 The affected design reports FEAT_HAFDBS as not implemented in 436 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 437 as required by the architecture. The unadvertised HAFDBS 438 implementation suffers from an additional erratum where hardware 439 A/D updates can occur after a PTE has been marked invalid. 440 441 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 442 which avoids enabling unadvertised hardware Access Flag management 443 at stage-2. 444 445 If unsure, say Y. 446 447config AMPERE_ERRATUM_AC04_CPU_23 448 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 449 default y 450 help 451 This option adds an alternative code sequence to work around Ampere 452 errata AC04_CPU_23 on AmpereOne. 453 454 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 455 data addresses initiated by load/store instructions. Only 456 instruction initiated translations are vulnerable, not translations 457 from prefetches for example. A DSB before the store to HCR_EL2 is 458 sufficient to prevent older instructions from hitting the window 459 for corruption, and an ISB after is sufficient to prevent younger 460 instructions from hitting the window for corruption. 461 462 If unsure, say Y. 463 464config ARM64_WORKAROUND_CLEAN_CACHE 465 bool 466 467config ARM64_ERRATUM_826319 468 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 469 default y 470 select ARM64_WORKAROUND_CLEAN_CACHE 471 help 472 This option adds an alternative code sequence to work around ARM 473 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 474 AXI master interface and an L2 cache. 475 476 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 477 and is unable to accept a certain write via this interface, it will 478 not progress on read data presented on the read data channel and the 479 system can deadlock. 480 481 The workaround promotes data cache clean instructions to 482 data cache clean-and-invalidate. 483 Please note that this does not necessarily enable the workaround, 484 as it depends on the alternative framework, which will only patch 485 the kernel if an affected CPU is detected. 486 487 If unsure, say Y. 488 489config ARM64_ERRATUM_827319 490 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 491 default y 492 select ARM64_WORKAROUND_CLEAN_CACHE 493 help 494 This option adds an alternative code sequence to work around ARM 495 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 496 master interface and an L2 cache. 497 498 Under certain conditions this erratum can cause a clean line eviction 499 to occur at the same time as another transaction to the same address 500 on the AMBA 5 CHI interface, which can cause data corruption if the 501 interconnect reorders the two transactions. 502 503 The workaround promotes data cache clean instructions to 504 data cache clean-and-invalidate. 505 Please note that this does not necessarily enable the workaround, 506 as it depends on the alternative framework, which will only patch 507 the kernel if an affected CPU is detected. 508 509 If unsure, say Y. 510 511config ARM64_ERRATUM_824069 512 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 513 default y 514 select ARM64_WORKAROUND_CLEAN_CACHE 515 help 516 This option adds an alternative code sequence to work around ARM 517 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 518 to a coherent interconnect. 519 520 If a Cortex-A53 processor is executing a store or prefetch for 521 write instruction at the same time as a processor in another 522 cluster is executing a cache maintenance operation to the same 523 address, then this erratum might cause a clean cache line to be 524 incorrectly marked as dirty. 525 526 The workaround promotes data cache clean instructions to 527 data cache clean-and-invalidate. 528 Please note that this option does not necessarily enable the 529 workaround, as it depends on the alternative framework, which will 530 only patch the kernel if an affected CPU is detected. 531 532 If unsure, say Y. 533 534config ARM64_ERRATUM_819472 535 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 536 default y 537 select ARM64_WORKAROUND_CLEAN_CACHE 538 help 539 This option adds an alternative code sequence to work around ARM 540 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 541 present when it is connected to a coherent interconnect. 542 543 If the processor is executing a load and store exclusive sequence at 544 the same time as a processor in another cluster is executing a cache 545 maintenance operation to the same address, then this erratum might 546 cause data corruption. 547 548 The workaround promotes data cache clean instructions to 549 data cache clean-and-invalidate. 550 Please note that this does not necessarily enable the workaround, 551 as it depends on the alternative framework, which will only patch 552 the kernel if an affected CPU is detected. 553 554 If unsure, say Y. 555 556config ARM64_ERRATUM_832075 557 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 558 default y 559 help 560 This option adds an alternative code sequence to work around ARM 561 erratum 832075 on Cortex-A57 parts up to r1p2. 562 563 Affected Cortex-A57 parts might deadlock when exclusive load/store 564 instructions to Write-Back memory are mixed with Device loads. 565 566 The workaround is to promote device loads to use Load-Acquire 567 semantics. 568 Please note that this does not necessarily enable the workaround, 569 as it depends on the alternative framework, which will only patch 570 the kernel if an affected CPU is detected. 571 572 If unsure, say Y. 573 574config ARM64_ERRATUM_834220 575 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 576 depends on KVM 577 help 578 This option adds an alternative code sequence to work around ARM 579 erratum 834220 on Cortex-A57 parts up to r1p2. 580 581 Affected Cortex-A57 parts might report a Stage 2 translation 582 fault as the result of a Stage 1 fault for load crossing a 583 page boundary when there is a permission or device memory 584 alignment fault at Stage 1 and a translation fault at Stage 2. 585 586 The workaround is to verify that the Stage 1 translation 587 doesn't generate a fault before handling the Stage 2 fault. 588 Please note that this does not necessarily enable the workaround, 589 as it depends on the alternative framework, which will only patch 590 the kernel if an affected CPU is detected. 591 592 If unsure, say N. 593 594config ARM64_ERRATUM_1742098 595 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 596 depends on COMPAT 597 default y 598 help 599 This option removes the AES hwcap for aarch32 user-space to 600 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 601 602 Affected parts may corrupt the AES state if an interrupt is 603 taken between a pair of AES instructions. These instructions 604 are only present if the cryptography extensions are present. 605 All software should have a fallback implementation for CPUs 606 that don't implement the cryptography extensions. 607 608 If unsure, say Y. 609 610config ARM64_ERRATUM_845719 611 bool "Cortex-A53: 845719: a load might read incorrect data" 612 depends on COMPAT 613 default y 614 help 615 This option adds an alternative code sequence to work around ARM 616 erratum 845719 on Cortex-A53 parts up to r0p4. 617 618 When running a compat (AArch32) userspace on an affected Cortex-A53 619 part, a load at EL0 from a virtual address that matches the bottom 32 620 bits of the virtual address used by a recent load at (AArch64) EL1 621 might return incorrect data. 622 623 The workaround is to write the contextidr_el1 register on exception 624 return to a 32-bit task. 625 Please note that this does not necessarily enable the workaround, 626 as it depends on the alternative framework, which will only patch 627 the kernel if an affected CPU is detected. 628 629 If unsure, say Y. 630 631config ARM64_ERRATUM_843419 632 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 633 default y 634 help 635 This option links the kernel with '--fix-cortex-a53-843419' and 636 enables PLT support to replace certain ADRP instructions, which can 637 cause subsequent memory accesses to use an incorrect address on 638 Cortex-A53 parts up to r0p4. 639 640 If unsure, say Y. 641 642config ARM64_ERRATUM_1024718 643 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 644 default y 645 help 646 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 647 648 Affected Cortex-A55 cores (all revisions) could cause incorrect 649 update of the hardware dirty bit when the DBM/AP bits are updated 650 without a break-before-make. The workaround is to disable the usage 651 of hardware DBM locally on the affected cores. CPUs not affected by 652 this erratum will continue to use the feature. 653 654 If unsure, say Y. 655 656config ARM64_ERRATUM_1418040 657 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 658 default y 659 depends on COMPAT 660 help 661 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 662 errata 1188873 and 1418040. 663 664 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 665 cause register corruption when accessing the timer registers 666 from AArch32 userspace. 667 668 If unsure, say Y. 669 670config ARM64_WORKAROUND_SPECULATIVE_AT 671 bool 672 673config ARM64_ERRATUM_1165522 674 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 675 default y 676 select ARM64_WORKAROUND_SPECULATIVE_AT 677 help 678 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 679 680 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 681 corrupted TLBs by speculating an AT instruction during a guest 682 context switch. 683 684 If unsure, say Y. 685 686config ARM64_ERRATUM_1319367 687 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 688 default y 689 select ARM64_WORKAROUND_SPECULATIVE_AT 690 help 691 This option adds work arounds for ARM Cortex-A57 erratum 1319537 692 and A72 erratum 1319367 693 694 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 695 speculating an AT instruction during a guest context switch. 696 697 If unsure, say Y. 698 699config ARM64_ERRATUM_1530923 700 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 701 default y 702 select ARM64_WORKAROUND_SPECULATIVE_AT 703 help 704 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 705 706 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 707 corrupted TLBs by speculating an AT instruction during a guest 708 context switch. 709 710 If unsure, say Y. 711 712config ARM64_WORKAROUND_REPEAT_TLBI 713 bool 714 715config ARM64_ERRATUM_2441007 716 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 717 select ARM64_WORKAROUND_REPEAT_TLBI 718 help 719 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 720 721 Under very rare circumstances, affected Cortex-A55 CPUs 722 may not handle a race between a break-before-make sequence on one 723 CPU, and another CPU accessing the same page. This could allow a 724 store to a page that has been unmapped. 725 726 Work around this by adding the affected CPUs to the list that needs 727 TLB sequences to be done twice. 728 729 If unsure, say N. 730 731config ARM64_ERRATUM_1286807 732 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 733 select ARM64_WORKAROUND_REPEAT_TLBI 734 help 735 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 736 737 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 738 address for a cacheable mapping of a location is being 739 accessed by a core while another core is remapping the virtual 740 address to a new physical page using the recommended 741 break-before-make sequence, then under very rare circumstances 742 TLBI+DSB completes before a read using the translation being 743 invalidated has been observed by other observers. The 744 workaround repeats the TLBI+DSB operation. 745 746 If unsure, say N. 747 748config ARM64_ERRATUM_1463225 749 bool "Cortex-A76: Software Step might prevent interrupt recognition" 750 default y 751 help 752 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 753 754 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 755 of a system call instruction (SVC) can prevent recognition of 756 subsequent interrupts when software stepping is disabled in the 757 exception handler of the system call and either kernel debugging 758 is enabled or VHE is in use. 759 760 Work around the erratum by triggering a dummy step exception 761 when handling a system call from a task that is being stepped 762 in a VHE configuration of the kernel. 763 764 If unsure, say Y. 765 766config ARM64_ERRATUM_1542419 767 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 768 help 769 This option adds a workaround for ARM Neoverse-N1 erratum 770 1542419. 771 772 Affected Neoverse-N1 cores could execute a stale instruction when 773 modified by another CPU. The workaround depends on a firmware 774 counterpart. 775 776 Workaround the issue by hiding the DIC feature from EL0. This 777 forces user-space to perform cache maintenance. 778 779 If unsure, say N. 780 781config ARM64_ERRATUM_1508412 782 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 783 default y 784 help 785 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 786 787 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 788 of a store-exclusive or read of PAR_EL1 and a load with device or 789 non-cacheable memory attributes. The workaround depends on a firmware 790 counterpart. 791 792 KVM guests must also have the workaround implemented or they can 793 deadlock the system. 794 795 Work around the issue by inserting DMB SY barriers around PAR_EL1 796 register reads and warning KVM users. The DMB barrier is sufficient 797 to prevent a speculative PAR_EL1 read. 798 799 If unsure, say Y. 800 801config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 802 bool 803 804config ARM64_ERRATUM_2051678 805 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 806 default y 807 help 808 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 809 Affected Cortex-A510 might not respect the ordering rules for 810 hardware update of the page table's dirty bit. The workaround 811 is to not enable the feature on affected CPUs. 812 813 If unsure, say Y. 814 815config ARM64_ERRATUM_2077057 816 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 817 default y 818 help 819 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 820 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 821 expected, but a Pointer Authentication trap is taken instead. The 822 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 823 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 824 825 This can only happen when EL2 is stepping EL1. 826 827 When these conditions occur, the SPSR_EL2 value is unchanged from the 828 previous guest entry, and can be restored from the in-memory copy. 829 830 If unsure, say Y. 831 832config ARM64_ERRATUM_2658417 833 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 834 default y 835 help 836 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 837 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 838 BFMMLA or VMMLA instructions in rare circumstances when a pair of 839 A510 CPUs are using shared neon hardware. As the sharing is not 840 discoverable by the kernel, hide the BF16 HWCAP to indicate that 841 user-space should not be using these instructions. 842 843 If unsure, say Y. 844 845config ARM64_ERRATUM_2119858 846 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 847 default y 848 depends on CORESIGHT_TRBE 849 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 850 help 851 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 852 853 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 854 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 855 the event of a WRAP event. 856 857 Work around the issue by always making sure we move the TRBPTR_EL1 by 858 256 bytes before enabling the buffer and filling the first 256 bytes of 859 the buffer with ETM ignore packets upon disabling. 860 861 If unsure, say Y. 862 863config ARM64_ERRATUM_2139208 864 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 865 default y 866 depends on CORESIGHT_TRBE 867 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 868 help 869 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 870 871 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 872 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 873 the event of a WRAP event. 874 875 Work around the issue by always making sure we move the TRBPTR_EL1 by 876 256 bytes before enabling the buffer and filling the first 256 bytes of 877 the buffer with ETM ignore packets upon disabling. 878 879 If unsure, say Y. 880 881config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 882 bool 883 884config ARM64_ERRATUM_2054223 885 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 886 default y 887 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 888 help 889 Enable workaround for ARM Cortex-A710 erratum 2054223 890 891 Affected cores may fail to flush the trace data on a TSB instruction, when 892 the PE is in trace prohibited state. This will cause losing a few bytes 893 of the trace cached. 894 895 Workaround is to issue two TSB consecutively on affected cores. 896 897 If unsure, say Y. 898 899config ARM64_ERRATUM_2067961 900 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 901 default y 902 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 903 help 904 Enable workaround for ARM Neoverse-N2 erratum 2067961 905 906 Affected cores may fail to flush the trace data on a TSB instruction, when 907 the PE is in trace prohibited state. This will cause losing a few bytes 908 of the trace cached. 909 910 Workaround is to issue two TSB consecutively on affected cores. 911 912 If unsure, say Y. 913 914config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 915 bool 916 917config ARM64_ERRATUM_2253138 918 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 919 depends on CORESIGHT_TRBE 920 default y 921 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 922 help 923 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 924 925 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 926 for TRBE. Under some conditions, the TRBE might generate a write to the next 927 virtually addressed page following the last page of the TRBE address space 928 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 929 930 Work around this in the driver by always making sure that there is a 931 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 932 933 If unsure, say Y. 934 935config ARM64_ERRATUM_2224489 936 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 937 depends on CORESIGHT_TRBE 938 default y 939 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 940 help 941 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 942 943 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 944 for TRBE. Under some conditions, the TRBE might generate a write to the next 945 virtually addressed page following the last page of the TRBE address space 946 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 947 948 Work around this in the driver by always making sure that there is a 949 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 950 951 If unsure, say Y. 952 953config ARM64_ERRATUM_2441009 954 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 955 select ARM64_WORKAROUND_REPEAT_TLBI 956 help 957 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 958 959 Under very rare circumstances, affected Cortex-A510 CPUs 960 may not handle a race between a break-before-make sequence on one 961 CPU, and another CPU accessing the same page. This could allow a 962 store to a page that has been unmapped. 963 964 Work around this by adding the affected CPUs to the list that needs 965 TLB sequences to be done twice. 966 967 If unsure, say N. 968 969config ARM64_ERRATUM_2064142 970 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 971 depends on CORESIGHT_TRBE 972 default y 973 help 974 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 975 976 Affected Cortex-A510 core might fail to write into system registers after the 977 TRBE has been disabled. Under some conditions after the TRBE has been disabled 978 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 979 and TRBTRG_EL1 will be ignored and will not be effected. 980 981 Work around this in the driver by executing TSB CSYNC and DSB after collection 982 is stopped and before performing a system register write to one of the affected 983 registers. 984 985 If unsure, say Y. 986 987config ARM64_ERRATUM_2038923 988 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 989 depends on CORESIGHT_TRBE 990 default y 991 help 992 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 993 994 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 995 prohibited within the CPU. As a result, the trace buffer or trace buffer state 996 might be corrupted. This happens after TRBE buffer has been enabled by setting 997 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 998 execution changes from a context, in which trace is prohibited to one where it 999 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1000 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1001 the trace buffer state might be corrupted. 1002 1003 Work around this in the driver by preventing an inconsistent view of whether the 1004 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1005 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1006 two ISB instructions if no ERET is to take place. 1007 1008 If unsure, say Y. 1009 1010config ARM64_ERRATUM_1902691 1011 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1012 depends on CORESIGHT_TRBE 1013 default y 1014 help 1015 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1016 1017 Affected Cortex-A510 core might cause trace data corruption, when being written 1018 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1019 trace data. 1020 1021 Work around this problem in the driver by just preventing TRBE initialization on 1022 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1023 on such implementations. This will cover the kernel for any firmware that doesn't 1024 do this already. 1025 1026 If unsure, say Y. 1027 1028config ARM64_ERRATUM_2457168 1029 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1030 depends on ARM64_AMU_EXTN 1031 default y 1032 help 1033 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1034 1035 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1036 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1037 incorrectly giving a significantly higher output value. 1038 1039 Work around this problem by returning 0 when reading the affected counter in 1040 key locations that results in disabling all users of this counter. This effect 1041 is the same to firmware disabling affected counters. 1042 1043 If unsure, say Y. 1044 1045config ARM64_ERRATUM_2645198 1046 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1047 default y 1048 help 1049 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1050 1051 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1052 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1053 next instruction abort caused by permission fault. 1054 1055 Only user-space does executable to non-executable permission transition via 1056 mprotect() system call. Workaround the problem by doing a break-before-make 1057 TLB invalidation, for all changes to executable user space mappings. 1058 1059 If unsure, say Y. 1060 1061config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1062 bool 1063 1064config ARM64_ERRATUM_2966298 1065 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1066 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1067 default y 1068 help 1069 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1070 1071 On an affected Cortex-A520 core, a speculatively executed unprivileged 1072 load might leak data from a privileged level via a cache side channel. 1073 1074 Work around this problem by executing a TLBI before returning to EL0. 1075 1076 If unsure, say Y. 1077 1078config ARM64_ERRATUM_3117295 1079 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1080 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1081 default y 1082 help 1083 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1084 1085 On an affected Cortex-A510 core, a speculatively executed unprivileged 1086 load might leak data from a privileged level via a cache side channel. 1087 1088 Work around this problem by executing a TLBI before returning to EL0. 1089 1090 If unsure, say Y. 1091 1092config ARM64_ERRATUM_3194386 1093 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1094 default y 1095 help 1096 This option adds the workaround for the following errata: 1097 1098 * ARM Cortex-A76 erratum 3324349 1099 * ARM Cortex-A77 erratum 3324348 1100 * ARM Cortex-A78 erratum 3324344 1101 * ARM Cortex-A78C erratum 3324346 1102 * ARM Cortex-A78C erratum 3324347 1103 * ARM Cortex-A710 erratam 3324338 1104 * ARM Cortex-A715 errartum 3456084 1105 * ARM Cortex-A720 erratum 3456091 1106 * ARM Cortex-A725 erratum 3456106 1107 * ARM Cortex-X1 erratum 3324344 1108 * ARM Cortex-X1C erratum 3324346 1109 * ARM Cortex-X2 erratum 3324338 1110 * ARM Cortex-X3 erratum 3324335 1111 * ARM Cortex-X4 erratum 3194386 1112 * ARM Cortex-X925 erratum 3324334 1113 * ARM Neoverse-N1 erratum 3324349 1114 * ARM Neoverse N2 erratum 3324339 1115 * ARM Neoverse-N3 erratum 3456111 1116 * ARM Neoverse-V1 erratum 3324341 1117 * ARM Neoverse V2 erratum 3324336 1118 * ARM Neoverse-V3 erratum 3312417 1119 * ARM Neoverse-V3AE erratum 3312417 1120 1121 On affected cores "MSR SSBS, #0" instructions may not affect 1122 subsequent speculative instructions, which may permit unexepected 1123 speculative store bypassing. 1124 1125 Work around this problem by placing a Speculation Barrier (SB) or 1126 Instruction Synchronization Barrier (ISB) after kernel changes to 1127 SSBS. The presence of the SSBS special-purpose register is hidden 1128 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1129 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1130 1131 If unsure, say Y. 1132 1133config ARM64_ERRATUM_4311569 1134 bool "SI L1: 4311569: workaround for premature CMO completion erratum" 1135 default y 1136 help 1137 This option adds the workaround for ARM SI L1 erratum 4311569. 1138 1139 The erratum of SI L1 can cause an early response to a combined write 1140 and cache maintenance operation (WR+CMO) before the operation is fully 1141 completed to the Point of Serialization (POS). 1142 This can result in a non-I/O coherent agent observing stale data, 1143 potentially leading to system instability or incorrect behavior. 1144 1145 Enabling this option implements a software workaround by inserting a 1146 second loop of Cache Maintenance Operation (CMO) immediately following the 1147 end of function to do CMOs. This ensures that the data is correctly serialized 1148 before the buffer is handed off to a non-coherent agent. 1149 1150 If unsure, say Y. 1151 1152config ARM64_ERRATUM_4193714 1153 bool "C1-Pro: 4193714: SME DVMSync early acknowledgement" 1154 depends on ARM64_SME 1155 default y 1156 help 1157 Enable workaround for C1-Pro acknowledging the DVMSync before 1158 the SME memory accesses are complete. This will cause TLB 1159 maintenance for processes using SME to also issue an IPI to 1160 the affected CPUs. 1161 1162 If unsure, say Y. 1163 1164config CAVIUM_ERRATUM_22375 1165 bool "Cavium erratum 22375, 24313" 1166 default y 1167 help 1168 Enable workaround for errata 22375 and 24313. 1169 1170 This implements two gicv3-its errata workarounds for ThunderX. Both 1171 with a small impact affecting only ITS table allocation. 1172 1173 erratum 22375: only alloc 8MB table size 1174 erratum 24313: ignore memory access type 1175 1176 The fixes are in ITS initialization and basically ignore memory access 1177 type and table size provided by the TYPER and BASER registers. 1178 1179 If unsure, say Y. 1180 1181config CAVIUM_ERRATUM_23144 1182 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1183 depends on NUMA 1184 default y 1185 help 1186 ITS SYNC command hang for cross node io and collections/cpu mapping. 1187 1188 If unsure, say Y. 1189 1190config CAVIUM_ERRATUM_23154 1191 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1192 default y 1193 help 1194 The ThunderX GICv3 implementation requires a modified version for 1195 reading the IAR status to ensure data synchronization 1196 (access to icc_iar1_el1 is not sync'ed before and after). 1197 1198 It also suffers from erratum 38545 (also present on Marvell's 1199 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1200 spuriously presented to the CPU interface. 1201 1202 If unsure, say Y. 1203 1204config CAVIUM_ERRATUM_27456 1205 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1206 default y 1207 help 1208 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1209 instructions may cause the icache to become corrupted if it 1210 contains data for a non-current ASID. The fix is to 1211 invalidate the icache when changing the mm context. 1212 1213 If unsure, say Y. 1214 1215config CAVIUM_ERRATUM_30115 1216 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1217 default y 1218 help 1219 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1220 1.2, and T83 Pass 1.0, KVM guest execution may disable 1221 interrupts in host. Trapping both GICv3 group-0 and group-1 1222 accesses sidesteps the issue. 1223 1224 If unsure, say Y. 1225 1226config CAVIUM_TX2_ERRATUM_219 1227 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1228 default y 1229 help 1230 On Cavium ThunderX2, a load, store or prefetch instruction between a 1231 TTBR update and the corresponding context synchronizing operation can 1232 cause a spurious Data Abort to be delivered to any hardware thread in 1233 the CPU core. 1234 1235 Work around the issue by avoiding the problematic code sequence and 1236 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1237 trap handler performs the corresponding register access, skips the 1238 instruction and ensures context synchronization by virtue of the 1239 exception return. 1240 1241 If unsure, say Y. 1242 1243config FUJITSU_ERRATUM_010001 1244 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1245 default y 1246 help 1247 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1248 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1249 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1250 This fault occurs under a specific hardware condition when a 1251 load/store instruction performs an address translation using: 1252 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1253 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1254 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1255 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1256 1257 The workaround is to ensure these bits are clear in TCR_ELx. 1258 The workaround only affects the Fujitsu-A64FX. 1259 1260 If unsure, say Y. 1261 1262config HISILICON_ERRATUM_161600802 1263 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1264 default y 1265 help 1266 The HiSilicon Hip07 SoC uses the wrong redistributor base 1267 when issued ITS commands such as VMOVP and VMAPP, and requires 1268 a 128kB offset to be applied to the target address in this commands. 1269 1270 If unsure, say Y. 1271 1272config HISILICON_ERRATUM_162100801 1273 bool "Hip09 162100801 erratum support" 1274 default y 1275 help 1276 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1277 during unmapping operation, which will cause some vSGIs lost. 1278 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1279 after VMOVP. 1280 1281 If unsure, say Y. 1282 1283config QCOM_FALKOR_ERRATUM_1003 1284 bool "Falkor E1003: Incorrect translation due to ASID change" 1285 default y 1286 help 1287 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1288 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1289 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1290 then only for entries in the walk cache, since the leaf translation 1291 is unchanged. Work around the erratum by invalidating the walk cache 1292 entries for the trampoline before entering the kernel proper. 1293 1294config QCOM_FALKOR_ERRATUM_1009 1295 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1296 default y 1297 select ARM64_WORKAROUND_REPEAT_TLBI 1298 help 1299 On Falkor v1, the CPU may prematurely complete a DSB following a 1300 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1301 one more time to fix the issue. 1302 1303 If unsure, say Y. 1304 1305config QCOM_QDF2400_ERRATUM_0065 1306 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1307 default y 1308 help 1309 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1310 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1311 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1312 1313 If unsure, say Y. 1314 1315config QCOM_FALKOR_ERRATUM_E1041 1316 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1317 default y 1318 help 1319 Falkor CPU may speculatively fetch instructions from an improper 1320 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1321 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1322 1323 If unsure, say Y. 1324 1325config NVIDIA_CARMEL_CNP_ERRATUM 1326 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1327 default y 1328 help 1329 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1330 invalidate shared TLB entries installed by a different core, as it would 1331 on standard ARM cores. 1332 1333 If unsure, say Y. 1334 1335config ROCKCHIP_ERRATUM_3568002 1336 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1337 default y 1338 help 1339 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1340 addressing limited to the first 32bit of physical address space. 1341 1342 If unsure, say Y. 1343 1344config ROCKCHIP_ERRATUM_3588001 1345 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1346 default y 1347 help 1348 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1349 This means, that its sharability feature may not be used, even though it 1350 is supported by the IP itself. 1351 1352 If unsure, say Y. 1353 1354config SOCIONEXT_SYNQUACER_PREITS 1355 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1356 default y 1357 help 1358 Socionext Synquacer SoCs implement a separate h/w block to generate 1359 MSI doorbell writes with non-zero values for the device ID. 1360 1361 If unsure, say Y. 1362 1363endmenu # "ARM errata workarounds via the alternatives framework" 1364 1365choice 1366 prompt "Page size" 1367 default ARM64_4K_PAGES 1368 help 1369 Page size (translation granule) configuration. 1370 1371config ARM64_4K_PAGES 1372 bool "4KB" 1373 select HAVE_PAGE_SIZE_4KB 1374 help 1375 This feature enables 4KB pages support. 1376 1377config ARM64_16K_PAGES 1378 bool "16KB" 1379 select HAVE_PAGE_SIZE_16KB 1380 help 1381 The system will use 16KB pages support. AArch32 emulation 1382 requires applications compiled with 16K (or a multiple of 16K) 1383 aligned segments. 1384 1385config ARM64_64K_PAGES 1386 bool "64KB" 1387 select HAVE_PAGE_SIZE_64KB 1388 help 1389 This feature enables 64KB pages support (4KB by default) 1390 allowing only two levels of page tables and faster TLB 1391 look-up. AArch32 emulation requires applications compiled 1392 with 64K aligned segments. 1393 1394endchoice 1395 1396choice 1397 prompt "Virtual address space size" 1398 default ARM64_VA_BITS_52 1399 help 1400 Allows choosing one of multiple possible virtual address 1401 space sizes. The level of translation table is determined by 1402 a combination of page size and virtual address space size. 1403 1404config ARM64_VA_BITS_36 1405 bool "36-bit" if EXPERT 1406 depends on PAGE_SIZE_16KB 1407 1408config ARM64_VA_BITS_39 1409 bool "39-bit" 1410 depends on PAGE_SIZE_4KB 1411 1412config ARM64_VA_BITS_42 1413 bool "42-bit" 1414 depends on PAGE_SIZE_64KB 1415 1416config ARM64_VA_BITS_47 1417 bool "47-bit" 1418 depends on PAGE_SIZE_16KB 1419 1420config ARM64_VA_BITS_48 1421 bool "48-bit" 1422 1423config ARM64_VA_BITS_52 1424 bool "52-bit" 1425 help 1426 Enable 52-bit virtual addressing for userspace when explicitly 1427 requested via a hint to mmap(). The kernel will also use 52-bit 1428 virtual addresses for its own mappings (provided HW support for 1429 this feature is available, otherwise it reverts to 48-bit). 1430 1431 NOTE: Enabling 52-bit virtual addressing in conjunction with 1432 ARMv8.3 Pointer Authentication will result in the PAC being 1433 reduced from 7 bits to 3 bits, which may have a significant 1434 impact on its susceptibility to brute-force attacks. 1435 1436 If unsure, select 48-bit virtual addressing instead. 1437 1438endchoice 1439 1440config ARM64_FORCE_52BIT 1441 bool "Force 52-bit virtual addresses for userspace" 1442 depends on ARM64_VA_BITS_52 && EXPERT 1443 help 1444 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1445 to maintain compatibility with older software by providing 48-bit VAs 1446 unless a hint is supplied to mmap. 1447 1448 This configuration option disables the 48-bit compatibility logic, and 1449 forces all userspace addresses to be 52-bit on HW that supports it. One 1450 should only enable this configuration option for stress testing userspace 1451 memory management code. If unsure say N here. 1452 1453config ARM64_VA_BITS 1454 int 1455 default 36 if ARM64_VA_BITS_36 1456 default 39 if ARM64_VA_BITS_39 1457 default 42 if ARM64_VA_BITS_42 1458 default 47 if ARM64_VA_BITS_47 1459 default 48 if ARM64_VA_BITS_48 1460 default 52 if ARM64_VA_BITS_52 1461 1462choice 1463 prompt "Physical address space size" 1464 default ARM64_PA_BITS_48 1465 help 1466 Choose the maximum physical address range that the kernel will 1467 support. 1468 1469config ARM64_PA_BITS_48 1470 bool "48-bit" 1471 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1472 1473config ARM64_PA_BITS_52 1474 bool "52-bit" 1475 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1476 help 1477 Enable support for a 52-bit physical address space, introduced as 1478 part of the ARMv8.2-LPA extension. 1479 1480 With this enabled, the kernel will also continue to work on CPUs that 1481 do not support ARMv8.2-LPA, but with some added memory overhead (and 1482 minor performance overhead). 1483 1484endchoice 1485 1486config ARM64_PA_BITS 1487 int 1488 default 48 if ARM64_PA_BITS_48 1489 default 52 if ARM64_PA_BITS_52 1490 1491config ARM64_LPA2 1492 def_bool y 1493 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1494 1495choice 1496 prompt "Endianness" 1497 default CPU_LITTLE_ENDIAN 1498 help 1499 Select the endianness of data accesses performed by the CPU. Userspace 1500 applications will need to be compiled and linked for the endianness 1501 that is selected here. 1502 1503config CPU_BIG_ENDIAN 1504 bool "Build big-endian kernel" 1505 depends on BROKEN 1506 help 1507 Say Y if you plan on running a kernel with a big-endian userspace. 1508 1509config CPU_LITTLE_ENDIAN 1510 bool "Build little-endian kernel" 1511 help 1512 Say Y if you plan on running a kernel with a little-endian userspace. 1513 This is usually the case for distributions targeting arm64. 1514 1515endchoice 1516 1517config NR_CPUS 1518 int "Maximum number of CPUs (2-4096)" 1519 range 2 4096 1520 default "512" 1521 1522config HOTPLUG_CPU 1523 bool "Support for hot-pluggable CPUs" 1524 select GENERIC_IRQ_MIGRATION 1525 help 1526 Say Y here to experiment with turning CPUs off and on. CPUs 1527 can be controlled through /sys/devices/system/cpu. 1528 1529# Common NUMA Features 1530config NUMA 1531 bool "NUMA Memory Allocation and Scheduler Support" 1532 select GENERIC_ARCH_NUMA 1533 select OF_NUMA 1534 select HAVE_SETUP_PER_CPU_AREA 1535 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1536 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1537 select USE_PERCPU_NUMA_NODE_ID 1538 help 1539 Enable NUMA (Non-Uniform Memory Access) support. 1540 1541 The kernel will try to allocate memory used by a CPU on the 1542 local memory of the CPU and add some more 1543 NUMA awareness to the kernel. 1544 1545config NODES_SHIFT 1546 int "Maximum NUMA Nodes (as a power of 2)" 1547 range 1 10 1548 default "4" 1549 depends on NUMA 1550 help 1551 Specify the maximum number of NUMA Nodes available on the target 1552 system. Increases memory reserved to accommodate various tables. 1553 1554source "kernel/Kconfig.hz" 1555 1556config ARCH_SPARSEMEM_ENABLE 1557 def_bool y 1558 select SPARSEMEM_VMEMMAP_ENABLE 1559 1560config HW_PERF_EVENTS 1561 def_bool y 1562 depends on ARM_PMU 1563 1564# Supported by clang >= 7.0 or GCC >= 12.0.0 1565config CC_HAVE_SHADOW_CALL_STACK 1566 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1567 1568config PARAVIRT 1569 bool "Enable paravirtualization code" 1570 select HAVE_PV_STEAL_CLOCK_GEN 1571 help 1572 This changes the kernel so it can modify itself when it is run 1573 under a hypervisor, potentially improving performance significantly 1574 over full virtualization. 1575 1576config PARAVIRT_TIME_ACCOUNTING 1577 bool "Paravirtual steal time accounting" 1578 select PARAVIRT 1579 help 1580 Select this option to enable fine granularity task steal time 1581 accounting. Time spent executing other tasks in parallel with 1582 the current vCPU is discounted from the vCPU power. To account for 1583 that, there can be a small performance impact. 1584 1585 If in doubt, say N here. 1586 1587config ARCH_SUPPORTS_KEXEC 1588 def_bool PM_SLEEP_SMP 1589 1590config ARCH_SUPPORTS_KEXEC_FILE 1591 def_bool y 1592 1593config ARCH_SELECTS_KEXEC_FILE 1594 def_bool y 1595 depends on KEXEC_FILE 1596 select HAVE_IMA_KEXEC if IMA 1597 1598config ARCH_SUPPORTS_KEXEC_SIG 1599 def_bool y 1600 1601config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1602 def_bool y 1603 1604config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1605 def_bool y 1606 1607config ARCH_SUPPORTS_KEXEC_HANDOVER 1608 def_bool y 1609 1610config ARCH_SUPPORTS_CRASH_DUMP 1611 def_bool y 1612 1613config ARCH_DEFAULT_CRASH_DUMP 1614 def_bool y 1615 1616config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1617 def_bool CRASH_RESERVE 1618 1619config TRANS_TABLE 1620 def_bool y 1621 depends on HIBERNATION || KEXEC_CORE 1622 1623config XEN_DOM0 1624 def_bool y 1625 depends on XEN 1626 1627config XEN 1628 bool "Xen guest support on ARM64" 1629 depends on ARM64 && OF 1630 select SWIOTLB_XEN 1631 select PARAVIRT 1632 help 1633 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1634 1635# include/linux/mmzone.h requires the following to be true: 1636# 1637# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1638# 1639# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1640# 1641# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1642# ----+-------------------+--------------+----------------------+-------------------------+ 1643# 4K | 27 | 12 | 15 | 10 | 1644# 16K | 27 | 14 | 13 | 11 | 1645# 64K | 29 | 16 | 13 | 13 | 1646config ARCH_FORCE_MAX_ORDER 1647 int 1648 default "13" if ARM64_64K_PAGES 1649 default "11" if ARM64_16K_PAGES 1650 default "10" 1651 help 1652 The kernel page allocator limits the size of maximal physically 1653 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1654 defines the maximal power of two of number of pages that can be 1655 allocated as a single contiguous block. This option allows 1656 overriding the default setting when ability to allocate very 1657 large blocks of physically contiguous memory is required. 1658 1659 The maximal size of allocation cannot exceed the size of the 1660 section, so the value of MAX_PAGE_ORDER should satisfy 1661 1662 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1663 1664 Don't change if unsure. 1665 1666config UNMAP_KERNEL_AT_EL0 1667 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1668 default y 1669 help 1670 Speculation attacks against some high-performance processors can 1671 be used to bypass MMU permission checks and leak kernel data to 1672 userspace. This can be defended against by unmapping the kernel 1673 when running in userspace, mapping it back in on exception entry 1674 via a trampoline page in the vector table. 1675 1676 If unsure, say Y. 1677 1678config MITIGATE_SPECTRE_BRANCH_HISTORY 1679 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1680 default y 1681 help 1682 Speculation attacks against some high-performance processors can 1683 make use of branch history to influence future speculation. 1684 When taking an exception from user-space, a sequence of branches 1685 or a firmware call overwrites the branch history. 1686 1687config ARM64_SW_TTBR0_PAN 1688 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1689 depends on !KCSAN 1690 help 1691 Enabling this option prevents the kernel from accessing 1692 user-space memory directly by pointing TTBR0_EL1 to a reserved 1693 zeroed area and reserved ASID. The user access routines 1694 restore the valid TTBR0_EL1 temporarily. 1695 1696config ARM64_TAGGED_ADDR_ABI 1697 bool "Enable the tagged user addresses syscall ABI" 1698 default y 1699 help 1700 When this option is enabled, user applications can opt in to a 1701 relaxed ABI via prctl() allowing tagged addresses to be passed 1702 to system calls as pointer arguments. For details, see 1703 Documentation/arch/arm64/tagged-address-abi.rst. 1704 1705menuconfig COMPAT 1706 bool "Kernel support for 32-bit EL0" 1707 depends on ARM64_4K_PAGES || EXPERT 1708 select HAVE_UID16 1709 select OLD_SIGSUSPEND3 1710 select COMPAT_OLD_SIGACTION 1711 help 1712 This option enables support for a 32-bit EL0 running under a 64-bit 1713 kernel at EL1. AArch32-specific components such as system calls, 1714 the user helper functions, VFP support and the ptrace interface are 1715 handled appropriately by the kernel. 1716 1717 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1718 that you will only be able to execute AArch32 binaries that were compiled 1719 with page size aligned segments. 1720 1721 If you want to execute 32-bit userspace applications, say Y. 1722 1723if COMPAT 1724 1725config KUSER_HELPERS 1726 bool "Enable kuser helpers page for 32-bit applications" 1727 default y 1728 help 1729 Warning: disabling this option may break 32-bit user programs. 1730 1731 Provide kuser helpers to compat tasks. The kernel provides 1732 helper code to userspace in read only form at a fixed location 1733 to allow userspace to be independent of the CPU type fitted to 1734 the system. This permits binaries to be run on ARMv4 through 1735 to ARMv8 without modification. 1736 1737 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1738 1739 However, the fixed address nature of these helpers can be used 1740 by ROP (return orientated programming) authors when creating 1741 exploits. 1742 1743 If all of the binaries and libraries which run on your platform 1744 are built specifically for your platform, and make no use of 1745 these helpers, then you can turn this option off to hinder 1746 such exploits. However, in that case, if a binary or library 1747 relying on those helpers is run, it will not function correctly. 1748 1749 Say N here only if you are absolutely certain that you do not 1750 need these helpers; otherwise, the safe option is to say Y. 1751 1752config COMPAT_VDSO 1753 bool "Enable vDSO for 32-bit applications" 1754 depends on !CPU_BIG_ENDIAN 1755 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1756 default y 1757 help 1758 Place in the process address space of 32-bit applications an 1759 ELF shared object providing fast implementations of gettimeofday 1760 and clock_gettime. 1761 1762 You must have a 32-bit build of glibc 2.22 or later for programs 1763 to seamlessly take advantage of this. 1764 1765config THUMB2_COMPAT_VDSO 1766 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1767 depends on COMPAT_VDSO 1768 default y 1769 help 1770 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1771 otherwise with '-marm'. 1772 1773config COMPAT_ALIGNMENT_FIXUPS 1774 bool "Fix up misaligned multi-word loads and stores in user space" 1775 1776menuconfig ARMV8_DEPRECATED 1777 bool "Emulate deprecated/obsolete ARMv8 instructions" 1778 depends on SYSCTL 1779 help 1780 Legacy software support may require certain instructions 1781 that have been deprecated or obsoleted in the architecture. 1782 1783 Enable this config to enable selective emulation of these 1784 features. 1785 1786 If unsure, say Y 1787 1788if ARMV8_DEPRECATED 1789 1790config SWP_EMULATION 1791 bool "Emulate SWP/SWPB instructions" 1792 help 1793 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1794 they are always undefined. Say Y here to enable software 1795 emulation of these instructions for userspace using LDXR/STXR. 1796 This feature can be controlled at runtime with the abi.swp 1797 sysctl which is disabled by default. 1798 1799 In some older versions of glibc [<=2.8] SWP is used during futex 1800 trylock() operations with the assumption that the code will not 1801 be preempted. This invalid assumption may be more likely to fail 1802 with SWP emulation enabled, leading to deadlock of the user 1803 application. 1804 1805 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1806 on an external transaction monitoring block called a global 1807 monitor to maintain update atomicity. If your system does not 1808 implement a global monitor, this option can cause programs that 1809 perform SWP operations to uncached memory to deadlock. 1810 1811 If unsure, say Y 1812 1813config CP15_BARRIER_EMULATION 1814 bool "Emulate CP15 Barrier instructions" 1815 help 1816 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1817 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1818 strongly recommended to use the ISB, DSB, and DMB 1819 instructions instead. 1820 1821 Say Y here to enable software emulation of these 1822 instructions for AArch32 userspace code. When this option is 1823 enabled, CP15 barrier usage is traced which can help 1824 identify software that needs updating. This feature can be 1825 controlled at runtime with the abi.cp15_barrier sysctl. 1826 1827 If unsure, say Y 1828 1829config SETEND_EMULATION 1830 bool "Emulate SETEND instruction" 1831 help 1832 The SETEND instruction alters the data-endianness of the 1833 AArch32 EL0, and is deprecated in ARMv8. 1834 1835 Say Y here to enable software emulation of the instruction 1836 for AArch32 userspace code. This feature can be controlled 1837 at runtime with the abi.setend sysctl. 1838 1839 Note: All the cpus on the system must have mixed endian support at EL0 1840 for this feature to be enabled. If a new CPU - which doesn't support mixed 1841 endian - is hotplugged in after this feature has been enabled, there could 1842 be unexpected results in the applications. 1843 1844 If unsure, say Y 1845endif # ARMV8_DEPRECATED 1846 1847endif # COMPAT 1848 1849menu "ARMv8.1 architectural features" 1850 1851config ARM64_HW_AFDBM 1852 bool "Support for hardware updates of the Access and Dirty page flags" 1853 default y 1854 help 1855 The ARMv8.1 architecture extensions introduce support for 1856 hardware updates of the access and dirty information in page 1857 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1858 capable processors, accesses to pages with PTE_AF cleared will 1859 set this bit instead of raising an access flag fault. 1860 Similarly, writes to read-only pages with the DBM bit set will 1861 clear the read-only bit (AP[2]) instead of raising a 1862 permission fault. 1863 1864 Kernels built with this configuration option enabled continue 1865 to work on pre-ARMv8.1 hardware and the performance impact is 1866 minimal. If unsure, say Y. 1867 1868endmenu # "ARMv8.1 architectural features" 1869 1870menu "ARMv8.2 architectural features" 1871 1872config ARM64_PMEM 1873 bool "Enable support for persistent memory" 1874 select ARCH_HAS_PMEM_API 1875 select ARCH_HAS_UACCESS_FLUSHCACHE 1876 help 1877 Say Y to enable support for the persistent memory API based on the 1878 ARMv8.2 DCPoP feature. 1879 1880 The feature is detected at runtime, and the kernel will use DC CVAC 1881 operations if DC CVAP is not supported (following the behaviour of 1882 DC CVAP itself if the system does not define a point of persistence). 1883 1884config ARM64_RAS_EXTN 1885 bool "Enable support for RAS CPU Extensions" 1886 default y 1887 help 1888 CPUs that support the Reliability, Availability and Serviceability 1889 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1890 errors, classify them and report them to software. 1891 1892 On CPUs with these extensions system software can use additional 1893 barriers to determine if faults are pending and read the 1894 classification from a new set of registers. 1895 1896 Selecting this feature will allow the kernel to use these barriers 1897 and access the new registers if the system supports the extension. 1898 Platform RAS features may additionally depend on firmware support. 1899 1900config ARM64_CNP 1901 bool "Enable support for Common Not Private (CNP) translations" 1902 default y 1903 help 1904 Common Not Private (CNP) allows translation table entries to 1905 be shared between different PEs in the same inner shareable 1906 domain, so the hardware can use this fact to optimise the 1907 caching of such entries in the TLB. 1908 1909 Selecting this option allows the CNP feature to be detected 1910 at runtime, and does not affect PEs that do not implement 1911 this feature. 1912 1913endmenu # "ARMv8.2 architectural features" 1914 1915menu "ARMv8.3 architectural features" 1916 1917config ARM64_PTR_AUTH 1918 bool "Enable support for pointer authentication" 1919 default y 1920 help 1921 Pointer authentication (part of the ARMv8.3 Extensions) provides 1922 instructions for signing and authenticating pointers against secret 1923 keys, which can be used to mitigate Return Oriented Programming (ROP) 1924 and other attacks. 1925 1926 This option enables these instructions at EL0 (i.e. for userspace). 1927 Choosing this option will cause the kernel to initialise secret keys 1928 for each process at exec() time, with these keys being 1929 context-switched along with the process. 1930 1931 The feature is detected at runtime. If the feature is not present in 1932 hardware it will not be advertised to userspace/KVM guest nor will it 1933 be enabled. 1934 1935 If the feature is present on the boot CPU but not on a late CPU, then 1936 the late CPU will be parked. Also, if the boot CPU does not have 1937 address auth and the late CPU has then the late CPU will still boot 1938 but with the feature disabled. On such a system, this option should 1939 not be selected. 1940 1941config ARM64_PTR_AUTH_KERNEL 1942 bool "Use pointer authentication for kernel" 1943 default y 1944 depends on ARM64_PTR_AUTH 1945 # Modern compilers insert a .note.gnu.property section note for PAC 1946 # which is only understood by binutils starting with version 2.33.1. 1947 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1948 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1949 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1950 help 1951 If the compiler supports the -mbranch-protection or 1952 -msign-return-address flag (e.g. GCC 7 or later), then this option 1953 will cause the kernel itself to be compiled with return address 1954 protection. In this case, and if the target hardware is known to 1955 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1956 disabled with minimal loss of protection. 1957 1958 This feature works with FUNCTION_GRAPH_TRACER option only if 1959 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1960 1961config CC_HAS_BRANCH_PROT_PAC_RET 1962 # GCC 9 or later, clang 8 or later 1963 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1964 1965config AS_HAS_CFI_NEGATE_RA_STATE 1966 # binutils 2.34+ 1967 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1968 1969endmenu # "ARMv8.3 architectural features" 1970 1971menu "ARMv8.4 architectural features" 1972 1973config ARM64_AMU_EXTN 1974 bool "Enable support for the Activity Monitors Unit CPU extension" 1975 default y 1976 help 1977 The activity monitors extension is an optional extension introduced 1978 by the ARMv8.4 CPU architecture. This enables support for version 1 1979 of the activity monitors architecture, AMUv1. 1980 1981 To enable the use of this extension on CPUs that implement it, say Y. 1982 1983 Note that for architectural reasons, firmware _must_ implement AMU 1984 support when running on CPUs that present the activity monitors 1985 extension. The required support is present in: 1986 * Version 1.5 and later of the ARM Trusted Firmware 1987 1988 For kernels that have this configuration enabled but boot with broken 1989 firmware, you may need to say N here until the firmware is fixed. 1990 Otherwise you may experience firmware panics or lockups when 1991 accessing the counter registers. Even if you are not observing these 1992 symptoms, the values returned by the register reads might not 1993 correctly reflect reality. Most commonly, the value read will be 0, 1994 indicating that the counter is not enabled. 1995 1996config ARM64_TLB_RANGE 1997 bool "Enable support for tlbi range feature" 1998 default y 1999 help 2000 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2001 range of input addresses. 2002 2003config ARM64_MPAM 2004 bool "Enable support for MPAM" 2005 select ARM64_MPAM_DRIVER 2006 select ARCH_HAS_CPU_RESCTRL 2007 help 2008 Memory System Resource Partitioning and Monitoring (MPAM) is an 2009 optional extension to the Arm architecture that allows each 2010 transaction issued to the memory system to be labelled with a 2011 Partition identifier (PARTID) and Performance Monitoring Group 2012 identifier (PMG). 2013 2014 Memory system components, such as the caches, can be configured with 2015 policies to control how much of various physical resources (such as 2016 memory bandwidth or cache memory) the transactions labelled with each 2017 PARTID can consume. Depending on the capabilities of the hardware, 2018 the PARTID and PMG can also be used as filtering criteria to measure 2019 the memory system resource consumption of different parts of a 2020 workload. 2021 2022 Use of this extension requires CPU support, support in the 2023 Memory System Components (MSC), and a description from firmware 2024 of where the MSCs are in the address space. 2025 2026 MPAM is exposed to user-space via the resctrl pseudo filesystem. 2027 2028 This option enables the extra context switch code. 2029 2030endmenu # "ARMv8.4 architectural features" 2031 2032menu "ARMv8.5 architectural features" 2033 2034config AS_HAS_ARMV8_5 2035 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2036 2037config ARM64_BTI 2038 bool "Branch Target Identification support" 2039 default y 2040 help 2041 Branch Target Identification (part of the ARMv8.5 Extensions) 2042 provides a mechanism to limit the set of locations to which computed 2043 branch instructions such as BR or BLR can jump. 2044 2045 To make use of BTI on CPUs that support it, say Y. 2046 2047 BTI is intended to provide complementary protection to other control 2048 flow integrity protection mechanisms, such as the Pointer 2049 authentication mechanism provided as part of the ARMv8.3 Extensions. 2050 For this reason, it does not make sense to enable this option without 2051 also enabling support for pointer authentication. Thus, when 2052 enabling this option you should also select ARM64_PTR_AUTH=y. 2053 2054 Userspace binaries must also be specifically compiled to make use of 2055 this mechanism. If you say N here or the hardware does not support 2056 BTI, such binaries can still run, but you get no additional 2057 enforcement of branch destinations. 2058 2059config ARM64_BTI_KERNEL 2060 bool "Use Branch Target Identification for kernel" 2061 default y 2062 depends on ARM64_BTI 2063 depends on ARM64_PTR_AUTH_KERNEL 2064 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2065 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2066 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2067 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2068 depends on !CC_IS_GCC 2069 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2070 help 2071 Build the kernel with Branch Target Identification annotations 2072 and enable enforcement of this for kernel code. When this option 2073 is enabled and the system supports BTI all kernel code including 2074 modular code must have BTI enabled. 2075 2076config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2077 # GCC 9 or later, clang 8 or later 2078 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2079 2080config ARM64_E0PD 2081 bool "Enable support for E0PD" 2082 default y 2083 help 2084 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2085 that EL0 accesses made via TTBR1 always fault in constant time, 2086 providing similar benefits to KASLR as those provided by KPTI, but 2087 with lower overhead and without disrupting legitimate access to 2088 kernel memory such as SPE. 2089 2090 This option enables E0PD for TTBR1 where available. 2091 2092config ARM64_AS_HAS_MTE 2093 # Initial support for MTE went in binutils 2.32.0, checked with 2094 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2095 # as a late addition to the final architecture spec (LDGM/STGM) 2096 # is only supported in the newer 2.32.x and 2.33 binutils 2097 # versions, hence the extra "stgm" instruction check below. 2098 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2099 2100config ARM64_MTE 2101 bool "Memory Tagging Extension support" 2102 default y 2103 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2104 depends on AS_HAS_ARMV8_5 2105 # Required for tag checking in the uaccess routines 2106 select ARCH_HAS_SUBPAGE_FAULTS 2107 select ARCH_USES_HIGH_VMA_FLAGS 2108 select ARCH_USES_PG_ARCH_2 2109 select ARCH_USES_PG_ARCH_3 2110 help 2111 Memory Tagging (part of the ARMv8.5 Extensions) provides 2112 architectural support for run-time, always-on detection of 2113 various classes of memory error to aid with software debugging 2114 to eliminate vulnerabilities arising from memory-unsafe 2115 languages. 2116 2117 This option enables the support for the Memory Tagging 2118 Extension at EL0 (i.e. for userspace). 2119 2120 Selecting this option allows the feature to be detected at 2121 runtime. Any secondary CPU not implementing this feature will 2122 not be allowed a late bring-up. 2123 2124 Userspace binaries that want to use this feature must 2125 explicitly opt in. The mechanism for the userspace is 2126 described in: 2127 2128 Documentation/arch/arm64/memory-tagging-extension.rst. 2129 2130endmenu # "ARMv8.5 architectural features" 2131 2132menu "ARMv8.7 architectural features" 2133 2134config ARM64_EPAN 2135 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2136 default y 2137 help 2138 Enhanced Privileged Access Never (EPAN) allows Privileged 2139 Access Never to be used with Execute-only mappings. 2140 2141 The feature is detected at runtime, and will remain disabled 2142 if the cpu does not implement the feature. 2143endmenu # "ARMv8.7 architectural features" 2144 2145config AS_HAS_MOPS 2146 def_bool $(as-instr,.arch_extension mops) 2147 2148menu "ARMv8.9 architectural features" 2149 2150config ARM64_POE 2151 prompt "Permission Overlay Extension" 2152 def_bool y 2153 select ARCH_USES_HIGH_VMA_FLAGS 2154 select ARCH_HAS_PKEYS 2155 help 2156 The Permission Overlay Extension is used to implement Memory 2157 Protection Keys. Memory Protection Keys provides a mechanism for 2158 enforcing page-based protections, but without requiring modification 2159 of the page tables when an application changes protection domains. 2160 2161 For details, see Documentation/core-api/protection-keys.rst 2162 2163 If unsure, say y. 2164 2165config ARCH_PKEY_BITS 2166 int 2167 default 3 2168 2169config ARM64_HAFT 2170 bool "Support for Hardware managed Access Flag for Table Descriptors" 2171 depends on ARM64_HW_AFDBM 2172 default y 2173 help 2174 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2175 Flag for Table descriptors. When enabled an architectural executed 2176 memory access will update the Access Flag in each Table descriptor 2177 which is accessed during the translation table walk and for which 2178 the Access Flag is 0. The Access Flag of the Table descriptor use 2179 the same bit of PTE_AF. 2180 2181 The feature will only be enabled if all the CPUs in the system 2182 support this feature. If unsure, say Y. 2183 2184endmenu # "ARMv8.9 architectural features" 2185 2186menu "ARMv9.4 architectural features" 2187 2188config ARM64_GCS 2189 bool "Enable support for Guarded Control Stack (GCS)" 2190 default y 2191 select ARCH_HAS_USER_SHADOW_STACK 2192 select ARCH_USES_HIGH_VMA_FLAGS 2193 help 2194 Guarded Control Stack (GCS) provides support for a separate 2195 stack with restricted access which contains only return 2196 addresses. This can be used to harden against some attacks 2197 by comparing return address used by the program with what is 2198 stored in the GCS, and may also be used to efficiently obtain 2199 the call stack for applications such as profiling. 2200 2201 The feature is detected at runtime, and will remain disabled 2202 if the system does not implement the feature. 2203 2204endmenu # "ARMv9.4 architectural features" 2205 2206config AS_HAS_LSUI 2207 def_bool $(as-instr,.arch_extension lsui) 2208 help 2209 Supported by LLVM 20+ and binutils 2.45+. 2210 2211menu "ARMv9.6 architectural features" 2212 2213config ARM64_LSUI 2214 bool "Support Unprivileged Load Store Instructions (LSUI)" 2215 default y 2216 depends on AS_HAS_LSUI && !CPU_BIG_ENDIAN 2217 help 2218 The Unprivileged Load Store Instructions (LSUI) provides 2219 variants load/store instructions that access user-space memory 2220 from the kernel without clearing PSTATE.PAN bit. 2221 2222 This feature is supported by LLVM 20+ and binutils 2.45+. 2223 2224endmenu # "ARMv9.6 architectural feature" 2225 2226config ARM64_SVE 2227 bool "ARM Scalable Vector Extension support" 2228 default y 2229 help 2230 The Scalable Vector Extension (SVE) is an extension to the AArch64 2231 execution state which complements and extends the SIMD functionality 2232 of the base architecture to support much larger vectors and to enable 2233 additional vectorisation opportunities. 2234 2235 To enable use of this extension on CPUs that implement it, say Y. 2236 2237 On CPUs that support the SVE2 extensions, this option will enable 2238 those too. 2239 2240 Note that for architectural reasons, firmware _must_ implement SVE 2241 support when running on SVE capable hardware. The required support 2242 is present in: 2243 2244 * version 1.5 and later of the ARM Trusted Firmware 2245 * the AArch64 boot wrapper since commit 5e1261e08abf 2246 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2247 2248 For other firmware implementations, consult the firmware documentation 2249 or vendor. 2250 2251 If you need the kernel to boot on SVE-capable hardware with broken 2252 firmware, you may need to say N here until you get your firmware 2253 fixed. Otherwise, you may experience firmware panics or lockups when 2254 booting the kernel. If unsure and you are not observing these 2255 symptoms, you should assume that it is safe to say Y. 2256 2257config ARM64_SME 2258 bool "ARM Scalable Matrix Extension support" 2259 default y 2260 depends on ARM64_SVE 2261 help 2262 The Scalable Matrix Extension (SME) is an extension to the AArch64 2263 execution state which utilises a substantial subset of the SVE 2264 instruction set, together with the addition of new architectural 2265 register state capable of holding two dimensional matrix tiles to 2266 enable various matrix operations. 2267 2268config ARM64_PSEUDO_NMI 2269 bool "Support for NMI-like interrupts" 2270 select ARM_GIC_V3 2271 help 2272 Adds support for mimicking Non-Maskable Interrupts through the use of 2273 GIC interrupt priority. This support requires version 3 or later of 2274 ARM GIC. 2275 2276 This high priority configuration for interrupts needs to be 2277 explicitly enabled by setting the kernel parameter 2278 "irqchip.gicv3_pseudo_nmi" to 1. 2279 2280 If unsure, say N 2281 2282if ARM64_PSEUDO_NMI 2283config ARM64_DEBUG_PRIORITY_MASKING 2284 bool "Debug interrupt priority masking" 2285 help 2286 This adds runtime checks to functions enabling/disabling 2287 interrupts when using priority masking. The additional checks verify 2288 the validity of ICC_PMR_EL1 when calling concerned functions. 2289 2290 If unsure, say N 2291endif # ARM64_PSEUDO_NMI 2292 2293config RELOCATABLE 2294 bool "Build a relocatable kernel image" if EXPERT 2295 select ARCH_HAS_RELR 2296 default y 2297 help 2298 This builds the kernel as a Position Independent Executable (PIE), 2299 which retains all relocation metadata required to relocate the 2300 kernel binary at runtime to a different virtual address than the 2301 address it was linked at. 2302 Since AArch64 uses the RELA relocation format, this requires a 2303 relocation pass at runtime even if the kernel is loaded at the 2304 same address it was linked at. 2305 2306config RANDOMIZE_BASE 2307 bool "Randomize the address of the kernel image" 2308 select RELOCATABLE 2309 help 2310 Randomizes the virtual address at which the kernel image is 2311 loaded, as a security feature that deters exploit attempts 2312 relying on knowledge of the location of kernel internals. 2313 2314 It is the bootloader's job to provide entropy, by passing a 2315 random u64 value in /chosen/kaslr-seed at kernel entry. 2316 2317 When booting via the UEFI stub, it will invoke the firmware's 2318 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2319 to the kernel proper. In addition, it will randomise the physical 2320 location of the kernel Image as well. 2321 2322 If unsure, say N. 2323 2324config RANDOMIZE_MODULE_REGION_FULL 2325 bool "Randomize the module region over a 2 GB range" 2326 depends on RANDOMIZE_BASE 2327 default y 2328 help 2329 Randomizes the location of the module region inside a 2 GB window 2330 covering the core kernel. This way, it is less likely for modules 2331 to leak information about the location of core kernel data structures 2332 but it does imply that function calls between modules and the core 2333 kernel will need to be resolved via veneers in the module PLT. 2334 2335 When this option is not set, the module region will be randomized over 2336 a limited range that contains the [_stext, _etext] interval of the 2337 core kernel, so branch relocations are almost always in range unless 2338 the region is exhausted. In this particular case of region 2339 exhaustion, modules might be able to fall back to a larger 2GB area. 2340 2341config CC_HAVE_STACKPROTECTOR_SYSREG 2342 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2343 2344config STACKPROTECTOR_PER_TASK 2345 def_bool y 2346 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2347 2348config UNWIND_PATCH_PAC_INTO_SCS 2349 bool "Enable shadow call stack dynamically using code patching" 2350 depends on CC_IS_CLANG 2351 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2352 depends on SHADOW_CALL_STACK 2353 select UNWIND_TABLES 2354 select DYNAMIC_SCS 2355 2356config ARM64_CONTPTE 2357 bool "Contiguous PTE mappings for user memory" if EXPERT 2358 depends on TRANSPARENT_HUGEPAGE 2359 default y 2360 help 2361 When enabled, user mappings are configured using the PTE contiguous 2362 bit, for any mappings that meet the size and alignment requirements. 2363 This reduces TLB pressure and improves performance. 2364 2365endmenu # "Kernel Features" 2366 2367menu "Boot options" 2368 2369config ARM64_ACPI_PARKING_PROTOCOL 2370 bool "Enable support for the ARM64 ACPI parking protocol" 2371 depends on ACPI 2372 help 2373 Enable support for the ARM64 ACPI parking protocol. If disabled 2374 the kernel will not allow booting through the ARM64 ACPI parking 2375 protocol even if the corresponding data is present in the ACPI 2376 MADT table. 2377 2378config CMDLINE 2379 string "Default kernel command string" 2380 default "" 2381 help 2382 Provide a set of default command-line options at build time by 2383 entering them here. As a minimum, you should specify the 2384 root device (e.g. root=/dev/nfs). 2385 2386choice 2387 prompt "Kernel command line type" 2388 depends on CMDLINE != "" 2389 default CMDLINE_FROM_BOOTLOADER 2390 help 2391 Choose how the kernel will handle the provided default kernel 2392 command line string. 2393 2394config CMDLINE_FROM_BOOTLOADER 2395 bool "Use bootloader kernel arguments if available" 2396 help 2397 Uses the command-line options passed by the boot loader. If 2398 the boot loader doesn't provide any, the default kernel command 2399 string provided in CMDLINE will be used. 2400 2401config CMDLINE_FORCE 2402 bool "Always use the default kernel command string" 2403 help 2404 Always use the default kernel command string, even if the boot 2405 loader passes other arguments to the kernel. 2406 This is useful if you cannot or don't want to change the 2407 command-line options your boot loader passes to the kernel. 2408 2409endchoice 2410 2411config EFI_STUB 2412 bool 2413 2414config EFI 2415 bool "UEFI runtime support" 2416 depends on OF && !CPU_BIG_ENDIAN 2417 depends on KERNEL_MODE_NEON 2418 select ARCH_SUPPORTS_ACPI 2419 select LIBFDT 2420 select UCS2_STRING 2421 select EFI_PARAMS_FROM_FDT 2422 select EFI_RUNTIME_WRAPPERS 2423 select EFI_STUB 2424 select EFI_GENERIC_STUB 2425 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2426 default y 2427 help 2428 This option provides support for runtime services provided 2429 by UEFI firmware (such as non-volatile variables, realtime 2430 clock, and platform reset). A UEFI stub is also provided to 2431 allow the kernel to be booted as an EFI application. This 2432 is only useful on systems that have UEFI firmware. 2433 2434config COMPRESSED_INSTALL 2435 bool "Install compressed image by default" 2436 help 2437 This makes the regular "make install" install the compressed 2438 image we built, not the legacy uncompressed one. 2439 2440 You can check that a compressed image works for you by doing 2441 "make zinstall" first, and verifying that everything is fine 2442 in your environment before making "make install" do this for 2443 you. 2444 2445config DMI 2446 bool "Enable support for SMBIOS (DMI) tables" 2447 depends on EFI 2448 default y 2449 help 2450 This enables SMBIOS/DMI feature for systems. 2451 2452 This option is only useful on systems that have UEFI firmware. 2453 However, even with this option, the resultant kernel should 2454 continue to boot on existing non-UEFI platforms. 2455 2456endmenu # "Boot options" 2457 2458menu "Power management options" 2459 2460source "kernel/power/Kconfig" 2461 2462config ARCH_HIBERNATION_POSSIBLE 2463 def_bool y 2464 depends on CPU_PM 2465 2466config ARCH_HIBERNATION_HEADER 2467 def_bool y 2468 depends on HIBERNATION 2469 2470config ARCH_SUSPEND_POSSIBLE 2471 def_bool y 2472 2473endmenu # "Power management options" 2474 2475menu "CPU Power Management" 2476 2477source "drivers/cpuidle/Kconfig" 2478 2479source "drivers/cpufreq/Kconfig" 2480 2481endmenu # "CPU Power Management" 2482 2483source "drivers/acpi/Kconfig" 2484 2485source "arch/arm64/kvm/Kconfig" 2486 2487source "kernel/livepatch/Kconfig" 2488