1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 18 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 19 select ARCH_ENABLE_MEMORY_HOTPLUG 20 select ARCH_ENABLE_MEMORY_HOTREMOVE 21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 22 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 23 select ARCH_HAS_CACHE_LINE_SIZE 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_PREP_COHERENT 28 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 29 select ARCH_HAS_FAST_MULTIPLIER 30 select ARCH_HAS_FORTIFY_SOURCE 31 select ARCH_HAS_GCOV_PROFILE_ALL 32 select ARCH_HAS_GIGANTIC_PAGE 33 select ARCH_HAS_KCOV 34 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 35 select ARCH_HAS_KEEPINITRD 36 select ARCH_HAS_MEMBARRIER_SYNC_CORE 37 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 38 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 39 select ARCH_HAS_PTE_DEVMAP 40 select ARCH_HAS_PTE_SPECIAL 41 select ARCH_HAS_HW_PTE_YOUNG 42 select ARCH_HAS_SETUP_DMA_OPS 43 select ARCH_HAS_SET_DIRECT_MAP 44 select ARCH_HAS_SET_MEMORY 45 select ARCH_STACKWALK 46 select ARCH_HAS_STRICT_KERNEL_RWX 47 select ARCH_HAS_STRICT_MODULE_RWX 48 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 49 select ARCH_HAS_SYNC_DMA_FOR_CPU 50 select ARCH_HAS_SYSCALL_WRAPPER 51 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 52 select ARCH_HAS_ZONE_DMA_SET if EXPERT 53 select ARCH_HAVE_ELF_PROT 54 select ARCH_HAVE_NMI_SAFE_CMPXCHG 55 select ARCH_HAVE_TRACE_MMIO_ACCESS 56 select ARCH_INLINE_READ_LOCK if !PREEMPTION 57 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 60 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 61 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 64 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 68 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 69 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 71 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 72 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 73 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 74 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 78 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 79 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 81 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 82 select ARCH_KEEP_MEMBLOCK 83 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 84 select ARCH_USE_CMPXCHG_LOCKREF 85 select ARCH_USE_GNU_PROPERTY 86 select ARCH_USE_MEMTEST 87 select ARCH_USE_QUEUED_RWLOCKS 88 select ARCH_USE_QUEUED_SPINLOCKS 89 select ARCH_USE_SYM_ANNOTATIONS 90 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 91 select ARCH_SUPPORTS_HUGETLBFS 92 select ARCH_SUPPORTS_MEMORY_FAILURE 93 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 94 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 95 select ARCH_SUPPORTS_LTO_CLANG_THIN 96 select ARCH_SUPPORTS_CFI_CLANG 97 select ARCH_SUPPORTS_ATOMIC_RMW 98 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 99 select ARCH_SUPPORTS_NUMA_BALANCING 100 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 101 select ARCH_SUPPORTS_PER_VMA_LOCK 102 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 103 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 104 select ARCH_WANT_DEFAULT_BPF_JIT 105 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 106 select ARCH_WANT_FRAME_POINTERS 107 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 108 select ARCH_WANT_LD_ORPHAN_WARN 109 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 110 select ARCH_WANTS_NO_INSTR 111 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 112 select ARCH_HAS_UBSAN 113 select ARM_AMBA 114 select ARM_ARCH_TIMER 115 select ARM_GIC 116 select AUDIT_ARCH_COMPAT_GENERIC 117 select ARM_GIC_V2M if PCI 118 select ARM_GIC_V3 119 select ARM_GIC_V3_ITS if PCI 120 select ARM_PSCI_FW 121 select BUILDTIME_TABLE_SORT 122 select CLONE_BACKWARDS 123 select COMMON_CLK 124 select CPU_PM if (SUSPEND || CPU_IDLE) 125 select CPUMASK_OFFSTACK if NR_CPUS > 256 126 select CRC32 127 select DCACHE_WORD_ACCESS 128 select DYNAMIC_FTRACE if FUNCTION_TRACER 129 select DMA_BOUNCE_UNALIGNED_KMALLOC 130 select DMA_DIRECT_REMAP 131 select EDAC_SUPPORT 132 select FRAME_POINTER 133 select FUNCTION_ALIGNMENT_4B 134 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 135 select GENERIC_ALLOCATOR 136 select GENERIC_ARCH_TOPOLOGY 137 select GENERIC_CLOCKEVENTS_BROADCAST 138 select GENERIC_CPU_AUTOPROBE 139 select GENERIC_CPU_DEVICES 140 select GENERIC_CPU_VULNERABILITIES 141 select GENERIC_EARLY_IOREMAP 142 select GENERIC_IDLE_POLL_SETUP 143 select GENERIC_IOREMAP 144 select GENERIC_IRQ_IPI 145 select GENERIC_IRQ_PROBE 146 select GENERIC_IRQ_SHOW 147 select GENERIC_IRQ_SHOW_LEVEL 148 select GENERIC_LIB_DEVMEM_IS_ALLOWED 149 select GENERIC_PCI_IOMAP 150 select GENERIC_PTDUMP 151 select GENERIC_SCHED_CLOCK 152 select GENERIC_SMP_IDLE_THREAD 153 select GENERIC_TIME_VSYSCALL 154 select GENERIC_GETTIMEOFDAY 155 select GENERIC_VDSO_TIME_NS 156 select HARDIRQS_SW_RESEND 157 select HAS_IOPORT 158 select HAVE_MOVE_PMD 159 select HAVE_MOVE_PUD 160 select HAVE_PCI 161 select HAVE_ACPI_APEI if (ACPI && EFI) 162 select HAVE_ALIGNED_STRUCT_PAGE 163 select HAVE_ARCH_AUDITSYSCALL 164 select HAVE_ARCH_BITREVERSE 165 select HAVE_ARCH_COMPILER_H 166 select HAVE_ARCH_HUGE_VMALLOC 167 select HAVE_ARCH_HUGE_VMAP 168 select HAVE_ARCH_JUMP_LABEL 169 select HAVE_ARCH_JUMP_LABEL_RELATIVE 170 select HAVE_ARCH_KASAN 171 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 172 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 173 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 174 # Some instrumentation may be unsound, hence EXPERT 175 select HAVE_ARCH_KCSAN if EXPERT 176 select HAVE_ARCH_KFENCE 177 select HAVE_ARCH_KGDB 178 select HAVE_ARCH_MMAP_RND_BITS 179 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 180 select HAVE_ARCH_PREL32_RELOCATIONS 181 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 182 select HAVE_ARCH_SECCOMP_FILTER 183 select HAVE_ARCH_STACKLEAK 184 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 185 select HAVE_ARCH_TRACEHOOK 186 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 187 select HAVE_ARCH_VMAP_STACK 188 select HAVE_ARM_SMCCC 189 select HAVE_ASM_MODVERSIONS 190 select HAVE_EBPF_JIT 191 select HAVE_C_RECORDMCOUNT 192 select HAVE_CMPXCHG_DOUBLE 193 select HAVE_CMPXCHG_LOCAL 194 select HAVE_CONTEXT_TRACKING_USER 195 select HAVE_DEBUG_KMEMLEAK 196 select HAVE_DMA_CONTIGUOUS 197 select HAVE_DYNAMIC_FTRACE 198 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 199 if $(cc-option,-fpatchable-function-entry=2) 200 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 201 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 202 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 203 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 204 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 205 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 206 if DYNAMIC_FTRACE_WITH_ARGS 207 select HAVE_SAMPLE_FTRACE_DIRECT 208 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 209 select HAVE_EFFICIENT_UNALIGNED_ACCESS 210 select HAVE_GUP_FAST 211 select HAVE_FTRACE_MCOUNT_RECORD 212 select HAVE_FUNCTION_TRACER 213 select HAVE_FUNCTION_ERROR_INJECTION 214 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 215 select HAVE_FUNCTION_GRAPH_TRACER 216 select HAVE_GCC_PLUGINS 217 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 218 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 219 select HAVE_HW_BREAKPOINT if PERF_EVENTS 220 select HAVE_IOREMAP_PROT 221 select HAVE_IRQ_TIME_ACCOUNTING 222 select HAVE_MOD_ARCH_SPECIFIC 223 select HAVE_NMI 224 select HAVE_PERF_EVENTS 225 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 226 select HAVE_PERF_REGS 227 select HAVE_PERF_USER_STACK_DUMP 228 select HAVE_PREEMPT_DYNAMIC_KEY 229 select HAVE_REGS_AND_STACK_ACCESS_API 230 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 231 select HAVE_FUNCTION_ARG_ACCESS_API 232 select MMU_GATHER_RCU_TABLE_FREE 233 select HAVE_RSEQ 234 select HAVE_RUST if CPU_LITTLE_ENDIAN 235 select HAVE_STACKPROTECTOR 236 select HAVE_SYSCALL_TRACEPOINTS 237 select HAVE_KPROBES 238 select HAVE_KRETPROBES 239 select HAVE_GENERIC_VDSO 240 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 241 select IRQ_DOMAIN 242 select IRQ_FORCED_THREADING 243 select KASAN_VMALLOC if KASAN 244 select LOCK_MM_AND_FIND_VMA 245 select MODULES_USE_ELF_RELA 246 select NEED_DMA_MAP_STATE 247 select NEED_SG_DMA_LENGTH 248 select OF 249 select OF_EARLY_FLATTREE 250 select PCI_DOMAINS_GENERIC if PCI 251 select PCI_ECAM if (ACPI && PCI) 252 select PCI_SYSCALL if PCI 253 select POWER_RESET 254 select POWER_SUPPLY 255 select SPARSE_IRQ 256 select SWIOTLB 257 select SYSCTL_EXCEPTION_TRACE 258 select THREAD_INFO_IN_TASK 259 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 260 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 261 select TRACE_IRQFLAGS_SUPPORT 262 select TRACE_IRQFLAGS_NMI_SUPPORT 263 select HAVE_SOFTIRQ_ON_OWN_STACK 264 select USER_STACKTRACE_SUPPORT 265 help 266 ARM 64-bit (AArch64) Linux support. 267 268config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 269 def_bool CC_IS_CLANG 270 # https://github.com/ClangBuiltLinux/linux/issues/1507 271 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 272 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 273 274config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 275 def_bool CC_IS_GCC 276 depends on $(cc-option,-fpatchable-function-entry=2) 277 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 278 279config 64BIT 280 def_bool y 281 282config MMU 283 def_bool y 284 285config ARM64_CONT_PTE_SHIFT 286 int 287 default 5 if PAGE_SIZE_64KB 288 default 7 if PAGE_SIZE_16KB 289 default 4 290 291config ARM64_CONT_PMD_SHIFT 292 int 293 default 5 if PAGE_SIZE_64KB 294 default 5 if PAGE_SIZE_16KB 295 default 4 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 14 if PAGE_SIZE_64KB 299 default 16 if PAGE_SIZE_16KB 300 default 18 301 302# max bits determined by the following formula: 303# VA_BITS - PAGE_SHIFT - 3 304config ARCH_MMAP_RND_BITS_MAX 305 default 19 if ARM64_VA_BITS=36 306 default 24 if ARM64_VA_BITS=39 307 default 27 if ARM64_VA_BITS=42 308 default 30 if ARM64_VA_BITS=47 309 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 310 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 311 default 33 if ARM64_VA_BITS=48 312 default 14 if ARM64_64K_PAGES 313 default 16 if ARM64_16K_PAGES 314 default 18 315 316config ARCH_MMAP_RND_COMPAT_BITS_MIN 317 default 7 if ARM64_64K_PAGES 318 default 9 if ARM64_16K_PAGES 319 default 11 320 321config ARCH_MMAP_RND_COMPAT_BITS_MAX 322 default 16 323 324config NO_IOPORT_MAP 325 def_bool y if !PCI 326 327config STACKTRACE_SUPPORT 328 def_bool y 329 330config ILLEGAL_POINTER_VALUE 331 hex 332 default 0xdead000000000000 333 334config LOCKDEP_SUPPORT 335 def_bool y 336 337config GENERIC_BUG 338 def_bool y 339 depends on BUG 340 341config GENERIC_BUG_RELATIVE_POINTERS 342 def_bool y 343 depends on GENERIC_BUG 344 345config GENERIC_HWEIGHT 346 def_bool y 347 348config GENERIC_CSUM 349 def_bool y 350 351config GENERIC_CALIBRATE_DELAY 352 def_bool y 353 354config SMP 355 def_bool y 356 357config KERNEL_MODE_NEON 358 def_bool y 359 360config FIX_EARLYCON_MEM 361 def_bool y 362 363config PGTABLE_LEVELS 364 int 365 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 366 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 367 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 368 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 369 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 370 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 371 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 372 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 373 374config ARCH_SUPPORTS_UPROBES 375 def_bool y 376 377config ARCH_PROC_KCORE_TEXT 378 def_bool y 379 380config BROKEN_GAS_INST 381 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 382 383config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 384 bool 385 # Clang's __builtin_return_address() strips the PAC since 12.0.0 386 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 387 default y if CC_IS_CLANG 388 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 389 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 390 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 391 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 392 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 393 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 394 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 395 default n 396 397config KASAN_SHADOW_OFFSET 398 hex 399 depends on KASAN_GENERIC || KASAN_SW_TAGS 400 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 401 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 402 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 403 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 404 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 405 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 406 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 407 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 408 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 409 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 410 default 0xffffffffffffffff 411 412config UNWIND_TABLES 413 bool 414 415source "arch/arm64/Kconfig.platforms" 416 417menu "Kernel Features" 418 419menu "ARM errata workarounds via the alternatives framework" 420 421config AMPERE_ERRATUM_AC03_CPU_38 422 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 423 default y 424 help 425 This option adds an alternative code sequence to work around Ampere 426 erratum AC03_CPU_38 on AmpereOne. 427 428 The affected design reports FEAT_HAFDBS as not implemented in 429 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 430 as required by the architecture. The unadvertised HAFDBS 431 implementation suffers from an additional erratum where hardware 432 A/D updates can occur after a PTE has been marked invalid. 433 434 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 435 which avoids enabling unadvertised hardware Access Flag management 436 at stage-2. 437 438 If unsure, say Y. 439 440config ARM64_WORKAROUND_CLEAN_CACHE 441 bool 442 443config ARM64_ERRATUM_826319 444 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 445 default y 446 select ARM64_WORKAROUND_CLEAN_CACHE 447 help 448 This option adds an alternative code sequence to work around ARM 449 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 450 AXI master interface and an L2 cache. 451 452 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 453 and is unable to accept a certain write via this interface, it will 454 not progress on read data presented on the read data channel and the 455 system can deadlock. 456 457 The workaround promotes data cache clean instructions to 458 data cache clean-and-invalidate. 459 Please note that this does not necessarily enable the workaround, 460 as it depends on the alternative framework, which will only patch 461 the kernel if an affected CPU is detected. 462 463 If unsure, say Y. 464 465config ARM64_ERRATUM_827319 466 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 467 default y 468 select ARM64_WORKAROUND_CLEAN_CACHE 469 help 470 This option adds an alternative code sequence to work around ARM 471 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 472 master interface and an L2 cache. 473 474 Under certain conditions this erratum can cause a clean line eviction 475 to occur at the same time as another transaction to the same address 476 on the AMBA 5 CHI interface, which can cause data corruption if the 477 interconnect reorders the two transactions. 478 479 The workaround promotes data cache clean instructions to 480 data cache clean-and-invalidate. 481 Please note that this does not necessarily enable the workaround, 482 as it depends on the alternative framework, which will only patch 483 the kernel if an affected CPU is detected. 484 485 If unsure, say Y. 486 487config ARM64_ERRATUM_824069 488 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 489 default y 490 select ARM64_WORKAROUND_CLEAN_CACHE 491 help 492 This option adds an alternative code sequence to work around ARM 493 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 494 to a coherent interconnect. 495 496 If a Cortex-A53 processor is executing a store or prefetch for 497 write instruction at the same time as a processor in another 498 cluster is executing a cache maintenance operation to the same 499 address, then this erratum might cause a clean cache line to be 500 incorrectly marked as dirty. 501 502 The workaround promotes data cache clean instructions to 503 data cache clean-and-invalidate. 504 Please note that this option does not necessarily enable the 505 workaround, as it depends on the alternative framework, which will 506 only patch the kernel if an affected CPU is detected. 507 508 If unsure, say Y. 509 510config ARM64_ERRATUM_819472 511 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 512 default y 513 select ARM64_WORKAROUND_CLEAN_CACHE 514 help 515 This option adds an alternative code sequence to work around ARM 516 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 517 present when it is connected to a coherent interconnect. 518 519 If the processor is executing a load and store exclusive sequence at 520 the same time as a processor in another cluster is executing a cache 521 maintenance operation to the same address, then this erratum might 522 cause data corruption. 523 524 The workaround promotes data cache clean instructions to 525 data cache clean-and-invalidate. 526 Please note that this does not necessarily enable the workaround, 527 as it depends on the alternative framework, which will only patch 528 the kernel if an affected CPU is detected. 529 530 If unsure, say Y. 531 532config ARM64_ERRATUM_832075 533 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 534 default y 535 help 536 This option adds an alternative code sequence to work around ARM 537 erratum 832075 on Cortex-A57 parts up to r1p2. 538 539 Affected Cortex-A57 parts might deadlock when exclusive load/store 540 instructions to Write-Back memory are mixed with Device loads. 541 542 The workaround is to promote device loads to use Load-Acquire 543 semantics. 544 Please note that this does not necessarily enable the workaround, 545 as it depends on the alternative framework, which will only patch 546 the kernel if an affected CPU is detected. 547 548 If unsure, say Y. 549 550config ARM64_ERRATUM_834220 551 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 552 depends on KVM 553 help 554 This option adds an alternative code sequence to work around ARM 555 erratum 834220 on Cortex-A57 parts up to r1p2. 556 557 Affected Cortex-A57 parts might report a Stage 2 translation 558 fault as the result of a Stage 1 fault for load crossing a 559 page boundary when there is a permission or device memory 560 alignment fault at Stage 1 and a translation fault at Stage 2. 561 562 The workaround is to verify that the Stage 1 translation 563 doesn't generate a fault before handling the Stage 2 fault. 564 Please note that this does not necessarily enable the workaround, 565 as it depends on the alternative framework, which will only patch 566 the kernel if an affected CPU is detected. 567 568 If unsure, say N. 569 570config ARM64_ERRATUM_1742098 571 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 572 depends on COMPAT 573 default y 574 help 575 This option removes the AES hwcap for aarch32 user-space to 576 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 577 578 Affected parts may corrupt the AES state if an interrupt is 579 taken between a pair of AES instructions. These instructions 580 are only present if the cryptography extensions are present. 581 All software should have a fallback implementation for CPUs 582 that don't implement the cryptography extensions. 583 584 If unsure, say Y. 585 586config ARM64_ERRATUM_845719 587 bool "Cortex-A53: 845719: a load might read incorrect data" 588 depends on COMPAT 589 default y 590 help 591 This option adds an alternative code sequence to work around ARM 592 erratum 845719 on Cortex-A53 parts up to r0p4. 593 594 When running a compat (AArch32) userspace on an affected Cortex-A53 595 part, a load at EL0 from a virtual address that matches the bottom 32 596 bits of the virtual address used by a recent load at (AArch64) EL1 597 might return incorrect data. 598 599 The workaround is to write the contextidr_el1 register on exception 600 return to a 32-bit task. 601 Please note that this does not necessarily enable the workaround, 602 as it depends on the alternative framework, which will only patch 603 the kernel if an affected CPU is detected. 604 605 If unsure, say Y. 606 607config ARM64_ERRATUM_843419 608 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 609 default y 610 help 611 This option links the kernel with '--fix-cortex-a53-843419' and 612 enables PLT support to replace certain ADRP instructions, which can 613 cause subsequent memory accesses to use an incorrect address on 614 Cortex-A53 parts up to r0p4. 615 616 If unsure, say Y. 617 618config ARM64_LD_HAS_FIX_ERRATUM_843419 619 def_bool $(ld-option,--fix-cortex-a53-843419) 620 621config ARM64_ERRATUM_1024718 622 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 623 default y 624 help 625 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 626 627 Affected Cortex-A55 cores (all revisions) could cause incorrect 628 update of the hardware dirty bit when the DBM/AP bits are updated 629 without a break-before-make. The workaround is to disable the usage 630 of hardware DBM locally on the affected cores. CPUs not affected by 631 this erratum will continue to use the feature. 632 633 If unsure, say Y. 634 635config ARM64_ERRATUM_1418040 636 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 637 default y 638 depends on COMPAT 639 help 640 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 641 errata 1188873 and 1418040. 642 643 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 644 cause register corruption when accessing the timer registers 645 from AArch32 userspace. 646 647 If unsure, say Y. 648 649config ARM64_WORKAROUND_SPECULATIVE_AT 650 bool 651 652config ARM64_ERRATUM_1165522 653 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 654 default y 655 select ARM64_WORKAROUND_SPECULATIVE_AT 656 help 657 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 658 659 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 660 corrupted TLBs by speculating an AT instruction during a guest 661 context switch. 662 663 If unsure, say Y. 664 665config ARM64_ERRATUM_1319367 666 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 667 default y 668 select ARM64_WORKAROUND_SPECULATIVE_AT 669 help 670 This option adds work arounds for ARM Cortex-A57 erratum 1319537 671 and A72 erratum 1319367 672 673 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 674 speculating an AT instruction during a guest context switch. 675 676 If unsure, say Y. 677 678config ARM64_ERRATUM_1530923 679 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 680 default y 681 select ARM64_WORKAROUND_SPECULATIVE_AT 682 help 683 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 684 685 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 686 corrupted TLBs by speculating an AT instruction during a guest 687 context switch. 688 689 If unsure, say Y. 690 691config ARM64_WORKAROUND_REPEAT_TLBI 692 bool 693 694config ARM64_ERRATUM_2441007 695 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 696 select ARM64_WORKAROUND_REPEAT_TLBI 697 help 698 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 699 700 Under very rare circumstances, affected Cortex-A55 CPUs 701 may not handle a race between a break-before-make sequence on one 702 CPU, and another CPU accessing the same page. This could allow a 703 store to a page that has been unmapped. 704 705 Work around this by adding the affected CPUs to the list that needs 706 TLB sequences to be done twice. 707 708 If unsure, say N. 709 710config ARM64_ERRATUM_1286807 711 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 712 select ARM64_WORKAROUND_REPEAT_TLBI 713 help 714 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 715 716 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 717 address for a cacheable mapping of a location is being 718 accessed by a core while another core is remapping the virtual 719 address to a new physical page using the recommended 720 break-before-make sequence, then under very rare circumstances 721 TLBI+DSB completes before a read using the translation being 722 invalidated has been observed by other observers. The 723 workaround repeats the TLBI+DSB operation. 724 725 If unsure, say N. 726 727config ARM64_ERRATUM_1463225 728 bool "Cortex-A76: Software Step might prevent interrupt recognition" 729 default y 730 help 731 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 732 733 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 734 of a system call instruction (SVC) can prevent recognition of 735 subsequent interrupts when software stepping is disabled in the 736 exception handler of the system call and either kernel debugging 737 is enabled or VHE is in use. 738 739 Work around the erratum by triggering a dummy step exception 740 when handling a system call from a task that is being stepped 741 in a VHE configuration of the kernel. 742 743 If unsure, say Y. 744 745config ARM64_ERRATUM_1542419 746 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 747 help 748 This option adds a workaround for ARM Neoverse-N1 erratum 749 1542419. 750 751 Affected Neoverse-N1 cores could execute a stale instruction when 752 modified by another CPU. The workaround depends on a firmware 753 counterpart. 754 755 Workaround the issue by hiding the DIC feature from EL0. This 756 forces user-space to perform cache maintenance. 757 758 If unsure, say N. 759 760config ARM64_ERRATUM_1508412 761 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 762 default y 763 help 764 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 765 766 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 767 of a store-exclusive or read of PAR_EL1 and a load with device or 768 non-cacheable memory attributes. The workaround depends on a firmware 769 counterpart. 770 771 KVM guests must also have the workaround implemented or they can 772 deadlock the system. 773 774 Work around the issue by inserting DMB SY barriers around PAR_EL1 775 register reads and warning KVM users. The DMB barrier is sufficient 776 to prevent a speculative PAR_EL1 read. 777 778 If unsure, say Y. 779 780config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 781 bool 782 783config ARM64_ERRATUM_2051678 784 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 785 default y 786 help 787 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 788 Affected Cortex-A510 might not respect the ordering rules for 789 hardware update of the page table's dirty bit. The workaround 790 is to not enable the feature on affected CPUs. 791 792 If unsure, say Y. 793 794config ARM64_ERRATUM_2077057 795 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 796 default y 797 help 798 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 799 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 800 expected, but a Pointer Authentication trap is taken instead. The 801 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 802 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 803 804 This can only happen when EL2 is stepping EL1. 805 806 When these conditions occur, the SPSR_EL2 value is unchanged from the 807 previous guest entry, and can be restored from the in-memory copy. 808 809 If unsure, say Y. 810 811config ARM64_ERRATUM_2658417 812 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 813 default y 814 help 815 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 816 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 817 BFMMLA or VMMLA instructions in rare circumstances when a pair of 818 A510 CPUs are using shared neon hardware. As the sharing is not 819 discoverable by the kernel, hide the BF16 HWCAP to indicate that 820 user-space should not be using these instructions. 821 822 If unsure, say Y. 823 824config ARM64_ERRATUM_2119858 825 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 826 default y 827 depends on CORESIGHT_TRBE 828 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 829 help 830 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 831 832 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 833 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 834 the event of a WRAP event. 835 836 Work around the issue by always making sure we move the TRBPTR_EL1 by 837 256 bytes before enabling the buffer and filling the first 256 bytes of 838 the buffer with ETM ignore packets upon disabling. 839 840 If unsure, say Y. 841 842config ARM64_ERRATUM_2139208 843 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 844 default y 845 depends on CORESIGHT_TRBE 846 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 847 help 848 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 849 850 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 851 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 852 the event of a WRAP event. 853 854 Work around the issue by always making sure we move the TRBPTR_EL1 by 855 256 bytes before enabling the buffer and filling the first 256 bytes of 856 the buffer with ETM ignore packets upon disabling. 857 858 If unsure, say Y. 859 860config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 861 bool 862 863config ARM64_ERRATUM_2054223 864 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 865 default y 866 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 867 help 868 Enable workaround for ARM Cortex-A710 erratum 2054223 869 870 Affected cores may fail to flush the trace data on a TSB instruction, when 871 the PE is in trace prohibited state. This will cause losing a few bytes 872 of the trace cached. 873 874 Workaround is to issue two TSB consecutively on affected cores. 875 876 If unsure, say Y. 877 878config ARM64_ERRATUM_2067961 879 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 880 default y 881 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 882 help 883 Enable workaround for ARM Neoverse-N2 erratum 2067961 884 885 Affected cores may fail to flush the trace data on a TSB instruction, when 886 the PE is in trace prohibited state. This will cause losing a few bytes 887 of the trace cached. 888 889 Workaround is to issue two TSB consecutively on affected cores. 890 891 If unsure, say Y. 892 893config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 894 bool 895 896config ARM64_ERRATUM_2253138 897 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 898 depends on CORESIGHT_TRBE 899 default y 900 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 901 help 902 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 903 904 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 905 for TRBE. Under some conditions, the TRBE might generate a write to the next 906 virtually addressed page following the last page of the TRBE address space 907 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 908 909 Work around this in the driver by always making sure that there is a 910 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 911 912 If unsure, say Y. 913 914config ARM64_ERRATUM_2224489 915 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 916 depends on CORESIGHT_TRBE 917 default y 918 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 919 help 920 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 921 922 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 923 for TRBE. Under some conditions, the TRBE might generate a write to the next 924 virtually addressed page following the last page of the TRBE address space 925 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 926 927 Work around this in the driver by always making sure that there is a 928 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 929 930 If unsure, say Y. 931 932config ARM64_ERRATUM_2441009 933 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 934 select ARM64_WORKAROUND_REPEAT_TLBI 935 help 936 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 937 938 Under very rare circumstances, affected Cortex-A510 CPUs 939 may not handle a race between a break-before-make sequence on one 940 CPU, and another CPU accessing the same page. This could allow a 941 store to a page that has been unmapped. 942 943 Work around this by adding the affected CPUs to the list that needs 944 TLB sequences to be done twice. 945 946 If unsure, say N. 947 948config ARM64_ERRATUM_2064142 949 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 950 depends on CORESIGHT_TRBE 951 default y 952 help 953 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 954 955 Affected Cortex-A510 core might fail to write into system registers after the 956 TRBE has been disabled. Under some conditions after the TRBE has been disabled 957 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 958 and TRBTRG_EL1 will be ignored and will not be effected. 959 960 Work around this in the driver by executing TSB CSYNC and DSB after collection 961 is stopped and before performing a system register write to one of the affected 962 registers. 963 964 If unsure, say Y. 965 966config ARM64_ERRATUM_2038923 967 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 968 depends on CORESIGHT_TRBE 969 default y 970 help 971 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 972 973 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 974 prohibited within the CPU. As a result, the trace buffer or trace buffer state 975 might be corrupted. This happens after TRBE buffer has been enabled by setting 976 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 977 execution changes from a context, in which trace is prohibited to one where it 978 isn't, or vice versa. In these mentioned conditions, the view of whether trace 979 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 980 the trace buffer state might be corrupted. 981 982 Work around this in the driver by preventing an inconsistent view of whether the 983 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 984 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 985 two ISB instructions if no ERET is to take place. 986 987 If unsure, say Y. 988 989config ARM64_ERRATUM_1902691 990 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 991 depends on CORESIGHT_TRBE 992 default y 993 help 994 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 995 996 Affected Cortex-A510 core might cause trace data corruption, when being written 997 into the memory. Effectively TRBE is broken and hence cannot be used to capture 998 trace data. 999 1000 Work around this problem in the driver by just preventing TRBE initialization on 1001 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1002 on such implementations. This will cover the kernel for any firmware that doesn't 1003 do this already. 1004 1005 If unsure, say Y. 1006 1007config ARM64_ERRATUM_2457168 1008 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1009 depends on ARM64_AMU_EXTN 1010 default y 1011 help 1012 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1013 1014 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1015 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1016 incorrectly giving a significantly higher output value. 1017 1018 Work around this problem by returning 0 when reading the affected counter in 1019 key locations that results in disabling all users of this counter. This effect 1020 is the same to firmware disabling affected counters. 1021 1022 If unsure, say Y. 1023 1024config ARM64_ERRATUM_2645198 1025 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1026 default y 1027 help 1028 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1029 1030 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1031 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1032 next instruction abort caused by permission fault. 1033 1034 Only user-space does executable to non-executable permission transition via 1035 mprotect() system call. Workaround the problem by doing a break-before-make 1036 TLB invalidation, for all changes to executable user space mappings. 1037 1038 If unsure, say Y. 1039 1040config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1041 bool 1042 1043config ARM64_ERRATUM_2966298 1044 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1045 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1046 default y 1047 help 1048 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1049 1050 On an affected Cortex-A520 core, a speculatively executed unprivileged 1051 load might leak data from a privileged level via a cache side channel. 1052 1053 Work around this problem by executing a TLBI before returning to EL0. 1054 1055 If unsure, say Y. 1056 1057config ARM64_ERRATUM_3117295 1058 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1059 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1060 default y 1061 help 1062 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1063 1064 On an affected Cortex-A510 core, a speculatively executed unprivileged 1065 load might leak data from a privileged level via a cache side channel. 1066 1067 Work around this problem by executing a TLBI before returning to EL0. 1068 1069 If unsure, say Y. 1070 1071config ARM64_ERRATUM_3194386 1072 bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing" 1073 default y 1074 help 1075 This option adds the workaround for the following errata: 1076 1077 * ARM Cortex-A710 erratam 3324338 1078 * ARM Cortex-A720 erratum 3456091 1079 * ARM Cortex-X2 erratum 3324338 1080 * ARM Cortex-X3 erratum 3324335 1081 * ARM Cortex-X4 erratum 3194386 1082 * ARM Cortex-X925 erratum 3324334 1083 * ARM Neoverse N2 erratum 3324339 1084 * ARM Neoverse V2 erratum 3324336 1085 * ARM Neoverse-V3 erratum 3312417 1086 1087 On affected cores "MSR SSBS, #0" instructions may not affect 1088 subsequent speculative instructions, which may permit unexepected 1089 speculative store bypassing. 1090 1091 Work around this problem by placing a speculation barrier after 1092 kernel changes to SSBS. The presence of the SSBS special-purpose 1093 register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such 1094 that userspace will use the PR_SPEC_STORE_BYPASS prctl to change 1095 SSBS. 1096 1097 If unsure, say Y. 1098 1099config CAVIUM_ERRATUM_22375 1100 bool "Cavium erratum 22375, 24313" 1101 default y 1102 help 1103 Enable workaround for errata 22375 and 24313. 1104 1105 This implements two gicv3-its errata workarounds for ThunderX. Both 1106 with a small impact affecting only ITS table allocation. 1107 1108 erratum 22375: only alloc 8MB table size 1109 erratum 24313: ignore memory access type 1110 1111 The fixes are in ITS initialization and basically ignore memory access 1112 type and table size provided by the TYPER and BASER registers. 1113 1114 If unsure, say Y. 1115 1116config CAVIUM_ERRATUM_23144 1117 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1118 depends on NUMA 1119 default y 1120 help 1121 ITS SYNC command hang for cross node io and collections/cpu mapping. 1122 1123 If unsure, say Y. 1124 1125config CAVIUM_ERRATUM_23154 1126 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1127 default y 1128 help 1129 The ThunderX GICv3 implementation requires a modified version for 1130 reading the IAR status to ensure data synchronization 1131 (access to icc_iar1_el1 is not sync'ed before and after). 1132 1133 It also suffers from erratum 38545 (also present on Marvell's 1134 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1135 spuriously presented to the CPU interface. 1136 1137 If unsure, say Y. 1138 1139config CAVIUM_ERRATUM_27456 1140 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1141 default y 1142 help 1143 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1144 instructions may cause the icache to become corrupted if it 1145 contains data for a non-current ASID. The fix is to 1146 invalidate the icache when changing the mm context. 1147 1148 If unsure, say Y. 1149 1150config CAVIUM_ERRATUM_30115 1151 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1152 default y 1153 help 1154 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1155 1.2, and T83 Pass 1.0, KVM guest execution may disable 1156 interrupts in host. Trapping both GICv3 group-0 and group-1 1157 accesses sidesteps the issue. 1158 1159 If unsure, say Y. 1160 1161config CAVIUM_TX2_ERRATUM_219 1162 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1163 default y 1164 help 1165 On Cavium ThunderX2, a load, store or prefetch instruction between a 1166 TTBR update and the corresponding context synchronizing operation can 1167 cause a spurious Data Abort to be delivered to any hardware thread in 1168 the CPU core. 1169 1170 Work around the issue by avoiding the problematic code sequence and 1171 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1172 trap handler performs the corresponding register access, skips the 1173 instruction and ensures context synchronization by virtue of the 1174 exception return. 1175 1176 If unsure, say Y. 1177 1178config FUJITSU_ERRATUM_010001 1179 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1180 default y 1181 help 1182 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1183 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1184 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1185 This fault occurs under a specific hardware condition when a 1186 load/store instruction performs an address translation using: 1187 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1188 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1189 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1190 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1191 1192 The workaround is to ensure these bits are clear in TCR_ELx. 1193 The workaround only affects the Fujitsu-A64FX. 1194 1195 If unsure, say Y. 1196 1197config HISILICON_ERRATUM_161600802 1198 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1199 default y 1200 help 1201 The HiSilicon Hip07 SoC uses the wrong redistributor base 1202 when issued ITS commands such as VMOVP and VMAPP, and requires 1203 a 128kB offset to be applied to the target address in this commands. 1204 1205 If unsure, say Y. 1206 1207config QCOM_FALKOR_ERRATUM_1003 1208 bool "Falkor E1003: Incorrect translation due to ASID change" 1209 default y 1210 help 1211 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1212 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1213 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1214 then only for entries in the walk cache, since the leaf translation 1215 is unchanged. Work around the erratum by invalidating the walk cache 1216 entries for the trampoline before entering the kernel proper. 1217 1218config QCOM_FALKOR_ERRATUM_1009 1219 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1220 default y 1221 select ARM64_WORKAROUND_REPEAT_TLBI 1222 help 1223 On Falkor v1, the CPU may prematurely complete a DSB following a 1224 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1225 one more time to fix the issue. 1226 1227 If unsure, say Y. 1228 1229config QCOM_QDF2400_ERRATUM_0065 1230 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1231 default y 1232 help 1233 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1234 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1235 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1236 1237 If unsure, say Y. 1238 1239config QCOM_FALKOR_ERRATUM_E1041 1240 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1241 default y 1242 help 1243 Falkor CPU may speculatively fetch instructions from an improper 1244 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1245 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1246 1247 If unsure, say Y. 1248 1249config NVIDIA_CARMEL_CNP_ERRATUM 1250 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1251 default y 1252 help 1253 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1254 invalidate shared TLB entries installed by a different core, as it would 1255 on standard ARM cores. 1256 1257 If unsure, say Y. 1258 1259config ROCKCHIP_ERRATUM_3588001 1260 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1261 default y 1262 help 1263 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1264 This means, that its sharability feature may not be used, even though it 1265 is supported by the IP itself. 1266 1267 If unsure, say Y. 1268 1269config SOCIONEXT_SYNQUACER_PREITS 1270 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1271 default y 1272 help 1273 Socionext Synquacer SoCs implement a separate h/w block to generate 1274 MSI doorbell writes with non-zero values for the device ID. 1275 1276 If unsure, say Y. 1277 1278endmenu # "ARM errata workarounds via the alternatives framework" 1279 1280choice 1281 prompt "Page size" 1282 default ARM64_4K_PAGES 1283 help 1284 Page size (translation granule) configuration. 1285 1286config ARM64_4K_PAGES 1287 bool "4KB" 1288 select HAVE_PAGE_SIZE_4KB 1289 help 1290 This feature enables 4KB pages support. 1291 1292config ARM64_16K_PAGES 1293 bool "16KB" 1294 select HAVE_PAGE_SIZE_16KB 1295 help 1296 The system will use 16KB pages support. AArch32 emulation 1297 requires applications compiled with 16K (or a multiple of 16K) 1298 aligned segments. 1299 1300config ARM64_64K_PAGES 1301 bool "64KB" 1302 select HAVE_PAGE_SIZE_64KB 1303 help 1304 This feature enables 64KB pages support (4KB by default) 1305 allowing only two levels of page tables and faster TLB 1306 look-up. AArch32 emulation requires applications compiled 1307 with 64K aligned segments. 1308 1309endchoice 1310 1311choice 1312 prompt "Virtual address space size" 1313 default ARM64_VA_BITS_52 1314 help 1315 Allows choosing one of multiple possible virtual address 1316 space sizes. The level of translation table is determined by 1317 a combination of page size and virtual address space size. 1318 1319config ARM64_VA_BITS_36 1320 bool "36-bit" if EXPERT 1321 depends on PAGE_SIZE_16KB 1322 1323config ARM64_VA_BITS_39 1324 bool "39-bit" 1325 depends on PAGE_SIZE_4KB 1326 1327config ARM64_VA_BITS_42 1328 bool "42-bit" 1329 depends on PAGE_SIZE_64KB 1330 1331config ARM64_VA_BITS_47 1332 bool "47-bit" 1333 depends on PAGE_SIZE_16KB 1334 1335config ARM64_VA_BITS_48 1336 bool "48-bit" 1337 1338config ARM64_VA_BITS_52 1339 bool "52-bit" 1340 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1341 help 1342 Enable 52-bit virtual addressing for userspace when explicitly 1343 requested via a hint to mmap(). The kernel will also use 52-bit 1344 virtual addresses for its own mappings (provided HW support for 1345 this feature is available, otherwise it reverts to 48-bit). 1346 1347 NOTE: Enabling 52-bit virtual addressing in conjunction with 1348 ARMv8.3 Pointer Authentication will result in the PAC being 1349 reduced from 7 bits to 3 bits, which may have a significant 1350 impact on its susceptibility to brute-force attacks. 1351 1352 If unsure, select 48-bit virtual addressing instead. 1353 1354endchoice 1355 1356config ARM64_FORCE_52BIT 1357 bool "Force 52-bit virtual addresses for userspace" 1358 depends on ARM64_VA_BITS_52 && EXPERT 1359 help 1360 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1361 to maintain compatibility with older software by providing 48-bit VAs 1362 unless a hint is supplied to mmap. 1363 1364 This configuration option disables the 48-bit compatibility logic, and 1365 forces all userspace addresses to be 52-bit on HW that supports it. One 1366 should only enable this configuration option for stress testing userspace 1367 memory management code. If unsure say N here. 1368 1369config ARM64_VA_BITS 1370 int 1371 default 36 if ARM64_VA_BITS_36 1372 default 39 if ARM64_VA_BITS_39 1373 default 42 if ARM64_VA_BITS_42 1374 default 47 if ARM64_VA_BITS_47 1375 default 48 if ARM64_VA_BITS_48 1376 default 52 if ARM64_VA_BITS_52 1377 1378choice 1379 prompt "Physical address space size" 1380 default ARM64_PA_BITS_48 1381 help 1382 Choose the maximum physical address range that the kernel will 1383 support. 1384 1385config ARM64_PA_BITS_48 1386 bool "48-bit" 1387 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1388 1389config ARM64_PA_BITS_52 1390 bool "52-bit" 1391 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1392 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1393 help 1394 Enable support for a 52-bit physical address space, introduced as 1395 part of the ARMv8.2-LPA extension. 1396 1397 With this enabled, the kernel will also continue to work on CPUs that 1398 do not support ARMv8.2-LPA, but with some added memory overhead (and 1399 minor performance overhead). 1400 1401endchoice 1402 1403config ARM64_PA_BITS 1404 int 1405 default 48 if ARM64_PA_BITS_48 1406 default 52 if ARM64_PA_BITS_52 1407 1408config ARM64_LPA2 1409 def_bool y 1410 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1411 1412choice 1413 prompt "Endianness" 1414 default CPU_LITTLE_ENDIAN 1415 help 1416 Select the endianness of data accesses performed by the CPU. Userspace 1417 applications will need to be compiled and linked for the endianness 1418 that is selected here. 1419 1420config CPU_BIG_ENDIAN 1421 bool "Build big-endian kernel" 1422 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1423 depends on AS_IS_GNU || AS_VERSION >= 150000 1424 help 1425 Say Y if you plan on running a kernel with a big-endian userspace. 1426 1427config CPU_LITTLE_ENDIAN 1428 bool "Build little-endian kernel" 1429 help 1430 Say Y if you plan on running a kernel with a little-endian userspace. 1431 This is usually the case for distributions targeting arm64. 1432 1433endchoice 1434 1435config SCHED_MC 1436 bool "Multi-core scheduler support" 1437 help 1438 Multi-core scheduler support improves the CPU scheduler's decision 1439 making when dealing with multi-core CPU chips at a cost of slightly 1440 increased overhead in some places. If unsure say N here. 1441 1442config SCHED_CLUSTER 1443 bool "Cluster scheduler support" 1444 help 1445 Cluster scheduler support improves the CPU scheduler's decision 1446 making when dealing with machines that have clusters of CPUs. 1447 Cluster usually means a couple of CPUs which are placed closely 1448 by sharing mid-level caches, last-level cache tags or internal 1449 busses. 1450 1451config SCHED_SMT 1452 bool "SMT scheduler support" 1453 help 1454 Improves the CPU scheduler's decision making when dealing with 1455 MultiThreading at a cost of slightly increased overhead in some 1456 places. If unsure say N here. 1457 1458config NR_CPUS 1459 int "Maximum number of CPUs (2-4096)" 1460 range 2 4096 1461 default "512" 1462 1463config HOTPLUG_CPU 1464 bool "Support for hot-pluggable CPUs" 1465 select GENERIC_IRQ_MIGRATION 1466 help 1467 Say Y here to experiment with turning CPUs off and on. CPUs 1468 can be controlled through /sys/devices/system/cpu. 1469 1470# Common NUMA Features 1471config NUMA 1472 bool "NUMA Memory Allocation and Scheduler Support" 1473 select GENERIC_ARCH_NUMA 1474 select ACPI_NUMA if ACPI 1475 select OF_NUMA 1476 select HAVE_SETUP_PER_CPU_AREA 1477 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1478 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1479 select USE_PERCPU_NUMA_NODE_ID 1480 help 1481 Enable NUMA (Non-Uniform Memory Access) support. 1482 1483 The kernel will try to allocate memory used by a CPU on the 1484 local memory of the CPU and add some more 1485 NUMA awareness to the kernel. 1486 1487config NODES_SHIFT 1488 int "Maximum NUMA Nodes (as a power of 2)" 1489 range 1 10 1490 default "4" 1491 depends on NUMA 1492 help 1493 Specify the maximum number of NUMA Nodes available on the target 1494 system. Increases memory reserved to accommodate various tables. 1495 1496source "kernel/Kconfig.hz" 1497 1498config ARCH_SPARSEMEM_ENABLE 1499 def_bool y 1500 select SPARSEMEM_VMEMMAP_ENABLE 1501 select SPARSEMEM_VMEMMAP 1502 1503config HW_PERF_EVENTS 1504 def_bool y 1505 depends on ARM_PMU 1506 1507# Supported by clang >= 7.0 or GCC >= 12.0.0 1508config CC_HAVE_SHADOW_CALL_STACK 1509 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1510 1511config PARAVIRT 1512 bool "Enable paravirtualization code" 1513 help 1514 This changes the kernel so it can modify itself when it is run 1515 under a hypervisor, potentially improving performance significantly 1516 over full virtualization. 1517 1518config PARAVIRT_TIME_ACCOUNTING 1519 bool "Paravirtual steal time accounting" 1520 select PARAVIRT 1521 help 1522 Select this option to enable fine granularity task steal time 1523 accounting. Time spent executing other tasks in parallel with 1524 the current vCPU is discounted from the vCPU power. To account for 1525 that, there can be a small performance impact. 1526 1527 If in doubt, say N here. 1528 1529config ARCH_SUPPORTS_KEXEC 1530 def_bool PM_SLEEP_SMP 1531 1532config ARCH_SUPPORTS_KEXEC_FILE 1533 def_bool y 1534 1535config ARCH_SELECTS_KEXEC_FILE 1536 def_bool y 1537 depends on KEXEC_FILE 1538 select HAVE_IMA_KEXEC if IMA 1539 1540config ARCH_SUPPORTS_KEXEC_SIG 1541 def_bool y 1542 1543config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1544 def_bool y 1545 1546config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1547 def_bool y 1548 1549config ARCH_SUPPORTS_CRASH_DUMP 1550 def_bool y 1551 1552config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1553 def_bool CRASH_RESERVE 1554 1555config TRANS_TABLE 1556 def_bool y 1557 depends on HIBERNATION || KEXEC_CORE 1558 1559config XEN_DOM0 1560 def_bool y 1561 depends on XEN 1562 1563config XEN 1564 bool "Xen guest support on ARM64" 1565 depends on ARM64 && OF 1566 select SWIOTLB_XEN 1567 select PARAVIRT 1568 help 1569 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1570 1571# include/linux/mmzone.h requires the following to be true: 1572# 1573# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1574# 1575# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1576# 1577# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1578# ----+-------------------+--------------+----------------------+-------------------------+ 1579# 4K | 27 | 12 | 15 | 10 | 1580# 16K | 27 | 14 | 13 | 11 | 1581# 64K | 29 | 16 | 13 | 13 | 1582config ARCH_FORCE_MAX_ORDER 1583 int 1584 default "13" if ARM64_64K_PAGES 1585 default "11" if ARM64_16K_PAGES 1586 default "10" 1587 help 1588 The kernel page allocator limits the size of maximal physically 1589 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1590 defines the maximal power of two of number of pages that can be 1591 allocated as a single contiguous block. This option allows 1592 overriding the default setting when ability to allocate very 1593 large blocks of physically contiguous memory is required. 1594 1595 The maximal size of allocation cannot exceed the size of the 1596 section, so the value of MAX_PAGE_ORDER should satisfy 1597 1598 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1599 1600 Don't change if unsure. 1601 1602config UNMAP_KERNEL_AT_EL0 1603 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1604 default y 1605 help 1606 Speculation attacks against some high-performance processors can 1607 be used to bypass MMU permission checks and leak kernel data to 1608 userspace. This can be defended against by unmapping the kernel 1609 when running in userspace, mapping it back in on exception entry 1610 via a trampoline page in the vector table. 1611 1612 If unsure, say Y. 1613 1614config MITIGATE_SPECTRE_BRANCH_HISTORY 1615 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1616 default y 1617 help 1618 Speculation attacks against some high-performance processors can 1619 make use of branch history to influence future speculation. 1620 When taking an exception from user-space, a sequence of branches 1621 or a firmware call overwrites the branch history. 1622 1623config RODATA_FULL_DEFAULT_ENABLED 1624 bool "Apply r/o permissions of VM areas also to their linear aliases" 1625 default y 1626 help 1627 Apply read-only attributes of VM areas to the linear alias of 1628 the backing pages as well. This prevents code or read-only data 1629 from being modified (inadvertently or intentionally) via another 1630 mapping of the same memory page. This additional enhancement can 1631 be turned off at runtime by passing rodata=[off|on] (and turned on 1632 with rodata=full if this option is set to 'n') 1633 1634 This requires the linear region to be mapped down to pages, 1635 which may adversely affect performance in some cases. 1636 1637config ARM64_SW_TTBR0_PAN 1638 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1639 depends on !KCSAN 1640 help 1641 Enabling this option prevents the kernel from accessing 1642 user-space memory directly by pointing TTBR0_EL1 to a reserved 1643 zeroed area and reserved ASID. The user access routines 1644 restore the valid TTBR0_EL1 temporarily. 1645 1646config ARM64_TAGGED_ADDR_ABI 1647 bool "Enable the tagged user addresses syscall ABI" 1648 default y 1649 help 1650 When this option is enabled, user applications can opt in to a 1651 relaxed ABI via prctl() allowing tagged addresses to be passed 1652 to system calls as pointer arguments. For details, see 1653 Documentation/arch/arm64/tagged-address-abi.rst. 1654 1655menuconfig COMPAT 1656 bool "Kernel support for 32-bit EL0" 1657 depends on ARM64_4K_PAGES || EXPERT 1658 select HAVE_UID16 1659 select OLD_SIGSUSPEND3 1660 select COMPAT_OLD_SIGACTION 1661 help 1662 This option enables support for a 32-bit EL0 running under a 64-bit 1663 kernel at EL1. AArch32-specific components such as system calls, 1664 the user helper functions, VFP support and the ptrace interface are 1665 handled appropriately by the kernel. 1666 1667 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1668 that you will only be able to execute AArch32 binaries that were compiled 1669 with page size aligned segments. 1670 1671 If you want to execute 32-bit userspace applications, say Y. 1672 1673if COMPAT 1674 1675config KUSER_HELPERS 1676 bool "Enable kuser helpers page for 32-bit applications" 1677 default y 1678 help 1679 Warning: disabling this option may break 32-bit user programs. 1680 1681 Provide kuser helpers to compat tasks. The kernel provides 1682 helper code to userspace in read only form at a fixed location 1683 to allow userspace to be independent of the CPU type fitted to 1684 the system. This permits binaries to be run on ARMv4 through 1685 to ARMv8 without modification. 1686 1687 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1688 1689 However, the fixed address nature of these helpers can be used 1690 by ROP (return orientated programming) authors when creating 1691 exploits. 1692 1693 If all of the binaries and libraries which run on your platform 1694 are built specifically for your platform, and make no use of 1695 these helpers, then you can turn this option off to hinder 1696 such exploits. However, in that case, if a binary or library 1697 relying on those helpers is run, it will not function correctly. 1698 1699 Say N here only if you are absolutely certain that you do not 1700 need these helpers; otherwise, the safe option is to say Y. 1701 1702config COMPAT_VDSO 1703 bool "Enable vDSO for 32-bit applications" 1704 depends on !CPU_BIG_ENDIAN 1705 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1706 select GENERIC_COMPAT_VDSO 1707 default y 1708 help 1709 Place in the process address space of 32-bit applications an 1710 ELF shared object providing fast implementations of gettimeofday 1711 and clock_gettime. 1712 1713 You must have a 32-bit build of glibc 2.22 or later for programs 1714 to seamlessly take advantage of this. 1715 1716config THUMB2_COMPAT_VDSO 1717 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1718 depends on COMPAT_VDSO 1719 default y 1720 help 1721 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1722 otherwise with '-marm'. 1723 1724config COMPAT_ALIGNMENT_FIXUPS 1725 bool "Fix up misaligned multi-word loads and stores in user space" 1726 1727menuconfig ARMV8_DEPRECATED 1728 bool "Emulate deprecated/obsolete ARMv8 instructions" 1729 depends on SYSCTL 1730 help 1731 Legacy software support may require certain instructions 1732 that have been deprecated or obsoleted in the architecture. 1733 1734 Enable this config to enable selective emulation of these 1735 features. 1736 1737 If unsure, say Y 1738 1739if ARMV8_DEPRECATED 1740 1741config SWP_EMULATION 1742 bool "Emulate SWP/SWPB instructions" 1743 help 1744 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1745 they are always undefined. Say Y here to enable software 1746 emulation of these instructions for userspace using LDXR/STXR. 1747 This feature can be controlled at runtime with the abi.swp 1748 sysctl which is disabled by default. 1749 1750 In some older versions of glibc [<=2.8] SWP is used during futex 1751 trylock() operations with the assumption that the code will not 1752 be preempted. This invalid assumption may be more likely to fail 1753 with SWP emulation enabled, leading to deadlock of the user 1754 application. 1755 1756 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1757 on an external transaction monitoring block called a global 1758 monitor to maintain update atomicity. If your system does not 1759 implement a global monitor, this option can cause programs that 1760 perform SWP operations to uncached memory to deadlock. 1761 1762 If unsure, say Y 1763 1764config CP15_BARRIER_EMULATION 1765 bool "Emulate CP15 Barrier instructions" 1766 help 1767 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1768 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1769 strongly recommended to use the ISB, DSB, and DMB 1770 instructions instead. 1771 1772 Say Y here to enable software emulation of these 1773 instructions for AArch32 userspace code. When this option is 1774 enabled, CP15 barrier usage is traced which can help 1775 identify software that needs updating. This feature can be 1776 controlled at runtime with the abi.cp15_barrier sysctl. 1777 1778 If unsure, say Y 1779 1780config SETEND_EMULATION 1781 bool "Emulate SETEND instruction" 1782 help 1783 The SETEND instruction alters the data-endianness of the 1784 AArch32 EL0, and is deprecated in ARMv8. 1785 1786 Say Y here to enable software emulation of the instruction 1787 for AArch32 userspace code. This feature can be controlled 1788 at runtime with the abi.setend sysctl. 1789 1790 Note: All the cpus on the system must have mixed endian support at EL0 1791 for this feature to be enabled. If a new CPU - which doesn't support mixed 1792 endian - is hotplugged in after this feature has been enabled, there could 1793 be unexpected results in the applications. 1794 1795 If unsure, say Y 1796endif # ARMV8_DEPRECATED 1797 1798endif # COMPAT 1799 1800menu "ARMv8.1 architectural features" 1801 1802config ARM64_HW_AFDBM 1803 bool "Support for hardware updates of the Access and Dirty page flags" 1804 default y 1805 help 1806 The ARMv8.1 architecture extensions introduce support for 1807 hardware updates of the access and dirty information in page 1808 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1809 capable processors, accesses to pages with PTE_AF cleared will 1810 set this bit instead of raising an access flag fault. 1811 Similarly, writes to read-only pages with the DBM bit set will 1812 clear the read-only bit (AP[2]) instead of raising a 1813 permission fault. 1814 1815 Kernels built with this configuration option enabled continue 1816 to work on pre-ARMv8.1 hardware and the performance impact is 1817 minimal. If unsure, say Y. 1818 1819config ARM64_PAN 1820 bool "Enable support for Privileged Access Never (PAN)" 1821 default y 1822 help 1823 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1824 prevents the kernel or hypervisor from accessing user-space (EL0) 1825 memory directly. 1826 1827 Choosing this option will cause any unprotected (not using 1828 copy_to_user et al) memory access to fail with a permission fault. 1829 1830 The feature is detected at runtime, and will remain as a 'nop' 1831 instruction if the cpu does not implement the feature. 1832 1833config AS_HAS_LSE_ATOMICS 1834 def_bool $(as-instr,.arch_extension lse) 1835 1836config ARM64_LSE_ATOMICS 1837 bool 1838 default ARM64_USE_LSE_ATOMICS 1839 depends on AS_HAS_LSE_ATOMICS 1840 1841config ARM64_USE_LSE_ATOMICS 1842 bool "Atomic instructions" 1843 default y 1844 help 1845 As part of the Large System Extensions, ARMv8.1 introduces new 1846 atomic instructions that are designed specifically to scale in 1847 very large systems. 1848 1849 Say Y here to make use of these instructions for the in-kernel 1850 atomic routines. This incurs a small overhead on CPUs that do 1851 not support these instructions and requires the kernel to be 1852 built with binutils >= 2.25 in order for the new instructions 1853 to be used. 1854 1855endmenu # "ARMv8.1 architectural features" 1856 1857menu "ARMv8.2 architectural features" 1858 1859config AS_HAS_ARMV8_2 1860 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1861 1862config AS_HAS_SHA3 1863 def_bool $(as-instr,.arch armv8.2-a+sha3) 1864 1865config ARM64_PMEM 1866 bool "Enable support for persistent memory" 1867 select ARCH_HAS_PMEM_API 1868 select ARCH_HAS_UACCESS_FLUSHCACHE 1869 help 1870 Say Y to enable support for the persistent memory API based on the 1871 ARMv8.2 DCPoP feature. 1872 1873 The feature is detected at runtime, and the kernel will use DC CVAC 1874 operations if DC CVAP is not supported (following the behaviour of 1875 DC CVAP itself if the system does not define a point of persistence). 1876 1877config ARM64_RAS_EXTN 1878 bool "Enable support for RAS CPU Extensions" 1879 default y 1880 help 1881 CPUs that support the Reliability, Availability and Serviceability 1882 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1883 errors, classify them and report them to software. 1884 1885 On CPUs with these extensions system software can use additional 1886 barriers to determine if faults are pending and read the 1887 classification from a new set of registers. 1888 1889 Selecting this feature will allow the kernel to use these barriers 1890 and access the new registers if the system supports the extension. 1891 Platform RAS features may additionally depend on firmware support. 1892 1893config ARM64_CNP 1894 bool "Enable support for Common Not Private (CNP) translations" 1895 default y 1896 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1897 help 1898 Common Not Private (CNP) allows translation table entries to 1899 be shared between different PEs in the same inner shareable 1900 domain, so the hardware can use this fact to optimise the 1901 caching of such entries in the TLB. 1902 1903 Selecting this option allows the CNP feature to be detected 1904 at runtime, and does not affect PEs that do not implement 1905 this feature. 1906 1907endmenu # "ARMv8.2 architectural features" 1908 1909menu "ARMv8.3 architectural features" 1910 1911config ARM64_PTR_AUTH 1912 bool "Enable support for pointer authentication" 1913 default y 1914 help 1915 Pointer authentication (part of the ARMv8.3 Extensions) provides 1916 instructions for signing and authenticating pointers against secret 1917 keys, which can be used to mitigate Return Oriented Programming (ROP) 1918 and other attacks. 1919 1920 This option enables these instructions at EL0 (i.e. for userspace). 1921 Choosing this option will cause the kernel to initialise secret keys 1922 for each process at exec() time, with these keys being 1923 context-switched along with the process. 1924 1925 The feature is detected at runtime. If the feature is not present in 1926 hardware it will not be advertised to userspace/KVM guest nor will it 1927 be enabled. 1928 1929 If the feature is present on the boot CPU but not on a late CPU, then 1930 the late CPU will be parked. Also, if the boot CPU does not have 1931 address auth and the late CPU has then the late CPU will still boot 1932 but with the feature disabled. On such a system, this option should 1933 not be selected. 1934 1935config ARM64_PTR_AUTH_KERNEL 1936 bool "Use pointer authentication for kernel" 1937 default y 1938 depends on ARM64_PTR_AUTH 1939 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1940 # Modern compilers insert a .note.gnu.property section note for PAC 1941 # which is only understood by binutils starting with version 2.33.1. 1942 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1943 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1944 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1945 help 1946 If the compiler supports the -mbranch-protection or 1947 -msign-return-address flag (e.g. GCC 7 or later), then this option 1948 will cause the kernel itself to be compiled with return address 1949 protection. In this case, and if the target hardware is known to 1950 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1951 disabled with minimal loss of protection. 1952 1953 This feature works with FUNCTION_GRAPH_TRACER option only if 1954 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1955 1956config CC_HAS_BRANCH_PROT_PAC_RET 1957 # GCC 9 or later, clang 8 or later 1958 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1959 1960config CC_HAS_SIGN_RETURN_ADDRESS 1961 # GCC 7, 8 1962 def_bool $(cc-option,-msign-return-address=all) 1963 1964config AS_HAS_ARMV8_3 1965 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1966 1967config AS_HAS_CFI_NEGATE_RA_STATE 1968 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1969 1970config AS_HAS_LDAPR 1971 def_bool $(as-instr,.arch_extension rcpc) 1972 1973endmenu # "ARMv8.3 architectural features" 1974 1975menu "ARMv8.4 architectural features" 1976 1977config ARM64_AMU_EXTN 1978 bool "Enable support for the Activity Monitors Unit CPU extension" 1979 default y 1980 help 1981 The activity monitors extension is an optional extension introduced 1982 by the ARMv8.4 CPU architecture. This enables support for version 1 1983 of the activity monitors architecture, AMUv1. 1984 1985 To enable the use of this extension on CPUs that implement it, say Y. 1986 1987 Note that for architectural reasons, firmware _must_ implement AMU 1988 support when running on CPUs that present the activity monitors 1989 extension. The required support is present in: 1990 * Version 1.5 and later of the ARM Trusted Firmware 1991 1992 For kernels that have this configuration enabled but boot with broken 1993 firmware, you may need to say N here until the firmware is fixed. 1994 Otherwise you may experience firmware panics or lockups when 1995 accessing the counter registers. Even if you are not observing these 1996 symptoms, the values returned by the register reads might not 1997 correctly reflect reality. Most commonly, the value read will be 0, 1998 indicating that the counter is not enabled. 1999 2000config AS_HAS_ARMV8_4 2001 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2002 2003config ARM64_TLB_RANGE 2004 bool "Enable support for tlbi range feature" 2005 default y 2006 depends on AS_HAS_ARMV8_4 2007 help 2008 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2009 range of input addresses. 2010 2011 The feature introduces new assembly instructions, and they were 2012 support when binutils >= 2.30. 2013 2014endmenu # "ARMv8.4 architectural features" 2015 2016menu "ARMv8.5 architectural features" 2017 2018config AS_HAS_ARMV8_5 2019 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2020 2021config ARM64_BTI 2022 bool "Branch Target Identification support" 2023 default y 2024 help 2025 Branch Target Identification (part of the ARMv8.5 Extensions) 2026 provides a mechanism to limit the set of locations to which computed 2027 branch instructions such as BR or BLR can jump. 2028 2029 To make use of BTI on CPUs that support it, say Y. 2030 2031 BTI is intended to provide complementary protection to other control 2032 flow integrity protection mechanisms, such as the Pointer 2033 authentication mechanism provided as part of the ARMv8.3 Extensions. 2034 For this reason, it does not make sense to enable this option without 2035 also enabling support for pointer authentication. Thus, when 2036 enabling this option you should also select ARM64_PTR_AUTH=y. 2037 2038 Userspace binaries must also be specifically compiled to make use of 2039 this mechanism. If you say N here or the hardware does not support 2040 BTI, such binaries can still run, but you get no additional 2041 enforcement of branch destinations. 2042 2043config ARM64_BTI_KERNEL 2044 bool "Use Branch Target Identification for kernel" 2045 default y 2046 depends on ARM64_BTI 2047 depends on ARM64_PTR_AUTH_KERNEL 2048 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2049 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2050 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2051 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2052 depends on !CC_IS_GCC 2053 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2054 help 2055 Build the kernel with Branch Target Identification annotations 2056 and enable enforcement of this for kernel code. When this option 2057 is enabled and the system supports BTI all kernel code including 2058 modular code must have BTI enabled. 2059 2060config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2061 # GCC 9 or later, clang 8 or later 2062 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2063 2064config ARM64_E0PD 2065 bool "Enable support for E0PD" 2066 default y 2067 help 2068 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2069 that EL0 accesses made via TTBR1 always fault in constant time, 2070 providing similar benefits to KASLR as those provided by KPTI, but 2071 with lower overhead and without disrupting legitimate access to 2072 kernel memory such as SPE. 2073 2074 This option enables E0PD for TTBR1 where available. 2075 2076config ARM64_AS_HAS_MTE 2077 # Initial support for MTE went in binutils 2.32.0, checked with 2078 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2079 # as a late addition to the final architecture spec (LDGM/STGM) 2080 # is only supported in the newer 2.32.x and 2.33 binutils 2081 # versions, hence the extra "stgm" instruction check below. 2082 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2083 2084config ARM64_MTE 2085 bool "Memory Tagging Extension support" 2086 default y 2087 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2088 depends on AS_HAS_ARMV8_5 2089 depends on AS_HAS_LSE_ATOMICS 2090 # Required for tag checking in the uaccess routines 2091 depends on ARM64_PAN 2092 select ARCH_HAS_SUBPAGE_FAULTS 2093 select ARCH_USES_HIGH_VMA_FLAGS 2094 select ARCH_USES_PG_ARCH_X 2095 help 2096 Memory Tagging (part of the ARMv8.5 Extensions) provides 2097 architectural support for run-time, always-on detection of 2098 various classes of memory error to aid with software debugging 2099 to eliminate vulnerabilities arising from memory-unsafe 2100 languages. 2101 2102 This option enables the support for the Memory Tagging 2103 Extension at EL0 (i.e. for userspace). 2104 2105 Selecting this option allows the feature to be detected at 2106 runtime. Any secondary CPU not implementing this feature will 2107 not be allowed a late bring-up. 2108 2109 Userspace binaries that want to use this feature must 2110 explicitly opt in. The mechanism for the userspace is 2111 described in: 2112 2113 Documentation/arch/arm64/memory-tagging-extension.rst. 2114 2115endmenu # "ARMv8.5 architectural features" 2116 2117menu "ARMv8.7 architectural features" 2118 2119config ARM64_EPAN 2120 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2121 default y 2122 depends on ARM64_PAN 2123 help 2124 Enhanced Privileged Access Never (EPAN) allows Privileged 2125 Access Never to be used with Execute-only mappings. 2126 2127 The feature is detected at runtime, and will remain disabled 2128 if the cpu does not implement the feature. 2129endmenu # "ARMv8.7 architectural features" 2130 2131config ARM64_SVE 2132 bool "ARM Scalable Vector Extension support" 2133 default y 2134 help 2135 The Scalable Vector Extension (SVE) is an extension to the AArch64 2136 execution state which complements and extends the SIMD functionality 2137 of the base architecture to support much larger vectors and to enable 2138 additional vectorisation opportunities. 2139 2140 To enable use of this extension on CPUs that implement it, say Y. 2141 2142 On CPUs that support the SVE2 extensions, this option will enable 2143 those too. 2144 2145 Note that for architectural reasons, firmware _must_ implement SVE 2146 support when running on SVE capable hardware. The required support 2147 is present in: 2148 2149 * version 1.5 and later of the ARM Trusted Firmware 2150 * the AArch64 boot wrapper since commit 5e1261e08abf 2151 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2152 2153 For other firmware implementations, consult the firmware documentation 2154 or vendor. 2155 2156 If you need the kernel to boot on SVE-capable hardware with broken 2157 firmware, you may need to say N here until you get your firmware 2158 fixed. Otherwise, you may experience firmware panics or lockups when 2159 booting the kernel. If unsure and you are not observing these 2160 symptoms, you should assume that it is safe to say Y. 2161 2162config ARM64_SME 2163 bool "ARM Scalable Matrix Extension support" 2164 default y 2165 depends on ARM64_SVE 2166 help 2167 The Scalable Matrix Extension (SME) is an extension to the AArch64 2168 execution state which utilises a substantial subset of the SVE 2169 instruction set, together with the addition of new architectural 2170 register state capable of holding two dimensional matrix tiles to 2171 enable various matrix operations. 2172 2173config ARM64_PSEUDO_NMI 2174 bool "Support for NMI-like interrupts" 2175 select ARM_GIC_V3 2176 help 2177 Adds support for mimicking Non-Maskable Interrupts through the use of 2178 GIC interrupt priority. This support requires version 3 or later of 2179 ARM GIC. 2180 2181 This high priority configuration for interrupts needs to be 2182 explicitly enabled by setting the kernel parameter 2183 "irqchip.gicv3_pseudo_nmi" to 1. 2184 2185 If unsure, say N 2186 2187if ARM64_PSEUDO_NMI 2188config ARM64_DEBUG_PRIORITY_MASKING 2189 bool "Debug interrupt priority masking" 2190 help 2191 This adds runtime checks to functions enabling/disabling 2192 interrupts when using priority masking. The additional checks verify 2193 the validity of ICC_PMR_EL1 when calling concerned functions. 2194 2195 If unsure, say N 2196endif # ARM64_PSEUDO_NMI 2197 2198config RELOCATABLE 2199 bool "Build a relocatable kernel image" if EXPERT 2200 select ARCH_HAS_RELR 2201 default y 2202 help 2203 This builds the kernel as a Position Independent Executable (PIE), 2204 which retains all relocation metadata required to relocate the 2205 kernel binary at runtime to a different virtual address than the 2206 address it was linked at. 2207 Since AArch64 uses the RELA relocation format, this requires a 2208 relocation pass at runtime even if the kernel is loaded at the 2209 same address it was linked at. 2210 2211config RANDOMIZE_BASE 2212 bool "Randomize the address of the kernel image" 2213 select RELOCATABLE 2214 help 2215 Randomizes the virtual address at which the kernel image is 2216 loaded, as a security feature that deters exploit attempts 2217 relying on knowledge of the location of kernel internals. 2218 2219 It is the bootloader's job to provide entropy, by passing a 2220 random u64 value in /chosen/kaslr-seed at kernel entry. 2221 2222 When booting via the UEFI stub, it will invoke the firmware's 2223 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2224 to the kernel proper. In addition, it will randomise the physical 2225 location of the kernel Image as well. 2226 2227 If unsure, say N. 2228 2229config RANDOMIZE_MODULE_REGION_FULL 2230 bool "Randomize the module region over a 2 GB range" 2231 depends on RANDOMIZE_BASE 2232 default y 2233 help 2234 Randomizes the location of the module region inside a 2 GB window 2235 covering the core kernel. This way, it is less likely for modules 2236 to leak information about the location of core kernel data structures 2237 but it does imply that function calls between modules and the core 2238 kernel will need to be resolved via veneers in the module PLT. 2239 2240 When this option is not set, the module region will be randomized over 2241 a limited range that contains the [_stext, _etext] interval of the 2242 core kernel, so branch relocations are almost always in range unless 2243 the region is exhausted. In this particular case of region 2244 exhaustion, modules might be able to fall back to a larger 2GB area. 2245 2246config CC_HAVE_STACKPROTECTOR_SYSREG 2247 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2248 2249config STACKPROTECTOR_PER_TASK 2250 def_bool y 2251 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2252 2253config UNWIND_PATCH_PAC_INTO_SCS 2254 bool "Enable shadow call stack dynamically using code patching" 2255 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2256 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2257 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2258 depends on SHADOW_CALL_STACK 2259 select UNWIND_TABLES 2260 select DYNAMIC_SCS 2261 2262config ARM64_CONTPTE 2263 bool "Contiguous PTE mappings for user memory" if EXPERT 2264 depends on TRANSPARENT_HUGEPAGE 2265 default y 2266 help 2267 When enabled, user mappings are configured using the PTE contiguous 2268 bit, for any mappings that meet the size and alignment requirements. 2269 This reduces TLB pressure and improves performance. 2270 2271endmenu # "Kernel Features" 2272 2273menu "Boot options" 2274 2275config ARM64_ACPI_PARKING_PROTOCOL 2276 bool "Enable support for the ARM64 ACPI parking protocol" 2277 depends on ACPI 2278 help 2279 Enable support for the ARM64 ACPI parking protocol. If disabled 2280 the kernel will not allow booting through the ARM64 ACPI parking 2281 protocol even if the corresponding data is present in the ACPI 2282 MADT table. 2283 2284config CMDLINE 2285 string "Default kernel command string" 2286 default "" 2287 help 2288 Provide a set of default command-line options at build time by 2289 entering them here. As a minimum, you should specify the the 2290 root device (e.g. root=/dev/nfs). 2291 2292choice 2293 prompt "Kernel command line type" if CMDLINE != "" 2294 default CMDLINE_FROM_BOOTLOADER 2295 help 2296 Choose how the kernel will handle the provided default kernel 2297 command line string. 2298 2299config CMDLINE_FROM_BOOTLOADER 2300 bool "Use bootloader kernel arguments if available" 2301 help 2302 Uses the command-line options passed by the boot loader. If 2303 the boot loader doesn't provide any, the default kernel command 2304 string provided in CMDLINE will be used. 2305 2306config CMDLINE_FORCE 2307 bool "Always use the default kernel command string" 2308 help 2309 Always use the default kernel command string, even if the boot 2310 loader passes other arguments to the kernel. 2311 This is useful if you cannot or don't want to change the 2312 command-line options your boot loader passes to the kernel. 2313 2314endchoice 2315 2316config EFI_STUB 2317 bool 2318 2319config EFI 2320 bool "UEFI runtime support" 2321 depends on OF && !CPU_BIG_ENDIAN 2322 depends on KERNEL_MODE_NEON 2323 select ARCH_SUPPORTS_ACPI 2324 select LIBFDT 2325 select UCS2_STRING 2326 select EFI_PARAMS_FROM_FDT 2327 select EFI_RUNTIME_WRAPPERS 2328 select EFI_STUB 2329 select EFI_GENERIC_STUB 2330 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2331 default y 2332 help 2333 This option provides support for runtime services provided 2334 by UEFI firmware (such as non-volatile variables, realtime 2335 clock, and platform reset). A UEFI stub is also provided to 2336 allow the kernel to be booted as an EFI application. This 2337 is only useful on systems that have UEFI firmware. 2338 2339config DMI 2340 bool "Enable support for SMBIOS (DMI) tables" 2341 depends on EFI 2342 default y 2343 help 2344 This enables SMBIOS/DMI feature for systems. 2345 2346 This option is only useful on systems that have UEFI firmware. 2347 However, even with this option, the resultant kernel should 2348 continue to boot on existing non-UEFI platforms. 2349 2350endmenu # "Boot options" 2351 2352menu "Power management options" 2353 2354source "kernel/power/Kconfig" 2355 2356config ARCH_HIBERNATION_POSSIBLE 2357 def_bool y 2358 depends on CPU_PM 2359 2360config ARCH_HIBERNATION_HEADER 2361 def_bool y 2362 depends on HIBERNATION 2363 2364config ARCH_SUSPEND_POSSIBLE 2365 def_bool y 2366 2367endmenu # "Power management options" 2368 2369menu "CPU Power Management" 2370 2371source "drivers/cpuidle/Kconfig" 2372 2373source "drivers/cpufreq/Kconfig" 2374 2375endmenu # "CPU Power Management" 2376 2377source "drivers/acpi/Kconfig" 2378 2379source "arch/arm64/kvm/Kconfig" 2380 2381