1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_HAVE_TRACE_MMIO_ACCESS 52 select ARCH_INLINE_READ_LOCK if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 78 select ARCH_KEEP_MEMBLOCK 79 select ARCH_USE_CMPXCHG_LOCKREF 80 select ARCH_USE_GNU_PROPERTY 81 select ARCH_USE_MEMTEST 82 select ARCH_USE_QUEUED_RWLOCKS 83 select ARCH_USE_QUEUED_SPINLOCKS 84 select ARCH_USE_SYM_ANNOTATIONS 85 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 86 select ARCH_SUPPORTS_HUGETLBFS 87 select ARCH_SUPPORTS_MEMORY_FAILURE 88 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 89 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 90 select ARCH_SUPPORTS_LTO_CLANG_THIN 91 select ARCH_SUPPORTS_CFI_CLANG 92 select ARCH_SUPPORTS_ATOMIC_RMW 93 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 94 select ARCH_SUPPORTS_NUMA_BALANCING 95 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 96 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 97 select ARCH_WANT_DEFAULT_BPF_JIT 98 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 99 select ARCH_WANT_FRAME_POINTERS 100 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 101 select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP 102 select ARCH_WANT_LD_ORPHAN_WARN 103 select ARCH_WANTS_NO_INSTR 104 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 105 select ARCH_HAS_UBSAN_SANITIZE_ALL 106 select ARM_AMBA 107 select ARM_ARCH_TIMER 108 select ARM_GIC 109 select AUDIT_ARCH_COMPAT_GENERIC 110 select ARM_GIC_V2M if PCI 111 select ARM_GIC_V3 112 select ARM_GIC_V3_ITS if PCI 113 select ARM_PSCI_FW 114 select BUILDTIME_TABLE_SORT 115 select CLONE_BACKWARDS 116 select COMMON_CLK 117 select CPU_PM if (SUSPEND || CPU_IDLE) 118 select CRC32 119 select DCACHE_WORD_ACCESS 120 select DMA_DIRECT_REMAP 121 select EDAC_SUPPORT 122 select FRAME_POINTER 123 select GENERIC_ALLOCATOR 124 select GENERIC_ARCH_TOPOLOGY 125 select GENERIC_CLOCKEVENTS_BROADCAST 126 select GENERIC_CPU_AUTOPROBE 127 select GENERIC_CPU_VULNERABILITIES 128 select GENERIC_EARLY_IOREMAP 129 select GENERIC_IDLE_POLL_SETUP 130 select GENERIC_IOREMAP 131 select GENERIC_IRQ_IPI 132 select GENERIC_IRQ_PROBE 133 select GENERIC_IRQ_SHOW 134 select GENERIC_IRQ_SHOW_LEVEL 135 select GENERIC_LIB_DEVMEM_IS_ALLOWED 136 select GENERIC_PCI_IOMAP 137 select GENERIC_PTDUMP 138 select GENERIC_SCHED_CLOCK 139 select GENERIC_SMP_IDLE_THREAD 140 select GENERIC_TIME_VSYSCALL 141 select GENERIC_GETTIMEOFDAY 142 select GENERIC_VDSO_TIME_NS 143 select HARDIRQS_SW_RESEND 144 select HAVE_MOVE_PMD 145 select HAVE_MOVE_PUD 146 select HAVE_PCI 147 select HAVE_ACPI_APEI if (ACPI && EFI) 148 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 149 select HAVE_ARCH_AUDITSYSCALL 150 select HAVE_ARCH_BITREVERSE 151 select HAVE_ARCH_COMPILER_H 152 select HAVE_ARCH_HUGE_VMALLOC 153 select HAVE_ARCH_HUGE_VMAP 154 select HAVE_ARCH_JUMP_LABEL 155 select HAVE_ARCH_JUMP_LABEL_RELATIVE 156 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 157 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 158 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 159 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 160 # Some instrumentation may be unsound, hence EXPERT 161 select HAVE_ARCH_KCSAN if EXPERT 162 select HAVE_ARCH_KFENCE 163 select HAVE_ARCH_KGDB 164 select HAVE_ARCH_MMAP_RND_BITS 165 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 166 select HAVE_ARCH_PREL32_RELOCATIONS 167 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 168 select HAVE_ARCH_SECCOMP_FILTER 169 select HAVE_ARCH_STACKLEAK 170 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 171 select HAVE_ARCH_TRACEHOOK 172 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 173 select HAVE_ARCH_VMAP_STACK 174 select HAVE_ARM_SMCCC 175 select HAVE_ASM_MODVERSIONS 176 select HAVE_EBPF_JIT 177 select HAVE_C_RECORDMCOUNT 178 select HAVE_CMPXCHG_DOUBLE 179 select HAVE_CMPXCHG_LOCAL 180 select HAVE_CONTEXT_TRACKING_USER 181 select HAVE_DEBUG_KMEMLEAK 182 select HAVE_DMA_CONTIGUOUS 183 select HAVE_DYNAMIC_FTRACE 184 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 185 if DYNAMIC_FTRACE_WITH_REGS 186 select HAVE_EFFICIENT_UNALIGNED_ACCESS 187 select HAVE_FAST_GUP 188 select HAVE_FTRACE_MCOUNT_RECORD 189 select HAVE_FUNCTION_TRACER 190 select HAVE_FUNCTION_ERROR_INJECTION 191 select HAVE_FUNCTION_GRAPH_TRACER 192 select HAVE_GCC_PLUGINS 193 select HAVE_HW_BREAKPOINT if PERF_EVENTS 194 select HAVE_IOREMAP_PROT 195 select HAVE_IRQ_TIME_ACCOUNTING 196 select HAVE_KVM 197 select HAVE_NMI 198 select HAVE_PERF_EVENTS 199 select HAVE_PERF_REGS 200 select HAVE_PERF_USER_STACK_DUMP 201 select HAVE_PREEMPT_DYNAMIC_KEY 202 select HAVE_REGS_AND_STACK_ACCESS_API 203 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 204 select HAVE_FUNCTION_ARG_ACCESS_API 205 select MMU_GATHER_RCU_TABLE_FREE 206 select HAVE_RSEQ 207 select HAVE_STACKPROTECTOR 208 select HAVE_SYSCALL_TRACEPOINTS 209 select HAVE_KPROBES 210 select HAVE_KRETPROBES 211 select HAVE_GENERIC_VDSO 212 select IRQ_DOMAIN 213 select IRQ_FORCED_THREADING 214 select KASAN_VMALLOC if KASAN 215 select MODULES_USE_ELF_RELA 216 select NEED_DMA_MAP_STATE 217 select NEED_SG_DMA_LENGTH 218 select OF 219 select OF_EARLY_FLATTREE 220 select PCI_DOMAINS_GENERIC if PCI 221 select PCI_ECAM if (ACPI && PCI) 222 select PCI_SYSCALL if PCI 223 select POWER_RESET 224 select POWER_SUPPLY 225 select SPARSE_IRQ 226 select SWIOTLB 227 select SYSCTL_EXCEPTION_TRACE 228 select THREAD_INFO_IN_TASK 229 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 230 select TRACE_IRQFLAGS_SUPPORT 231 select TRACE_IRQFLAGS_NMI_SUPPORT 232 select HAVE_SOFTIRQ_ON_OWN_STACK 233 help 234 ARM 64-bit (AArch64) Linux support. 235 236config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 237 def_bool CC_IS_CLANG 238 # https://github.com/ClangBuiltLinux/linux/issues/1507 239 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 240 select HAVE_DYNAMIC_FTRACE_WITH_REGS 241 242config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 243 def_bool CC_IS_GCC 244 depends on $(cc-option,-fpatchable-function-entry=2) 245 select HAVE_DYNAMIC_FTRACE_WITH_REGS 246 247config 64BIT 248 def_bool y 249 250config MMU 251 def_bool y 252 253config ARM64_PAGE_SHIFT 254 int 255 default 16 if ARM64_64K_PAGES 256 default 14 if ARM64_16K_PAGES 257 default 12 258 259config ARM64_CONT_PTE_SHIFT 260 int 261 default 5 if ARM64_64K_PAGES 262 default 7 if ARM64_16K_PAGES 263 default 4 264 265config ARM64_CONT_PMD_SHIFT 266 int 267 default 5 if ARM64_64K_PAGES 268 default 5 if ARM64_16K_PAGES 269 default 4 270 271config ARCH_MMAP_RND_BITS_MIN 272 default 14 if ARM64_64K_PAGES 273 default 16 if ARM64_16K_PAGES 274 default 18 275 276# max bits determined by the following formula: 277# VA_BITS - PAGE_SHIFT - 3 278config ARCH_MMAP_RND_BITS_MAX 279 default 19 if ARM64_VA_BITS=36 280 default 24 if ARM64_VA_BITS=39 281 default 27 if ARM64_VA_BITS=42 282 default 30 if ARM64_VA_BITS=47 283 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 284 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 285 default 33 if ARM64_VA_BITS=48 286 default 14 if ARM64_64K_PAGES 287 default 16 if ARM64_16K_PAGES 288 default 18 289 290config ARCH_MMAP_RND_COMPAT_BITS_MIN 291 default 7 if ARM64_64K_PAGES 292 default 9 if ARM64_16K_PAGES 293 default 11 294 295config ARCH_MMAP_RND_COMPAT_BITS_MAX 296 default 16 297 298config NO_IOPORT_MAP 299 def_bool y if !PCI 300 301config STACKTRACE_SUPPORT 302 def_bool y 303 304config ILLEGAL_POINTER_VALUE 305 hex 306 default 0xdead000000000000 307 308config LOCKDEP_SUPPORT 309 def_bool y 310 311config GENERIC_BUG 312 def_bool y 313 depends on BUG 314 315config GENERIC_BUG_RELATIVE_POINTERS 316 def_bool y 317 depends on GENERIC_BUG 318 319config GENERIC_HWEIGHT 320 def_bool y 321 322config GENERIC_CSUM 323 def_bool y 324 325config GENERIC_CALIBRATE_DELAY 326 def_bool y 327 328config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 329 def_bool y 330 331config SMP 332 def_bool y 333 334config KERNEL_MODE_NEON 335 def_bool y 336 337config FIX_EARLYCON_MEM 338 def_bool y 339 340config PGTABLE_LEVELS 341 int 342 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 343 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 344 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 345 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 346 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 347 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 348 349config ARCH_SUPPORTS_UPROBES 350 def_bool y 351 352config ARCH_PROC_KCORE_TEXT 353 def_bool y 354 355config BROKEN_GAS_INST 356 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 357 358config KASAN_SHADOW_OFFSET 359 hex 360 depends on KASAN_GENERIC || KASAN_SW_TAGS 361 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 362 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 363 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 364 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 365 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 366 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 367 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 368 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 369 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 370 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 371 default 0xffffffffffffffff 372 373config UNWIND_TABLES 374 bool 375 376source "arch/arm64/Kconfig.platforms" 377 378menu "Kernel Features" 379 380menu "ARM errata workarounds via the alternatives framework" 381 382config ARM64_WORKAROUND_CLEAN_CACHE 383 bool 384 385config ARM64_ERRATUM_826319 386 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 387 default y 388 select ARM64_WORKAROUND_CLEAN_CACHE 389 help 390 This option adds an alternative code sequence to work around ARM 391 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 392 AXI master interface and an L2 cache. 393 394 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 395 and is unable to accept a certain write via this interface, it will 396 not progress on read data presented on the read data channel and the 397 system can deadlock. 398 399 The workaround promotes data cache clean instructions to 400 data cache clean-and-invalidate. 401 Please note that this does not necessarily enable the workaround, 402 as it depends on the alternative framework, which will only patch 403 the kernel if an affected CPU is detected. 404 405 If unsure, say Y. 406 407config ARM64_ERRATUM_827319 408 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 409 default y 410 select ARM64_WORKAROUND_CLEAN_CACHE 411 help 412 This option adds an alternative code sequence to work around ARM 413 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 414 master interface and an L2 cache. 415 416 Under certain conditions this erratum can cause a clean line eviction 417 to occur at the same time as another transaction to the same address 418 on the AMBA 5 CHI interface, which can cause data corruption if the 419 interconnect reorders the two transactions. 420 421 The workaround promotes data cache clean instructions to 422 data cache clean-and-invalidate. 423 Please note that this does not necessarily enable the workaround, 424 as it depends on the alternative framework, which will only patch 425 the kernel if an affected CPU is detected. 426 427 If unsure, say Y. 428 429config ARM64_ERRATUM_824069 430 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 431 default y 432 select ARM64_WORKAROUND_CLEAN_CACHE 433 help 434 This option adds an alternative code sequence to work around ARM 435 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 436 to a coherent interconnect. 437 438 If a Cortex-A53 processor is executing a store or prefetch for 439 write instruction at the same time as a processor in another 440 cluster is executing a cache maintenance operation to the same 441 address, then this erratum might cause a clean cache line to be 442 incorrectly marked as dirty. 443 444 The workaround promotes data cache clean instructions to 445 data cache clean-and-invalidate. 446 Please note that this option does not necessarily enable the 447 workaround, as it depends on the alternative framework, which will 448 only patch the kernel if an affected CPU is detected. 449 450 If unsure, say Y. 451 452config ARM64_ERRATUM_819472 453 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 454 default y 455 select ARM64_WORKAROUND_CLEAN_CACHE 456 help 457 This option adds an alternative code sequence to work around ARM 458 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 459 present when it is connected to a coherent interconnect. 460 461 If the processor is executing a load and store exclusive sequence at 462 the same time as a processor in another cluster is executing a cache 463 maintenance operation to the same address, then this erratum might 464 cause data corruption. 465 466 The workaround promotes data cache clean instructions to 467 data cache clean-and-invalidate. 468 Please note that this does not necessarily enable the workaround, 469 as it depends on the alternative framework, which will only patch 470 the kernel if an affected CPU is detected. 471 472 If unsure, say Y. 473 474config ARM64_ERRATUM_832075 475 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 476 default y 477 help 478 This option adds an alternative code sequence to work around ARM 479 erratum 832075 on Cortex-A57 parts up to r1p2. 480 481 Affected Cortex-A57 parts might deadlock when exclusive load/store 482 instructions to Write-Back memory are mixed with Device loads. 483 484 The workaround is to promote device loads to use Load-Acquire 485 semantics. 486 Please note that this does not necessarily enable the workaround, 487 as it depends on the alternative framework, which will only patch 488 the kernel if an affected CPU is detected. 489 490 If unsure, say Y. 491 492config ARM64_ERRATUM_834220 493 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 494 depends on KVM 495 default y 496 help 497 This option adds an alternative code sequence to work around ARM 498 erratum 834220 on Cortex-A57 parts up to r1p2. 499 500 Affected Cortex-A57 parts might report a Stage 2 translation 501 fault as the result of a Stage 1 fault for load crossing a 502 page boundary when there is a permission or device memory 503 alignment fault at Stage 1 and a translation fault at Stage 2. 504 505 The workaround is to verify that the Stage 1 translation 506 doesn't generate a fault before handling the Stage 2 fault. 507 Please note that this does not necessarily enable the workaround, 508 as it depends on the alternative framework, which will only patch 509 the kernel if an affected CPU is detected. 510 511 If unsure, say Y. 512 513config ARM64_ERRATUM_1742098 514 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 515 depends on COMPAT 516 default y 517 help 518 This option removes the AES hwcap for aarch32 user-space to 519 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 520 521 Affected parts may corrupt the AES state if an interrupt is 522 taken between a pair of AES instructions. These instructions 523 are only present if the cryptography extensions are present. 524 All software should have a fallback implementation for CPUs 525 that don't implement the cryptography extensions. 526 527 If unsure, say Y. 528 529config ARM64_ERRATUM_845719 530 bool "Cortex-A53: 845719: a load might read incorrect data" 531 depends on COMPAT 532 default y 533 help 534 This option adds an alternative code sequence to work around ARM 535 erratum 845719 on Cortex-A53 parts up to r0p4. 536 537 When running a compat (AArch32) userspace on an affected Cortex-A53 538 part, a load at EL0 from a virtual address that matches the bottom 32 539 bits of the virtual address used by a recent load at (AArch64) EL1 540 might return incorrect data. 541 542 The workaround is to write the contextidr_el1 register on exception 543 return to a 32-bit task. 544 Please note that this does not necessarily enable the workaround, 545 as it depends on the alternative framework, which will only patch 546 the kernel if an affected CPU is detected. 547 548 If unsure, say Y. 549 550config ARM64_ERRATUM_843419 551 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 552 default y 553 select ARM64_MODULE_PLTS if MODULES 554 help 555 This option links the kernel with '--fix-cortex-a53-843419' and 556 enables PLT support to replace certain ADRP instructions, which can 557 cause subsequent memory accesses to use an incorrect address on 558 Cortex-A53 parts up to r0p4. 559 560 If unsure, say Y. 561 562config ARM64_LD_HAS_FIX_ERRATUM_843419 563 def_bool $(ld-option,--fix-cortex-a53-843419) 564 565config ARM64_ERRATUM_1024718 566 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 567 default y 568 help 569 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 570 571 Affected Cortex-A55 cores (all revisions) could cause incorrect 572 update of the hardware dirty bit when the DBM/AP bits are updated 573 without a break-before-make. The workaround is to disable the usage 574 of hardware DBM locally on the affected cores. CPUs not affected by 575 this erratum will continue to use the feature. 576 577 If unsure, say Y. 578 579config ARM64_ERRATUM_1418040 580 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 581 default y 582 depends on COMPAT 583 help 584 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 585 errata 1188873 and 1418040. 586 587 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 588 cause register corruption when accessing the timer registers 589 from AArch32 userspace. 590 591 If unsure, say Y. 592 593config ARM64_WORKAROUND_SPECULATIVE_AT 594 bool 595 596config ARM64_ERRATUM_1165522 597 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 598 default y 599 select ARM64_WORKAROUND_SPECULATIVE_AT 600 help 601 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 602 603 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 604 corrupted TLBs by speculating an AT instruction during a guest 605 context switch. 606 607 If unsure, say Y. 608 609config ARM64_ERRATUM_1319367 610 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 611 default y 612 select ARM64_WORKAROUND_SPECULATIVE_AT 613 help 614 This option adds work arounds for ARM Cortex-A57 erratum 1319537 615 and A72 erratum 1319367 616 617 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 618 speculating an AT instruction during a guest context switch. 619 620 If unsure, say Y. 621 622config ARM64_ERRATUM_1530923 623 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 624 default y 625 select ARM64_WORKAROUND_SPECULATIVE_AT 626 help 627 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 628 629 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 630 corrupted TLBs by speculating an AT instruction during a guest 631 context switch. 632 633 If unsure, say Y. 634 635config ARM64_WORKAROUND_REPEAT_TLBI 636 bool 637 638config ARM64_ERRATUM_2441007 639 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 640 default y 641 select ARM64_WORKAROUND_REPEAT_TLBI 642 help 643 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 644 645 Under very rare circumstances, affected Cortex-A55 CPUs 646 may not handle a race between a break-before-make sequence on one 647 CPU, and another CPU accessing the same page. This could allow a 648 store to a page that has been unmapped. 649 650 Work around this by adding the affected CPUs to the list that needs 651 TLB sequences to be done twice. 652 653 If unsure, say Y. 654 655config ARM64_ERRATUM_1286807 656 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 657 default y 658 select ARM64_WORKAROUND_REPEAT_TLBI 659 help 660 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 661 662 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 663 address for a cacheable mapping of a location is being 664 accessed by a core while another core is remapping the virtual 665 address to a new physical page using the recommended 666 break-before-make sequence, then under very rare circumstances 667 TLBI+DSB completes before a read using the translation being 668 invalidated has been observed by other observers. The 669 workaround repeats the TLBI+DSB operation. 670 671config ARM64_ERRATUM_1463225 672 bool "Cortex-A76: Software Step might prevent interrupt recognition" 673 default y 674 help 675 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 676 677 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 678 of a system call instruction (SVC) can prevent recognition of 679 subsequent interrupts when software stepping is disabled in the 680 exception handler of the system call and either kernel debugging 681 is enabled or VHE is in use. 682 683 Work around the erratum by triggering a dummy step exception 684 when handling a system call from a task that is being stepped 685 in a VHE configuration of the kernel. 686 687 If unsure, say Y. 688 689config ARM64_ERRATUM_1542419 690 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 691 default y 692 help 693 This option adds a workaround for ARM Neoverse-N1 erratum 694 1542419. 695 696 Affected Neoverse-N1 cores could execute a stale instruction when 697 modified by another CPU. The workaround depends on a firmware 698 counterpart. 699 700 Workaround the issue by hiding the DIC feature from EL0. This 701 forces user-space to perform cache maintenance. 702 703 If unsure, say Y. 704 705config ARM64_ERRATUM_1508412 706 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 707 default y 708 help 709 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 710 711 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 712 of a store-exclusive or read of PAR_EL1 and a load with device or 713 non-cacheable memory attributes. The workaround depends on a firmware 714 counterpart. 715 716 KVM guests must also have the workaround implemented or they can 717 deadlock the system. 718 719 Work around the issue by inserting DMB SY barriers around PAR_EL1 720 register reads and warning KVM users. The DMB barrier is sufficient 721 to prevent a speculative PAR_EL1 read. 722 723 If unsure, say Y. 724 725config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 726 bool 727 728config ARM64_ERRATUM_2051678 729 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 730 default y 731 help 732 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 733 Affected Cortex-A510 might not respect the ordering rules for 734 hardware update of the page table's dirty bit. The workaround 735 is to not enable the feature on affected CPUs. 736 737 If unsure, say Y. 738 739config ARM64_ERRATUM_2077057 740 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 741 default y 742 help 743 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 744 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 745 expected, but a Pointer Authentication trap is taken instead. The 746 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 747 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 748 749 This can only happen when EL2 is stepping EL1. 750 751 When these conditions occur, the SPSR_EL2 value is unchanged from the 752 previous guest entry, and can be restored from the in-memory copy. 753 754 If unsure, say Y. 755 756config ARM64_ERRATUM_2658417 757 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 758 default y 759 help 760 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 761 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 762 BFMMLA or VMMLA instructions in rare circumstances when a pair of 763 A510 CPUs are using shared neon hardware. As the sharing is not 764 discoverable by the kernel, hide the BF16 HWCAP to indicate that 765 user-space should not be using these instructions. 766 767 If unsure, say Y. 768 769config ARM64_ERRATUM_2119858 770 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 771 default y 772 depends on CORESIGHT_TRBE 773 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 774 help 775 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 776 777 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 778 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 779 the event of a WRAP event. 780 781 Work around the issue by always making sure we move the TRBPTR_EL1 by 782 256 bytes before enabling the buffer and filling the first 256 bytes of 783 the buffer with ETM ignore packets upon disabling. 784 785 If unsure, say Y. 786 787config ARM64_ERRATUM_2139208 788 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 789 default y 790 depends on CORESIGHT_TRBE 791 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 792 help 793 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 794 795 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 796 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 797 the event of a WRAP event. 798 799 Work around the issue by always making sure we move the TRBPTR_EL1 by 800 256 bytes before enabling the buffer and filling the first 256 bytes of 801 the buffer with ETM ignore packets upon disabling. 802 803 If unsure, say Y. 804 805config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 806 bool 807 808config ARM64_ERRATUM_2054223 809 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 810 default y 811 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 812 help 813 Enable workaround for ARM Cortex-A710 erratum 2054223 814 815 Affected cores may fail to flush the trace data on a TSB instruction, when 816 the PE is in trace prohibited state. This will cause losing a few bytes 817 of the trace cached. 818 819 Workaround is to issue two TSB consecutively on affected cores. 820 821 If unsure, say Y. 822 823config ARM64_ERRATUM_2067961 824 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 825 default y 826 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 827 help 828 Enable workaround for ARM Neoverse-N2 erratum 2067961 829 830 Affected cores may fail to flush the trace data on a TSB instruction, when 831 the PE is in trace prohibited state. This will cause losing a few bytes 832 of the trace cached. 833 834 Workaround is to issue two TSB consecutively on affected cores. 835 836 If unsure, say Y. 837 838config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 839 bool 840 841config ARM64_ERRATUM_2253138 842 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 843 depends on CORESIGHT_TRBE 844 default y 845 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 846 help 847 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 848 849 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 850 for TRBE. Under some conditions, the TRBE might generate a write to the next 851 virtually addressed page following the last page of the TRBE address space 852 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 853 854 Work around this in the driver by always making sure that there is a 855 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 856 857 If unsure, say Y. 858 859config ARM64_ERRATUM_2224489 860 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 861 depends on CORESIGHT_TRBE 862 default y 863 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 864 help 865 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 866 867 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 868 for TRBE. Under some conditions, the TRBE might generate a write to the next 869 virtually addressed page following the last page of the TRBE address space 870 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 871 872 Work around this in the driver by always making sure that there is a 873 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 874 875 If unsure, say Y. 876 877config ARM64_ERRATUM_2441009 878 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 879 default y 880 select ARM64_WORKAROUND_REPEAT_TLBI 881 help 882 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 883 884 Under very rare circumstances, affected Cortex-A510 CPUs 885 may not handle a race between a break-before-make sequence on one 886 CPU, and another CPU accessing the same page. This could allow a 887 store to a page that has been unmapped. 888 889 Work around this by adding the affected CPUs to the list that needs 890 TLB sequences to be done twice. 891 892 If unsure, say Y. 893 894config ARM64_ERRATUM_2064142 895 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 896 depends on CORESIGHT_TRBE 897 default y 898 help 899 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 900 901 Affected Cortex-A510 core might fail to write into system registers after the 902 TRBE has been disabled. Under some conditions after the TRBE has been disabled 903 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 904 and TRBTRG_EL1 will be ignored and will not be effected. 905 906 Work around this in the driver by executing TSB CSYNC and DSB after collection 907 is stopped and before performing a system register write to one of the affected 908 registers. 909 910 If unsure, say Y. 911 912config ARM64_ERRATUM_2038923 913 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 914 depends on CORESIGHT_TRBE 915 default y 916 help 917 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 918 919 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 920 prohibited within the CPU. As a result, the trace buffer or trace buffer state 921 might be corrupted. This happens after TRBE buffer has been enabled by setting 922 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 923 execution changes from a context, in which trace is prohibited to one where it 924 isn't, or vice versa. In these mentioned conditions, the view of whether trace 925 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 926 the trace buffer state might be corrupted. 927 928 Work around this in the driver by preventing an inconsistent view of whether the 929 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 930 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 931 two ISB instructions if no ERET is to take place. 932 933 If unsure, say Y. 934 935config ARM64_ERRATUM_1902691 936 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 937 depends on CORESIGHT_TRBE 938 default y 939 help 940 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 941 942 Affected Cortex-A510 core might cause trace data corruption, when being written 943 into the memory. Effectively TRBE is broken and hence cannot be used to capture 944 trace data. 945 946 Work around this problem in the driver by just preventing TRBE initialization on 947 affected cpus. The firmware must have disabled the access to TRBE for the kernel 948 on such implementations. This will cover the kernel for any firmware that doesn't 949 do this already. 950 951 If unsure, say Y. 952 953config ARM64_ERRATUM_2457168 954 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 955 depends on ARM64_AMU_EXTN 956 default y 957 help 958 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 959 960 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 961 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 962 incorrectly giving a significantly higher output value. 963 964 Work around this problem by returning 0 when reading the affected counter in 965 key locations that results in disabling all users of this counter. This effect 966 is the same to firmware disabling affected counters. 967 968 If unsure, say Y. 969 970config CAVIUM_ERRATUM_22375 971 bool "Cavium erratum 22375, 24313" 972 default y 973 help 974 Enable workaround for errata 22375 and 24313. 975 976 This implements two gicv3-its errata workarounds for ThunderX. Both 977 with a small impact affecting only ITS table allocation. 978 979 erratum 22375: only alloc 8MB table size 980 erratum 24313: ignore memory access type 981 982 The fixes are in ITS initialization and basically ignore memory access 983 type and table size provided by the TYPER and BASER registers. 984 985 If unsure, say Y. 986 987config CAVIUM_ERRATUM_23144 988 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 989 depends on NUMA 990 default y 991 help 992 ITS SYNC command hang for cross node io and collections/cpu mapping. 993 994 If unsure, say Y. 995 996config CAVIUM_ERRATUM_23154 997 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 998 default y 999 help 1000 The ThunderX GICv3 implementation requires a modified version for 1001 reading the IAR status to ensure data synchronization 1002 (access to icc_iar1_el1 is not sync'ed before and after). 1003 1004 It also suffers from erratum 38545 (also present on Marvell's 1005 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1006 spuriously presented to the CPU interface. 1007 1008 If unsure, say Y. 1009 1010config CAVIUM_ERRATUM_27456 1011 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1012 default y 1013 help 1014 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1015 instructions may cause the icache to become corrupted if it 1016 contains data for a non-current ASID. The fix is to 1017 invalidate the icache when changing the mm context. 1018 1019 If unsure, say Y. 1020 1021config CAVIUM_ERRATUM_30115 1022 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1023 default y 1024 help 1025 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1026 1.2, and T83 Pass 1.0, KVM guest execution may disable 1027 interrupts in host. Trapping both GICv3 group-0 and group-1 1028 accesses sidesteps the issue. 1029 1030 If unsure, say Y. 1031 1032config CAVIUM_TX2_ERRATUM_219 1033 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1034 default y 1035 help 1036 On Cavium ThunderX2, a load, store or prefetch instruction between a 1037 TTBR update and the corresponding context synchronizing operation can 1038 cause a spurious Data Abort to be delivered to any hardware thread in 1039 the CPU core. 1040 1041 Work around the issue by avoiding the problematic code sequence and 1042 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1043 trap handler performs the corresponding register access, skips the 1044 instruction and ensures context synchronization by virtue of the 1045 exception return. 1046 1047 If unsure, say Y. 1048 1049config FUJITSU_ERRATUM_010001 1050 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1051 default y 1052 help 1053 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1054 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1055 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1056 This fault occurs under a specific hardware condition when a 1057 load/store instruction performs an address translation using: 1058 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1059 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1060 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1061 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1062 1063 The workaround is to ensure these bits are clear in TCR_ELx. 1064 The workaround only affects the Fujitsu-A64FX. 1065 1066 If unsure, say Y. 1067 1068config HISILICON_ERRATUM_161600802 1069 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1070 default y 1071 help 1072 The HiSilicon Hip07 SoC uses the wrong redistributor base 1073 when issued ITS commands such as VMOVP and VMAPP, and requires 1074 a 128kB offset to be applied to the target address in this commands. 1075 1076 If unsure, say Y. 1077 1078config QCOM_FALKOR_ERRATUM_1003 1079 bool "Falkor E1003: Incorrect translation due to ASID change" 1080 default y 1081 help 1082 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1083 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1084 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1085 then only for entries in the walk cache, since the leaf translation 1086 is unchanged. Work around the erratum by invalidating the walk cache 1087 entries for the trampoline before entering the kernel proper. 1088 1089config QCOM_FALKOR_ERRATUM_1009 1090 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1091 default y 1092 select ARM64_WORKAROUND_REPEAT_TLBI 1093 help 1094 On Falkor v1, the CPU may prematurely complete a DSB following a 1095 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1096 one more time to fix the issue. 1097 1098 If unsure, say Y. 1099 1100config QCOM_QDF2400_ERRATUM_0065 1101 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1102 default y 1103 help 1104 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1105 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1106 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1107 1108 If unsure, say Y. 1109 1110config QCOM_FALKOR_ERRATUM_E1041 1111 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1112 default y 1113 help 1114 Falkor CPU may speculatively fetch instructions from an improper 1115 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1116 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1117 1118 If unsure, say Y. 1119 1120config NVIDIA_CARMEL_CNP_ERRATUM 1121 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1122 default y 1123 help 1124 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1125 invalidate shared TLB entries installed by a different core, as it would 1126 on standard ARM cores. 1127 1128 If unsure, say Y. 1129 1130config SOCIONEXT_SYNQUACER_PREITS 1131 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1132 default y 1133 help 1134 Socionext Synquacer SoCs implement a separate h/w block to generate 1135 MSI doorbell writes with non-zero values for the device ID. 1136 1137 If unsure, say Y. 1138 1139endmenu # "ARM errata workarounds via the alternatives framework" 1140 1141choice 1142 prompt "Page size" 1143 default ARM64_4K_PAGES 1144 help 1145 Page size (translation granule) configuration. 1146 1147config ARM64_4K_PAGES 1148 bool "4KB" 1149 help 1150 This feature enables 4KB pages support. 1151 1152config ARM64_16K_PAGES 1153 bool "16KB" 1154 help 1155 The system will use 16KB pages support. AArch32 emulation 1156 requires applications compiled with 16K (or a multiple of 16K) 1157 aligned segments. 1158 1159config ARM64_64K_PAGES 1160 bool "64KB" 1161 help 1162 This feature enables 64KB pages support (4KB by default) 1163 allowing only two levels of page tables and faster TLB 1164 look-up. AArch32 emulation requires applications compiled 1165 with 64K aligned segments. 1166 1167endchoice 1168 1169choice 1170 prompt "Virtual address space size" 1171 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1172 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1173 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1174 help 1175 Allows choosing one of multiple possible virtual address 1176 space sizes. The level of translation table is determined by 1177 a combination of page size and virtual address space size. 1178 1179config ARM64_VA_BITS_36 1180 bool "36-bit" if EXPERT 1181 depends on ARM64_16K_PAGES 1182 1183config ARM64_VA_BITS_39 1184 bool "39-bit" 1185 depends on ARM64_4K_PAGES 1186 1187config ARM64_VA_BITS_42 1188 bool "42-bit" 1189 depends on ARM64_64K_PAGES 1190 1191config ARM64_VA_BITS_47 1192 bool "47-bit" 1193 depends on ARM64_16K_PAGES 1194 1195config ARM64_VA_BITS_48 1196 bool "48-bit" 1197 1198config ARM64_VA_BITS_52 1199 bool "52-bit" 1200 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1201 help 1202 Enable 52-bit virtual addressing for userspace when explicitly 1203 requested via a hint to mmap(). The kernel will also use 52-bit 1204 virtual addresses for its own mappings (provided HW support for 1205 this feature is available, otherwise it reverts to 48-bit). 1206 1207 NOTE: Enabling 52-bit virtual addressing in conjunction with 1208 ARMv8.3 Pointer Authentication will result in the PAC being 1209 reduced from 7 bits to 3 bits, which may have a significant 1210 impact on its susceptibility to brute-force attacks. 1211 1212 If unsure, select 48-bit virtual addressing instead. 1213 1214endchoice 1215 1216config ARM64_FORCE_52BIT 1217 bool "Force 52-bit virtual addresses for userspace" 1218 depends on ARM64_VA_BITS_52 && EXPERT 1219 help 1220 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1221 to maintain compatibility with older software by providing 48-bit VAs 1222 unless a hint is supplied to mmap. 1223 1224 This configuration option disables the 48-bit compatibility logic, and 1225 forces all userspace addresses to be 52-bit on HW that supports it. One 1226 should only enable this configuration option for stress testing userspace 1227 memory management code. If unsure say N here. 1228 1229config ARM64_VA_BITS 1230 int 1231 default 36 if ARM64_VA_BITS_36 1232 default 39 if ARM64_VA_BITS_39 1233 default 42 if ARM64_VA_BITS_42 1234 default 47 if ARM64_VA_BITS_47 1235 default 48 if ARM64_VA_BITS_48 1236 default 52 if ARM64_VA_BITS_52 1237 1238choice 1239 prompt "Physical address space size" 1240 default ARM64_PA_BITS_48 1241 help 1242 Choose the maximum physical address range that the kernel will 1243 support. 1244 1245config ARM64_PA_BITS_48 1246 bool "48-bit" 1247 1248config ARM64_PA_BITS_52 1249 bool "52-bit (ARMv8.2)" 1250 depends on ARM64_64K_PAGES 1251 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1252 help 1253 Enable support for a 52-bit physical address space, introduced as 1254 part of the ARMv8.2-LPA extension. 1255 1256 With this enabled, the kernel will also continue to work on CPUs that 1257 do not support ARMv8.2-LPA, but with some added memory overhead (and 1258 minor performance overhead). 1259 1260endchoice 1261 1262config ARM64_PA_BITS 1263 int 1264 default 48 if ARM64_PA_BITS_48 1265 default 52 if ARM64_PA_BITS_52 1266 1267choice 1268 prompt "Endianness" 1269 default CPU_LITTLE_ENDIAN 1270 help 1271 Select the endianness of data accesses performed by the CPU. Userspace 1272 applications will need to be compiled and linked for the endianness 1273 that is selected here. 1274 1275config CPU_BIG_ENDIAN 1276 bool "Build big-endian kernel" 1277 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1278 help 1279 Say Y if you plan on running a kernel with a big-endian userspace. 1280 1281config CPU_LITTLE_ENDIAN 1282 bool "Build little-endian kernel" 1283 help 1284 Say Y if you plan on running a kernel with a little-endian userspace. 1285 This is usually the case for distributions targeting arm64. 1286 1287endchoice 1288 1289config SCHED_MC 1290 bool "Multi-core scheduler support" 1291 help 1292 Multi-core scheduler support improves the CPU scheduler's decision 1293 making when dealing with multi-core CPU chips at a cost of slightly 1294 increased overhead in some places. If unsure say N here. 1295 1296config SCHED_CLUSTER 1297 bool "Cluster scheduler support" 1298 help 1299 Cluster scheduler support improves the CPU scheduler's decision 1300 making when dealing with machines that have clusters of CPUs. 1301 Cluster usually means a couple of CPUs which are placed closely 1302 by sharing mid-level caches, last-level cache tags or internal 1303 busses. 1304 1305config SCHED_SMT 1306 bool "SMT scheduler support" 1307 help 1308 Improves the CPU scheduler's decision making when dealing with 1309 MultiThreading at a cost of slightly increased overhead in some 1310 places. If unsure say N here. 1311 1312config NR_CPUS 1313 int "Maximum number of CPUs (2-4096)" 1314 range 2 4096 1315 default "256" 1316 1317config HOTPLUG_CPU 1318 bool "Support for hot-pluggable CPUs" 1319 select GENERIC_IRQ_MIGRATION 1320 help 1321 Say Y here to experiment with turning CPUs off and on. CPUs 1322 can be controlled through /sys/devices/system/cpu. 1323 1324# Common NUMA Features 1325config NUMA 1326 bool "NUMA Memory Allocation and Scheduler Support" 1327 select GENERIC_ARCH_NUMA 1328 select ACPI_NUMA if ACPI 1329 select OF_NUMA 1330 select HAVE_SETUP_PER_CPU_AREA 1331 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1332 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1333 select USE_PERCPU_NUMA_NODE_ID 1334 help 1335 Enable NUMA (Non-Uniform Memory Access) support. 1336 1337 The kernel will try to allocate memory used by a CPU on the 1338 local memory of the CPU and add some more 1339 NUMA awareness to the kernel. 1340 1341config NODES_SHIFT 1342 int "Maximum NUMA Nodes (as a power of 2)" 1343 range 1 10 1344 default "4" 1345 depends on NUMA 1346 help 1347 Specify the maximum number of NUMA Nodes available on the target 1348 system. Increases memory reserved to accommodate various tables. 1349 1350source "kernel/Kconfig.hz" 1351 1352config ARCH_SPARSEMEM_ENABLE 1353 def_bool y 1354 select SPARSEMEM_VMEMMAP_ENABLE 1355 select SPARSEMEM_VMEMMAP 1356 1357config HW_PERF_EVENTS 1358 def_bool y 1359 depends on ARM_PMU 1360 1361# Supported by clang >= 7.0 or GCC >= 12.0.0 1362config CC_HAVE_SHADOW_CALL_STACK 1363 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1364 1365config PARAVIRT 1366 bool "Enable paravirtualization code" 1367 help 1368 This changes the kernel so it can modify itself when it is run 1369 under a hypervisor, potentially improving performance significantly 1370 over full virtualization. 1371 1372config PARAVIRT_TIME_ACCOUNTING 1373 bool "Paravirtual steal time accounting" 1374 select PARAVIRT 1375 help 1376 Select this option to enable fine granularity task steal time 1377 accounting. Time spent executing other tasks in parallel with 1378 the current vCPU is discounted from the vCPU power. To account for 1379 that, there can be a small performance impact. 1380 1381 If in doubt, say N here. 1382 1383config KEXEC 1384 depends on PM_SLEEP_SMP 1385 select KEXEC_CORE 1386 bool "kexec system call" 1387 help 1388 kexec is a system call that implements the ability to shutdown your 1389 current kernel, and to start another kernel. It is like a reboot 1390 but it is independent of the system firmware. And like a reboot 1391 you can start any kernel with it, not just Linux. 1392 1393config KEXEC_FILE 1394 bool "kexec file based system call" 1395 select KEXEC_CORE 1396 select HAVE_IMA_KEXEC if IMA 1397 help 1398 This is new version of kexec system call. This system call is 1399 file based and takes file descriptors as system call argument 1400 for kernel and initramfs as opposed to list of segments as 1401 accepted by previous system call. 1402 1403config KEXEC_SIG 1404 bool "Verify kernel signature during kexec_file_load() syscall" 1405 depends on KEXEC_FILE 1406 help 1407 Select this option to verify a signature with loaded kernel 1408 image. If configured, any attempt of loading a image without 1409 valid signature will fail. 1410 1411 In addition to that option, you need to enable signature 1412 verification for the corresponding kernel image type being 1413 loaded in order for this to work. 1414 1415config KEXEC_IMAGE_VERIFY_SIG 1416 bool "Enable Image signature verification support" 1417 default y 1418 depends on KEXEC_SIG 1419 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1420 help 1421 Enable Image signature verification support. 1422 1423comment "Support for PE file signature verification disabled" 1424 depends on KEXEC_SIG 1425 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1426 1427config CRASH_DUMP 1428 bool "Build kdump crash kernel" 1429 help 1430 Generate crash dump after being started by kexec. This should 1431 be normally only set in special crash dump kernels which are 1432 loaded in the main kernel with kexec-tools into a specially 1433 reserved region and then later executed after a crash by 1434 kdump/kexec. 1435 1436 For more details see Documentation/admin-guide/kdump/kdump.rst 1437 1438config TRANS_TABLE 1439 def_bool y 1440 depends on HIBERNATION || KEXEC_CORE 1441 1442config XEN_DOM0 1443 def_bool y 1444 depends on XEN 1445 1446config XEN 1447 bool "Xen guest support on ARM64" 1448 depends on ARM64 && OF 1449 select SWIOTLB_XEN 1450 select PARAVIRT 1451 help 1452 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1453 1454config ARCH_FORCE_MAX_ORDER 1455 int 1456 default "14" if ARM64_64K_PAGES 1457 default "12" if ARM64_16K_PAGES 1458 default "11" 1459 help 1460 The kernel memory allocator divides physically contiguous memory 1461 blocks into "zones", where each zone is a power of two number of 1462 pages. This option selects the largest power of two that the kernel 1463 keeps in the memory allocator. If you need to allocate very large 1464 blocks of physically contiguous memory, then you may need to 1465 increase this value. 1466 1467 This config option is actually maximum order plus one. For example, 1468 a value of 11 means that the largest free memory block is 2^10 pages. 1469 1470 We make sure that we can allocate upto a HugePage size for each configuration. 1471 Hence we have : 1472 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1473 1474 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1475 4M allocations matching the default size used by generic code. 1476 1477config UNMAP_KERNEL_AT_EL0 1478 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1479 default y 1480 help 1481 Speculation attacks against some high-performance processors can 1482 be used to bypass MMU permission checks and leak kernel data to 1483 userspace. This can be defended against by unmapping the kernel 1484 when running in userspace, mapping it back in on exception entry 1485 via a trampoline page in the vector table. 1486 1487 If unsure, say Y. 1488 1489config MITIGATE_SPECTRE_BRANCH_HISTORY 1490 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1491 default y 1492 help 1493 Speculation attacks against some high-performance processors can 1494 make use of branch history to influence future speculation. 1495 When taking an exception from user-space, a sequence of branches 1496 or a firmware call overwrites the branch history. 1497 1498config RODATA_FULL_DEFAULT_ENABLED 1499 bool "Apply r/o permissions of VM areas also to their linear aliases" 1500 default y 1501 help 1502 Apply read-only attributes of VM areas to the linear alias of 1503 the backing pages as well. This prevents code or read-only data 1504 from being modified (inadvertently or intentionally) via another 1505 mapping of the same memory page. This additional enhancement can 1506 be turned off at runtime by passing rodata=[off|on] (and turned on 1507 with rodata=full if this option is set to 'n') 1508 1509 This requires the linear region to be mapped down to pages, 1510 which may adversely affect performance in some cases. 1511 1512config ARM64_SW_TTBR0_PAN 1513 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1514 help 1515 Enabling this option prevents the kernel from accessing 1516 user-space memory directly by pointing TTBR0_EL1 to a reserved 1517 zeroed area and reserved ASID. The user access routines 1518 restore the valid TTBR0_EL1 temporarily. 1519 1520config ARM64_TAGGED_ADDR_ABI 1521 bool "Enable the tagged user addresses syscall ABI" 1522 default y 1523 help 1524 When this option is enabled, user applications can opt in to a 1525 relaxed ABI via prctl() allowing tagged addresses to be passed 1526 to system calls as pointer arguments. For details, see 1527 Documentation/arm64/tagged-address-abi.rst. 1528 1529menuconfig COMPAT 1530 bool "Kernel support for 32-bit EL0" 1531 depends on ARM64_4K_PAGES || EXPERT 1532 select HAVE_UID16 1533 select OLD_SIGSUSPEND3 1534 select COMPAT_OLD_SIGACTION 1535 help 1536 This option enables support for a 32-bit EL0 running under a 64-bit 1537 kernel at EL1. AArch32-specific components such as system calls, 1538 the user helper functions, VFP support and the ptrace interface are 1539 handled appropriately by the kernel. 1540 1541 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1542 that you will only be able to execute AArch32 binaries that were compiled 1543 with page size aligned segments. 1544 1545 If you want to execute 32-bit userspace applications, say Y. 1546 1547if COMPAT 1548 1549config KUSER_HELPERS 1550 bool "Enable kuser helpers page for 32-bit applications" 1551 default y 1552 help 1553 Warning: disabling this option may break 32-bit user programs. 1554 1555 Provide kuser helpers to compat tasks. The kernel provides 1556 helper code to userspace in read only form at a fixed location 1557 to allow userspace to be independent of the CPU type fitted to 1558 the system. This permits binaries to be run on ARMv4 through 1559 to ARMv8 without modification. 1560 1561 See Documentation/arm/kernel_user_helpers.rst for details. 1562 1563 However, the fixed address nature of these helpers can be used 1564 by ROP (return orientated programming) authors when creating 1565 exploits. 1566 1567 If all of the binaries and libraries which run on your platform 1568 are built specifically for your platform, and make no use of 1569 these helpers, then you can turn this option off to hinder 1570 such exploits. However, in that case, if a binary or library 1571 relying on those helpers is run, it will not function correctly. 1572 1573 Say N here only if you are absolutely certain that you do not 1574 need these helpers; otherwise, the safe option is to say Y. 1575 1576config COMPAT_VDSO 1577 bool "Enable vDSO for 32-bit applications" 1578 depends on !CPU_BIG_ENDIAN 1579 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1580 select GENERIC_COMPAT_VDSO 1581 default y 1582 help 1583 Place in the process address space of 32-bit applications an 1584 ELF shared object providing fast implementations of gettimeofday 1585 and clock_gettime. 1586 1587 You must have a 32-bit build of glibc 2.22 or later for programs 1588 to seamlessly take advantage of this. 1589 1590config THUMB2_COMPAT_VDSO 1591 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1592 depends on COMPAT_VDSO 1593 default y 1594 help 1595 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1596 otherwise with '-marm'. 1597 1598config COMPAT_ALIGNMENT_FIXUPS 1599 bool "Fix up misaligned multi-word loads and stores in user space" 1600 1601menuconfig ARMV8_DEPRECATED 1602 bool "Emulate deprecated/obsolete ARMv8 instructions" 1603 depends on SYSCTL 1604 help 1605 Legacy software support may require certain instructions 1606 that have been deprecated or obsoleted in the architecture. 1607 1608 Enable this config to enable selective emulation of these 1609 features. 1610 1611 If unsure, say Y 1612 1613if ARMV8_DEPRECATED 1614 1615config SWP_EMULATION 1616 bool "Emulate SWP/SWPB instructions" 1617 help 1618 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1619 they are always undefined. Say Y here to enable software 1620 emulation of these instructions for userspace using LDXR/STXR. 1621 This feature can be controlled at runtime with the abi.swp 1622 sysctl which is disabled by default. 1623 1624 In some older versions of glibc [<=2.8] SWP is used during futex 1625 trylock() operations with the assumption that the code will not 1626 be preempted. This invalid assumption may be more likely to fail 1627 with SWP emulation enabled, leading to deadlock of the user 1628 application. 1629 1630 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1631 on an external transaction monitoring block called a global 1632 monitor to maintain update atomicity. If your system does not 1633 implement a global monitor, this option can cause programs that 1634 perform SWP operations to uncached memory to deadlock. 1635 1636 If unsure, say Y 1637 1638config CP15_BARRIER_EMULATION 1639 bool "Emulate CP15 Barrier instructions" 1640 help 1641 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1642 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1643 strongly recommended to use the ISB, DSB, and DMB 1644 instructions instead. 1645 1646 Say Y here to enable software emulation of these 1647 instructions for AArch32 userspace code. When this option is 1648 enabled, CP15 barrier usage is traced which can help 1649 identify software that needs updating. This feature can be 1650 controlled at runtime with the abi.cp15_barrier sysctl. 1651 1652 If unsure, say Y 1653 1654config SETEND_EMULATION 1655 bool "Emulate SETEND instruction" 1656 help 1657 The SETEND instruction alters the data-endianness of the 1658 AArch32 EL0, and is deprecated in ARMv8. 1659 1660 Say Y here to enable software emulation of the instruction 1661 for AArch32 userspace code. This feature can be controlled 1662 at runtime with the abi.setend sysctl. 1663 1664 Note: All the cpus on the system must have mixed endian support at EL0 1665 for this feature to be enabled. If a new CPU - which doesn't support mixed 1666 endian - is hotplugged in after this feature has been enabled, there could 1667 be unexpected results in the applications. 1668 1669 If unsure, say Y 1670endif # ARMV8_DEPRECATED 1671 1672endif # COMPAT 1673 1674menu "ARMv8.1 architectural features" 1675 1676config ARM64_HW_AFDBM 1677 bool "Support for hardware updates of the Access and Dirty page flags" 1678 default y 1679 help 1680 The ARMv8.1 architecture extensions introduce support for 1681 hardware updates of the access and dirty information in page 1682 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1683 capable processors, accesses to pages with PTE_AF cleared will 1684 set this bit instead of raising an access flag fault. 1685 Similarly, writes to read-only pages with the DBM bit set will 1686 clear the read-only bit (AP[2]) instead of raising a 1687 permission fault. 1688 1689 Kernels built with this configuration option enabled continue 1690 to work on pre-ARMv8.1 hardware and the performance impact is 1691 minimal. If unsure, say Y. 1692 1693config ARM64_PAN 1694 bool "Enable support for Privileged Access Never (PAN)" 1695 default y 1696 help 1697 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1698 prevents the kernel or hypervisor from accessing user-space (EL0) 1699 memory directly. 1700 1701 Choosing this option will cause any unprotected (not using 1702 copy_to_user et al) memory access to fail with a permission fault. 1703 1704 The feature is detected at runtime, and will remain as a 'nop' 1705 instruction if the cpu does not implement the feature. 1706 1707config AS_HAS_LDAPR 1708 def_bool $(as-instr,.arch_extension rcpc) 1709 1710config AS_HAS_LSE_ATOMICS 1711 def_bool $(as-instr,.arch_extension lse) 1712 1713config ARM64_LSE_ATOMICS 1714 bool 1715 default ARM64_USE_LSE_ATOMICS 1716 depends on AS_HAS_LSE_ATOMICS 1717 1718config ARM64_USE_LSE_ATOMICS 1719 bool "Atomic instructions" 1720 depends on JUMP_LABEL 1721 default y 1722 help 1723 As part of the Large System Extensions, ARMv8.1 introduces new 1724 atomic instructions that are designed specifically to scale in 1725 very large systems. 1726 1727 Say Y here to make use of these instructions for the in-kernel 1728 atomic routines. This incurs a small overhead on CPUs that do 1729 not support these instructions and requires the kernel to be 1730 built with binutils >= 2.25 in order for the new instructions 1731 to be used. 1732 1733endmenu # "ARMv8.1 architectural features" 1734 1735menu "ARMv8.2 architectural features" 1736 1737config AS_HAS_ARMV8_2 1738 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1739 1740config AS_HAS_SHA3 1741 def_bool $(as-instr,.arch armv8.2-a+sha3) 1742 1743config ARM64_PMEM 1744 bool "Enable support for persistent memory" 1745 select ARCH_HAS_PMEM_API 1746 select ARCH_HAS_UACCESS_FLUSHCACHE 1747 help 1748 Say Y to enable support for the persistent memory API based on the 1749 ARMv8.2 DCPoP feature. 1750 1751 The feature is detected at runtime, and the kernel will use DC CVAC 1752 operations if DC CVAP is not supported (following the behaviour of 1753 DC CVAP itself if the system does not define a point of persistence). 1754 1755config ARM64_RAS_EXTN 1756 bool "Enable support for RAS CPU Extensions" 1757 default y 1758 help 1759 CPUs that support the Reliability, Availability and Serviceability 1760 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1761 errors, classify them and report them to software. 1762 1763 On CPUs with these extensions system software can use additional 1764 barriers to determine if faults are pending and read the 1765 classification from a new set of registers. 1766 1767 Selecting this feature will allow the kernel to use these barriers 1768 and access the new registers if the system supports the extension. 1769 Platform RAS features may additionally depend on firmware support. 1770 1771config ARM64_CNP 1772 bool "Enable support for Common Not Private (CNP) translations" 1773 default y 1774 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1775 help 1776 Common Not Private (CNP) allows translation table entries to 1777 be shared between different PEs in the same inner shareable 1778 domain, so the hardware can use this fact to optimise the 1779 caching of such entries in the TLB. 1780 1781 Selecting this option allows the CNP feature to be detected 1782 at runtime, and does not affect PEs that do not implement 1783 this feature. 1784 1785endmenu # "ARMv8.2 architectural features" 1786 1787menu "ARMv8.3 architectural features" 1788 1789config ARM64_PTR_AUTH 1790 bool "Enable support for pointer authentication" 1791 default y 1792 help 1793 Pointer authentication (part of the ARMv8.3 Extensions) provides 1794 instructions for signing and authenticating pointers against secret 1795 keys, which can be used to mitigate Return Oriented Programming (ROP) 1796 and other attacks. 1797 1798 This option enables these instructions at EL0 (i.e. for userspace). 1799 Choosing this option will cause the kernel to initialise secret keys 1800 for each process at exec() time, with these keys being 1801 context-switched along with the process. 1802 1803 The feature is detected at runtime. If the feature is not present in 1804 hardware it will not be advertised to userspace/KVM guest nor will it 1805 be enabled. 1806 1807 If the feature is present on the boot CPU but not on a late CPU, then 1808 the late CPU will be parked. Also, if the boot CPU does not have 1809 address auth and the late CPU has then the late CPU will still boot 1810 but with the feature disabled. On such a system, this option should 1811 not be selected. 1812 1813config ARM64_PTR_AUTH_KERNEL 1814 bool "Use pointer authentication for kernel" 1815 default y 1816 depends on ARM64_PTR_AUTH 1817 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1818 # Modern compilers insert a .note.gnu.property section note for PAC 1819 # which is only understood by binutils starting with version 2.33.1. 1820 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1821 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1822 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1823 help 1824 If the compiler supports the -mbranch-protection or 1825 -msign-return-address flag (e.g. GCC 7 or later), then this option 1826 will cause the kernel itself to be compiled with return address 1827 protection. In this case, and if the target hardware is known to 1828 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1829 disabled with minimal loss of protection. 1830 1831 This feature works with FUNCTION_GRAPH_TRACER option only if 1832 DYNAMIC_FTRACE_WITH_REGS is enabled. 1833 1834config CC_HAS_BRANCH_PROT_PAC_RET 1835 # GCC 9 or later, clang 8 or later 1836 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1837 1838config CC_HAS_SIGN_RETURN_ADDRESS 1839 # GCC 7, 8 1840 def_bool $(cc-option,-msign-return-address=all) 1841 1842config AS_HAS_PAC 1843 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1844 1845config AS_HAS_CFI_NEGATE_RA_STATE 1846 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1847 1848endmenu # "ARMv8.3 architectural features" 1849 1850menu "ARMv8.4 architectural features" 1851 1852config ARM64_AMU_EXTN 1853 bool "Enable support for the Activity Monitors Unit CPU extension" 1854 default y 1855 help 1856 The activity monitors extension is an optional extension introduced 1857 by the ARMv8.4 CPU architecture. This enables support for version 1 1858 of the activity monitors architecture, AMUv1. 1859 1860 To enable the use of this extension on CPUs that implement it, say Y. 1861 1862 Note that for architectural reasons, firmware _must_ implement AMU 1863 support when running on CPUs that present the activity monitors 1864 extension. The required support is present in: 1865 * Version 1.5 and later of the ARM Trusted Firmware 1866 1867 For kernels that have this configuration enabled but boot with broken 1868 firmware, you may need to say N here until the firmware is fixed. 1869 Otherwise you may experience firmware panics or lockups when 1870 accessing the counter registers. Even if you are not observing these 1871 symptoms, the values returned by the register reads might not 1872 correctly reflect reality. Most commonly, the value read will be 0, 1873 indicating that the counter is not enabled. 1874 1875config AS_HAS_ARMV8_4 1876 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1877 1878config ARM64_TLB_RANGE 1879 bool "Enable support for tlbi range feature" 1880 default y 1881 depends on AS_HAS_ARMV8_4 1882 help 1883 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1884 range of input addresses. 1885 1886 The feature introduces new assembly instructions, and they were 1887 support when binutils >= 2.30. 1888 1889endmenu # "ARMv8.4 architectural features" 1890 1891menu "ARMv8.5 architectural features" 1892 1893config AS_HAS_ARMV8_5 1894 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1895 1896config ARM64_BTI 1897 bool "Branch Target Identification support" 1898 default y 1899 help 1900 Branch Target Identification (part of the ARMv8.5 Extensions) 1901 provides a mechanism to limit the set of locations to which computed 1902 branch instructions such as BR or BLR can jump. 1903 1904 To make use of BTI on CPUs that support it, say Y. 1905 1906 BTI is intended to provide complementary protection to other control 1907 flow integrity protection mechanisms, such as the Pointer 1908 authentication mechanism provided as part of the ARMv8.3 Extensions. 1909 For this reason, it does not make sense to enable this option without 1910 also enabling support for pointer authentication. Thus, when 1911 enabling this option you should also select ARM64_PTR_AUTH=y. 1912 1913 Userspace binaries must also be specifically compiled to make use of 1914 this mechanism. If you say N here or the hardware does not support 1915 BTI, such binaries can still run, but you get no additional 1916 enforcement of branch destinations. 1917 1918config ARM64_BTI_KERNEL 1919 bool "Use Branch Target Identification for kernel" 1920 default y 1921 depends on ARM64_BTI 1922 depends on ARM64_PTR_AUTH_KERNEL 1923 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1924 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1925 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1926 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 1927 depends on !CC_IS_GCC 1928 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1929 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1930 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1931 help 1932 Build the kernel with Branch Target Identification annotations 1933 and enable enforcement of this for kernel code. When this option 1934 is enabled and the system supports BTI all kernel code including 1935 modular code must have BTI enabled. 1936 1937config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1938 # GCC 9 or later, clang 8 or later 1939 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1940 1941config ARM64_E0PD 1942 bool "Enable support for E0PD" 1943 default y 1944 help 1945 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1946 that EL0 accesses made via TTBR1 always fault in constant time, 1947 providing similar benefits to KASLR as those provided by KPTI, but 1948 with lower overhead and without disrupting legitimate access to 1949 kernel memory such as SPE. 1950 1951 This option enables E0PD for TTBR1 where available. 1952 1953config ARM64_AS_HAS_MTE 1954 # Initial support for MTE went in binutils 2.32.0, checked with 1955 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1956 # as a late addition to the final architecture spec (LDGM/STGM) 1957 # is only supported in the newer 2.32.x and 2.33 binutils 1958 # versions, hence the extra "stgm" instruction check below. 1959 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1960 1961config ARM64_MTE 1962 bool "Memory Tagging Extension support" 1963 default y 1964 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1965 depends on AS_HAS_ARMV8_5 1966 depends on AS_HAS_LSE_ATOMICS 1967 # Required for tag checking in the uaccess routines 1968 depends on ARM64_PAN 1969 select ARCH_HAS_SUBPAGE_FAULTS 1970 select ARCH_USES_HIGH_VMA_FLAGS 1971 help 1972 Memory Tagging (part of the ARMv8.5 Extensions) provides 1973 architectural support for run-time, always-on detection of 1974 various classes of memory error to aid with software debugging 1975 to eliminate vulnerabilities arising from memory-unsafe 1976 languages. 1977 1978 This option enables the support for the Memory Tagging 1979 Extension at EL0 (i.e. for userspace). 1980 1981 Selecting this option allows the feature to be detected at 1982 runtime. Any secondary CPU not implementing this feature will 1983 not be allowed a late bring-up. 1984 1985 Userspace binaries that want to use this feature must 1986 explicitly opt in. The mechanism for the userspace is 1987 described in: 1988 1989 Documentation/arm64/memory-tagging-extension.rst. 1990 1991endmenu # "ARMv8.5 architectural features" 1992 1993menu "ARMv8.7 architectural features" 1994 1995config ARM64_EPAN 1996 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1997 default y 1998 depends on ARM64_PAN 1999 help 2000 Enhanced Privileged Access Never (EPAN) allows Privileged 2001 Access Never to be used with Execute-only mappings. 2002 2003 The feature is detected at runtime, and will remain disabled 2004 if the cpu does not implement the feature. 2005endmenu # "ARMv8.7 architectural features" 2006 2007config ARM64_SVE 2008 bool "ARM Scalable Vector Extension support" 2009 default y 2010 help 2011 The Scalable Vector Extension (SVE) is an extension to the AArch64 2012 execution state which complements and extends the SIMD functionality 2013 of the base architecture to support much larger vectors and to enable 2014 additional vectorisation opportunities. 2015 2016 To enable use of this extension on CPUs that implement it, say Y. 2017 2018 On CPUs that support the SVE2 extensions, this option will enable 2019 those too. 2020 2021 Note that for architectural reasons, firmware _must_ implement SVE 2022 support when running on SVE capable hardware. The required support 2023 is present in: 2024 2025 * version 1.5 and later of the ARM Trusted Firmware 2026 * the AArch64 boot wrapper since commit 5e1261e08abf 2027 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2028 2029 For other firmware implementations, consult the firmware documentation 2030 or vendor. 2031 2032 If you need the kernel to boot on SVE-capable hardware with broken 2033 firmware, you may need to say N here until you get your firmware 2034 fixed. Otherwise, you may experience firmware panics or lockups when 2035 booting the kernel. If unsure and you are not observing these 2036 symptoms, you should assume that it is safe to say Y. 2037 2038config ARM64_SME 2039 bool "ARM Scalable Matrix Extension support" 2040 default y 2041 depends on ARM64_SVE 2042 help 2043 The Scalable Matrix Extension (SME) is an extension to the AArch64 2044 execution state which utilises a substantial subset of the SVE 2045 instruction set, together with the addition of new architectural 2046 register state capable of holding two dimensional matrix tiles to 2047 enable various matrix operations. 2048 2049config ARM64_MODULE_PLTS 2050 bool "Use PLTs to allow module memory to spill over into vmalloc area" 2051 depends on MODULES 2052 select HAVE_MOD_ARCH_SPECIFIC 2053 help 2054 Allocate PLTs when loading modules so that jumps and calls whose 2055 targets are too far away for their relative offsets to be encoded 2056 in the instructions themselves can be bounced via veneers in the 2057 module's PLT. This allows modules to be allocated in the generic 2058 vmalloc area after the dedicated module memory area has been 2059 exhausted. 2060 2061 When running with address space randomization (KASLR), the module 2062 region itself may be too far away for ordinary relative jumps and 2063 calls, and so in that case, module PLTs are required and cannot be 2064 disabled. 2065 2066 Specific errata workaround(s) might also force module PLTs to be 2067 enabled (ARM64_ERRATUM_843419). 2068 2069config ARM64_PSEUDO_NMI 2070 bool "Support for NMI-like interrupts" 2071 select ARM_GIC_V3 2072 help 2073 Adds support for mimicking Non-Maskable Interrupts through the use of 2074 GIC interrupt priority. This support requires version 3 or later of 2075 ARM GIC. 2076 2077 This high priority configuration for interrupts needs to be 2078 explicitly enabled by setting the kernel parameter 2079 "irqchip.gicv3_pseudo_nmi" to 1. 2080 2081 If unsure, say N 2082 2083if ARM64_PSEUDO_NMI 2084config ARM64_DEBUG_PRIORITY_MASKING 2085 bool "Debug interrupt priority masking" 2086 help 2087 This adds runtime checks to functions enabling/disabling 2088 interrupts when using priority masking. The additional checks verify 2089 the validity of ICC_PMR_EL1 when calling concerned functions. 2090 2091 If unsure, say N 2092endif # ARM64_PSEUDO_NMI 2093 2094config RELOCATABLE 2095 bool "Build a relocatable kernel image" if EXPERT 2096 select ARCH_HAS_RELR 2097 default y 2098 help 2099 This builds the kernel as a Position Independent Executable (PIE), 2100 which retains all relocation metadata required to relocate the 2101 kernel binary at runtime to a different virtual address than the 2102 address it was linked at. 2103 Since AArch64 uses the RELA relocation format, this requires a 2104 relocation pass at runtime even if the kernel is loaded at the 2105 same address it was linked at. 2106 2107config RANDOMIZE_BASE 2108 bool "Randomize the address of the kernel image" 2109 select ARM64_MODULE_PLTS if MODULES 2110 select RELOCATABLE 2111 help 2112 Randomizes the virtual address at which the kernel image is 2113 loaded, as a security feature that deters exploit attempts 2114 relying on knowledge of the location of kernel internals. 2115 2116 It is the bootloader's job to provide entropy, by passing a 2117 random u64 value in /chosen/kaslr-seed at kernel entry. 2118 2119 When booting via the UEFI stub, it will invoke the firmware's 2120 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2121 to the kernel proper. In addition, it will randomise the physical 2122 location of the kernel Image as well. 2123 2124 If unsure, say N. 2125 2126config RANDOMIZE_MODULE_REGION_FULL 2127 bool "Randomize the module region over a 2 GB range" 2128 depends on RANDOMIZE_BASE 2129 default y 2130 help 2131 Randomizes the location of the module region inside a 2 GB window 2132 covering the core kernel. This way, it is less likely for modules 2133 to leak information about the location of core kernel data structures 2134 but it does imply that function calls between modules and the core 2135 kernel will need to be resolved via veneers in the module PLT. 2136 2137 When this option is not set, the module region will be randomized over 2138 a limited range that contains the [_stext, _etext] interval of the 2139 core kernel, so branch relocations are almost always in range unless 2140 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2141 particular case of region exhaustion, modules might be able to fall 2142 back to a larger 2GB area. 2143 2144config CC_HAVE_STACKPROTECTOR_SYSREG 2145 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2146 2147config STACKPROTECTOR_PER_TASK 2148 def_bool y 2149 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2150 2151# The GPIO number here must be sorted by descending number. In case of 2152# a multiplatform kernel, we just want the highest value required by the 2153# selected platforms. 2154config ARCH_NR_GPIO 2155 int 2156 default 2048 if ARCH_APPLE 2157 default 0 2158 help 2159 Maximum number of GPIOs in the system. 2160 2161 If unsure, leave the default value. 2162 2163endmenu # "Kernel Features" 2164 2165menu "Boot options" 2166 2167config ARM64_ACPI_PARKING_PROTOCOL 2168 bool "Enable support for the ARM64 ACPI parking protocol" 2169 depends on ACPI 2170 help 2171 Enable support for the ARM64 ACPI parking protocol. If disabled 2172 the kernel will not allow booting through the ARM64 ACPI parking 2173 protocol even if the corresponding data is present in the ACPI 2174 MADT table. 2175 2176config CMDLINE 2177 string "Default kernel command string" 2178 default "" 2179 help 2180 Provide a set of default command-line options at build time by 2181 entering them here. As a minimum, you should specify the the 2182 root device (e.g. root=/dev/nfs). 2183 2184choice 2185 prompt "Kernel command line type" if CMDLINE != "" 2186 default CMDLINE_FROM_BOOTLOADER 2187 help 2188 Choose how the kernel will handle the provided default kernel 2189 command line string. 2190 2191config CMDLINE_FROM_BOOTLOADER 2192 bool "Use bootloader kernel arguments if available" 2193 help 2194 Uses the command-line options passed by the boot loader. If 2195 the boot loader doesn't provide any, the default kernel command 2196 string provided in CMDLINE will be used. 2197 2198config CMDLINE_FORCE 2199 bool "Always use the default kernel command string" 2200 help 2201 Always use the default kernel command string, even if the boot 2202 loader passes other arguments to the kernel. 2203 This is useful if you cannot or don't want to change the 2204 command-line options your boot loader passes to the kernel. 2205 2206endchoice 2207 2208config EFI_STUB 2209 bool 2210 2211config EFI 2212 bool "UEFI runtime support" 2213 depends on OF && !CPU_BIG_ENDIAN 2214 depends on KERNEL_MODE_NEON 2215 select ARCH_SUPPORTS_ACPI 2216 select LIBFDT 2217 select UCS2_STRING 2218 select EFI_PARAMS_FROM_FDT 2219 select EFI_RUNTIME_WRAPPERS 2220 select EFI_STUB 2221 select EFI_GENERIC_STUB 2222 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2223 default y 2224 help 2225 This option provides support for runtime services provided 2226 by UEFI firmware (such as non-volatile variables, realtime 2227 clock, and platform reset). A UEFI stub is also provided to 2228 allow the kernel to be booted as an EFI application. This 2229 is only useful on systems that have UEFI firmware. 2230 2231config DMI 2232 bool "Enable support for SMBIOS (DMI) tables" 2233 depends on EFI 2234 default y 2235 help 2236 This enables SMBIOS/DMI feature for systems. 2237 2238 This option is only useful on systems that have UEFI firmware. 2239 However, even with this option, the resultant kernel should 2240 continue to boot on existing non-UEFI platforms. 2241 2242endmenu # "Boot options" 2243 2244menu "Power management options" 2245 2246source "kernel/power/Kconfig" 2247 2248config ARCH_HIBERNATION_POSSIBLE 2249 def_bool y 2250 depends on CPU_PM 2251 2252config ARCH_HIBERNATION_HEADER 2253 def_bool y 2254 depends on HIBERNATION 2255 2256config ARCH_SUSPEND_POSSIBLE 2257 def_bool y 2258 2259endmenu # "Power management options" 2260 2261menu "CPU Power Management" 2262 2263source "drivers/cpuidle/Kconfig" 2264 2265source "drivers/cpufreq/Kconfig" 2266 2267endmenu # "CPU Power Management" 2268 2269source "drivers/acpi/Kconfig" 2270 2271source "arch/arm64/kvm/Kconfig" 2272 2273