1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_DEBUG_VIRTUAL 23 select ARCH_HAS_DEBUG_VM_PGTABLE 24 select ARCH_HAS_DMA_PREP_COHERENT 25 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 26 select ARCH_HAS_FAST_MULTIPLIER 27 select ARCH_HAS_FORTIFY_SOURCE 28 select ARCH_HAS_GCOV_PROFILE_ALL 29 select ARCH_HAS_GIGANTIC_PAGE 30 select ARCH_HAS_KCOV 31 select ARCH_HAS_KEEPINITRD 32 select ARCH_HAS_MEMBARRIER_SYNC_CORE 33 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 34 select ARCH_HAS_PTE_DEVMAP 35 select ARCH_HAS_PTE_SPECIAL 36 select ARCH_HAS_SETUP_DMA_OPS 37 select ARCH_HAS_SET_DIRECT_MAP 38 select ARCH_HAS_SET_MEMORY 39 select ARCH_STACKWALK 40 select ARCH_HAS_STRICT_KERNEL_RWX 41 select ARCH_HAS_STRICT_MODULE_RWX 42 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 43 select ARCH_HAS_SYNC_DMA_FOR_CPU 44 select ARCH_HAS_SYSCALL_WRAPPER 45 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 46 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 47 select ARCH_HAS_ZONE_DMA_SET if EXPERT 48 select ARCH_HAVE_ELF_PROT 49 select ARCH_HAVE_NMI_SAFE_CMPXCHG 50 select ARCH_INLINE_READ_LOCK if !PREEMPTION 51 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 52 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 54 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 55 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 58 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 59 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 62 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 63 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 66 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 67 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 68 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 69 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 72 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 73 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 76 select ARCH_KEEP_MEMBLOCK 77 select ARCH_USE_CMPXCHG_LOCKREF 78 select ARCH_USE_GNU_PROPERTY 79 select ARCH_USE_MEMTEST 80 select ARCH_USE_QUEUED_RWLOCKS 81 select ARCH_USE_QUEUED_SPINLOCKS 82 select ARCH_USE_SYM_ANNOTATIONS 83 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 84 select ARCH_SUPPORTS_HUGETLBFS 85 select ARCH_SUPPORTS_MEMORY_FAILURE 86 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 87 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 88 select ARCH_SUPPORTS_LTO_CLANG_THIN 89 select ARCH_SUPPORTS_CFI_CLANG 90 select ARCH_SUPPORTS_ATOMIC_RMW 91 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 92 select ARCH_SUPPORTS_NUMA_BALANCING 93 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 94 select ARCH_WANT_DEFAULT_BPF_JIT 95 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 96 select ARCH_WANT_FRAME_POINTERS 97 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 98 select ARCH_WANT_LD_ORPHAN_WARN 99 select ARCH_WANTS_NO_INSTR 100 select ARCH_HAS_UBSAN_SANITIZE_ALL 101 select ARM_AMBA 102 select ARM_ARCH_TIMER 103 select ARM_GIC 104 select AUDIT_ARCH_COMPAT_GENERIC 105 select ARM_GIC_V2M if PCI 106 select ARM_GIC_V3 107 select ARM_GIC_V3_ITS if PCI 108 select ARM_PSCI_FW 109 select BUILDTIME_TABLE_SORT 110 select CLONE_BACKWARDS 111 select COMMON_CLK 112 select CPU_PM if (SUSPEND || CPU_IDLE) 113 select CRC32 114 select DCACHE_WORD_ACCESS 115 select DMA_DIRECT_REMAP 116 select EDAC_SUPPORT 117 select FRAME_POINTER 118 select GENERIC_ALLOCATOR 119 select GENERIC_ARCH_TOPOLOGY 120 select GENERIC_CLOCKEVENTS_BROADCAST 121 select GENERIC_CPU_AUTOPROBE 122 select GENERIC_CPU_VULNERABILITIES 123 select GENERIC_EARLY_IOREMAP 124 select GENERIC_IDLE_POLL_SETUP 125 select GENERIC_IRQ_IPI 126 select GENERIC_IRQ_PROBE 127 select GENERIC_IRQ_SHOW 128 select GENERIC_IRQ_SHOW_LEVEL 129 select GENERIC_LIB_DEVMEM_IS_ALLOWED 130 select GENERIC_PCI_IOMAP 131 select GENERIC_PTDUMP 132 select GENERIC_SCHED_CLOCK 133 select GENERIC_SMP_IDLE_THREAD 134 select GENERIC_TIME_VSYSCALL 135 select GENERIC_GETTIMEOFDAY 136 select GENERIC_VDSO_TIME_NS 137 select HARDIRQS_SW_RESEND 138 select HAVE_MOVE_PMD 139 select HAVE_MOVE_PUD 140 select HAVE_PCI 141 select HAVE_ACPI_APEI if (ACPI && EFI) 142 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 143 select HAVE_ARCH_AUDITSYSCALL 144 select HAVE_ARCH_BITREVERSE 145 select HAVE_ARCH_COMPILER_H 146 select HAVE_ARCH_HUGE_VMAP 147 select HAVE_ARCH_JUMP_LABEL 148 select HAVE_ARCH_JUMP_LABEL_RELATIVE 149 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 150 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 151 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 152 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 153 # Some instrumentation may be unsound, hence EXPERT 154 select HAVE_ARCH_KCSAN if EXPERT 155 select HAVE_ARCH_KFENCE 156 select HAVE_ARCH_KGDB 157 select HAVE_ARCH_MMAP_RND_BITS 158 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 159 select HAVE_ARCH_PREL32_RELOCATIONS 160 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 161 select HAVE_ARCH_SECCOMP_FILTER 162 select HAVE_ARCH_STACKLEAK 163 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 164 select HAVE_ARCH_TRACEHOOK 165 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 166 select HAVE_ARCH_VMAP_STACK 167 select HAVE_ARM_SMCCC 168 select HAVE_ASM_MODVERSIONS 169 select HAVE_EBPF_JIT 170 select HAVE_C_RECORDMCOUNT 171 select HAVE_CMPXCHG_DOUBLE 172 select HAVE_CMPXCHG_LOCAL 173 select HAVE_CONTEXT_TRACKING 174 select HAVE_DEBUG_KMEMLEAK 175 select HAVE_DMA_CONTIGUOUS 176 select HAVE_DYNAMIC_FTRACE 177 select HAVE_DYNAMIC_FTRACE_WITH_REGS \ 178 if $(cc-option,-fpatchable-function-entry=2) 179 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 180 if DYNAMIC_FTRACE_WITH_REGS 181 select HAVE_EFFICIENT_UNALIGNED_ACCESS 182 select HAVE_FAST_GUP 183 select HAVE_FTRACE_MCOUNT_RECORD 184 select HAVE_FUNCTION_TRACER 185 select HAVE_FUNCTION_ERROR_INJECTION 186 select HAVE_FUNCTION_GRAPH_TRACER 187 select HAVE_GCC_PLUGINS 188 select HAVE_HW_BREAKPOINT if PERF_EVENTS 189 select HAVE_IRQ_TIME_ACCOUNTING 190 select HAVE_KVM 191 select HAVE_NMI 192 select HAVE_PATA_PLATFORM 193 select HAVE_PERF_EVENTS 194 select HAVE_PERF_REGS 195 select HAVE_PERF_USER_STACK_DUMP 196 select HAVE_REGS_AND_STACK_ACCESS_API 197 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 198 select HAVE_FUNCTION_ARG_ACCESS_API 199 select MMU_GATHER_RCU_TABLE_FREE 200 select HAVE_RSEQ 201 select HAVE_STACKPROTECTOR 202 select HAVE_SYSCALL_TRACEPOINTS 203 select HAVE_KPROBES 204 select HAVE_KRETPROBES 205 select HAVE_GENERIC_VDSO 206 select IOMMU_DMA if IOMMU_SUPPORT 207 select IRQ_DOMAIN 208 select IRQ_FORCED_THREADING 209 select KASAN_VMALLOC if KASAN_GENERIC 210 select MODULES_USE_ELF_RELA 211 select NEED_DMA_MAP_STATE 212 select NEED_SG_DMA_LENGTH 213 select OF 214 select OF_EARLY_FLATTREE 215 select PCI_DOMAINS_GENERIC if PCI 216 select PCI_ECAM if (ACPI && PCI) 217 select PCI_SYSCALL if PCI 218 select POWER_RESET 219 select POWER_SUPPLY 220 select SPARSE_IRQ 221 select SWIOTLB 222 select SYSCTL_EXCEPTION_TRACE 223 select THREAD_INFO_IN_TASK 224 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 225 select TRACE_IRQFLAGS_SUPPORT 226 help 227 ARM 64-bit (AArch64) Linux support. 228 229config 64BIT 230 def_bool y 231 232config MMU 233 def_bool y 234 235config ARM64_PAGE_SHIFT 236 int 237 default 16 if ARM64_64K_PAGES 238 default 14 if ARM64_16K_PAGES 239 default 12 240 241config ARM64_CONT_PTE_SHIFT 242 int 243 default 5 if ARM64_64K_PAGES 244 default 7 if ARM64_16K_PAGES 245 default 4 246 247config ARM64_CONT_PMD_SHIFT 248 int 249 default 5 if ARM64_64K_PAGES 250 default 5 if ARM64_16K_PAGES 251 default 4 252 253config ARCH_MMAP_RND_BITS_MIN 254 default 14 if ARM64_64K_PAGES 255 default 16 if ARM64_16K_PAGES 256 default 18 257 258# max bits determined by the following formula: 259# VA_BITS - PAGE_SHIFT - 3 260config ARCH_MMAP_RND_BITS_MAX 261 default 19 if ARM64_VA_BITS=36 262 default 24 if ARM64_VA_BITS=39 263 default 27 if ARM64_VA_BITS=42 264 default 30 if ARM64_VA_BITS=47 265 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 266 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 267 default 33 if ARM64_VA_BITS=48 268 default 14 if ARM64_64K_PAGES 269 default 16 if ARM64_16K_PAGES 270 default 18 271 272config ARCH_MMAP_RND_COMPAT_BITS_MIN 273 default 7 if ARM64_64K_PAGES 274 default 9 if ARM64_16K_PAGES 275 default 11 276 277config ARCH_MMAP_RND_COMPAT_BITS_MAX 278 default 16 279 280config NO_IOPORT_MAP 281 def_bool y if !PCI 282 283config STACKTRACE_SUPPORT 284 def_bool y 285 286config ILLEGAL_POINTER_VALUE 287 hex 288 default 0xdead000000000000 289 290config LOCKDEP_SUPPORT 291 def_bool y 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config GENERIC_BUG_RELATIVE_POINTERS 298 def_bool y 299 depends on GENERIC_BUG 300 301config GENERIC_HWEIGHT 302 def_bool y 303 304config GENERIC_CSUM 305 def_bool y 306 307config GENERIC_CALIBRATE_DELAY 308 def_bool y 309 310config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 311 def_bool y 312 313config SMP 314 def_bool y 315 316config KERNEL_MODE_NEON 317 def_bool y 318 319config FIX_EARLYCON_MEM 320 def_bool y 321 322config PGTABLE_LEVELS 323 int 324 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 325 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 326 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 327 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 328 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 329 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 330 331config ARCH_SUPPORTS_UPROBES 332 def_bool y 333 334config ARCH_PROC_KCORE_TEXT 335 def_bool y 336 337config BROKEN_GAS_INST 338 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 339 340config KASAN_SHADOW_OFFSET 341 hex 342 depends on KASAN_GENERIC || KASAN_SW_TAGS 343 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 344 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 345 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 346 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 347 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 348 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 349 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 350 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 351 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 352 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 353 default 0xffffffffffffffff 354 355source "arch/arm64/Kconfig.platforms" 356 357menu "Kernel Features" 358 359menu "ARM errata workarounds via the alternatives framework" 360 361config ARM64_WORKAROUND_CLEAN_CACHE 362 bool 363 364config ARM64_ERRATUM_826319 365 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 366 default y 367 select ARM64_WORKAROUND_CLEAN_CACHE 368 help 369 This option adds an alternative code sequence to work around ARM 370 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 371 AXI master interface and an L2 cache. 372 373 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 374 and is unable to accept a certain write via this interface, it will 375 not progress on read data presented on the read data channel and the 376 system can deadlock. 377 378 The workaround promotes data cache clean instructions to 379 data cache clean-and-invalidate. 380 Please note that this does not necessarily enable the workaround, 381 as it depends on the alternative framework, which will only patch 382 the kernel if an affected CPU is detected. 383 384 If unsure, say Y. 385 386config ARM64_ERRATUM_827319 387 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 388 default y 389 select ARM64_WORKAROUND_CLEAN_CACHE 390 help 391 This option adds an alternative code sequence to work around ARM 392 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 393 master interface and an L2 cache. 394 395 Under certain conditions this erratum can cause a clean line eviction 396 to occur at the same time as another transaction to the same address 397 on the AMBA 5 CHI interface, which can cause data corruption if the 398 interconnect reorders the two transactions. 399 400 The workaround promotes data cache clean instructions to 401 data cache clean-and-invalidate. 402 Please note that this does not necessarily enable the workaround, 403 as it depends on the alternative framework, which will only patch 404 the kernel if an affected CPU is detected. 405 406 If unsure, say Y. 407 408config ARM64_ERRATUM_824069 409 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 410 default y 411 select ARM64_WORKAROUND_CLEAN_CACHE 412 help 413 This option adds an alternative code sequence to work around ARM 414 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 415 to a coherent interconnect. 416 417 If a Cortex-A53 processor is executing a store or prefetch for 418 write instruction at the same time as a processor in another 419 cluster is executing a cache maintenance operation to the same 420 address, then this erratum might cause a clean cache line to be 421 incorrectly marked as dirty. 422 423 The workaround promotes data cache clean instructions to 424 data cache clean-and-invalidate. 425 Please note that this option does not necessarily enable the 426 workaround, as it depends on the alternative framework, which will 427 only patch the kernel if an affected CPU is detected. 428 429 If unsure, say Y. 430 431config ARM64_ERRATUM_819472 432 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 433 default y 434 select ARM64_WORKAROUND_CLEAN_CACHE 435 help 436 This option adds an alternative code sequence to work around ARM 437 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 438 present when it is connected to a coherent interconnect. 439 440 If the processor is executing a load and store exclusive sequence at 441 the same time as a processor in another cluster is executing a cache 442 maintenance operation to the same address, then this erratum might 443 cause data corruption. 444 445 The workaround promotes data cache clean instructions to 446 data cache clean-and-invalidate. 447 Please note that this does not necessarily enable the workaround, 448 as it depends on the alternative framework, which will only patch 449 the kernel if an affected CPU is detected. 450 451 If unsure, say Y. 452 453config ARM64_ERRATUM_832075 454 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 455 default y 456 help 457 This option adds an alternative code sequence to work around ARM 458 erratum 832075 on Cortex-A57 parts up to r1p2. 459 460 Affected Cortex-A57 parts might deadlock when exclusive load/store 461 instructions to Write-Back memory are mixed with Device loads. 462 463 The workaround is to promote device loads to use Load-Acquire 464 semantics. 465 Please note that this does not necessarily enable the workaround, 466 as it depends on the alternative framework, which will only patch 467 the kernel if an affected CPU is detected. 468 469 If unsure, say Y. 470 471config ARM64_ERRATUM_834220 472 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 473 depends on KVM 474 default y 475 help 476 This option adds an alternative code sequence to work around ARM 477 erratum 834220 on Cortex-A57 parts up to r1p2. 478 479 Affected Cortex-A57 parts might report a Stage 2 translation 480 fault as the result of a Stage 1 fault for load crossing a 481 page boundary when there is a permission or device memory 482 alignment fault at Stage 1 and a translation fault at Stage 2. 483 484 The workaround is to verify that the Stage 1 translation 485 doesn't generate a fault before handling the Stage 2 fault. 486 Please note that this does not necessarily enable the workaround, 487 as it depends on the alternative framework, which will only patch 488 the kernel if an affected CPU is detected. 489 490 If unsure, say Y. 491 492config ARM64_ERRATUM_845719 493 bool "Cortex-A53: 845719: a load might read incorrect data" 494 depends on COMPAT 495 default y 496 help 497 This option adds an alternative code sequence to work around ARM 498 erratum 845719 on Cortex-A53 parts up to r0p4. 499 500 When running a compat (AArch32) userspace on an affected Cortex-A53 501 part, a load at EL0 from a virtual address that matches the bottom 32 502 bits of the virtual address used by a recent load at (AArch64) EL1 503 might return incorrect data. 504 505 The workaround is to write the contextidr_el1 register on exception 506 return to a 32-bit task. 507 Please note that this does not necessarily enable the workaround, 508 as it depends on the alternative framework, which will only patch 509 the kernel if an affected CPU is detected. 510 511 If unsure, say Y. 512 513config ARM64_ERRATUM_843419 514 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 515 default y 516 select ARM64_MODULE_PLTS if MODULES 517 help 518 This option links the kernel with '--fix-cortex-a53-843419' and 519 enables PLT support to replace certain ADRP instructions, which can 520 cause subsequent memory accesses to use an incorrect address on 521 Cortex-A53 parts up to r0p4. 522 523 If unsure, say Y. 524 525config ARM64_LD_HAS_FIX_ERRATUM_843419 526 def_bool $(ld-option,--fix-cortex-a53-843419) 527 528config ARM64_ERRATUM_1024718 529 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 530 default y 531 help 532 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 533 534 Affected Cortex-A55 cores (all revisions) could cause incorrect 535 update of the hardware dirty bit when the DBM/AP bits are updated 536 without a break-before-make. The workaround is to disable the usage 537 of hardware DBM locally on the affected cores. CPUs not affected by 538 this erratum will continue to use the feature. 539 540 If unsure, say Y. 541 542config ARM64_ERRATUM_1418040 543 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 544 default y 545 depends on COMPAT 546 help 547 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 548 errata 1188873 and 1418040. 549 550 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 551 cause register corruption when accessing the timer registers 552 from AArch32 userspace. 553 554 If unsure, say Y. 555 556config ARM64_WORKAROUND_SPECULATIVE_AT 557 bool 558 559config ARM64_ERRATUM_1165522 560 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 561 default y 562 select ARM64_WORKAROUND_SPECULATIVE_AT 563 help 564 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 565 566 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 567 corrupted TLBs by speculating an AT instruction during a guest 568 context switch. 569 570 If unsure, say Y. 571 572config ARM64_ERRATUM_1319367 573 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 574 default y 575 select ARM64_WORKAROUND_SPECULATIVE_AT 576 help 577 This option adds work arounds for ARM Cortex-A57 erratum 1319537 578 and A72 erratum 1319367 579 580 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 581 speculating an AT instruction during a guest context switch. 582 583 If unsure, say Y. 584 585config ARM64_ERRATUM_1530923 586 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 587 default y 588 select ARM64_WORKAROUND_SPECULATIVE_AT 589 help 590 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 591 592 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 593 corrupted TLBs by speculating an AT instruction during a guest 594 context switch. 595 596 If unsure, say Y. 597 598config ARM64_WORKAROUND_REPEAT_TLBI 599 bool 600 601config ARM64_ERRATUM_1286807 602 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 603 default y 604 select ARM64_WORKAROUND_REPEAT_TLBI 605 help 606 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 607 608 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 609 address for a cacheable mapping of a location is being 610 accessed by a core while another core is remapping the virtual 611 address to a new physical page using the recommended 612 break-before-make sequence, then under very rare circumstances 613 TLBI+DSB completes before a read using the translation being 614 invalidated has been observed by other observers. The 615 workaround repeats the TLBI+DSB operation. 616 617config ARM64_ERRATUM_1463225 618 bool "Cortex-A76: Software Step might prevent interrupt recognition" 619 default y 620 help 621 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 622 623 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 624 of a system call instruction (SVC) can prevent recognition of 625 subsequent interrupts when software stepping is disabled in the 626 exception handler of the system call and either kernel debugging 627 is enabled or VHE is in use. 628 629 Work around the erratum by triggering a dummy step exception 630 when handling a system call from a task that is being stepped 631 in a VHE configuration of the kernel. 632 633 If unsure, say Y. 634 635config ARM64_ERRATUM_1542419 636 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 637 default y 638 help 639 This option adds a workaround for ARM Neoverse-N1 erratum 640 1542419. 641 642 Affected Neoverse-N1 cores could execute a stale instruction when 643 modified by another CPU. The workaround depends on a firmware 644 counterpart. 645 646 Workaround the issue by hiding the DIC feature from EL0. This 647 forces user-space to perform cache maintenance. 648 649 If unsure, say Y. 650 651config ARM64_ERRATUM_1508412 652 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 653 default y 654 help 655 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 656 657 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 658 of a store-exclusive or read of PAR_EL1 and a load with device or 659 non-cacheable memory attributes. The workaround depends on a firmware 660 counterpart. 661 662 KVM guests must also have the workaround implemented or they can 663 deadlock the system. 664 665 Work around the issue by inserting DMB SY barriers around PAR_EL1 666 register reads and warning KVM users. The DMB barrier is sufficient 667 to prevent a speculative PAR_EL1 read. 668 669 If unsure, say Y. 670 671config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 672 bool 673 674config ARM64_ERRATUM_2051678 675 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 676 default y 677 help 678 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 679 Affected Coretex-A510 might not respect the ordering rules for 680 hardware update of the page table's dirty bit. The workaround 681 is to not enable the feature on affected CPUs. 682 683 If unsure, say Y. 684 685config ARM64_ERRATUM_2077057 686 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 687 help 688 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 689 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 690 expected, but a Pointer Authentication trap is taken instead. The 691 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 692 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 693 694 This can only happen when EL2 is stepping EL1. 695 696 When these conditions occur, the SPSR_EL2 value is unchanged from the 697 previous guest entry, and can be restored from the in-memory copy. 698 699 If unsure, say Y. 700 701config ARM64_ERRATUM_2119858 702 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 703 default y 704 depends on CORESIGHT_TRBE 705 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 706 help 707 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 708 709 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 710 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 711 the event of a WRAP event. 712 713 Work around the issue by always making sure we move the TRBPTR_EL1 by 714 256 bytes before enabling the buffer and filling the first 256 bytes of 715 the buffer with ETM ignore packets upon disabling. 716 717 If unsure, say Y. 718 719config ARM64_ERRATUM_2139208 720 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 721 default y 722 depends on CORESIGHT_TRBE 723 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 724 help 725 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 726 727 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 728 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 729 the event of a WRAP event. 730 731 Work around the issue by always making sure we move the TRBPTR_EL1 by 732 256 bytes before enabling the buffer and filling the first 256 bytes of 733 the buffer with ETM ignore packets upon disabling. 734 735 If unsure, say Y. 736 737config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 738 bool 739 740config ARM64_ERRATUM_2054223 741 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 742 default y 743 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 744 help 745 Enable workaround for ARM Cortex-A710 erratum 2054223 746 747 Affected cores may fail to flush the trace data on a TSB instruction, when 748 the PE is in trace prohibited state. This will cause losing a few bytes 749 of the trace cached. 750 751 Workaround is to issue two TSB consecutively on affected cores. 752 753 If unsure, say Y. 754 755config ARM64_ERRATUM_2067961 756 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 757 default y 758 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 759 help 760 Enable workaround for ARM Neoverse-N2 erratum 2067961 761 762 Affected cores may fail to flush the trace data on a TSB instruction, when 763 the PE is in trace prohibited state. This will cause losing a few bytes 764 of the trace cached. 765 766 Workaround is to issue two TSB consecutively on affected cores. 767 768 If unsure, say Y. 769 770config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 771 bool 772 773config ARM64_ERRATUM_2253138 774 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 775 depends on CORESIGHT_TRBE 776 default y 777 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 778 help 779 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 780 781 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 782 for TRBE. Under some conditions, the TRBE might generate a write to the next 783 virtually addressed page following the last page of the TRBE address space 784 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 785 786 Work around this in the driver by always making sure that there is a 787 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 788 789 If unsure, say Y. 790 791config ARM64_ERRATUM_2224489 792 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 793 depends on CORESIGHT_TRBE 794 default y 795 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 796 help 797 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 798 799 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 800 for TRBE. Under some conditions, the TRBE might generate a write to the next 801 virtually addressed page following the last page of the TRBE address space 802 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 803 804 Work around this in the driver by always making sure that there is a 805 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 806 807 If unsure, say Y. 808 809config ARM64_ERRATUM_2064142 810 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 811 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 812 default y 813 help 814 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 815 816 Affected Cortex-A510 core might fail to write into system registers after the 817 TRBE has been disabled. Under some conditions after the TRBE has been disabled 818 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 819 and TRBTRG_EL1 will be ignored and will not be effected. 820 821 Work around this in the driver by executing TSB CSYNC and DSB after collection 822 is stopped and before performing a system register write to one of the affected 823 registers. 824 825 If unsure, say Y. 826 827config ARM64_ERRATUM_2038923 828 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 829 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 830 default y 831 help 832 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 833 834 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 835 prohibited within the CPU. As a result, the trace buffer or trace buffer state 836 might be corrupted. This happens after TRBE buffer has been enabled by setting 837 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 838 execution changes from a context, in which trace is prohibited to one where it 839 isn't, or vice versa. In these mentioned conditions, the view of whether trace 840 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 841 the trace buffer state might be corrupted. 842 843 Work around this in the driver by preventing an inconsistent view of whether the 844 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 845 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 846 two ISB instructions if no ERET is to take place. 847 848 If unsure, say Y. 849 850config ARM64_ERRATUM_1902691 851 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 852 depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in 853 default y 854 help 855 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 856 857 Affected Cortex-A510 core might cause trace data corruption, when being written 858 into the memory. Effectively TRBE is broken and hence cannot be used to capture 859 trace data. 860 861 Work around this problem in the driver by just preventing TRBE initialization on 862 affected cpus. The firmware must have disabled the access to TRBE for the kernel 863 on such implementations. This will cover the kernel for any firmware that doesn't 864 do this already. 865 866 If unsure, say Y. 867 868config CAVIUM_ERRATUM_22375 869 bool "Cavium erratum 22375, 24313" 870 default y 871 help 872 Enable workaround for errata 22375 and 24313. 873 874 This implements two gicv3-its errata workarounds for ThunderX. Both 875 with a small impact affecting only ITS table allocation. 876 877 erratum 22375: only alloc 8MB table size 878 erratum 24313: ignore memory access type 879 880 The fixes are in ITS initialization and basically ignore memory access 881 type and table size provided by the TYPER and BASER registers. 882 883 If unsure, say Y. 884 885config CAVIUM_ERRATUM_23144 886 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 887 depends on NUMA 888 default y 889 help 890 ITS SYNC command hang for cross node io and collections/cpu mapping. 891 892 If unsure, say Y. 893 894config CAVIUM_ERRATUM_23154 895 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 896 default y 897 help 898 The ThunderX GICv3 implementation requires a modified version for 899 reading the IAR status to ensure data synchronization 900 (access to icc_iar1_el1 is not sync'ed before and after). 901 902 It also suffers from erratum 38545 (also present on Marvell's 903 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 904 spuriously presented to the CPU interface. 905 906 If unsure, say Y. 907 908config CAVIUM_ERRATUM_27456 909 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 910 default y 911 help 912 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 913 instructions may cause the icache to become corrupted if it 914 contains data for a non-current ASID. The fix is to 915 invalidate the icache when changing the mm context. 916 917 If unsure, say Y. 918 919config CAVIUM_ERRATUM_30115 920 bool "Cavium erratum 30115: Guest may disable interrupts in host" 921 default y 922 help 923 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 924 1.2, and T83 Pass 1.0, KVM guest execution may disable 925 interrupts in host. Trapping both GICv3 group-0 and group-1 926 accesses sidesteps the issue. 927 928 If unsure, say Y. 929 930config CAVIUM_TX2_ERRATUM_219 931 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 932 default y 933 help 934 On Cavium ThunderX2, a load, store or prefetch instruction between a 935 TTBR update and the corresponding context synchronizing operation can 936 cause a spurious Data Abort to be delivered to any hardware thread in 937 the CPU core. 938 939 Work around the issue by avoiding the problematic code sequence and 940 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 941 trap handler performs the corresponding register access, skips the 942 instruction and ensures context synchronization by virtue of the 943 exception return. 944 945 If unsure, say Y. 946 947config FUJITSU_ERRATUM_010001 948 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 949 default y 950 help 951 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 952 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 953 accesses may cause undefined fault (Data abort, DFSC=0b111111). 954 This fault occurs under a specific hardware condition when a 955 load/store instruction performs an address translation using: 956 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 957 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 958 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 959 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 960 961 The workaround is to ensure these bits are clear in TCR_ELx. 962 The workaround only affects the Fujitsu-A64FX. 963 964 If unsure, say Y. 965 966config HISILICON_ERRATUM_161600802 967 bool "Hip07 161600802: Erroneous redistributor VLPI base" 968 default y 969 help 970 The HiSilicon Hip07 SoC uses the wrong redistributor base 971 when issued ITS commands such as VMOVP and VMAPP, and requires 972 a 128kB offset to be applied to the target address in this commands. 973 974 If unsure, say Y. 975 976config QCOM_FALKOR_ERRATUM_1003 977 bool "Falkor E1003: Incorrect translation due to ASID change" 978 default y 979 help 980 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 981 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 982 in TTBR1_EL1, this situation only occurs in the entry trampoline and 983 then only for entries in the walk cache, since the leaf translation 984 is unchanged. Work around the erratum by invalidating the walk cache 985 entries for the trampoline before entering the kernel proper. 986 987config QCOM_FALKOR_ERRATUM_1009 988 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 989 default y 990 select ARM64_WORKAROUND_REPEAT_TLBI 991 help 992 On Falkor v1, the CPU may prematurely complete a DSB following a 993 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 994 one more time to fix the issue. 995 996 If unsure, say Y. 997 998config QCOM_QDF2400_ERRATUM_0065 999 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1000 default y 1001 help 1002 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1003 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1004 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1005 1006 If unsure, say Y. 1007 1008config QCOM_FALKOR_ERRATUM_E1041 1009 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1010 default y 1011 help 1012 Falkor CPU may speculatively fetch instructions from an improper 1013 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1014 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1015 1016 If unsure, say Y. 1017 1018config NVIDIA_CARMEL_CNP_ERRATUM 1019 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1020 default y 1021 help 1022 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1023 invalidate shared TLB entries installed by a different core, as it would 1024 on standard ARM cores. 1025 1026 If unsure, say Y. 1027 1028config SOCIONEXT_SYNQUACER_PREITS 1029 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1030 default y 1031 help 1032 Socionext Synquacer SoCs implement a separate h/w block to generate 1033 MSI doorbell writes with non-zero values for the device ID. 1034 1035 If unsure, say Y. 1036 1037endmenu 1038 1039 1040choice 1041 prompt "Page size" 1042 default ARM64_4K_PAGES 1043 help 1044 Page size (translation granule) configuration. 1045 1046config ARM64_4K_PAGES 1047 bool "4KB" 1048 help 1049 This feature enables 4KB pages support. 1050 1051config ARM64_16K_PAGES 1052 bool "16KB" 1053 help 1054 The system will use 16KB pages support. AArch32 emulation 1055 requires applications compiled with 16K (or a multiple of 16K) 1056 aligned segments. 1057 1058config ARM64_64K_PAGES 1059 bool "64KB" 1060 help 1061 This feature enables 64KB pages support (4KB by default) 1062 allowing only two levels of page tables and faster TLB 1063 look-up. AArch32 emulation requires applications compiled 1064 with 64K aligned segments. 1065 1066endchoice 1067 1068choice 1069 prompt "Virtual address space size" 1070 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1071 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1072 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1073 help 1074 Allows choosing one of multiple possible virtual address 1075 space sizes. The level of translation table is determined by 1076 a combination of page size and virtual address space size. 1077 1078config ARM64_VA_BITS_36 1079 bool "36-bit" if EXPERT 1080 depends on ARM64_16K_PAGES 1081 1082config ARM64_VA_BITS_39 1083 bool "39-bit" 1084 depends on ARM64_4K_PAGES 1085 1086config ARM64_VA_BITS_42 1087 bool "42-bit" 1088 depends on ARM64_64K_PAGES 1089 1090config ARM64_VA_BITS_47 1091 bool "47-bit" 1092 depends on ARM64_16K_PAGES 1093 1094config ARM64_VA_BITS_48 1095 bool "48-bit" 1096 1097config ARM64_VA_BITS_52 1098 bool "52-bit" 1099 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1100 help 1101 Enable 52-bit virtual addressing for userspace when explicitly 1102 requested via a hint to mmap(). The kernel will also use 52-bit 1103 virtual addresses for its own mappings (provided HW support for 1104 this feature is available, otherwise it reverts to 48-bit). 1105 1106 NOTE: Enabling 52-bit virtual addressing in conjunction with 1107 ARMv8.3 Pointer Authentication will result in the PAC being 1108 reduced from 7 bits to 3 bits, which may have a significant 1109 impact on its susceptibility to brute-force attacks. 1110 1111 If unsure, select 48-bit virtual addressing instead. 1112 1113endchoice 1114 1115config ARM64_FORCE_52BIT 1116 bool "Force 52-bit virtual addresses for userspace" 1117 depends on ARM64_VA_BITS_52 && EXPERT 1118 help 1119 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1120 to maintain compatibility with older software by providing 48-bit VAs 1121 unless a hint is supplied to mmap. 1122 1123 This configuration option disables the 48-bit compatibility logic, and 1124 forces all userspace addresses to be 52-bit on HW that supports it. One 1125 should only enable this configuration option for stress testing userspace 1126 memory management code. If unsure say N here. 1127 1128config ARM64_VA_BITS 1129 int 1130 default 36 if ARM64_VA_BITS_36 1131 default 39 if ARM64_VA_BITS_39 1132 default 42 if ARM64_VA_BITS_42 1133 default 47 if ARM64_VA_BITS_47 1134 default 48 if ARM64_VA_BITS_48 1135 default 52 if ARM64_VA_BITS_52 1136 1137choice 1138 prompt "Physical address space size" 1139 default ARM64_PA_BITS_48 1140 help 1141 Choose the maximum physical address range that the kernel will 1142 support. 1143 1144config ARM64_PA_BITS_48 1145 bool "48-bit" 1146 1147config ARM64_PA_BITS_52 1148 bool "52-bit (ARMv8.2)" 1149 depends on ARM64_64K_PAGES 1150 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1151 help 1152 Enable support for a 52-bit physical address space, introduced as 1153 part of the ARMv8.2-LPA extension. 1154 1155 With this enabled, the kernel will also continue to work on CPUs that 1156 do not support ARMv8.2-LPA, but with some added memory overhead (and 1157 minor performance overhead). 1158 1159endchoice 1160 1161config ARM64_PA_BITS 1162 int 1163 default 48 if ARM64_PA_BITS_48 1164 default 52 if ARM64_PA_BITS_52 1165 1166choice 1167 prompt "Endianness" 1168 default CPU_LITTLE_ENDIAN 1169 help 1170 Select the endianness of data accesses performed by the CPU. Userspace 1171 applications will need to be compiled and linked for the endianness 1172 that is selected here. 1173 1174config CPU_BIG_ENDIAN 1175 bool "Build big-endian kernel" 1176 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1177 help 1178 Say Y if you plan on running a kernel with a big-endian userspace. 1179 1180config CPU_LITTLE_ENDIAN 1181 bool "Build little-endian kernel" 1182 help 1183 Say Y if you plan on running a kernel with a little-endian userspace. 1184 This is usually the case for distributions targeting arm64. 1185 1186endchoice 1187 1188config SCHED_MC 1189 bool "Multi-core scheduler support" 1190 help 1191 Multi-core scheduler support improves the CPU scheduler's decision 1192 making when dealing with multi-core CPU chips at a cost of slightly 1193 increased overhead in some places. If unsure say N here. 1194 1195config SCHED_CLUSTER 1196 bool "Cluster scheduler support" 1197 help 1198 Cluster scheduler support improves the CPU scheduler's decision 1199 making when dealing with machines that have clusters of CPUs. 1200 Cluster usually means a couple of CPUs which are placed closely 1201 by sharing mid-level caches, last-level cache tags or internal 1202 busses. 1203 1204config SCHED_SMT 1205 bool "SMT scheduler support" 1206 help 1207 Improves the CPU scheduler's decision making when dealing with 1208 MultiThreading at a cost of slightly increased overhead in some 1209 places. If unsure say N here. 1210 1211config NR_CPUS 1212 int "Maximum number of CPUs (2-4096)" 1213 range 2 4096 1214 default "256" 1215 1216config HOTPLUG_CPU 1217 bool "Support for hot-pluggable CPUs" 1218 select GENERIC_IRQ_MIGRATION 1219 help 1220 Say Y here to experiment with turning CPUs off and on. CPUs 1221 can be controlled through /sys/devices/system/cpu. 1222 1223# Common NUMA Features 1224config NUMA 1225 bool "NUMA Memory Allocation and Scheduler Support" 1226 select GENERIC_ARCH_NUMA 1227 select ACPI_NUMA if ACPI 1228 select OF_NUMA 1229 select HAVE_SETUP_PER_CPU_AREA 1230 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1231 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1232 select USE_PERCPU_NUMA_NODE_ID 1233 help 1234 Enable NUMA (Non-Uniform Memory Access) support. 1235 1236 The kernel will try to allocate memory used by a CPU on the 1237 local memory of the CPU and add some more 1238 NUMA awareness to the kernel. 1239 1240config NODES_SHIFT 1241 int "Maximum NUMA Nodes (as a power of 2)" 1242 range 1 10 1243 default "4" 1244 depends on NUMA 1245 help 1246 Specify the maximum number of NUMA Nodes available on the target 1247 system. Increases memory reserved to accommodate various tables. 1248 1249source "kernel/Kconfig.hz" 1250 1251config ARCH_SPARSEMEM_ENABLE 1252 def_bool y 1253 select SPARSEMEM_VMEMMAP_ENABLE 1254 select SPARSEMEM_VMEMMAP 1255 1256config HW_PERF_EVENTS 1257 def_bool y 1258 depends on ARM_PMU 1259 1260# Supported by clang >= 7.0 1261config CC_HAVE_SHADOW_CALL_STACK 1262 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1263 1264config PARAVIRT 1265 bool "Enable paravirtualization code" 1266 help 1267 This changes the kernel so it can modify itself when it is run 1268 under a hypervisor, potentially improving performance significantly 1269 over full virtualization. 1270 1271config PARAVIRT_TIME_ACCOUNTING 1272 bool "Paravirtual steal time accounting" 1273 select PARAVIRT 1274 help 1275 Select this option to enable fine granularity task steal time 1276 accounting. Time spent executing other tasks in parallel with 1277 the current vCPU is discounted from the vCPU power. To account for 1278 that, there can be a small performance impact. 1279 1280 If in doubt, say N here. 1281 1282config KEXEC 1283 depends on PM_SLEEP_SMP 1284 select KEXEC_CORE 1285 bool "kexec system call" 1286 help 1287 kexec is a system call that implements the ability to shutdown your 1288 current kernel, and to start another kernel. It is like a reboot 1289 but it is independent of the system firmware. And like a reboot 1290 you can start any kernel with it, not just Linux. 1291 1292config KEXEC_FILE 1293 bool "kexec file based system call" 1294 select KEXEC_CORE 1295 select HAVE_IMA_KEXEC if IMA 1296 help 1297 This is new version of kexec system call. This system call is 1298 file based and takes file descriptors as system call argument 1299 for kernel and initramfs as opposed to list of segments as 1300 accepted by previous system call. 1301 1302config KEXEC_SIG 1303 bool "Verify kernel signature during kexec_file_load() syscall" 1304 depends on KEXEC_FILE 1305 help 1306 Select this option to verify a signature with loaded kernel 1307 image. If configured, any attempt of loading a image without 1308 valid signature will fail. 1309 1310 In addition to that option, you need to enable signature 1311 verification for the corresponding kernel image type being 1312 loaded in order for this to work. 1313 1314config KEXEC_IMAGE_VERIFY_SIG 1315 bool "Enable Image signature verification support" 1316 default y 1317 depends on KEXEC_SIG 1318 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1319 help 1320 Enable Image signature verification support. 1321 1322comment "Support for PE file signature verification disabled" 1323 depends on KEXEC_SIG 1324 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1325 1326config CRASH_DUMP 1327 bool "Build kdump crash kernel" 1328 help 1329 Generate crash dump after being started by kexec. This should 1330 be normally only set in special crash dump kernels which are 1331 loaded in the main kernel with kexec-tools into a specially 1332 reserved region and then later executed after a crash by 1333 kdump/kexec. 1334 1335 For more details see Documentation/admin-guide/kdump/kdump.rst 1336 1337config TRANS_TABLE 1338 def_bool y 1339 depends on HIBERNATION || KEXEC_CORE 1340 1341config XEN_DOM0 1342 def_bool y 1343 depends on XEN 1344 1345config XEN 1346 bool "Xen guest support on ARM64" 1347 depends on ARM64 && OF 1348 select SWIOTLB_XEN 1349 select PARAVIRT 1350 help 1351 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1352 1353config FORCE_MAX_ZONEORDER 1354 int 1355 default "14" if ARM64_64K_PAGES 1356 default "12" if ARM64_16K_PAGES 1357 default "11" 1358 help 1359 The kernel memory allocator divides physically contiguous memory 1360 blocks into "zones", where each zone is a power of two number of 1361 pages. This option selects the largest power of two that the kernel 1362 keeps in the memory allocator. If you need to allocate very large 1363 blocks of physically contiguous memory, then you may need to 1364 increase this value. 1365 1366 This config option is actually maximum order plus one. For example, 1367 a value of 11 means that the largest free memory block is 2^10 pages. 1368 1369 We make sure that we can allocate upto a HugePage size for each configuration. 1370 Hence we have : 1371 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1372 1373 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1374 4M allocations matching the default size used by generic code. 1375 1376config UNMAP_KERNEL_AT_EL0 1377 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1378 default y 1379 help 1380 Speculation attacks against some high-performance processors can 1381 be used to bypass MMU permission checks and leak kernel data to 1382 userspace. This can be defended against by unmapping the kernel 1383 when running in userspace, mapping it back in on exception entry 1384 via a trampoline page in the vector table. 1385 1386 If unsure, say Y. 1387 1388config MITIGATE_SPECTRE_BRANCH_HISTORY 1389 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1390 default y 1391 help 1392 Speculation attacks against some high-performance processors can 1393 make use of branch history to influence future speculation. 1394 When taking an exception from user-space, a sequence of branches 1395 or a firmware call overwrites the branch history. 1396 1397config RODATA_FULL_DEFAULT_ENABLED 1398 bool "Apply r/o permissions of VM areas also to their linear aliases" 1399 default y 1400 help 1401 Apply read-only attributes of VM areas to the linear alias of 1402 the backing pages as well. This prevents code or read-only data 1403 from being modified (inadvertently or intentionally) via another 1404 mapping of the same memory page. This additional enhancement can 1405 be turned off at runtime by passing rodata=[off|on] (and turned on 1406 with rodata=full if this option is set to 'n') 1407 1408 This requires the linear region to be mapped down to pages, 1409 which may adversely affect performance in some cases. 1410 1411config ARM64_SW_TTBR0_PAN 1412 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1413 help 1414 Enabling this option prevents the kernel from accessing 1415 user-space memory directly by pointing TTBR0_EL1 to a reserved 1416 zeroed area and reserved ASID. The user access routines 1417 restore the valid TTBR0_EL1 temporarily. 1418 1419config ARM64_TAGGED_ADDR_ABI 1420 bool "Enable the tagged user addresses syscall ABI" 1421 default y 1422 help 1423 When this option is enabled, user applications can opt in to a 1424 relaxed ABI via prctl() allowing tagged addresses to be passed 1425 to system calls as pointer arguments. For details, see 1426 Documentation/arm64/tagged-address-abi.rst. 1427 1428menuconfig COMPAT 1429 bool "Kernel support for 32-bit EL0" 1430 depends on ARM64_4K_PAGES || EXPERT 1431 select HAVE_UID16 1432 select OLD_SIGSUSPEND3 1433 select COMPAT_OLD_SIGACTION 1434 help 1435 This option enables support for a 32-bit EL0 running under a 64-bit 1436 kernel at EL1. AArch32-specific components such as system calls, 1437 the user helper functions, VFP support and the ptrace interface are 1438 handled appropriately by the kernel. 1439 1440 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1441 that you will only be able to execute AArch32 binaries that were compiled 1442 with page size aligned segments. 1443 1444 If you want to execute 32-bit userspace applications, say Y. 1445 1446if COMPAT 1447 1448config KUSER_HELPERS 1449 bool "Enable kuser helpers page for 32-bit applications" 1450 default y 1451 help 1452 Warning: disabling this option may break 32-bit user programs. 1453 1454 Provide kuser helpers to compat tasks. The kernel provides 1455 helper code to userspace in read only form at a fixed location 1456 to allow userspace to be independent of the CPU type fitted to 1457 the system. This permits binaries to be run on ARMv4 through 1458 to ARMv8 without modification. 1459 1460 See Documentation/arm/kernel_user_helpers.rst for details. 1461 1462 However, the fixed address nature of these helpers can be used 1463 by ROP (return orientated programming) authors when creating 1464 exploits. 1465 1466 If all of the binaries and libraries which run on your platform 1467 are built specifically for your platform, and make no use of 1468 these helpers, then you can turn this option off to hinder 1469 such exploits. However, in that case, if a binary or library 1470 relying on those helpers is run, it will not function correctly. 1471 1472 Say N here only if you are absolutely certain that you do not 1473 need these helpers; otherwise, the safe option is to say Y. 1474 1475config COMPAT_VDSO 1476 bool "Enable vDSO for 32-bit applications" 1477 depends on !CPU_BIG_ENDIAN 1478 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1479 select GENERIC_COMPAT_VDSO 1480 default y 1481 help 1482 Place in the process address space of 32-bit applications an 1483 ELF shared object providing fast implementations of gettimeofday 1484 and clock_gettime. 1485 1486 You must have a 32-bit build of glibc 2.22 or later for programs 1487 to seamlessly take advantage of this. 1488 1489config THUMB2_COMPAT_VDSO 1490 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1491 depends on COMPAT_VDSO 1492 default y 1493 help 1494 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1495 otherwise with '-marm'. 1496 1497menuconfig ARMV8_DEPRECATED 1498 bool "Emulate deprecated/obsolete ARMv8 instructions" 1499 depends on SYSCTL 1500 help 1501 Legacy software support may require certain instructions 1502 that have been deprecated or obsoleted in the architecture. 1503 1504 Enable this config to enable selective emulation of these 1505 features. 1506 1507 If unsure, say Y 1508 1509if ARMV8_DEPRECATED 1510 1511config SWP_EMULATION 1512 bool "Emulate SWP/SWPB instructions" 1513 help 1514 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1515 they are always undefined. Say Y here to enable software 1516 emulation of these instructions for userspace using LDXR/STXR. 1517 This feature can be controlled at runtime with the abi.swp 1518 sysctl which is disabled by default. 1519 1520 In some older versions of glibc [<=2.8] SWP is used during futex 1521 trylock() operations with the assumption that the code will not 1522 be preempted. This invalid assumption may be more likely to fail 1523 with SWP emulation enabled, leading to deadlock of the user 1524 application. 1525 1526 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1527 on an external transaction monitoring block called a global 1528 monitor to maintain update atomicity. If your system does not 1529 implement a global monitor, this option can cause programs that 1530 perform SWP operations to uncached memory to deadlock. 1531 1532 If unsure, say Y 1533 1534config CP15_BARRIER_EMULATION 1535 bool "Emulate CP15 Barrier instructions" 1536 help 1537 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1538 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1539 strongly recommended to use the ISB, DSB, and DMB 1540 instructions instead. 1541 1542 Say Y here to enable software emulation of these 1543 instructions for AArch32 userspace code. When this option is 1544 enabled, CP15 barrier usage is traced which can help 1545 identify software that needs updating. This feature can be 1546 controlled at runtime with the abi.cp15_barrier sysctl. 1547 1548 If unsure, say Y 1549 1550config SETEND_EMULATION 1551 bool "Emulate SETEND instruction" 1552 help 1553 The SETEND instruction alters the data-endianness of the 1554 AArch32 EL0, and is deprecated in ARMv8. 1555 1556 Say Y here to enable software emulation of the instruction 1557 for AArch32 userspace code. This feature can be controlled 1558 at runtime with the abi.setend sysctl. 1559 1560 Note: All the cpus on the system must have mixed endian support at EL0 1561 for this feature to be enabled. If a new CPU - which doesn't support mixed 1562 endian - is hotplugged in after this feature has been enabled, there could 1563 be unexpected results in the applications. 1564 1565 If unsure, say Y 1566endif 1567 1568endif 1569 1570menu "ARMv8.1 architectural features" 1571 1572config ARM64_HW_AFDBM 1573 bool "Support for hardware updates of the Access and Dirty page flags" 1574 default y 1575 help 1576 The ARMv8.1 architecture extensions introduce support for 1577 hardware updates of the access and dirty information in page 1578 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1579 capable processors, accesses to pages with PTE_AF cleared will 1580 set this bit instead of raising an access flag fault. 1581 Similarly, writes to read-only pages with the DBM bit set will 1582 clear the read-only bit (AP[2]) instead of raising a 1583 permission fault. 1584 1585 Kernels built with this configuration option enabled continue 1586 to work on pre-ARMv8.1 hardware and the performance impact is 1587 minimal. If unsure, say Y. 1588 1589config ARM64_PAN 1590 bool "Enable support for Privileged Access Never (PAN)" 1591 default y 1592 help 1593 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1594 prevents the kernel or hypervisor from accessing user-space (EL0) 1595 memory directly. 1596 1597 Choosing this option will cause any unprotected (not using 1598 copy_to_user et al) memory access to fail with a permission fault. 1599 1600 The feature is detected at runtime, and will remain as a 'nop' 1601 instruction if the cpu does not implement the feature. 1602 1603config AS_HAS_LDAPR 1604 def_bool $(as-instr,.arch_extension rcpc) 1605 1606config AS_HAS_LSE_ATOMICS 1607 def_bool $(as-instr,.arch_extension lse) 1608 1609config ARM64_LSE_ATOMICS 1610 bool 1611 default ARM64_USE_LSE_ATOMICS 1612 depends on AS_HAS_LSE_ATOMICS 1613 1614config ARM64_USE_LSE_ATOMICS 1615 bool "Atomic instructions" 1616 depends on JUMP_LABEL 1617 default y 1618 help 1619 As part of the Large System Extensions, ARMv8.1 introduces new 1620 atomic instructions that are designed specifically to scale in 1621 very large systems. 1622 1623 Say Y here to make use of these instructions for the in-kernel 1624 atomic routines. This incurs a small overhead on CPUs that do 1625 not support these instructions and requires the kernel to be 1626 built with binutils >= 2.25 in order for the new instructions 1627 to be used. 1628 1629endmenu 1630 1631menu "ARMv8.2 architectural features" 1632 1633config AS_HAS_ARMV8_2 1634 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1635 1636config AS_HAS_SHA3 1637 def_bool $(as-instr,.arch armv8.2-a+sha3) 1638 1639config ARM64_PMEM 1640 bool "Enable support for persistent memory" 1641 select ARCH_HAS_PMEM_API 1642 select ARCH_HAS_UACCESS_FLUSHCACHE 1643 help 1644 Say Y to enable support for the persistent memory API based on the 1645 ARMv8.2 DCPoP feature. 1646 1647 The feature is detected at runtime, and the kernel will use DC CVAC 1648 operations if DC CVAP is not supported (following the behaviour of 1649 DC CVAP itself if the system does not define a point of persistence). 1650 1651config ARM64_RAS_EXTN 1652 bool "Enable support for RAS CPU Extensions" 1653 default y 1654 help 1655 CPUs that support the Reliability, Availability and Serviceability 1656 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1657 errors, classify them and report them to software. 1658 1659 On CPUs with these extensions system software can use additional 1660 barriers to determine if faults are pending and read the 1661 classification from a new set of registers. 1662 1663 Selecting this feature will allow the kernel to use these barriers 1664 and access the new registers if the system supports the extension. 1665 Platform RAS features may additionally depend on firmware support. 1666 1667config ARM64_CNP 1668 bool "Enable support for Common Not Private (CNP) translations" 1669 default y 1670 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1671 help 1672 Common Not Private (CNP) allows translation table entries to 1673 be shared between different PEs in the same inner shareable 1674 domain, so the hardware can use this fact to optimise the 1675 caching of such entries in the TLB. 1676 1677 Selecting this option allows the CNP feature to be detected 1678 at runtime, and does not affect PEs that do not implement 1679 this feature. 1680 1681endmenu 1682 1683menu "ARMv8.3 architectural features" 1684 1685config ARM64_PTR_AUTH 1686 bool "Enable support for pointer authentication" 1687 default y 1688 help 1689 Pointer authentication (part of the ARMv8.3 Extensions) provides 1690 instructions for signing and authenticating pointers against secret 1691 keys, which can be used to mitigate Return Oriented Programming (ROP) 1692 and other attacks. 1693 1694 This option enables these instructions at EL0 (i.e. for userspace). 1695 Choosing this option will cause the kernel to initialise secret keys 1696 for each process at exec() time, with these keys being 1697 context-switched along with the process. 1698 1699 The feature is detected at runtime. If the feature is not present in 1700 hardware it will not be advertised to userspace/KVM guest nor will it 1701 be enabled. 1702 1703 If the feature is present on the boot CPU but not on a late CPU, then 1704 the late CPU will be parked. Also, if the boot CPU does not have 1705 address auth and the late CPU has then the late CPU will still boot 1706 but with the feature disabled. On such a system, this option should 1707 not be selected. 1708 1709config ARM64_PTR_AUTH_KERNEL 1710 bool "Use pointer authentication for kernel" 1711 default y 1712 depends on ARM64_PTR_AUTH 1713 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1714 # Modern compilers insert a .note.gnu.property section note for PAC 1715 # which is only understood by binutils starting with version 2.33.1. 1716 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1717 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1718 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1719 help 1720 If the compiler supports the -mbranch-protection or 1721 -msign-return-address flag (e.g. GCC 7 or later), then this option 1722 will cause the kernel itself to be compiled with return address 1723 protection. In this case, and if the target hardware is known to 1724 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1725 disabled with minimal loss of protection. 1726 1727 This feature works with FUNCTION_GRAPH_TRACER option only if 1728 DYNAMIC_FTRACE_WITH_REGS is enabled. 1729 1730config CC_HAS_BRANCH_PROT_PAC_RET 1731 # GCC 9 or later, clang 8 or later 1732 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1733 1734config CC_HAS_SIGN_RETURN_ADDRESS 1735 # GCC 7, 8 1736 def_bool $(cc-option,-msign-return-address=all) 1737 1738config AS_HAS_PAC 1739 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1740 1741config AS_HAS_CFI_NEGATE_RA_STATE 1742 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1743 1744endmenu 1745 1746menu "ARMv8.4 architectural features" 1747 1748config ARM64_AMU_EXTN 1749 bool "Enable support for the Activity Monitors Unit CPU extension" 1750 default y 1751 help 1752 The activity monitors extension is an optional extension introduced 1753 by the ARMv8.4 CPU architecture. This enables support for version 1 1754 of the activity monitors architecture, AMUv1. 1755 1756 To enable the use of this extension on CPUs that implement it, say Y. 1757 1758 Note that for architectural reasons, firmware _must_ implement AMU 1759 support when running on CPUs that present the activity monitors 1760 extension. The required support is present in: 1761 * Version 1.5 and later of the ARM Trusted Firmware 1762 1763 For kernels that have this configuration enabled but boot with broken 1764 firmware, you may need to say N here until the firmware is fixed. 1765 Otherwise you may experience firmware panics or lockups when 1766 accessing the counter registers. Even if you are not observing these 1767 symptoms, the values returned by the register reads might not 1768 correctly reflect reality. Most commonly, the value read will be 0, 1769 indicating that the counter is not enabled. 1770 1771config AS_HAS_ARMV8_4 1772 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1773 1774config ARM64_TLB_RANGE 1775 bool "Enable support for tlbi range feature" 1776 default y 1777 depends on AS_HAS_ARMV8_4 1778 help 1779 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1780 range of input addresses. 1781 1782 The feature introduces new assembly instructions, and they were 1783 support when binutils >= 2.30. 1784 1785endmenu 1786 1787menu "ARMv8.5 architectural features" 1788 1789config AS_HAS_ARMV8_5 1790 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1791 1792config ARM64_BTI 1793 bool "Branch Target Identification support" 1794 default y 1795 help 1796 Branch Target Identification (part of the ARMv8.5 Extensions) 1797 provides a mechanism to limit the set of locations to which computed 1798 branch instructions such as BR or BLR can jump. 1799 1800 To make use of BTI on CPUs that support it, say Y. 1801 1802 BTI is intended to provide complementary protection to other control 1803 flow integrity protection mechanisms, such as the Pointer 1804 authentication mechanism provided as part of the ARMv8.3 Extensions. 1805 For this reason, it does not make sense to enable this option without 1806 also enabling support for pointer authentication. Thus, when 1807 enabling this option you should also select ARM64_PTR_AUTH=y. 1808 1809 Userspace binaries must also be specifically compiled to make use of 1810 this mechanism. If you say N here or the hardware does not support 1811 BTI, such binaries can still run, but you get no additional 1812 enforcement of branch destinations. 1813 1814config ARM64_BTI_KERNEL 1815 bool "Use Branch Target Identification for kernel" 1816 default y 1817 depends on ARM64_BTI 1818 depends on ARM64_PTR_AUTH_KERNEL 1819 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1820 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1821 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1822 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1823 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1824 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1825 help 1826 Build the kernel with Branch Target Identification annotations 1827 and enable enforcement of this for kernel code. When this option 1828 is enabled and the system supports BTI all kernel code including 1829 modular code must have BTI enabled. 1830 1831config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1832 # GCC 9 or later, clang 8 or later 1833 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1834 1835config ARM64_E0PD 1836 bool "Enable support for E0PD" 1837 default y 1838 help 1839 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1840 that EL0 accesses made via TTBR1 always fault in constant time, 1841 providing similar benefits to KASLR as those provided by KPTI, but 1842 with lower overhead and without disrupting legitimate access to 1843 kernel memory such as SPE. 1844 1845 This option enables E0PD for TTBR1 where available. 1846 1847config ARCH_RANDOM 1848 bool "Enable support for random number generation" 1849 default y 1850 help 1851 Random number generation (part of the ARMv8.5 Extensions) 1852 provides a high bandwidth, cryptographically secure 1853 hardware random number generator. 1854 1855config ARM64_AS_HAS_MTE 1856 # Initial support for MTE went in binutils 2.32.0, checked with 1857 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1858 # as a late addition to the final architecture spec (LDGM/STGM) 1859 # is only supported in the newer 2.32.x and 2.33 binutils 1860 # versions, hence the extra "stgm" instruction check below. 1861 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1862 1863config ARM64_MTE 1864 bool "Memory Tagging Extension support" 1865 default y 1866 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1867 depends on AS_HAS_ARMV8_5 1868 depends on AS_HAS_LSE_ATOMICS 1869 # Required for tag checking in the uaccess routines 1870 depends on ARM64_PAN 1871 select ARCH_USES_HIGH_VMA_FLAGS 1872 help 1873 Memory Tagging (part of the ARMv8.5 Extensions) provides 1874 architectural support for run-time, always-on detection of 1875 various classes of memory error to aid with software debugging 1876 to eliminate vulnerabilities arising from memory-unsafe 1877 languages. 1878 1879 This option enables the support for the Memory Tagging 1880 Extension at EL0 (i.e. for userspace). 1881 1882 Selecting this option allows the feature to be detected at 1883 runtime. Any secondary CPU not implementing this feature will 1884 not be allowed a late bring-up. 1885 1886 Userspace binaries that want to use this feature must 1887 explicitly opt in. The mechanism for the userspace is 1888 described in: 1889 1890 Documentation/arm64/memory-tagging-extension.rst. 1891 1892endmenu 1893 1894menu "ARMv8.7 architectural features" 1895 1896config ARM64_EPAN 1897 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1898 default y 1899 depends on ARM64_PAN 1900 help 1901 Enhanced Privileged Access Never (EPAN) allows Privileged 1902 Access Never to be used with Execute-only mappings. 1903 1904 The feature is detected at runtime, and will remain disabled 1905 if the cpu does not implement the feature. 1906endmenu 1907 1908config ARM64_SVE 1909 bool "ARM Scalable Vector Extension support" 1910 default y 1911 help 1912 The Scalable Vector Extension (SVE) is an extension to the AArch64 1913 execution state which complements and extends the SIMD functionality 1914 of the base architecture to support much larger vectors and to enable 1915 additional vectorisation opportunities. 1916 1917 To enable use of this extension on CPUs that implement it, say Y. 1918 1919 On CPUs that support the SVE2 extensions, this option will enable 1920 those too. 1921 1922 Note that for architectural reasons, firmware _must_ implement SVE 1923 support when running on SVE capable hardware. The required support 1924 is present in: 1925 1926 * version 1.5 and later of the ARM Trusted Firmware 1927 * the AArch64 boot wrapper since commit 5e1261e08abf 1928 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1929 1930 For other firmware implementations, consult the firmware documentation 1931 or vendor. 1932 1933 If you need the kernel to boot on SVE-capable hardware with broken 1934 firmware, you may need to say N here until you get your firmware 1935 fixed. Otherwise, you may experience firmware panics or lockups when 1936 booting the kernel. If unsure and you are not observing these 1937 symptoms, you should assume that it is safe to say Y. 1938 1939config ARM64_MODULE_PLTS 1940 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1941 depends on MODULES 1942 select HAVE_MOD_ARCH_SPECIFIC 1943 help 1944 Allocate PLTs when loading modules so that jumps and calls whose 1945 targets are too far away for their relative offsets to be encoded 1946 in the instructions themselves can be bounced via veneers in the 1947 module's PLT. This allows modules to be allocated in the generic 1948 vmalloc area after the dedicated module memory area has been 1949 exhausted. 1950 1951 When running with address space randomization (KASLR), the module 1952 region itself may be too far away for ordinary relative jumps and 1953 calls, and so in that case, module PLTs are required and cannot be 1954 disabled. 1955 1956 Specific errata workaround(s) might also force module PLTs to be 1957 enabled (ARM64_ERRATUM_843419). 1958 1959config ARM64_PSEUDO_NMI 1960 bool "Support for NMI-like interrupts" 1961 select ARM_GIC_V3 1962 help 1963 Adds support for mimicking Non-Maskable Interrupts through the use of 1964 GIC interrupt priority. This support requires version 3 or later of 1965 ARM GIC. 1966 1967 This high priority configuration for interrupts needs to be 1968 explicitly enabled by setting the kernel parameter 1969 "irqchip.gicv3_pseudo_nmi" to 1. 1970 1971 If unsure, say N 1972 1973if ARM64_PSEUDO_NMI 1974config ARM64_DEBUG_PRIORITY_MASKING 1975 bool "Debug interrupt priority masking" 1976 help 1977 This adds runtime checks to functions enabling/disabling 1978 interrupts when using priority masking. The additional checks verify 1979 the validity of ICC_PMR_EL1 when calling concerned functions. 1980 1981 If unsure, say N 1982endif 1983 1984config RELOCATABLE 1985 bool "Build a relocatable kernel image" if EXPERT 1986 select ARCH_HAS_RELR 1987 default y 1988 help 1989 This builds the kernel as a Position Independent Executable (PIE), 1990 which retains all relocation metadata required to relocate the 1991 kernel binary at runtime to a different virtual address than the 1992 address it was linked at. 1993 Since AArch64 uses the RELA relocation format, this requires a 1994 relocation pass at runtime even if the kernel is loaded at the 1995 same address it was linked at. 1996 1997config RANDOMIZE_BASE 1998 bool "Randomize the address of the kernel image" 1999 select ARM64_MODULE_PLTS if MODULES 2000 select RELOCATABLE 2001 help 2002 Randomizes the virtual address at which the kernel image is 2003 loaded, as a security feature that deters exploit attempts 2004 relying on knowledge of the location of kernel internals. 2005 2006 It is the bootloader's job to provide entropy, by passing a 2007 random u64 value in /chosen/kaslr-seed at kernel entry. 2008 2009 When booting via the UEFI stub, it will invoke the firmware's 2010 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2011 to the kernel proper. In addition, it will randomise the physical 2012 location of the kernel Image as well. 2013 2014 If unsure, say N. 2015 2016config RANDOMIZE_MODULE_REGION_FULL 2017 bool "Randomize the module region over a 2 GB range" 2018 depends on RANDOMIZE_BASE 2019 default y 2020 help 2021 Randomizes the location of the module region inside a 2 GB window 2022 covering the core kernel. This way, it is less likely for modules 2023 to leak information about the location of core kernel data structures 2024 but it does imply that function calls between modules and the core 2025 kernel will need to be resolved via veneers in the module PLT. 2026 2027 When this option is not set, the module region will be randomized over 2028 a limited range that contains the [_stext, _etext] interval of the 2029 core kernel, so branch relocations are almost always in range unless 2030 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2031 particular case of region exhaustion, modules might be able to fall 2032 back to a larger 2GB area. 2033 2034config CC_HAVE_STACKPROTECTOR_SYSREG 2035 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2036 2037config STACKPROTECTOR_PER_TASK 2038 def_bool y 2039 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2040 2041endmenu 2042 2043menu "Boot options" 2044 2045config ARM64_ACPI_PARKING_PROTOCOL 2046 bool "Enable support for the ARM64 ACPI parking protocol" 2047 depends on ACPI 2048 help 2049 Enable support for the ARM64 ACPI parking protocol. If disabled 2050 the kernel will not allow booting through the ARM64 ACPI parking 2051 protocol even if the corresponding data is present in the ACPI 2052 MADT table. 2053 2054config CMDLINE 2055 string "Default kernel command string" 2056 default "" 2057 help 2058 Provide a set of default command-line options at build time by 2059 entering them here. As a minimum, you should specify the the 2060 root device (e.g. root=/dev/nfs). 2061 2062choice 2063 prompt "Kernel command line type" if CMDLINE != "" 2064 default CMDLINE_FROM_BOOTLOADER 2065 help 2066 Choose how the kernel will handle the provided default kernel 2067 command line string. 2068 2069config CMDLINE_FROM_BOOTLOADER 2070 bool "Use bootloader kernel arguments if available" 2071 help 2072 Uses the command-line options passed by the boot loader. If 2073 the boot loader doesn't provide any, the default kernel command 2074 string provided in CMDLINE will be used. 2075 2076config CMDLINE_FORCE 2077 bool "Always use the default kernel command string" 2078 help 2079 Always use the default kernel command string, even if the boot 2080 loader passes other arguments to the kernel. 2081 This is useful if you cannot or don't want to change the 2082 command-line options your boot loader passes to the kernel. 2083 2084endchoice 2085 2086config EFI_STUB 2087 bool 2088 2089config EFI 2090 bool "UEFI runtime support" 2091 depends on OF && !CPU_BIG_ENDIAN 2092 depends on KERNEL_MODE_NEON 2093 select ARCH_SUPPORTS_ACPI 2094 select LIBFDT 2095 select UCS2_STRING 2096 select EFI_PARAMS_FROM_FDT 2097 select EFI_RUNTIME_WRAPPERS 2098 select EFI_STUB 2099 select EFI_GENERIC_STUB 2100 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2101 default y 2102 help 2103 This option provides support for runtime services provided 2104 by UEFI firmware (such as non-volatile variables, realtime 2105 clock, and platform reset). A UEFI stub is also provided to 2106 allow the kernel to be booted as an EFI application. This 2107 is only useful on systems that have UEFI firmware. 2108 2109config DMI 2110 bool "Enable support for SMBIOS (DMI) tables" 2111 depends on EFI 2112 default y 2113 help 2114 This enables SMBIOS/DMI feature for systems. 2115 2116 This option is only useful on systems that have UEFI firmware. 2117 However, even with this option, the resultant kernel should 2118 continue to boot on existing non-UEFI platforms. 2119 2120endmenu 2121 2122config SYSVIPC_COMPAT 2123 def_bool y 2124 depends on COMPAT && SYSVIPC 2125 2126menu "Power management options" 2127 2128source "kernel/power/Kconfig" 2129 2130config ARCH_HIBERNATION_POSSIBLE 2131 def_bool y 2132 depends on CPU_PM 2133 2134config ARCH_HIBERNATION_HEADER 2135 def_bool y 2136 depends on HIBERNATION 2137 2138config ARCH_SUSPEND_POSSIBLE 2139 def_bool y 2140 2141endmenu 2142 2143menu "CPU Power Management" 2144 2145source "drivers/cpuidle/Kconfig" 2146 2147source "drivers/cpufreq/Kconfig" 2148 2149endmenu 2150 2151source "drivers/acpi/Kconfig" 2152 2153source "arch/arm64/kvm/Kconfig" 2154 2155if CRYPTO 2156source "arch/arm64/crypto/Kconfig" 2157endif 2158