1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_IORT if ACPI 9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 10 select ACPI_MCFG if (ACPI && PCI) 11 select ACPI_SPCR_TABLE if ACPI 12 select ACPI_PPTT if ACPI 13 select ARCH_HAS_DEBUG_WX 14 select ARCH_BINFMT_ELF_EXTRA_PHDRS 15 select ARCH_BINFMT_ELF_STATE 16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CURRENT_STACK_POINTER 24 select ARCH_HAS_DEBUG_VIRTUAL 25 select ARCH_HAS_DEBUG_VM_PGTABLE 26 select ARCH_HAS_DMA_PREP_COHERENT 27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 28 select ARCH_HAS_FAST_MULTIPLIER 29 select ARCH_HAS_FORTIFY_SOURCE 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_HAS_GIGANTIC_PAGE 32 select ARCH_HAS_KCOV 33 select ARCH_HAS_KEEPINITRD 34 select ARCH_HAS_MEMBARRIER_SYNC_CORE 35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 37 select ARCH_HAS_PTE_DEVMAP 38 select ARCH_HAS_PTE_SPECIAL 39 select ARCH_HAS_HW_PTE_YOUNG 40 select ARCH_HAS_SETUP_DMA_OPS 41 select ARCH_HAS_SET_DIRECT_MAP 42 select ARCH_HAS_SET_MEMORY 43 select ARCH_STACKWALK 44 select ARCH_HAS_STRICT_KERNEL_RWX 45 select ARCH_HAS_STRICT_MODULE_RWX 46 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 47 select ARCH_HAS_SYNC_DMA_FOR_CPU 48 select ARCH_HAS_SYSCALL_WRAPPER 49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 50 select ARCH_HAS_ZONE_DMA_SET if EXPERT 51 select ARCH_HAVE_ELF_PROT 52 select ARCH_HAVE_NMI_SAFE_CMPXCHG 53 select ARCH_HAVE_TRACE_MMIO_ACCESS 54 select ARCH_INLINE_READ_LOCK if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 80 select ARCH_KEEP_MEMBLOCK 81 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 82 select ARCH_USE_CMPXCHG_LOCKREF 83 select ARCH_USE_GNU_PROPERTY 84 select ARCH_USE_MEMTEST 85 select ARCH_USE_QUEUED_RWLOCKS 86 select ARCH_USE_QUEUED_SPINLOCKS 87 select ARCH_USE_SYM_ANNOTATIONS 88 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 89 select ARCH_SUPPORTS_HUGETLBFS 90 select ARCH_SUPPORTS_MEMORY_FAILURE 91 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 92 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 93 select ARCH_SUPPORTS_LTO_CLANG_THIN 94 select ARCH_SUPPORTS_CFI_CLANG 95 select ARCH_SUPPORTS_ATOMIC_RMW 96 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 97 select ARCH_SUPPORTS_NUMA_BALANCING 98 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 99 select ARCH_SUPPORTS_PER_VMA_LOCK 100 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 101 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 102 select ARCH_WANT_DEFAULT_BPF_JIT 103 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 104 select ARCH_WANT_FRAME_POINTERS 105 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 106 select ARCH_WANT_LD_ORPHAN_WARN 107 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 108 select ARCH_WANTS_NO_INSTR 109 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 110 select ARCH_HAS_UBSAN 111 select ARM_AMBA 112 select ARM_ARCH_TIMER 113 select ARM_GIC 114 select AUDIT_ARCH_COMPAT_GENERIC 115 select ARM_GIC_V2M if PCI 116 select ARM_GIC_V3 117 select ARM_GIC_V3_ITS if PCI 118 select ARM_PSCI_FW 119 select BUILDTIME_TABLE_SORT 120 select CLONE_BACKWARDS 121 select COMMON_CLK 122 select CPU_PM if (SUSPEND || CPU_IDLE) 123 select CPUMASK_OFFSTACK if NR_CPUS > 256 124 select CRC32 125 select DCACHE_WORD_ACCESS 126 select DYNAMIC_FTRACE if FUNCTION_TRACER 127 select DMA_BOUNCE_UNALIGNED_KMALLOC 128 select DMA_DIRECT_REMAP 129 select EDAC_SUPPORT 130 select FRAME_POINTER 131 select FUNCTION_ALIGNMENT_4B 132 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 133 select GENERIC_ALLOCATOR 134 select GENERIC_ARCH_TOPOLOGY 135 select GENERIC_CLOCKEVENTS_BROADCAST 136 select GENERIC_CPU_AUTOPROBE 137 select GENERIC_CPU_DEVICES 138 select GENERIC_CPU_VULNERABILITIES 139 select GENERIC_EARLY_IOREMAP 140 select GENERIC_IDLE_POLL_SETUP 141 select GENERIC_IOREMAP 142 select GENERIC_IRQ_IPI 143 select GENERIC_IRQ_PROBE 144 select GENERIC_IRQ_SHOW 145 select GENERIC_IRQ_SHOW_LEVEL 146 select GENERIC_LIB_DEVMEM_IS_ALLOWED 147 select GENERIC_PCI_IOMAP 148 select GENERIC_PTDUMP 149 select GENERIC_SCHED_CLOCK 150 select GENERIC_SMP_IDLE_THREAD 151 select GENERIC_TIME_VSYSCALL 152 select GENERIC_GETTIMEOFDAY 153 select GENERIC_VDSO_TIME_NS 154 select HARDIRQS_SW_RESEND 155 select HAS_IOPORT 156 select HAVE_MOVE_PMD 157 select HAVE_MOVE_PUD 158 select HAVE_PCI 159 select HAVE_ACPI_APEI if (ACPI && EFI) 160 select HAVE_ALIGNED_STRUCT_PAGE 161 select HAVE_ARCH_AUDITSYSCALL 162 select HAVE_ARCH_BITREVERSE 163 select HAVE_ARCH_COMPILER_H 164 select HAVE_ARCH_HUGE_VMALLOC 165 select HAVE_ARCH_HUGE_VMAP 166 select HAVE_ARCH_JUMP_LABEL 167 select HAVE_ARCH_JUMP_LABEL_RELATIVE 168 select HAVE_ARCH_KASAN 169 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 170 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 171 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 172 # Some instrumentation may be unsound, hence EXPERT 173 select HAVE_ARCH_KCSAN if EXPERT 174 select HAVE_ARCH_KFENCE 175 select HAVE_ARCH_KGDB 176 select HAVE_ARCH_MMAP_RND_BITS 177 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 178 select HAVE_ARCH_PREL32_RELOCATIONS 179 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 180 select HAVE_ARCH_SECCOMP_FILTER 181 select HAVE_ARCH_STACKLEAK 182 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 183 select HAVE_ARCH_TRACEHOOK 184 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 185 select HAVE_ARCH_VMAP_STACK 186 select HAVE_ARM_SMCCC 187 select HAVE_ASM_MODVERSIONS 188 select HAVE_EBPF_JIT 189 select HAVE_C_RECORDMCOUNT 190 select HAVE_CMPXCHG_DOUBLE 191 select HAVE_CMPXCHG_LOCAL 192 select HAVE_CONTEXT_TRACKING_USER 193 select HAVE_DEBUG_KMEMLEAK 194 select HAVE_DMA_CONTIGUOUS 195 select HAVE_DYNAMIC_FTRACE 196 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 197 if $(cc-option,-fpatchable-function-entry=2) 198 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 199 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 200 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 201 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 202 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 203 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 204 if DYNAMIC_FTRACE_WITH_ARGS 205 select HAVE_SAMPLE_FTRACE_DIRECT 206 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 207 select HAVE_EFFICIENT_UNALIGNED_ACCESS 208 select HAVE_GUP_FAST 209 select HAVE_FTRACE_MCOUNT_RECORD 210 select HAVE_FUNCTION_TRACER 211 select HAVE_FUNCTION_ERROR_INJECTION 212 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 213 select HAVE_FUNCTION_GRAPH_TRACER 214 select HAVE_GCC_PLUGINS 215 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 216 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 217 select HAVE_HW_BREAKPOINT if PERF_EVENTS 218 select HAVE_IOREMAP_PROT 219 select HAVE_IRQ_TIME_ACCOUNTING 220 select HAVE_MOD_ARCH_SPECIFIC 221 select HAVE_NMI 222 select HAVE_PERF_EVENTS 223 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 224 select HAVE_PERF_REGS 225 select HAVE_PERF_USER_STACK_DUMP 226 select HAVE_PREEMPT_DYNAMIC_KEY 227 select HAVE_REGS_AND_STACK_ACCESS_API 228 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 229 select HAVE_FUNCTION_ARG_ACCESS_API 230 select MMU_GATHER_RCU_TABLE_FREE 231 select HAVE_RSEQ 232 select HAVE_RUST if CPU_LITTLE_ENDIAN 233 select HAVE_STACKPROTECTOR 234 select HAVE_SYSCALL_TRACEPOINTS 235 select HAVE_KPROBES 236 select HAVE_KRETPROBES 237 select HAVE_GENERIC_VDSO 238 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 239 select IRQ_DOMAIN 240 select IRQ_FORCED_THREADING 241 select KASAN_VMALLOC if KASAN 242 select LOCK_MM_AND_FIND_VMA 243 select MODULES_USE_ELF_RELA 244 select NEED_DMA_MAP_STATE 245 select NEED_SG_DMA_LENGTH 246 select OF 247 select OF_EARLY_FLATTREE 248 select PCI_DOMAINS_GENERIC if PCI 249 select PCI_ECAM if (ACPI && PCI) 250 select PCI_SYSCALL if PCI 251 select POWER_RESET 252 select POWER_SUPPLY 253 select SPARSE_IRQ 254 select SWIOTLB 255 select SYSCTL_EXCEPTION_TRACE 256 select THREAD_INFO_IN_TASK 257 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 258 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 259 select TRACE_IRQFLAGS_SUPPORT 260 select TRACE_IRQFLAGS_NMI_SUPPORT 261 select HAVE_SOFTIRQ_ON_OWN_STACK 262 select USER_STACKTRACE_SUPPORT 263 help 264 ARM 64-bit (AArch64) Linux support. 265 266config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 267 def_bool CC_IS_CLANG 268 # https://github.com/ClangBuiltLinux/linux/issues/1507 269 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 270 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 271 272config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 273 def_bool CC_IS_GCC 274 depends on $(cc-option,-fpatchable-function-entry=2) 275 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 276 277config 64BIT 278 def_bool y 279 280config MMU 281 def_bool y 282 283config ARM64_CONT_PTE_SHIFT 284 int 285 default 5 if PAGE_SIZE_64KB 286 default 7 if PAGE_SIZE_16KB 287 default 4 288 289config ARM64_CONT_PMD_SHIFT 290 int 291 default 5 if PAGE_SIZE_64KB 292 default 5 if PAGE_SIZE_16KB 293 default 4 294 295config ARCH_MMAP_RND_BITS_MIN 296 default 14 if PAGE_SIZE_64KB 297 default 16 if PAGE_SIZE_16KB 298 default 18 299 300# max bits determined by the following formula: 301# VA_BITS - PAGE_SHIFT - 3 302config ARCH_MMAP_RND_BITS_MAX 303 default 19 if ARM64_VA_BITS=36 304 default 24 if ARM64_VA_BITS=39 305 default 27 if ARM64_VA_BITS=42 306 default 30 if ARM64_VA_BITS=47 307 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 308 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 309 default 33 if ARM64_VA_BITS=48 310 default 14 if ARM64_64K_PAGES 311 default 16 if ARM64_16K_PAGES 312 default 18 313 314config ARCH_MMAP_RND_COMPAT_BITS_MIN 315 default 7 if ARM64_64K_PAGES 316 default 9 if ARM64_16K_PAGES 317 default 11 318 319config ARCH_MMAP_RND_COMPAT_BITS_MAX 320 default 16 321 322config NO_IOPORT_MAP 323 def_bool y if !PCI 324 325config STACKTRACE_SUPPORT 326 def_bool y 327 328config ILLEGAL_POINTER_VALUE 329 hex 330 default 0xdead000000000000 331 332config LOCKDEP_SUPPORT 333 def_bool y 334 335config GENERIC_BUG 336 def_bool y 337 depends on BUG 338 339config GENERIC_BUG_RELATIVE_POINTERS 340 def_bool y 341 depends on GENERIC_BUG 342 343config GENERIC_HWEIGHT 344 def_bool y 345 346config GENERIC_CSUM 347 def_bool y 348 349config GENERIC_CALIBRATE_DELAY 350 def_bool y 351 352config SMP 353 def_bool y 354 355config KERNEL_MODE_NEON 356 def_bool y 357 358config FIX_EARLYCON_MEM 359 def_bool y 360 361config PGTABLE_LEVELS 362 int 363 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 364 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 365 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 366 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 367 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 368 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 369 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 370 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 371 372config ARCH_SUPPORTS_UPROBES 373 def_bool y 374 375config ARCH_PROC_KCORE_TEXT 376 def_bool y 377 378config BROKEN_GAS_INST 379 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 380 381config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 382 bool 383 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0 384 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 385 default y if CC_IS_CLANG 386 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 387 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 388 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 389 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 390 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 391 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 392 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 393 default n 394 395config KASAN_SHADOW_OFFSET 396 hex 397 depends on KASAN_GENERIC || KASAN_SW_TAGS 398 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 399 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 400 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 401 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 402 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 403 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 404 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 405 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 406 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 407 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 408 default 0xffffffffffffffff 409 410config UNWIND_TABLES 411 bool 412 413source "arch/arm64/Kconfig.platforms" 414 415menu "Kernel Features" 416 417menu "ARM errata workarounds via the alternatives framework" 418 419config AMPERE_ERRATUM_AC03_CPU_38 420 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 421 default y 422 help 423 This option adds an alternative code sequence to work around Ampere 424 erratum AC03_CPU_38 on AmpereOne. 425 426 The affected design reports FEAT_HAFDBS as not implemented in 427 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 428 as required by the architecture. The unadvertised HAFDBS 429 implementation suffers from an additional erratum where hardware 430 A/D updates can occur after a PTE has been marked invalid. 431 432 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 433 which avoids enabling unadvertised hardware Access Flag management 434 at stage-2. 435 436 If unsure, say Y. 437 438config ARM64_WORKAROUND_CLEAN_CACHE 439 bool 440 441config ARM64_ERRATUM_826319 442 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 443 default y 444 select ARM64_WORKAROUND_CLEAN_CACHE 445 help 446 This option adds an alternative code sequence to work around ARM 447 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 448 AXI master interface and an L2 cache. 449 450 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 451 and is unable to accept a certain write via this interface, it will 452 not progress on read data presented on the read data channel and the 453 system can deadlock. 454 455 The workaround promotes data cache clean instructions to 456 data cache clean-and-invalidate. 457 Please note that this does not necessarily enable the workaround, 458 as it depends on the alternative framework, which will only patch 459 the kernel if an affected CPU is detected. 460 461 If unsure, say Y. 462 463config ARM64_ERRATUM_827319 464 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 465 default y 466 select ARM64_WORKAROUND_CLEAN_CACHE 467 help 468 This option adds an alternative code sequence to work around ARM 469 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 470 master interface and an L2 cache. 471 472 Under certain conditions this erratum can cause a clean line eviction 473 to occur at the same time as another transaction to the same address 474 on the AMBA 5 CHI interface, which can cause data corruption if the 475 interconnect reorders the two transactions. 476 477 The workaround promotes data cache clean instructions to 478 data cache clean-and-invalidate. 479 Please note that this does not necessarily enable the workaround, 480 as it depends on the alternative framework, which will only patch 481 the kernel if an affected CPU is detected. 482 483 If unsure, say Y. 484 485config ARM64_ERRATUM_824069 486 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 487 default y 488 select ARM64_WORKAROUND_CLEAN_CACHE 489 help 490 This option adds an alternative code sequence to work around ARM 491 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 492 to a coherent interconnect. 493 494 If a Cortex-A53 processor is executing a store or prefetch for 495 write instruction at the same time as a processor in another 496 cluster is executing a cache maintenance operation to the same 497 address, then this erratum might cause a clean cache line to be 498 incorrectly marked as dirty. 499 500 The workaround promotes data cache clean instructions to 501 data cache clean-and-invalidate. 502 Please note that this option does not necessarily enable the 503 workaround, as it depends on the alternative framework, which will 504 only patch the kernel if an affected CPU is detected. 505 506 If unsure, say Y. 507 508config ARM64_ERRATUM_819472 509 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 510 default y 511 select ARM64_WORKAROUND_CLEAN_CACHE 512 help 513 This option adds an alternative code sequence to work around ARM 514 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 515 present when it is connected to a coherent interconnect. 516 517 If the processor is executing a load and store exclusive sequence at 518 the same time as a processor in another cluster is executing a cache 519 maintenance operation to the same address, then this erratum might 520 cause data corruption. 521 522 The workaround promotes data cache clean instructions to 523 data cache clean-and-invalidate. 524 Please note that this does not necessarily enable the workaround, 525 as it depends on the alternative framework, which will only patch 526 the kernel if an affected CPU is detected. 527 528 If unsure, say Y. 529 530config ARM64_ERRATUM_832075 531 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 532 default y 533 help 534 This option adds an alternative code sequence to work around ARM 535 erratum 832075 on Cortex-A57 parts up to r1p2. 536 537 Affected Cortex-A57 parts might deadlock when exclusive load/store 538 instructions to Write-Back memory are mixed with Device loads. 539 540 The workaround is to promote device loads to use Load-Acquire 541 semantics. 542 Please note that this does not necessarily enable the workaround, 543 as it depends on the alternative framework, which will only patch 544 the kernel if an affected CPU is detected. 545 546 If unsure, say Y. 547 548config ARM64_ERRATUM_834220 549 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 550 depends on KVM 551 help 552 This option adds an alternative code sequence to work around ARM 553 erratum 834220 on Cortex-A57 parts up to r1p2. 554 555 Affected Cortex-A57 parts might report a Stage 2 translation 556 fault as the result of a Stage 1 fault for load crossing a 557 page boundary when there is a permission or device memory 558 alignment fault at Stage 1 and a translation fault at Stage 2. 559 560 The workaround is to verify that the Stage 1 translation 561 doesn't generate a fault before handling the Stage 2 fault. 562 Please note that this does not necessarily enable the workaround, 563 as it depends on the alternative framework, which will only patch 564 the kernel if an affected CPU is detected. 565 566 If unsure, say N. 567 568config ARM64_ERRATUM_1742098 569 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 570 depends on COMPAT 571 default y 572 help 573 This option removes the AES hwcap for aarch32 user-space to 574 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 575 576 Affected parts may corrupt the AES state if an interrupt is 577 taken between a pair of AES instructions. These instructions 578 are only present if the cryptography extensions are present. 579 All software should have a fallback implementation for CPUs 580 that don't implement the cryptography extensions. 581 582 If unsure, say Y. 583 584config ARM64_ERRATUM_845719 585 bool "Cortex-A53: 845719: a load might read incorrect data" 586 depends on COMPAT 587 default y 588 help 589 This option adds an alternative code sequence to work around ARM 590 erratum 845719 on Cortex-A53 parts up to r0p4. 591 592 When running a compat (AArch32) userspace on an affected Cortex-A53 593 part, a load at EL0 from a virtual address that matches the bottom 32 594 bits of the virtual address used by a recent load at (AArch64) EL1 595 might return incorrect data. 596 597 The workaround is to write the contextidr_el1 register on exception 598 return to a 32-bit task. 599 Please note that this does not necessarily enable the workaround, 600 as it depends on the alternative framework, which will only patch 601 the kernel if an affected CPU is detected. 602 603 If unsure, say Y. 604 605config ARM64_ERRATUM_843419 606 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 607 default y 608 help 609 This option links the kernel with '--fix-cortex-a53-843419' and 610 enables PLT support to replace certain ADRP instructions, which can 611 cause subsequent memory accesses to use an incorrect address on 612 Cortex-A53 parts up to r0p4. 613 614 If unsure, say Y. 615 616config ARM64_LD_HAS_FIX_ERRATUM_843419 617 def_bool $(ld-option,--fix-cortex-a53-843419) 618 619config ARM64_ERRATUM_1024718 620 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 621 default y 622 help 623 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 624 625 Affected Cortex-A55 cores (all revisions) could cause incorrect 626 update of the hardware dirty bit when the DBM/AP bits are updated 627 without a break-before-make. The workaround is to disable the usage 628 of hardware DBM locally on the affected cores. CPUs not affected by 629 this erratum will continue to use the feature. 630 631 If unsure, say Y. 632 633config ARM64_ERRATUM_1418040 634 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 635 default y 636 depends on COMPAT 637 help 638 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 639 errata 1188873 and 1418040. 640 641 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 642 cause register corruption when accessing the timer registers 643 from AArch32 userspace. 644 645 If unsure, say Y. 646 647config ARM64_WORKAROUND_SPECULATIVE_AT 648 bool 649 650config ARM64_ERRATUM_1165522 651 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 652 default y 653 select ARM64_WORKAROUND_SPECULATIVE_AT 654 help 655 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 656 657 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 658 corrupted TLBs by speculating an AT instruction during a guest 659 context switch. 660 661 If unsure, say Y. 662 663config ARM64_ERRATUM_1319367 664 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 665 default y 666 select ARM64_WORKAROUND_SPECULATIVE_AT 667 help 668 This option adds work arounds for ARM Cortex-A57 erratum 1319537 669 and A72 erratum 1319367 670 671 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 672 speculating an AT instruction during a guest context switch. 673 674 If unsure, say Y. 675 676config ARM64_ERRATUM_1530923 677 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 678 default y 679 select ARM64_WORKAROUND_SPECULATIVE_AT 680 help 681 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 682 683 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 684 corrupted TLBs by speculating an AT instruction during a guest 685 context switch. 686 687 If unsure, say Y. 688 689config ARM64_WORKAROUND_REPEAT_TLBI 690 bool 691 692config ARM64_ERRATUM_2441007 693 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 694 select ARM64_WORKAROUND_REPEAT_TLBI 695 help 696 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 697 698 Under very rare circumstances, affected Cortex-A55 CPUs 699 may not handle a race between a break-before-make sequence on one 700 CPU, and another CPU accessing the same page. This could allow a 701 store to a page that has been unmapped. 702 703 Work around this by adding the affected CPUs to the list that needs 704 TLB sequences to be done twice. 705 706 If unsure, say N. 707 708config ARM64_ERRATUM_1286807 709 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 710 select ARM64_WORKAROUND_REPEAT_TLBI 711 help 712 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 713 714 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 715 address for a cacheable mapping of a location is being 716 accessed by a core while another core is remapping the virtual 717 address to a new physical page using the recommended 718 break-before-make sequence, then under very rare circumstances 719 TLBI+DSB completes before a read using the translation being 720 invalidated has been observed by other observers. The 721 workaround repeats the TLBI+DSB operation. 722 723 If unsure, say N. 724 725config ARM64_ERRATUM_1463225 726 bool "Cortex-A76: Software Step might prevent interrupt recognition" 727 default y 728 help 729 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 730 731 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 732 of a system call instruction (SVC) can prevent recognition of 733 subsequent interrupts when software stepping is disabled in the 734 exception handler of the system call and either kernel debugging 735 is enabled or VHE is in use. 736 737 Work around the erratum by triggering a dummy step exception 738 when handling a system call from a task that is being stepped 739 in a VHE configuration of the kernel. 740 741 If unsure, say Y. 742 743config ARM64_ERRATUM_1542419 744 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 745 help 746 This option adds a workaround for ARM Neoverse-N1 erratum 747 1542419. 748 749 Affected Neoverse-N1 cores could execute a stale instruction when 750 modified by another CPU. The workaround depends on a firmware 751 counterpart. 752 753 Workaround the issue by hiding the DIC feature from EL0. This 754 forces user-space to perform cache maintenance. 755 756 If unsure, say N. 757 758config ARM64_ERRATUM_1508412 759 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 760 default y 761 help 762 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 763 764 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 765 of a store-exclusive or read of PAR_EL1 and a load with device or 766 non-cacheable memory attributes. The workaround depends on a firmware 767 counterpart. 768 769 KVM guests must also have the workaround implemented or they can 770 deadlock the system. 771 772 Work around the issue by inserting DMB SY barriers around PAR_EL1 773 register reads and warning KVM users. The DMB barrier is sufficient 774 to prevent a speculative PAR_EL1 read. 775 776 If unsure, say Y. 777 778config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 779 bool 780 781config ARM64_ERRATUM_2051678 782 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 783 default y 784 help 785 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 786 Affected Cortex-A510 might not respect the ordering rules for 787 hardware update of the page table's dirty bit. The workaround 788 is to not enable the feature on affected CPUs. 789 790 If unsure, say Y. 791 792config ARM64_ERRATUM_2077057 793 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 794 default y 795 help 796 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 797 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 798 expected, but a Pointer Authentication trap is taken instead. The 799 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 800 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 801 802 This can only happen when EL2 is stepping EL1. 803 804 When these conditions occur, the SPSR_EL2 value is unchanged from the 805 previous guest entry, and can be restored from the in-memory copy. 806 807 If unsure, say Y. 808 809config ARM64_ERRATUM_2658417 810 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 811 default y 812 help 813 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 814 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 815 BFMMLA or VMMLA instructions in rare circumstances when a pair of 816 A510 CPUs are using shared neon hardware. As the sharing is not 817 discoverable by the kernel, hide the BF16 HWCAP to indicate that 818 user-space should not be using these instructions. 819 820 If unsure, say Y. 821 822config ARM64_ERRATUM_2119858 823 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 824 default y 825 depends on CORESIGHT_TRBE 826 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 827 help 828 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 829 830 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 831 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 832 the event of a WRAP event. 833 834 Work around the issue by always making sure we move the TRBPTR_EL1 by 835 256 bytes before enabling the buffer and filling the first 256 bytes of 836 the buffer with ETM ignore packets upon disabling. 837 838 If unsure, say Y. 839 840config ARM64_ERRATUM_2139208 841 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 842 default y 843 depends on CORESIGHT_TRBE 844 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 845 help 846 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 847 848 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 849 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 850 the event of a WRAP event. 851 852 Work around the issue by always making sure we move the TRBPTR_EL1 by 853 256 bytes before enabling the buffer and filling the first 256 bytes of 854 the buffer with ETM ignore packets upon disabling. 855 856 If unsure, say Y. 857 858config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 859 bool 860 861config ARM64_ERRATUM_2054223 862 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 863 default y 864 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 865 help 866 Enable workaround for ARM Cortex-A710 erratum 2054223 867 868 Affected cores may fail to flush the trace data on a TSB instruction, when 869 the PE is in trace prohibited state. This will cause losing a few bytes 870 of the trace cached. 871 872 Workaround is to issue two TSB consecutively on affected cores. 873 874 If unsure, say Y. 875 876config ARM64_ERRATUM_2067961 877 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 878 default y 879 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 880 help 881 Enable workaround for ARM Neoverse-N2 erratum 2067961 882 883 Affected cores may fail to flush the trace data on a TSB instruction, when 884 the PE is in trace prohibited state. This will cause losing a few bytes 885 of the trace cached. 886 887 Workaround is to issue two TSB consecutively on affected cores. 888 889 If unsure, say Y. 890 891config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 892 bool 893 894config ARM64_ERRATUM_2253138 895 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 896 depends on CORESIGHT_TRBE 897 default y 898 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 899 help 900 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 901 902 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 903 for TRBE. Under some conditions, the TRBE might generate a write to the next 904 virtually addressed page following the last page of the TRBE address space 905 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 906 907 Work around this in the driver by always making sure that there is a 908 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 909 910 If unsure, say Y. 911 912config ARM64_ERRATUM_2224489 913 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 914 depends on CORESIGHT_TRBE 915 default y 916 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 917 help 918 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 919 920 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 921 for TRBE. Under some conditions, the TRBE might generate a write to the next 922 virtually addressed page following the last page of the TRBE address space 923 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 924 925 Work around this in the driver by always making sure that there is a 926 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 927 928 If unsure, say Y. 929 930config ARM64_ERRATUM_2441009 931 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 932 select ARM64_WORKAROUND_REPEAT_TLBI 933 help 934 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 935 936 Under very rare circumstances, affected Cortex-A510 CPUs 937 may not handle a race between a break-before-make sequence on one 938 CPU, and another CPU accessing the same page. This could allow a 939 store to a page that has been unmapped. 940 941 Work around this by adding the affected CPUs to the list that needs 942 TLB sequences to be done twice. 943 944 If unsure, say N. 945 946config ARM64_ERRATUM_2064142 947 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 948 depends on CORESIGHT_TRBE 949 default y 950 help 951 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 952 953 Affected Cortex-A510 core might fail to write into system registers after the 954 TRBE has been disabled. Under some conditions after the TRBE has been disabled 955 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 956 and TRBTRG_EL1 will be ignored and will not be effected. 957 958 Work around this in the driver by executing TSB CSYNC and DSB after collection 959 is stopped and before performing a system register write to one of the affected 960 registers. 961 962 If unsure, say Y. 963 964config ARM64_ERRATUM_2038923 965 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 966 depends on CORESIGHT_TRBE 967 default y 968 help 969 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 970 971 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 972 prohibited within the CPU. As a result, the trace buffer or trace buffer state 973 might be corrupted. This happens after TRBE buffer has been enabled by setting 974 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 975 execution changes from a context, in which trace is prohibited to one where it 976 isn't, or vice versa. In these mentioned conditions, the view of whether trace 977 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 978 the trace buffer state might be corrupted. 979 980 Work around this in the driver by preventing an inconsistent view of whether the 981 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 982 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 983 two ISB instructions if no ERET is to take place. 984 985 If unsure, say Y. 986 987config ARM64_ERRATUM_1902691 988 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 989 depends on CORESIGHT_TRBE 990 default y 991 help 992 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 993 994 Affected Cortex-A510 core might cause trace data corruption, when being written 995 into the memory. Effectively TRBE is broken and hence cannot be used to capture 996 trace data. 997 998 Work around this problem in the driver by just preventing TRBE initialization on 999 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1000 on such implementations. This will cover the kernel for any firmware that doesn't 1001 do this already. 1002 1003 If unsure, say Y. 1004 1005config ARM64_ERRATUM_2457168 1006 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1007 depends on ARM64_AMU_EXTN 1008 default y 1009 help 1010 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1011 1012 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1013 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1014 incorrectly giving a significantly higher output value. 1015 1016 Work around this problem by returning 0 when reading the affected counter in 1017 key locations that results in disabling all users of this counter. This effect 1018 is the same to firmware disabling affected counters. 1019 1020 If unsure, say Y. 1021 1022config ARM64_ERRATUM_2645198 1023 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1024 default y 1025 help 1026 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1027 1028 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1029 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1030 next instruction abort caused by permission fault. 1031 1032 Only user-space does executable to non-executable permission transition via 1033 mprotect() system call. Workaround the problem by doing a break-before-make 1034 TLB invalidation, for all changes to executable user space mappings. 1035 1036 If unsure, say Y. 1037 1038config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1039 bool 1040 1041config ARM64_ERRATUM_2966298 1042 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1043 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1044 default y 1045 help 1046 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1047 1048 On an affected Cortex-A520 core, a speculatively executed unprivileged 1049 load might leak data from a privileged level via a cache side channel. 1050 1051 Work around this problem by executing a TLBI before returning to EL0. 1052 1053 If unsure, say Y. 1054 1055config ARM64_ERRATUM_3117295 1056 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1057 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1058 default y 1059 help 1060 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1061 1062 On an affected Cortex-A510 core, a speculatively executed unprivileged 1063 load might leak data from a privileged level via a cache side channel. 1064 1065 Work around this problem by executing a TLBI before returning to EL0. 1066 1067 If unsure, say Y. 1068 1069config CAVIUM_ERRATUM_22375 1070 bool "Cavium erratum 22375, 24313" 1071 default y 1072 help 1073 Enable workaround for errata 22375 and 24313. 1074 1075 This implements two gicv3-its errata workarounds for ThunderX. Both 1076 with a small impact affecting only ITS table allocation. 1077 1078 erratum 22375: only alloc 8MB table size 1079 erratum 24313: ignore memory access type 1080 1081 The fixes are in ITS initialization and basically ignore memory access 1082 type and table size provided by the TYPER and BASER registers. 1083 1084 If unsure, say Y. 1085 1086config CAVIUM_ERRATUM_23144 1087 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1088 depends on NUMA 1089 default y 1090 help 1091 ITS SYNC command hang for cross node io and collections/cpu mapping. 1092 1093 If unsure, say Y. 1094 1095config CAVIUM_ERRATUM_23154 1096 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1097 default y 1098 help 1099 The ThunderX GICv3 implementation requires a modified version for 1100 reading the IAR status to ensure data synchronization 1101 (access to icc_iar1_el1 is not sync'ed before and after). 1102 1103 It also suffers from erratum 38545 (also present on Marvell's 1104 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1105 spuriously presented to the CPU interface. 1106 1107 If unsure, say Y. 1108 1109config CAVIUM_ERRATUM_27456 1110 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1111 default y 1112 help 1113 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1114 instructions may cause the icache to become corrupted if it 1115 contains data for a non-current ASID. The fix is to 1116 invalidate the icache when changing the mm context. 1117 1118 If unsure, say Y. 1119 1120config CAVIUM_ERRATUM_30115 1121 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1122 default y 1123 help 1124 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1125 1.2, and T83 Pass 1.0, KVM guest execution may disable 1126 interrupts in host. Trapping both GICv3 group-0 and group-1 1127 accesses sidesteps the issue. 1128 1129 If unsure, say Y. 1130 1131config CAVIUM_TX2_ERRATUM_219 1132 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1133 default y 1134 help 1135 On Cavium ThunderX2, a load, store or prefetch instruction between a 1136 TTBR update and the corresponding context synchronizing operation can 1137 cause a spurious Data Abort to be delivered to any hardware thread in 1138 the CPU core. 1139 1140 Work around the issue by avoiding the problematic code sequence and 1141 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1142 trap handler performs the corresponding register access, skips the 1143 instruction and ensures context synchronization by virtue of the 1144 exception return. 1145 1146 If unsure, say Y. 1147 1148config FUJITSU_ERRATUM_010001 1149 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1150 default y 1151 help 1152 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1153 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1154 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1155 This fault occurs under a specific hardware condition when a 1156 load/store instruction performs an address translation using: 1157 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1158 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1159 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1160 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1161 1162 The workaround is to ensure these bits are clear in TCR_ELx. 1163 The workaround only affects the Fujitsu-A64FX. 1164 1165 If unsure, say Y. 1166 1167config HISILICON_ERRATUM_161600802 1168 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1169 default y 1170 help 1171 The HiSilicon Hip07 SoC uses the wrong redistributor base 1172 when issued ITS commands such as VMOVP and VMAPP, and requires 1173 a 128kB offset to be applied to the target address in this commands. 1174 1175 If unsure, say Y. 1176 1177config QCOM_FALKOR_ERRATUM_1003 1178 bool "Falkor E1003: Incorrect translation due to ASID change" 1179 default y 1180 help 1181 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1182 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1183 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1184 then only for entries in the walk cache, since the leaf translation 1185 is unchanged. Work around the erratum by invalidating the walk cache 1186 entries for the trampoline before entering the kernel proper. 1187 1188config QCOM_FALKOR_ERRATUM_1009 1189 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1190 default y 1191 select ARM64_WORKAROUND_REPEAT_TLBI 1192 help 1193 On Falkor v1, the CPU may prematurely complete a DSB following a 1194 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1195 one more time to fix the issue. 1196 1197 If unsure, say Y. 1198 1199config QCOM_QDF2400_ERRATUM_0065 1200 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1201 default y 1202 help 1203 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1204 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1205 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1206 1207 If unsure, say Y. 1208 1209config QCOM_FALKOR_ERRATUM_E1041 1210 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1211 default y 1212 help 1213 Falkor CPU may speculatively fetch instructions from an improper 1214 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1215 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1216 1217 If unsure, say Y. 1218 1219config NVIDIA_CARMEL_CNP_ERRATUM 1220 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1221 default y 1222 help 1223 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1224 invalidate shared TLB entries installed by a different core, as it would 1225 on standard ARM cores. 1226 1227 If unsure, say Y. 1228 1229config ROCKCHIP_ERRATUM_3588001 1230 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1231 default y 1232 help 1233 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1234 This means, that its sharability feature may not be used, even though it 1235 is supported by the IP itself. 1236 1237 If unsure, say Y. 1238 1239config SOCIONEXT_SYNQUACER_PREITS 1240 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1241 default y 1242 help 1243 Socionext Synquacer SoCs implement a separate h/w block to generate 1244 MSI doorbell writes with non-zero values for the device ID. 1245 1246 If unsure, say Y. 1247 1248endmenu # "ARM errata workarounds via the alternatives framework" 1249 1250choice 1251 prompt "Page size" 1252 default ARM64_4K_PAGES 1253 help 1254 Page size (translation granule) configuration. 1255 1256config ARM64_4K_PAGES 1257 bool "4KB" 1258 select HAVE_PAGE_SIZE_4KB 1259 help 1260 This feature enables 4KB pages support. 1261 1262config ARM64_16K_PAGES 1263 bool "16KB" 1264 select HAVE_PAGE_SIZE_16KB 1265 help 1266 The system will use 16KB pages support. AArch32 emulation 1267 requires applications compiled with 16K (or a multiple of 16K) 1268 aligned segments. 1269 1270config ARM64_64K_PAGES 1271 bool "64KB" 1272 select HAVE_PAGE_SIZE_64KB 1273 help 1274 This feature enables 64KB pages support (4KB by default) 1275 allowing only two levels of page tables and faster TLB 1276 look-up. AArch32 emulation requires applications compiled 1277 with 64K aligned segments. 1278 1279endchoice 1280 1281choice 1282 prompt "Virtual address space size" 1283 default ARM64_VA_BITS_52 1284 help 1285 Allows choosing one of multiple possible virtual address 1286 space sizes. The level of translation table is determined by 1287 a combination of page size and virtual address space size. 1288 1289config ARM64_VA_BITS_36 1290 bool "36-bit" if EXPERT 1291 depends on PAGE_SIZE_16KB 1292 1293config ARM64_VA_BITS_39 1294 bool "39-bit" 1295 depends on PAGE_SIZE_4KB 1296 1297config ARM64_VA_BITS_42 1298 bool "42-bit" 1299 depends on PAGE_SIZE_64KB 1300 1301config ARM64_VA_BITS_47 1302 bool "47-bit" 1303 depends on PAGE_SIZE_16KB 1304 1305config ARM64_VA_BITS_48 1306 bool "48-bit" 1307 1308config ARM64_VA_BITS_52 1309 bool "52-bit" 1310 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1311 help 1312 Enable 52-bit virtual addressing for userspace when explicitly 1313 requested via a hint to mmap(). The kernel will also use 52-bit 1314 virtual addresses for its own mappings (provided HW support for 1315 this feature is available, otherwise it reverts to 48-bit). 1316 1317 NOTE: Enabling 52-bit virtual addressing in conjunction with 1318 ARMv8.3 Pointer Authentication will result in the PAC being 1319 reduced from 7 bits to 3 bits, which may have a significant 1320 impact on its susceptibility to brute-force attacks. 1321 1322 If unsure, select 48-bit virtual addressing instead. 1323 1324endchoice 1325 1326config ARM64_FORCE_52BIT 1327 bool "Force 52-bit virtual addresses for userspace" 1328 depends on ARM64_VA_BITS_52 && EXPERT 1329 help 1330 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1331 to maintain compatibility with older software by providing 48-bit VAs 1332 unless a hint is supplied to mmap. 1333 1334 This configuration option disables the 48-bit compatibility logic, and 1335 forces all userspace addresses to be 52-bit on HW that supports it. One 1336 should only enable this configuration option for stress testing userspace 1337 memory management code. If unsure say N here. 1338 1339config ARM64_VA_BITS 1340 int 1341 default 36 if ARM64_VA_BITS_36 1342 default 39 if ARM64_VA_BITS_39 1343 default 42 if ARM64_VA_BITS_42 1344 default 47 if ARM64_VA_BITS_47 1345 default 48 if ARM64_VA_BITS_48 1346 default 52 if ARM64_VA_BITS_52 1347 1348choice 1349 prompt "Physical address space size" 1350 default ARM64_PA_BITS_48 1351 help 1352 Choose the maximum physical address range that the kernel will 1353 support. 1354 1355config ARM64_PA_BITS_48 1356 bool "48-bit" 1357 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1358 1359config ARM64_PA_BITS_52 1360 bool "52-bit" 1361 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1362 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1363 help 1364 Enable support for a 52-bit physical address space, introduced as 1365 part of the ARMv8.2-LPA extension. 1366 1367 With this enabled, the kernel will also continue to work on CPUs that 1368 do not support ARMv8.2-LPA, but with some added memory overhead (and 1369 minor performance overhead). 1370 1371endchoice 1372 1373config ARM64_PA_BITS 1374 int 1375 default 48 if ARM64_PA_BITS_48 1376 default 52 if ARM64_PA_BITS_52 1377 1378config ARM64_LPA2 1379 def_bool y 1380 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1381 1382choice 1383 prompt "Endianness" 1384 default CPU_LITTLE_ENDIAN 1385 help 1386 Select the endianness of data accesses performed by the CPU. Userspace 1387 applications will need to be compiled and linked for the endianness 1388 that is selected here. 1389 1390config CPU_BIG_ENDIAN 1391 bool "Build big-endian kernel" 1392 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1393 depends on AS_IS_GNU || AS_VERSION >= 150000 1394 help 1395 Say Y if you plan on running a kernel with a big-endian userspace. 1396 1397config CPU_LITTLE_ENDIAN 1398 bool "Build little-endian kernel" 1399 help 1400 Say Y if you plan on running a kernel with a little-endian userspace. 1401 This is usually the case for distributions targeting arm64. 1402 1403endchoice 1404 1405config SCHED_MC 1406 bool "Multi-core scheduler support" 1407 help 1408 Multi-core scheduler support improves the CPU scheduler's decision 1409 making when dealing with multi-core CPU chips at a cost of slightly 1410 increased overhead in some places. If unsure say N here. 1411 1412config SCHED_CLUSTER 1413 bool "Cluster scheduler support" 1414 help 1415 Cluster scheduler support improves the CPU scheduler's decision 1416 making when dealing with machines that have clusters of CPUs. 1417 Cluster usually means a couple of CPUs which are placed closely 1418 by sharing mid-level caches, last-level cache tags or internal 1419 busses. 1420 1421config SCHED_SMT 1422 bool "SMT scheduler support" 1423 help 1424 Improves the CPU scheduler's decision making when dealing with 1425 MultiThreading at a cost of slightly increased overhead in some 1426 places. If unsure say N here. 1427 1428config NR_CPUS 1429 int "Maximum number of CPUs (2-4096)" 1430 range 2 4096 1431 default "512" 1432 1433config HOTPLUG_CPU 1434 bool "Support for hot-pluggable CPUs" 1435 select GENERIC_IRQ_MIGRATION 1436 help 1437 Say Y here to experiment with turning CPUs off and on. CPUs 1438 can be controlled through /sys/devices/system/cpu. 1439 1440# Common NUMA Features 1441config NUMA 1442 bool "NUMA Memory Allocation and Scheduler Support" 1443 select GENERIC_ARCH_NUMA 1444 select ACPI_NUMA if ACPI 1445 select OF_NUMA 1446 select HAVE_SETUP_PER_CPU_AREA 1447 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1448 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1449 select USE_PERCPU_NUMA_NODE_ID 1450 help 1451 Enable NUMA (Non-Uniform Memory Access) support. 1452 1453 The kernel will try to allocate memory used by a CPU on the 1454 local memory of the CPU and add some more 1455 NUMA awareness to the kernel. 1456 1457config NODES_SHIFT 1458 int "Maximum NUMA Nodes (as a power of 2)" 1459 range 1 10 1460 default "4" 1461 depends on NUMA 1462 help 1463 Specify the maximum number of NUMA Nodes available on the target 1464 system. Increases memory reserved to accommodate various tables. 1465 1466source "kernel/Kconfig.hz" 1467 1468config ARCH_SPARSEMEM_ENABLE 1469 def_bool y 1470 select SPARSEMEM_VMEMMAP_ENABLE 1471 select SPARSEMEM_VMEMMAP 1472 1473config HW_PERF_EVENTS 1474 def_bool y 1475 depends on ARM_PMU 1476 1477# Supported by clang >= 7.0 or GCC >= 12.0.0 1478config CC_HAVE_SHADOW_CALL_STACK 1479 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1480 1481config PARAVIRT 1482 bool "Enable paravirtualization code" 1483 help 1484 This changes the kernel so it can modify itself when it is run 1485 under a hypervisor, potentially improving performance significantly 1486 over full virtualization. 1487 1488config PARAVIRT_TIME_ACCOUNTING 1489 bool "Paravirtual steal time accounting" 1490 select PARAVIRT 1491 help 1492 Select this option to enable fine granularity task steal time 1493 accounting. Time spent executing other tasks in parallel with 1494 the current vCPU is discounted from the vCPU power. To account for 1495 that, there can be a small performance impact. 1496 1497 If in doubt, say N here. 1498 1499config ARCH_SUPPORTS_KEXEC 1500 def_bool PM_SLEEP_SMP 1501 1502config ARCH_SUPPORTS_KEXEC_FILE 1503 def_bool y 1504 1505config ARCH_SELECTS_KEXEC_FILE 1506 def_bool y 1507 depends on KEXEC_FILE 1508 select HAVE_IMA_KEXEC if IMA 1509 1510config ARCH_SUPPORTS_KEXEC_SIG 1511 def_bool y 1512 1513config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1514 def_bool y 1515 1516config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1517 def_bool y 1518 1519config ARCH_SUPPORTS_CRASH_DUMP 1520 def_bool y 1521 1522config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1523 def_bool CRASH_RESERVE 1524 1525config TRANS_TABLE 1526 def_bool y 1527 depends on HIBERNATION || KEXEC_CORE 1528 1529config XEN_DOM0 1530 def_bool y 1531 depends on XEN 1532 1533config XEN 1534 bool "Xen guest support on ARM64" 1535 depends on ARM64 && OF 1536 select SWIOTLB_XEN 1537 select PARAVIRT 1538 help 1539 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1540 1541# include/linux/mmzone.h requires the following to be true: 1542# 1543# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1544# 1545# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1546# 1547# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1548# ----+-------------------+--------------+----------------------+-------------------------+ 1549# 4K | 27 | 12 | 15 | 10 | 1550# 16K | 27 | 14 | 13 | 11 | 1551# 64K | 29 | 16 | 13 | 13 | 1552config ARCH_FORCE_MAX_ORDER 1553 int 1554 default "13" if ARM64_64K_PAGES 1555 default "11" if ARM64_16K_PAGES 1556 default "10" 1557 help 1558 The kernel page allocator limits the size of maximal physically 1559 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1560 defines the maximal power of two of number of pages that can be 1561 allocated as a single contiguous block. This option allows 1562 overriding the default setting when ability to allocate very 1563 large blocks of physically contiguous memory is required. 1564 1565 The maximal size of allocation cannot exceed the size of the 1566 section, so the value of MAX_PAGE_ORDER should satisfy 1567 1568 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1569 1570 Don't change if unsure. 1571 1572config UNMAP_KERNEL_AT_EL0 1573 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1574 default y 1575 help 1576 Speculation attacks against some high-performance processors can 1577 be used to bypass MMU permission checks and leak kernel data to 1578 userspace. This can be defended against by unmapping the kernel 1579 when running in userspace, mapping it back in on exception entry 1580 via a trampoline page in the vector table. 1581 1582 If unsure, say Y. 1583 1584config MITIGATE_SPECTRE_BRANCH_HISTORY 1585 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1586 default y 1587 help 1588 Speculation attacks against some high-performance processors can 1589 make use of branch history to influence future speculation. 1590 When taking an exception from user-space, a sequence of branches 1591 or a firmware call overwrites the branch history. 1592 1593config RODATA_FULL_DEFAULT_ENABLED 1594 bool "Apply r/o permissions of VM areas also to their linear aliases" 1595 default y 1596 help 1597 Apply read-only attributes of VM areas to the linear alias of 1598 the backing pages as well. This prevents code or read-only data 1599 from being modified (inadvertently or intentionally) via another 1600 mapping of the same memory page. This additional enhancement can 1601 be turned off at runtime by passing rodata=[off|on] (and turned on 1602 with rodata=full if this option is set to 'n') 1603 1604 This requires the linear region to be mapped down to pages, 1605 which may adversely affect performance in some cases. 1606 1607config ARM64_SW_TTBR0_PAN 1608 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1609 help 1610 Enabling this option prevents the kernel from accessing 1611 user-space memory directly by pointing TTBR0_EL1 to a reserved 1612 zeroed area and reserved ASID. The user access routines 1613 restore the valid TTBR0_EL1 temporarily. 1614 1615config ARM64_TAGGED_ADDR_ABI 1616 bool "Enable the tagged user addresses syscall ABI" 1617 default y 1618 help 1619 When this option is enabled, user applications can opt in to a 1620 relaxed ABI via prctl() allowing tagged addresses to be passed 1621 to system calls as pointer arguments. For details, see 1622 Documentation/arch/arm64/tagged-address-abi.rst. 1623 1624menuconfig COMPAT 1625 bool "Kernel support for 32-bit EL0" 1626 depends on ARM64_4K_PAGES || EXPERT 1627 select HAVE_UID16 1628 select OLD_SIGSUSPEND3 1629 select COMPAT_OLD_SIGACTION 1630 help 1631 This option enables support for a 32-bit EL0 running under a 64-bit 1632 kernel at EL1. AArch32-specific components such as system calls, 1633 the user helper functions, VFP support and the ptrace interface are 1634 handled appropriately by the kernel. 1635 1636 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1637 that you will only be able to execute AArch32 binaries that were compiled 1638 with page size aligned segments. 1639 1640 If you want to execute 32-bit userspace applications, say Y. 1641 1642if COMPAT 1643 1644config KUSER_HELPERS 1645 bool "Enable kuser helpers page for 32-bit applications" 1646 default y 1647 help 1648 Warning: disabling this option may break 32-bit user programs. 1649 1650 Provide kuser helpers to compat tasks. The kernel provides 1651 helper code to userspace in read only form at a fixed location 1652 to allow userspace to be independent of the CPU type fitted to 1653 the system. This permits binaries to be run on ARMv4 through 1654 to ARMv8 without modification. 1655 1656 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1657 1658 However, the fixed address nature of these helpers can be used 1659 by ROP (return orientated programming) authors when creating 1660 exploits. 1661 1662 If all of the binaries and libraries which run on your platform 1663 are built specifically for your platform, and make no use of 1664 these helpers, then you can turn this option off to hinder 1665 such exploits. However, in that case, if a binary or library 1666 relying on those helpers is run, it will not function correctly. 1667 1668 Say N here only if you are absolutely certain that you do not 1669 need these helpers; otherwise, the safe option is to say Y. 1670 1671config COMPAT_VDSO 1672 bool "Enable vDSO for 32-bit applications" 1673 depends on !CPU_BIG_ENDIAN 1674 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1675 select GENERIC_COMPAT_VDSO 1676 default y 1677 help 1678 Place in the process address space of 32-bit applications an 1679 ELF shared object providing fast implementations of gettimeofday 1680 and clock_gettime. 1681 1682 You must have a 32-bit build of glibc 2.22 or later for programs 1683 to seamlessly take advantage of this. 1684 1685config THUMB2_COMPAT_VDSO 1686 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1687 depends on COMPAT_VDSO 1688 default y 1689 help 1690 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1691 otherwise with '-marm'. 1692 1693config COMPAT_ALIGNMENT_FIXUPS 1694 bool "Fix up misaligned multi-word loads and stores in user space" 1695 1696menuconfig ARMV8_DEPRECATED 1697 bool "Emulate deprecated/obsolete ARMv8 instructions" 1698 depends on SYSCTL 1699 help 1700 Legacy software support may require certain instructions 1701 that have been deprecated or obsoleted in the architecture. 1702 1703 Enable this config to enable selective emulation of these 1704 features. 1705 1706 If unsure, say Y 1707 1708if ARMV8_DEPRECATED 1709 1710config SWP_EMULATION 1711 bool "Emulate SWP/SWPB instructions" 1712 help 1713 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1714 they are always undefined. Say Y here to enable software 1715 emulation of these instructions for userspace using LDXR/STXR. 1716 This feature can be controlled at runtime with the abi.swp 1717 sysctl which is disabled by default. 1718 1719 In some older versions of glibc [<=2.8] SWP is used during futex 1720 trylock() operations with the assumption that the code will not 1721 be preempted. This invalid assumption may be more likely to fail 1722 with SWP emulation enabled, leading to deadlock of the user 1723 application. 1724 1725 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1726 on an external transaction monitoring block called a global 1727 monitor to maintain update atomicity. If your system does not 1728 implement a global monitor, this option can cause programs that 1729 perform SWP operations to uncached memory to deadlock. 1730 1731 If unsure, say Y 1732 1733config CP15_BARRIER_EMULATION 1734 bool "Emulate CP15 Barrier instructions" 1735 help 1736 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1737 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1738 strongly recommended to use the ISB, DSB, and DMB 1739 instructions instead. 1740 1741 Say Y here to enable software emulation of these 1742 instructions for AArch32 userspace code. When this option is 1743 enabled, CP15 barrier usage is traced which can help 1744 identify software that needs updating. This feature can be 1745 controlled at runtime with the abi.cp15_barrier sysctl. 1746 1747 If unsure, say Y 1748 1749config SETEND_EMULATION 1750 bool "Emulate SETEND instruction" 1751 help 1752 The SETEND instruction alters the data-endianness of the 1753 AArch32 EL0, and is deprecated in ARMv8. 1754 1755 Say Y here to enable software emulation of the instruction 1756 for AArch32 userspace code. This feature can be controlled 1757 at runtime with the abi.setend sysctl. 1758 1759 Note: All the cpus on the system must have mixed endian support at EL0 1760 for this feature to be enabled. If a new CPU - which doesn't support mixed 1761 endian - is hotplugged in after this feature has been enabled, there could 1762 be unexpected results in the applications. 1763 1764 If unsure, say Y 1765endif # ARMV8_DEPRECATED 1766 1767endif # COMPAT 1768 1769menu "ARMv8.1 architectural features" 1770 1771config ARM64_HW_AFDBM 1772 bool "Support for hardware updates of the Access and Dirty page flags" 1773 default y 1774 help 1775 The ARMv8.1 architecture extensions introduce support for 1776 hardware updates of the access and dirty information in page 1777 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1778 capable processors, accesses to pages with PTE_AF cleared will 1779 set this bit instead of raising an access flag fault. 1780 Similarly, writes to read-only pages with the DBM bit set will 1781 clear the read-only bit (AP[2]) instead of raising a 1782 permission fault. 1783 1784 Kernels built with this configuration option enabled continue 1785 to work on pre-ARMv8.1 hardware and the performance impact is 1786 minimal. If unsure, say Y. 1787 1788config ARM64_PAN 1789 bool "Enable support for Privileged Access Never (PAN)" 1790 default y 1791 help 1792 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1793 prevents the kernel or hypervisor from accessing user-space (EL0) 1794 memory directly. 1795 1796 Choosing this option will cause any unprotected (not using 1797 copy_to_user et al) memory access to fail with a permission fault. 1798 1799 The feature is detected at runtime, and will remain as a 'nop' 1800 instruction if the cpu does not implement the feature. 1801 1802config AS_HAS_LSE_ATOMICS 1803 def_bool $(as-instr,.arch_extension lse) 1804 1805config ARM64_LSE_ATOMICS 1806 bool 1807 default ARM64_USE_LSE_ATOMICS 1808 depends on AS_HAS_LSE_ATOMICS 1809 1810config ARM64_USE_LSE_ATOMICS 1811 bool "Atomic instructions" 1812 default y 1813 help 1814 As part of the Large System Extensions, ARMv8.1 introduces new 1815 atomic instructions that are designed specifically to scale in 1816 very large systems. 1817 1818 Say Y here to make use of these instructions for the in-kernel 1819 atomic routines. This incurs a small overhead on CPUs that do 1820 not support these instructions and requires the kernel to be 1821 built with binutils >= 2.25 in order for the new instructions 1822 to be used. 1823 1824endmenu # "ARMv8.1 architectural features" 1825 1826menu "ARMv8.2 architectural features" 1827 1828config AS_HAS_ARMV8_2 1829 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1830 1831config AS_HAS_SHA3 1832 def_bool $(as-instr,.arch armv8.2-a+sha3) 1833 1834config ARM64_PMEM 1835 bool "Enable support for persistent memory" 1836 select ARCH_HAS_PMEM_API 1837 select ARCH_HAS_UACCESS_FLUSHCACHE 1838 help 1839 Say Y to enable support for the persistent memory API based on the 1840 ARMv8.2 DCPoP feature. 1841 1842 The feature is detected at runtime, and the kernel will use DC CVAC 1843 operations if DC CVAP is not supported (following the behaviour of 1844 DC CVAP itself if the system does not define a point of persistence). 1845 1846config ARM64_RAS_EXTN 1847 bool "Enable support for RAS CPU Extensions" 1848 default y 1849 help 1850 CPUs that support the Reliability, Availability and Serviceability 1851 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1852 errors, classify them and report them to software. 1853 1854 On CPUs with these extensions system software can use additional 1855 barriers to determine if faults are pending and read the 1856 classification from a new set of registers. 1857 1858 Selecting this feature will allow the kernel to use these barriers 1859 and access the new registers if the system supports the extension. 1860 Platform RAS features may additionally depend on firmware support. 1861 1862config ARM64_CNP 1863 bool "Enable support for Common Not Private (CNP) translations" 1864 default y 1865 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1866 help 1867 Common Not Private (CNP) allows translation table entries to 1868 be shared between different PEs in the same inner shareable 1869 domain, so the hardware can use this fact to optimise the 1870 caching of such entries in the TLB. 1871 1872 Selecting this option allows the CNP feature to be detected 1873 at runtime, and does not affect PEs that do not implement 1874 this feature. 1875 1876endmenu # "ARMv8.2 architectural features" 1877 1878menu "ARMv8.3 architectural features" 1879 1880config ARM64_PTR_AUTH 1881 bool "Enable support for pointer authentication" 1882 default y 1883 help 1884 Pointer authentication (part of the ARMv8.3 Extensions) provides 1885 instructions for signing and authenticating pointers against secret 1886 keys, which can be used to mitigate Return Oriented Programming (ROP) 1887 and other attacks. 1888 1889 This option enables these instructions at EL0 (i.e. for userspace). 1890 Choosing this option will cause the kernel to initialise secret keys 1891 for each process at exec() time, with these keys being 1892 context-switched along with the process. 1893 1894 The feature is detected at runtime. If the feature is not present in 1895 hardware it will not be advertised to userspace/KVM guest nor will it 1896 be enabled. 1897 1898 If the feature is present on the boot CPU but not on a late CPU, then 1899 the late CPU will be parked. Also, if the boot CPU does not have 1900 address auth and the late CPU has then the late CPU will still boot 1901 but with the feature disabled. On such a system, this option should 1902 not be selected. 1903 1904config ARM64_PTR_AUTH_KERNEL 1905 bool "Use pointer authentication for kernel" 1906 default y 1907 depends on ARM64_PTR_AUTH 1908 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1909 # Modern compilers insert a .note.gnu.property section note for PAC 1910 # which is only understood by binutils starting with version 2.33.1. 1911 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1912 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1913 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1914 help 1915 If the compiler supports the -mbranch-protection or 1916 -msign-return-address flag (e.g. GCC 7 or later), then this option 1917 will cause the kernel itself to be compiled with return address 1918 protection. In this case, and if the target hardware is known to 1919 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1920 disabled with minimal loss of protection. 1921 1922 This feature works with FUNCTION_GRAPH_TRACER option only if 1923 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1924 1925config CC_HAS_BRANCH_PROT_PAC_RET 1926 # GCC 9 or later, clang 8 or later 1927 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1928 1929config CC_HAS_SIGN_RETURN_ADDRESS 1930 # GCC 7, 8 1931 def_bool $(cc-option,-msign-return-address=all) 1932 1933config AS_HAS_ARMV8_3 1934 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1935 1936config AS_HAS_CFI_NEGATE_RA_STATE 1937 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1938 1939config AS_HAS_LDAPR 1940 def_bool $(as-instr,.arch_extension rcpc) 1941 1942endmenu # "ARMv8.3 architectural features" 1943 1944menu "ARMv8.4 architectural features" 1945 1946config ARM64_AMU_EXTN 1947 bool "Enable support for the Activity Monitors Unit CPU extension" 1948 default y 1949 help 1950 The activity monitors extension is an optional extension introduced 1951 by the ARMv8.4 CPU architecture. This enables support for version 1 1952 of the activity monitors architecture, AMUv1. 1953 1954 To enable the use of this extension on CPUs that implement it, say Y. 1955 1956 Note that for architectural reasons, firmware _must_ implement AMU 1957 support when running on CPUs that present the activity monitors 1958 extension. The required support is present in: 1959 * Version 1.5 and later of the ARM Trusted Firmware 1960 1961 For kernels that have this configuration enabled but boot with broken 1962 firmware, you may need to say N here until the firmware is fixed. 1963 Otherwise you may experience firmware panics or lockups when 1964 accessing the counter registers. Even if you are not observing these 1965 symptoms, the values returned by the register reads might not 1966 correctly reflect reality. Most commonly, the value read will be 0, 1967 indicating that the counter is not enabled. 1968 1969config AS_HAS_ARMV8_4 1970 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1971 1972config ARM64_TLB_RANGE 1973 bool "Enable support for tlbi range feature" 1974 default y 1975 depends on AS_HAS_ARMV8_4 1976 help 1977 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1978 range of input addresses. 1979 1980 The feature introduces new assembly instructions, and they were 1981 support when binutils >= 2.30. 1982 1983endmenu # "ARMv8.4 architectural features" 1984 1985menu "ARMv8.5 architectural features" 1986 1987config AS_HAS_ARMV8_5 1988 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1989 1990config ARM64_BTI 1991 bool "Branch Target Identification support" 1992 default y 1993 help 1994 Branch Target Identification (part of the ARMv8.5 Extensions) 1995 provides a mechanism to limit the set of locations to which computed 1996 branch instructions such as BR or BLR can jump. 1997 1998 To make use of BTI on CPUs that support it, say Y. 1999 2000 BTI is intended to provide complementary protection to other control 2001 flow integrity protection mechanisms, such as the Pointer 2002 authentication mechanism provided as part of the ARMv8.3 Extensions. 2003 For this reason, it does not make sense to enable this option without 2004 also enabling support for pointer authentication. Thus, when 2005 enabling this option you should also select ARM64_PTR_AUTH=y. 2006 2007 Userspace binaries must also be specifically compiled to make use of 2008 this mechanism. If you say N here or the hardware does not support 2009 BTI, such binaries can still run, but you get no additional 2010 enforcement of branch destinations. 2011 2012config ARM64_BTI_KERNEL 2013 bool "Use Branch Target Identification for kernel" 2014 default y 2015 depends on ARM64_BTI 2016 depends on ARM64_PTR_AUTH_KERNEL 2017 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2018 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2019 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2020 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2021 depends on !CC_IS_GCC 2022 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2023 help 2024 Build the kernel with Branch Target Identification annotations 2025 and enable enforcement of this for kernel code. When this option 2026 is enabled and the system supports BTI all kernel code including 2027 modular code must have BTI enabled. 2028 2029config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2030 # GCC 9 or later, clang 8 or later 2031 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2032 2033config ARM64_E0PD 2034 bool "Enable support for E0PD" 2035 default y 2036 help 2037 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2038 that EL0 accesses made via TTBR1 always fault in constant time, 2039 providing similar benefits to KASLR as those provided by KPTI, but 2040 with lower overhead and without disrupting legitimate access to 2041 kernel memory such as SPE. 2042 2043 This option enables E0PD for TTBR1 where available. 2044 2045config ARM64_AS_HAS_MTE 2046 # Initial support for MTE went in binutils 2.32.0, checked with 2047 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2048 # as a late addition to the final architecture spec (LDGM/STGM) 2049 # is only supported in the newer 2.32.x and 2.33 binutils 2050 # versions, hence the extra "stgm" instruction check below. 2051 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2052 2053config ARM64_MTE 2054 bool "Memory Tagging Extension support" 2055 default y 2056 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2057 depends on AS_HAS_ARMV8_5 2058 depends on AS_HAS_LSE_ATOMICS 2059 # Required for tag checking in the uaccess routines 2060 depends on ARM64_PAN 2061 select ARCH_HAS_SUBPAGE_FAULTS 2062 select ARCH_USES_HIGH_VMA_FLAGS 2063 select ARCH_USES_PG_ARCH_X 2064 help 2065 Memory Tagging (part of the ARMv8.5 Extensions) provides 2066 architectural support for run-time, always-on detection of 2067 various classes of memory error to aid with software debugging 2068 to eliminate vulnerabilities arising from memory-unsafe 2069 languages. 2070 2071 This option enables the support for the Memory Tagging 2072 Extension at EL0 (i.e. for userspace). 2073 2074 Selecting this option allows the feature to be detected at 2075 runtime. Any secondary CPU not implementing this feature will 2076 not be allowed a late bring-up. 2077 2078 Userspace binaries that want to use this feature must 2079 explicitly opt in. The mechanism for the userspace is 2080 described in: 2081 2082 Documentation/arch/arm64/memory-tagging-extension.rst. 2083 2084endmenu # "ARMv8.5 architectural features" 2085 2086menu "ARMv8.7 architectural features" 2087 2088config ARM64_EPAN 2089 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2090 default y 2091 depends on ARM64_PAN 2092 help 2093 Enhanced Privileged Access Never (EPAN) allows Privileged 2094 Access Never to be used with Execute-only mappings. 2095 2096 The feature is detected at runtime, and will remain disabled 2097 if the cpu does not implement the feature. 2098endmenu # "ARMv8.7 architectural features" 2099 2100config ARM64_SVE 2101 bool "ARM Scalable Vector Extension support" 2102 default y 2103 help 2104 The Scalable Vector Extension (SVE) is an extension to the AArch64 2105 execution state which complements and extends the SIMD functionality 2106 of the base architecture to support much larger vectors and to enable 2107 additional vectorisation opportunities. 2108 2109 To enable use of this extension on CPUs that implement it, say Y. 2110 2111 On CPUs that support the SVE2 extensions, this option will enable 2112 those too. 2113 2114 Note that for architectural reasons, firmware _must_ implement SVE 2115 support when running on SVE capable hardware. The required support 2116 is present in: 2117 2118 * version 1.5 and later of the ARM Trusted Firmware 2119 * the AArch64 boot wrapper since commit 5e1261e08abf 2120 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2121 2122 For other firmware implementations, consult the firmware documentation 2123 or vendor. 2124 2125 If you need the kernel to boot on SVE-capable hardware with broken 2126 firmware, you may need to say N here until you get your firmware 2127 fixed. Otherwise, you may experience firmware panics or lockups when 2128 booting the kernel. If unsure and you are not observing these 2129 symptoms, you should assume that it is safe to say Y. 2130 2131config ARM64_SME 2132 bool "ARM Scalable Matrix Extension support" 2133 default y 2134 depends on ARM64_SVE 2135 help 2136 The Scalable Matrix Extension (SME) is an extension to the AArch64 2137 execution state which utilises a substantial subset of the SVE 2138 instruction set, together with the addition of new architectural 2139 register state capable of holding two dimensional matrix tiles to 2140 enable various matrix operations. 2141 2142config ARM64_PSEUDO_NMI 2143 bool "Support for NMI-like interrupts" 2144 select ARM_GIC_V3 2145 help 2146 Adds support for mimicking Non-Maskable Interrupts through the use of 2147 GIC interrupt priority. This support requires version 3 or later of 2148 ARM GIC. 2149 2150 This high priority configuration for interrupts needs to be 2151 explicitly enabled by setting the kernel parameter 2152 "irqchip.gicv3_pseudo_nmi" to 1. 2153 2154 If unsure, say N 2155 2156if ARM64_PSEUDO_NMI 2157config ARM64_DEBUG_PRIORITY_MASKING 2158 bool "Debug interrupt priority masking" 2159 help 2160 This adds runtime checks to functions enabling/disabling 2161 interrupts when using priority masking. The additional checks verify 2162 the validity of ICC_PMR_EL1 when calling concerned functions. 2163 2164 If unsure, say N 2165endif # ARM64_PSEUDO_NMI 2166 2167config RELOCATABLE 2168 bool "Build a relocatable kernel image" if EXPERT 2169 select ARCH_HAS_RELR 2170 default y 2171 help 2172 This builds the kernel as a Position Independent Executable (PIE), 2173 which retains all relocation metadata required to relocate the 2174 kernel binary at runtime to a different virtual address than the 2175 address it was linked at. 2176 Since AArch64 uses the RELA relocation format, this requires a 2177 relocation pass at runtime even if the kernel is loaded at the 2178 same address it was linked at. 2179 2180config RANDOMIZE_BASE 2181 bool "Randomize the address of the kernel image" 2182 select RELOCATABLE 2183 help 2184 Randomizes the virtual address at which the kernel image is 2185 loaded, as a security feature that deters exploit attempts 2186 relying on knowledge of the location of kernel internals. 2187 2188 It is the bootloader's job to provide entropy, by passing a 2189 random u64 value in /chosen/kaslr-seed at kernel entry. 2190 2191 When booting via the UEFI stub, it will invoke the firmware's 2192 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2193 to the kernel proper. In addition, it will randomise the physical 2194 location of the kernel Image as well. 2195 2196 If unsure, say N. 2197 2198config RANDOMIZE_MODULE_REGION_FULL 2199 bool "Randomize the module region over a 2 GB range" 2200 depends on RANDOMIZE_BASE 2201 default y 2202 help 2203 Randomizes the location of the module region inside a 2 GB window 2204 covering the core kernel. This way, it is less likely for modules 2205 to leak information about the location of core kernel data structures 2206 but it does imply that function calls between modules and the core 2207 kernel will need to be resolved via veneers in the module PLT. 2208 2209 When this option is not set, the module region will be randomized over 2210 a limited range that contains the [_stext, _etext] interval of the 2211 core kernel, so branch relocations are almost always in range unless 2212 the region is exhausted. In this particular case of region 2213 exhaustion, modules might be able to fall back to a larger 2GB area. 2214 2215config CC_HAVE_STACKPROTECTOR_SYSREG 2216 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2217 2218config STACKPROTECTOR_PER_TASK 2219 def_bool y 2220 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2221 2222config UNWIND_PATCH_PAC_INTO_SCS 2223 bool "Enable shadow call stack dynamically using code patching" 2224 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2225 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2226 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2227 depends on SHADOW_CALL_STACK 2228 select UNWIND_TABLES 2229 select DYNAMIC_SCS 2230 2231config ARM64_CONTPTE 2232 bool "Contiguous PTE mappings for user memory" if EXPERT 2233 depends on TRANSPARENT_HUGEPAGE 2234 default y 2235 help 2236 When enabled, user mappings are configured using the PTE contiguous 2237 bit, for any mappings that meet the size and alignment requirements. 2238 This reduces TLB pressure and improves performance. 2239 2240endmenu # "Kernel Features" 2241 2242menu "Boot options" 2243 2244config ARM64_ACPI_PARKING_PROTOCOL 2245 bool "Enable support for the ARM64 ACPI parking protocol" 2246 depends on ACPI 2247 help 2248 Enable support for the ARM64 ACPI parking protocol. If disabled 2249 the kernel will not allow booting through the ARM64 ACPI parking 2250 protocol even if the corresponding data is present in the ACPI 2251 MADT table. 2252 2253config CMDLINE 2254 string "Default kernel command string" 2255 default "" 2256 help 2257 Provide a set of default command-line options at build time by 2258 entering them here. As a minimum, you should specify the the 2259 root device (e.g. root=/dev/nfs). 2260 2261choice 2262 prompt "Kernel command line type" if CMDLINE != "" 2263 default CMDLINE_FROM_BOOTLOADER 2264 help 2265 Choose how the kernel will handle the provided default kernel 2266 command line string. 2267 2268config CMDLINE_FROM_BOOTLOADER 2269 bool "Use bootloader kernel arguments if available" 2270 help 2271 Uses the command-line options passed by the boot loader. If 2272 the boot loader doesn't provide any, the default kernel command 2273 string provided in CMDLINE will be used. 2274 2275config CMDLINE_FORCE 2276 bool "Always use the default kernel command string" 2277 help 2278 Always use the default kernel command string, even if the boot 2279 loader passes other arguments to the kernel. 2280 This is useful if you cannot or don't want to change the 2281 command-line options your boot loader passes to the kernel. 2282 2283endchoice 2284 2285config EFI_STUB 2286 bool 2287 2288config EFI 2289 bool "UEFI runtime support" 2290 depends on OF && !CPU_BIG_ENDIAN 2291 depends on KERNEL_MODE_NEON 2292 select ARCH_SUPPORTS_ACPI 2293 select LIBFDT 2294 select UCS2_STRING 2295 select EFI_PARAMS_FROM_FDT 2296 select EFI_RUNTIME_WRAPPERS 2297 select EFI_STUB 2298 select EFI_GENERIC_STUB 2299 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2300 default y 2301 help 2302 This option provides support for runtime services provided 2303 by UEFI firmware (such as non-volatile variables, realtime 2304 clock, and platform reset). A UEFI stub is also provided to 2305 allow the kernel to be booted as an EFI application. This 2306 is only useful on systems that have UEFI firmware. 2307 2308config DMI 2309 bool "Enable support for SMBIOS (DMI) tables" 2310 depends on EFI 2311 default y 2312 help 2313 This enables SMBIOS/DMI feature for systems. 2314 2315 This option is only useful on systems that have UEFI firmware. 2316 However, even with this option, the resultant kernel should 2317 continue to boot on existing non-UEFI platforms. 2318 2319endmenu # "Boot options" 2320 2321menu "Power management options" 2322 2323source "kernel/power/Kconfig" 2324 2325config ARCH_HIBERNATION_POSSIBLE 2326 def_bool y 2327 depends on CPU_PM 2328 2329config ARCH_HIBERNATION_HEADER 2330 def_bool y 2331 depends on HIBERNATION 2332 2333config ARCH_SUSPEND_POSSIBLE 2334 def_bool y 2335 2336endmenu # "Power management options" 2337 2338menu "CPU Power Management" 2339 2340source "drivers/cpuidle/Kconfig" 2341 2342source "drivers/cpufreq/Kconfig" 2343 2344endmenu # "CPU Power Management" 2345 2346source "drivers/acpi/Kconfig" 2347 2348source "arch/arm64/kvm/Kconfig" 2349 2350