1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 18 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 19 select ARCH_ENABLE_MEMORY_HOTPLUG 20 select ARCH_ENABLE_MEMORY_HOTREMOVE 21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 22 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 23 select ARCH_HAS_CACHE_LINE_SIZE 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 41 select ARCH_HAS_PTE_DEVMAP 42 select ARCH_HAS_PTE_SPECIAL 43 select ARCH_HAS_HW_PTE_YOUNG 44 select ARCH_HAS_SETUP_DMA_OPS 45 select ARCH_HAS_SET_DIRECT_MAP 46 select ARCH_HAS_SET_MEMORY 47 select ARCH_STACKWALK 48 select ARCH_HAS_STRICT_KERNEL_RWX 49 select ARCH_HAS_STRICT_MODULE_RWX 50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 51 select ARCH_HAS_SYNC_DMA_FOR_CPU 52 select ARCH_HAS_SYSCALL_WRAPPER 53 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 54 select ARCH_HAS_ZONE_DMA_SET if EXPERT 55 select ARCH_HAVE_ELF_PROT 56 select ARCH_HAVE_NMI_SAFE_CMPXCHG 57 select ARCH_HAVE_TRACE_MMIO_ACCESS 58 select ARCH_INLINE_READ_LOCK if !PREEMPTION 59 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 63 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 64 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 71 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 74 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 81 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 83 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 84 select ARCH_KEEP_MEMBLOCK 85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 86 select ARCH_USE_CMPXCHG_LOCKREF 87 select ARCH_USE_GNU_PROPERTY 88 select ARCH_USE_MEMTEST 89 select ARCH_USE_QUEUED_RWLOCKS 90 select ARCH_USE_QUEUED_SPINLOCKS 91 select ARCH_USE_SYM_ANNOTATIONS 92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 93 select ARCH_SUPPORTS_HUGETLBFS 94 select ARCH_SUPPORTS_MEMORY_FAILURE 95 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 96 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 97 select ARCH_SUPPORTS_LTO_CLANG_THIN 98 select ARCH_SUPPORTS_CFI_CLANG 99 select ARCH_SUPPORTS_ATOMIC_RMW 100 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 101 select ARCH_SUPPORTS_NUMA_BALANCING 102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 103 select ARCH_SUPPORTS_PER_VMA_LOCK 104 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 105 select ARCH_SUPPORTS_RT 106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 107 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 108 select ARCH_WANT_DEFAULT_BPF_JIT 109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 110 select ARCH_WANT_FRAME_POINTERS 111 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 112 select ARCH_WANT_LD_ORPHAN_WARN 113 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 114 select ARCH_WANTS_NO_INSTR 115 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 116 select ARCH_HAS_UBSAN 117 select ARM_AMBA 118 select ARM_ARCH_TIMER 119 select ARM_GIC 120 select AUDIT_ARCH_COMPAT_GENERIC 121 select ARM_GIC_V2M if PCI 122 select ARM_GIC_V3 123 select ARM_GIC_V3_ITS if PCI 124 select ARM_PSCI_FW 125 select BUILDTIME_TABLE_SORT 126 select CLONE_BACKWARDS 127 select COMMON_CLK 128 select CPU_PM if (SUSPEND || CPU_IDLE) 129 select CPUMASK_OFFSTACK if NR_CPUS > 256 130 select CRC32 131 select DCACHE_WORD_ACCESS 132 select DYNAMIC_FTRACE if FUNCTION_TRACER 133 select DMA_BOUNCE_UNALIGNED_KMALLOC 134 select DMA_DIRECT_REMAP 135 select EDAC_SUPPORT 136 select FRAME_POINTER 137 select FUNCTION_ALIGNMENT_4B 138 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 139 select GENERIC_ALLOCATOR 140 select GENERIC_ARCH_TOPOLOGY 141 select GENERIC_CLOCKEVENTS_BROADCAST 142 select GENERIC_CPU_AUTOPROBE 143 select GENERIC_CPU_DEVICES 144 select GENERIC_CPU_VULNERABILITIES 145 select GENERIC_EARLY_IOREMAP 146 select GENERIC_IDLE_POLL_SETUP 147 select GENERIC_IOREMAP 148 select GENERIC_IRQ_IPI 149 select GENERIC_IRQ_PROBE 150 select GENERIC_IRQ_SHOW 151 select GENERIC_IRQ_SHOW_LEVEL 152 select GENERIC_LIB_DEVMEM_IS_ALLOWED 153 select GENERIC_PCI_IOMAP 154 select GENERIC_PTDUMP 155 select GENERIC_SCHED_CLOCK 156 select GENERIC_SMP_IDLE_THREAD 157 select GENERIC_TIME_VSYSCALL 158 select GENERIC_GETTIMEOFDAY 159 select GENERIC_VDSO_TIME_NS 160 select HARDIRQS_SW_RESEND 161 select HAS_IOPORT 162 select HAVE_MOVE_PMD 163 select HAVE_MOVE_PUD 164 select HAVE_PCI 165 select HAVE_ACPI_APEI if (ACPI && EFI) 166 select HAVE_ALIGNED_STRUCT_PAGE 167 select HAVE_ARCH_AUDITSYSCALL 168 select HAVE_ARCH_BITREVERSE 169 select HAVE_ARCH_COMPILER_H 170 select HAVE_ARCH_HUGE_VMALLOC 171 select HAVE_ARCH_HUGE_VMAP 172 select HAVE_ARCH_JUMP_LABEL 173 select HAVE_ARCH_JUMP_LABEL_RELATIVE 174 select HAVE_ARCH_KASAN 175 select HAVE_ARCH_KASAN_VMALLOC 176 select HAVE_ARCH_KASAN_SW_TAGS 177 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 178 # Some instrumentation may be unsound, hence EXPERT 179 select HAVE_ARCH_KCSAN if EXPERT 180 select HAVE_ARCH_KFENCE 181 select HAVE_ARCH_KGDB 182 select HAVE_ARCH_MMAP_RND_BITS 183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 184 select HAVE_ARCH_PREL32_RELOCATIONS 185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 186 select HAVE_ARCH_SECCOMP_FILTER 187 select HAVE_ARCH_STACKLEAK 188 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 189 select HAVE_ARCH_TRACEHOOK 190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 191 select HAVE_ARCH_VMAP_STACK 192 select HAVE_ARM_SMCCC 193 select HAVE_ASM_MODVERSIONS 194 select HAVE_EBPF_JIT 195 select HAVE_C_RECORDMCOUNT 196 select HAVE_CMPXCHG_DOUBLE 197 select HAVE_CMPXCHG_LOCAL 198 select HAVE_CONTEXT_TRACKING_USER 199 select HAVE_DEBUG_KMEMLEAK 200 select HAVE_DMA_CONTIGUOUS 201 select HAVE_DYNAMIC_FTRACE 202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 203 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 204 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 205 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 206 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 207 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 208 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 209 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 210 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 211 if DYNAMIC_FTRACE_WITH_ARGS 212 select HAVE_SAMPLE_FTRACE_DIRECT 213 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 214 select HAVE_EFFICIENT_UNALIGNED_ACCESS 215 select HAVE_GUP_FAST 216 select HAVE_FTRACE_MCOUNT_RECORD 217 select HAVE_FUNCTION_TRACER 218 select HAVE_FUNCTION_ERROR_INJECTION 219 select HAVE_FUNCTION_GRAPH_TRACER 220 select HAVE_FUNCTION_GRAPH_RETVAL 221 select HAVE_GCC_PLUGINS 222 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 223 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 224 select HAVE_HW_BREAKPOINT if PERF_EVENTS 225 select HAVE_IOREMAP_PROT 226 select HAVE_IRQ_TIME_ACCOUNTING 227 select HAVE_MOD_ARCH_SPECIFIC 228 select HAVE_NMI 229 select HAVE_PERF_EVENTS 230 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 231 select HAVE_PERF_REGS 232 select HAVE_PERF_USER_STACK_DUMP 233 select HAVE_PREEMPT_DYNAMIC_KEY 234 select HAVE_REGS_AND_STACK_ACCESS_API 235 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 236 select HAVE_FUNCTION_ARG_ACCESS_API 237 select MMU_GATHER_RCU_TABLE_FREE 238 select HAVE_RSEQ 239 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 240 select HAVE_STACKPROTECTOR 241 select HAVE_SYSCALL_TRACEPOINTS 242 select HAVE_KPROBES 243 select HAVE_KRETPROBES 244 select HAVE_GENERIC_VDSO 245 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 246 select IRQ_DOMAIN 247 select IRQ_FORCED_THREADING 248 select KASAN_VMALLOC if KASAN 249 select LOCK_MM_AND_FIND_VMA 250 select MODULES_USE_ELF_RELA 251 select NEED_DMA_MAP_STATE 252 select NEED_SG_DMA_LENGTH 253 select OF 254 select OF_EARLY_FLATTREE 255 select PCI_DOMAINS_GENERIC if PCI 256 select PCI_ECAM if (ACPI && PCI) 257 select PCI_SYSCALL if PCI 258 select POWER_RESET 259 select POWER_SUPPLY 260 select SPARSE_IRQ 261 select SWIOTLB 262 select SYSCTL_EXCEPTION_TRACE 263 select THREAD_INFO_IN_TASK 264 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 265 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 266 select TRACE_IRQFLAGS_SUPPORT 267 select TRACE_IRQFLAGS_NMI_SUPPORT 268 select HAVE_SOFTIRQ_ON_OWN_STACK 269 select USER_STACKTRACE_SUPPORT 270 select VDSO_GETRANDOM 271 help 272 ARM 64-bit (AArch64) Linux support. 273 274config RUSTC_SUPPORTS_ARM64 275 def_bool y 276 depends on CPU_LITTLE_ENDIAN 277 # Shadow call stack is only supported on certain rustc versions. 278 # 279 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 280 # required due to use of the -Zfixed-x18 flag. 281 # 282 # Otherwise, rustc version 1.82+ is required due to use of the 283 # -Zsanitizer=shadow-call-stack flag. 284 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 285 286config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 287 def_bool CC_IS_CLANG 288 # https://github.com/ClangBuiltLinux/linux/issues/1507 289 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 290 291config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 292 def_bool CC_IS_GCC 293 depends on $(cc-option,-fpatchable-function-entry=2) 294 295config 64BIT 296 def_bool y 297 298config MMU 299 def_bool y 300 301config ARM64_CONT_PTE_SHIFT 302 int 303 default 5 if PAGE_SIZE_64KB 304 default 7 if PAGE_SIZE_16KB 305 default 4 306 307config ARM64_CONT_PMD_SHIFT 308 int 309 default 5 if PAGE_SIZE_64KB 310 default 5 if PAGE_SIZE_16KB 311 default 4 312 313config ARCH_MMAP_RND_BITS_MIN 314 default 14 if PAGE_SIZE_64KB 315 default 16 if PAGE_SIZE_16KB 316 default 18 317 318# max bits determined by the following formula: 319# VA_BITS - PAGE_SHIFT - 3 320config ARCH_MMAP_RND_BITS_MAX 321 default 19 if ARM64_VA_BITS=36 322 default 24 if ARM64_VA_BITS=39 323 default 27 if ARM64_VA_BITS=42 324 default 30 if ARM64_VA_BITS=47 325 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 326 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 327 default 33 if ARM64_VA_BITS=48 328 default 14 if ARM64_64K_PAGES 329 default 16 if ARM64_16K_PAGES 330 default 18 331 332config ARCH_MMAP_RND_COMPAT_BITS_MIN 333 default 7 if ARM64_64K_PAGES 334 default 9 if ARM64_16K_PAGES 335 default 11 336 337config ARCH_MMAP_RND_COMPAT_BITS_MAX 338 default 16 339 340config NO_IOPORT_MAP 341 def_bool y if !PCI 342 343config STACKTRACE_SUPPORT 344 def_bool y 345 346config ILLEGAL_POINTER_VALUE 347 hex 348 default 0xdead000000000000 349 350config LOCKDEP_SUPPORT 351 def_bool y 352 353config GENERIC_BUG 354 def_bool y 355 depends on BUG 356 357config GENERIC_BUG_RELATIVE_POINTERS 358 def_bool y 359 depends on GENERIC_BUG 360 361config GENERIC_HWEIGHT 362 def_bool y 363 364config GENERIC_CSUM 365 def_bool y 366 367config GENERIC_CALIBRATE_DELAY 368 def_bool y 369 370config SMP 371 def_bool y 372 373config KERNEL_MODE_NEON 374 def_bool y 375 376config FIX_EARLYCON_MEM 377 def_bool y 378 379config PGTABLE_LEVELS 380 int 381 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 382 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 383 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 384 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 385 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 386 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 387 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 388 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 389 390config ARCH_SUPPORTS_UPROBES 391 def_bool y 392 393config ARCH_PROC_KCORE_TEXT 394 def_bool y 395 396config BROKEN_GAS_INST 397 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 398 399config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 400 bool 401 # Clang's __builtin_return_address() strips the PAC since 12.0.0 402 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 403 default y if CC_IS_CLANG 404 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 405 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 406 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 407 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 408 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 409 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 410 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 411 default n 412 413config KASAN_SHADOW_OFFSET 414 hex 415 depends on KASAN_GENERIC || KASAN_SW_TAGS 416 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 417 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 418 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 419 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 420 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 421 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 422 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 423 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 424 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 425 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 426 default 0xffffffffffffffff 427 428config UNWIND_TABLES 429 bool 430 431source "arch/arm64/Kconfig.platforms" 432 433menu "Kernel Features" 434 435menu "ARM errata workarounds via the alternatives framework" 436 437config AMPERE_ERRATUM_AC03_CPU_38 438 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 439 default y 440 help 441 This option adds an alternative code sequence to work around Ampere 442 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 443 444 The affected design reports FEAT_HAFDBS as not implemented in 445 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 446 as required by the architecture. The unadvertised HAFDBS 447 implementation suffers from an additional erratum where hardware 448 A/D updates can occur after a PTE has been marked invalid. 449 450 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 451 which avoids enabling unadvertised hardware Access Flag management 452 at stage-2. 453 454 If unsure, say Y. 455 456config ARM64_WORKAROUND_CLEAN_CACHE 457 bool 458 459config ARM64_ERRATUM_826319 460 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 461 default y 462 select ARM64_WORKAROUND_CLEAN_CACHE 463 help 464 This option adds an alternative code sequence to work around ARM 465 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 466 AXI master interface and an L2 cache. 467 468 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 469 and is unable to accept a certain write via this interface, it will 470 not progress on read data presented on the read data channel and the 471 system can deadlock. 472 473 The workaround promotes data cache clean instructions to 474 data cache clean-and-invalidate. 475 Please note that this does not necessarily enable the workaround, 476 as it depends on the alternative framework, which will only patch 477 the kernel if an affected CPU is detected. 478 479 If unsure, say Y. 480 481config ARM64_ERRATUM_827319 482 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 483 default y 484 select ARM64_WORKAROUND_CLEAN_CACHE 485 help 486 This option adds an alternative code sequence to work around ARM 487 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 488 master interface and an L2 cache. 489 490 Under certain conditions this erratum can cause a clean line eviction 491 to occur at the same time as another transaction to the same address 492 on the AMBA 5 CHI interface, which can cause data corruption if the 493 interconnect reorders the two transactions. 494 495 The workaround promotes data cache clean instructions to 496 data cache clean-and-invalidate. 497 Please note that this does not necessarily enable the workaround, 498 as it depends on the alternative framework, which will only patch 499 the kernel if an affected CPU is detected. 500 501 If unsure, say Y. 502 503config ARM64_ERRATUM_824069 504 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 505 default y 506 select ARM64_WORKAROUND_CLEAN_CACHE 507 help 508 This option adds an alternative code sequence to work around ARM 509 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 510 to a coherent interconnect. 511 512 If a Cortex-A53 processor is executing a store or prefetch for 513 write instruction at the same time as a processor in another 514 cluster is executing a cache maintenance operation to the same 515 address, then this erratum might cause a clean cache line to be 516 incorrectly marked as dirty. 517 518 The workaround promotes data cache clean instructions to 519 data cache clean-and-invalidate. 520 Please note that this option does not necessarily enable the 521 workaround, as it depends on the alternative framework, which will 522 only patch the kernel if an affected CPU is detected. 523 524 If unsure, say Y. 525 526config ARM64_ERRATUM_819472 527 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 528 default y 529 select ARM64_WORKAROUND_CLEAN_CACHE 530 help 531 This option adds an alternative code sequence to work around ARM 532 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 533 present when it is connected to a coherent interconnect. 534 535 If the processor is executing a load and store exclusive sequence at 536 the same time as a processor in another cluster is executing a cache 537 maintenance operation to the same address, then this erratum might 538 cause data corruption. 539 540 The workaround promotes data cache clean instructions to 541 data cache clean-and-invalidate. 542 Please note that this does not necessarily enable the workaround, 543 as it depends on the alternative framework, which will only patch 544 the kernel if an affected CPU is detected. 545 546 If unsure, say Y. 547 548config ARM64_ERRATUM_832075 549 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 550 default y 551 help 552 This option adds an alternative code sequence to work around ARM 553 erratum 832075 on Cortex-A57 parts up to r1p2. 554 555 Affected Cortex-A57 parts might deadlock when exclusive load/store 556 instructions to Write-Back memory are mixed with Device loads. 557 558 The workaround is to promote device loads to use Load-Acquire 559 semantics. 560 Please note that this does not necessarily enable the workaround, 561 as it depends on the alternative framework, which will only patch 562 the kernel if an affected CPU is detected. 563 564 If unsure, say Y. 565 566config ARM64_ERRATUM_834220 567 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 568 depends on KVM 569 help 570 This option adds an alternative code sequence to work around ARM 571 erratum 834220 on Cortex-A57 parts up to r1p2. 572 573 Affected Cortex-A57 parts might report a Stage 2 translation 574 fault as the result of a Stage 1 fault for load crossing a 575 page boundary when there is a permission or device memory 576 alignment fault at Stage 1 and a translation fault at Stage 2. 577 578 The workaround is to verify that the Stage 1 translation 579 doesn't generate a fault before handling the Stage 2 fault. 580 Please note that this does not necessarily enable the workaround, 581 as it depends on the alternative framework, which will only patch 582 the kernel if an affected CPU is detected. 583 584 If unsure, say N. 585 586config ARM64_ERRATUM_1742098 587 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 588 depends on COMPAT 589 default y 590 help 591 This option removes the AES hwcap for aarch32 user-space to 592 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 593 594 Affected parts may corrupt the AES state if an interrupt is 595 taken between a pair of AES instructions. These instructions 596 are only present if the cryptography extensions are present. 597 All software should have a fallback implementation for CPUs 598 that don't implement the cryptography extensions. 599 600 If unsure, say Y. 601 602config ARM64_ERRATUM_845719 603 bool "Cortex-A53: 845719: a load might read incorrect data" 604 depends on COMPAT 605 default y 606 help 607 This option adds an alternative code sequence to work around ARM 608 erratum 845719 on Cortex-A53 parts up to r0p4. 609 610 When running a compat (AArch32) userspace on an affected Cortex-A53 611 part, a load at EL0 from a virtual address that matches the bottom 32 612 bits of the virtual address used by a recent load at (AArch64) EL1 613 might return incorrect data. 614 615 The workaround is to write the contextidr_el1 register on exception 616 return to a 32-bit task. 617 Please note that this does not necessarily enable the workaround, 618 as it depends on the alternative framework, which will only patch 619 the kernel if an affected CPU is detected. 620 621 If unsure, say Y. 622 623config ARM64_ERRATUM_843419 624 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 625 default y 626 help 627 This option links the kernel with '--fix-cortex-a53-843419' and 628 enables PLT support to replace certain ADRP instructions, which can 629 cause subsequent memory accesses to use an incorrect address on 630 Cortex-A53 parts up to r0p4. 631 632 If unsure, say Y. 633 634config ARM64_LD_HAS_FIX_ERRATUM_843419 635 def_bool $(ld-option,--fix-cortex-a53-843419) 636 637config ARM64_ERRATUM_1024718 638 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 639 default y 640 help 641 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 642 643 Affected Cortex-A55 cores (all revisions) could cause incorrect 644 update of the hardware dirty bit when the DBM/AP bits are updated 645 without a break-before-make. The workaround is to disable the usage 646 of hardware DBM locally on the affected cores. CPUs not affected by 647 this erratum will continue to use the feature. 648 649 If unsure, say Y. 650 651config ARM64_ERRATUM_1418040 652 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 653 default y 654 depends on COMPAT 655 help 656 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 657 errata 1188873 and 1418040. 658 659 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 660 cause register corruption when accessing the timer registers 661 from AArch32 userspace. 662 663 If unsure, say Y. 664 665config ARM64_WORKAROUND_SPECULATIVE_AT 666 bool 667 668config ARM64_ERRATUM_1165522 669 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 670 default y 671 select ARM64_WORKAROUND_SPECULATIVE_AT 672 help 673 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 674 675 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 676 corrupted TLBs by speculating an AT instruction during a guest 677 context switch. 678 679 If unsure, say Y. 680 681config ARM64_ERRATUM_1319367 682 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 683 default y 684 select ARM64_WORKAROUND_SPECULATIVE_AT 685 help 686 This option adds work arounds for ARM Cortex-A57 erratum 1319537 687 and A72 erratum 1319367 688 689 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 690 speculating an AT instruction during a guest context switch. 691 692 If unsure, say Y. 693 694config ARM64_ERRATUM_1530923 695 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 696 default y 697 select ARM64_WORKAROUND_SPECULATIVE_AT 698 help 699 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 700 701 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 702 corrupted TLBs by speculating an AT instruction during a guest 703 context switch. 704 705 If unsure, say Y. 706 707config ARM64_WORKAROUND_REPEAT_TLBI 708 bool 709 710config ARM64_ERRATUM_2441007 711 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 712 select ARM64_WORKAROUND_REPEAT_TLBI 713 help 714 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 715 716 Under very rare circumstances, affected Cortex-A55 CPUs 717 may not handle a race between a break-before-make sequence on one 718 CPU, and another CPU accessing the same page. This could allow a 719 store to a page that has been unmapped. 720 721 Work around this by adding the affected CPUs to the list that needs 722 TLB sequences to be done twice. 723 724 If unsure, say N. 725 726config ARM64_ERRATUM_1286807 727 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 728 select ARM64_WORKAROUND_REPEAT_TLBI 729 help 730 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 731 732 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 733 address for a cacheable mapping of a location is being 734 accessed by a core while another core is remapping the virtual 735 address to a new physical page using the recommended 736 break-before-make sequence, then under very rare circumstances 737 TLBI+DSB completes before a read using the translation being 738 invalidated has been observed by other observers. The 739 workaround repeats the TLBI+DSB operation. 740 741 If unsure, say N. 742 743config ARM64_ERRATUM_1463225 744 bool "Cortex-A76: Software Step might prevent interrupt recognition" 745 default y 746 help 747 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 748 749 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 750 of a system call instruction (SVC) can prevent recognition of 751 subsequent interrupts when software stepping is disabled in the 752 exception handler of the system call and either kernel debugging 753 is enabled or VHE is in use. 754 755 Work around the erratum by triggering a dummy step exception 756 when handling a system call from a task that is being stepped 757 in a VHE configuration of the kernel. 758 759 If unsure, say Y. 760 761config ARM64_ERRATUM_1542419 762 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 763 help 764 This option adds a workaround for ARM Neoverse-N1 erratum 765 1542419. 766 767 Affected Neoverse-N1 cores could execute a stale instruction when 768 modified by another CPU. The workaround depends on a firmware 769 counterpart. 770 771 Workaround the issue by hiding the DIC feature from EL0. This 772 forces user-space to perform cache maintenance. 773 774 If unsure, say N. 775 776config ARM64_ERRATUM_1508412 777 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 778 default y 779 help 780 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 781 782 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 783 of a store-exclusive or read of PAR_EL1 and a load with device or 784 non-cacheable memory attributes. The workaround depends on a firmware 785 counterpart. 786 787 KVM guests must also have the workaround implemented or they can 788 deadlock the system. 789 790 Work around the issue by inserting DMB SY barriers around PAR_EL1 791 register reads and warning KVM users. The DMB barrier is sufficient 792 to prevent a speculative PAR_EL1 read. 793 794 If unsure, say Y. 795 796config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 797 bool 798 799config ARM64_ERRATUM_2051678 800 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 801 default y 802 help 803 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 804 Affected Cortex-A510 might not respect the ordering rules for 805 hardware update of the page table's dirty bit. The workaround 806 is to not enable the feature on affected CPUs. 807 808 If unsure, say Y. 809 810config ARM64_ERRATUM_2077057 811 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 812 default y 813 help 814 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 815 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 816 expected, but a Pointer Authentication trap is taken instead. The 817 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 818 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 819 820 This can only happen when EL2 is stepping EL1. 821 822 When these conditions occur, the SPSR_EL2 value is unchanged from the 823 previous guest entry, and can be restored from the in-memory copy. 824 825 If unsure, say Y. 826 827config ARM64_ERRATUM_2658417 828 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 829 default y 830 help 831 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 832 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 833 BFMMLA or VMMLA instructions in rare circumstances when a pair of 834 A510 CPUs are using shared neon hardware. As the sharing is not 835 discoverable by the kernel, hide the BF16 HWCAP to indicate that 836 user-space should not be using these instructions. 837 838 If unsure, say Y. 839 840config ARM64_ERRATUM_2119858 841 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 842 default y 843 depends on CORESIGHT_TRBE 844 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 845 help 846 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 847 848 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 849 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 850 the event of a WRAP event. 851 852 Work around the issue by always making sure we move the TRBPTR_EL1 by 853 256 bytes before enabling the buffer and filling the first 256 bytes of 854 the buffer with ETM ignore packets upon disabling. 855 856 If unsure, say Y. 857 858config ARM64_ERRATUM_2139208 859 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 860 default y 861 depends on CORESIGHT_TRBE 862 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 863 help 864 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 865 866 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 867 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 868 the event of a WRAP event. 869 870 Work around the issue by always making sure we move the TRBPTR_EL1 by 871 256 bytes before enabling the buffer and filling the first 256 bytes of 872 the buffer with ETM ignore packets upon disabling. 873 874 If unsure, say Y. 875 876config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 877 bool 878 879config ARM64_ERRATUM_2054223 880 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 881 default y 882 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 883 help 884 Enable workaround for ARM Cortex-A710 erratum 2054223 885 886 Affected cores may fail to flush the trace data on a TSB instruction, when 887 the PE is in trace prohibited state. This will cause losing a few bytes 888 of the trace cached. 889 890 Workaround is to issue two TSB consecutively on affected cores. 891 892 If unsure, say Y. 893 894config ARM64_ERRATUM_2067961 895 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 896 default y 897 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 898 help 899 Enable workaround for ARM Neoverse-N2 erratum 2067961 900 901 Affected cores may fail to flush the trace data on a TSB instruction, when 902 the PE is in trace prohibited state. This will cause losing a few bytes 903 of the trace cached. 904 905 Workaround is to issue two TSB consecutively on affected cores. 906 907 If unsure, say Y. 908 909config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 910 bool 911 912config ARM64_ERRATUM_2253138 913 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 914 depends on CORESIGHT_TRBE 915 default y 916 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 917 help 918 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 919 920 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 921 for TRBE. Under some conditions, the TRBE might generate a write to the next 922 virtually addressed page following the last page of the TRBE address space 923 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 924 925 Work around this in the driver by always making sure that there is a 926 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 927 928 If unsure, say Y. 929 930config ARM64_ERRATUM_2224489 931 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 932 depends on CORESIGHT_TRBE 933 default y 934 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 935 help 936 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 937 938 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 939 for TRBE. Under some conditions, the TRBE might generate a write to the next 940 virtually addressed page following the last page of the TRBE address space 941 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 942 943 Work around this in the driver by always making sure that there is a 944 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 945 946 If unsure, say Y. 947 948config ARM64_ERRATUM_2441009 949 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 950 select ARM64_WORKAROUND_REPEAT_TLBI 951 help 952 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 953 954 Under very rare circumstances, affected Cortex-A510 CPUs 955 may not handle a race between a break-before-make sequence on one 956 CPU, and another CPU accessing the same page. This could allow a 957 store to a page that has been unmapped. 958 959 Work around this by adding the affected CPUs to the list that needs 960 TLB sequences to be done twice. 961 962 If unsure, say N. 963 964config ARM64_ERRATUM_2064142 965 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 966 depends on CORESIGHT_TRBE 967 default y 968 help 969 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 970 971 Affected Cortex-A510 core might fail to write into system registers after the 972 TRBE has been disabled. Under some conditions after the TRBE has been disabled 973 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 974 and TRBTRG_EL1 will be ignored and will not be effected. 975 976 Work around this in the driver by executing TSB CSYNC and DSB after collection 977 is stopped and before performing a system register write to one of the affected 978 registers. 979 980 If unsure, say Y. 981 982config ARM64_ERRATUM_2038923 983 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 984 depends on CORESIGHT_TRBE 985 default y 986 help 987 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 988 989 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 990 prohibited within the CPU. As a result, the trace buffer or trace buffer state 991 might be corrupted. This happens after TRBE buffer has been enabled by setting 992 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 993 execution changes from a context, in which trace is prohibited to one where it 994 isn't, or vice versa. In these mentioned conditions, the view of whether trace 995 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 996 the trace buffer state might be corrupted. 997 998 Work around this in the driver by preventing an inconsistent view of whether the 999 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1000 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1001 two ISB instructions if no ERET is to take place. 1002 1003 If unsure, say Y. 1004 1005config ARM64_ERRATUM_1902691 1006 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1007 depends on CORESIGHT_TRBE 1008 default y 1009 help 1010 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1011 1012 Affected Cortex-A510 core might cause trace data corruption, when being written 1013 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1014 trace data. 1015 1016 Work around this problem in the driver by just preventing TRBE initialization on 1017 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1018 on such implementations. This will cover the kernel for any firmware that doesn't 1019 do this already. 1020 1021 If unsure, say Y. 1022 1023config ARM64_ERRATUM_2457168 1024 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1025 depends on ARM64_AMU_EXTN 1026 default y 1027 help 1028 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1029 1030 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1031 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1032 incorrectly giving a significantly higher output value. 1033 1034 Work around this problem by returning 0 when reading the affected counter in 1035 key locations that results in disabling all users of this counter. This effect 1036 is the same to firmware disabling affected counters. 1037 1038 If unsure, say Y. 1039 1040config ARM64_ERRATUM_2645198 1041 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1042 default y 1043 help 1044 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1045 1046 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1047 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1048 next instruction abort caused by permission fault. 1049 1050 Only user-space does executable to non-executable permission transition via 1051 mprotect() system call. Workaround the problem by doing a break-before-make 1052 TLB invalidation, for all changes to executable user space mappings. 1053 1054 If unsure, say Y. 1055 1056config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1057 bool 1058 1059config ARM64_ERRATUM_2966298 1060 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1061 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1062 default y 1063 help 1064 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1065 1066 On an affected Cortex-A520 core, a speculatively executed unprivileged 1067 load might leak data from a privileged level via a cache side channel. 1068 1069 Work around this problem by executing a TLBI before returning to EL0. 1070 1071 If unsure, say Y. 1072 1073config ARM64_ERRATUM_3117295 1074 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1075 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1076 default y 1077 help 1078 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1079 1080 On an affected Cortex-A510 core, a speculatively executed unprivileged 1081 load might leak data from a privileged level via a cache side channel. 1082 1083 Work around this problem by executing a TLBI before returning to EL0. 1084 1085 If unsure, say Y. 1086 1087config ARM64_ERRATUM_3194386 1088 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1089 default y 1090 help 1091 This option adds the workaround for the following errata: 1092 1093 * ARM Cortex-A76 erratum 3324349 1094 * ARM Cortex-A77 erratum 3324348 1095 * ARM Cortex-A78 erratum 3324344 1096 * ARM Cortex-A78C erratum 3324346 1097 * ARM Cortex-A78C erratum 3324347 1098 * ARM Cortex-A710 erratam 3324338 1099 * ARM Cortex-A715 errartum 3456084 1100 * ARM Cortex-A720 erratum 3456091 1101 * ARM Cortex-A725 erratum 3456106 1102 * ARM Cortex-X1 erratum 3324344 1103 * ARM Cortex-X1C erratum 3324346 1104 * ARM Cortex-X2 erratum 3324338 1105 * ARM Cortex-X3 erratum 3324335 1106 * ARM Cortex-X4 erratum 3194386 1107 * ARM Cortex-X925 erratum 3324334 1108 * ARM Neoverse-N1 erratum 3324349 1109 * ARM Neoverse N2 erratum 3324339 1110 * ARM Neoverse-N3 erratum 3456111 1111 * ARM Neoverse-V1 erratum 3324341 1112 * ARM Neoverse V2 erratum 3324336 1113 * ARM Neoverse-V3 erratum 3312417 1114 1115 On affected cores "MSR SSBS, #0" instructions may not affect 1116 subsequent speculative instructions, which may permit unexepected 1117 speculative store bypassing. 1118 1119 Work around this problem by placing a Speculation Barrier (SB) or 1120 Instruction Synchronization Barrier (ISB) after kernel changes to 1121 SSBS. The presence of the SSBS special-purpose register is hidden 1122 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1123 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1124 1125 If unsure, say Y. 1126 1127config CAVIUM_ERRATUM_22375 1128 bool "Cavium erratum 22375, 24313" 1129 default y 1130 help 1131 Enable workaround for errata 22375 and 24313. 1132 1133 This implements two gicv3-its errata workarounds for ThunderX. Both 1134 with a small impact affecting only ITS table allocation. 1135 1136 erratum 22375: only alloc 8MB table size 1137 erratum 24313: ignore memory access type 1138 1139 The fixes are in ITS initialization and basically ignore memory access 1140 type and table size provided by the TYPER and BASER registers. 1141 1142 If unsure, say Y. 1143 1144config CAVIUM_ERRATUM_23144 1145 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1146 depends on NUMA 1147 default y 1148 help 1149 ITS SYNC command hang for cross node io and collections/cpu mapping. 1150 1151 If unsure, say Y. 1152 1153config CAVIUM_ERRATUM_23154 1154 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1155 default y 1156 help 1157 The ThunderX GICv3 implementation requires a modified version for 1158 reading the IAR status to ensure data synchronization 1159 (access to icc_iar1_el1 is not sync'ed before and after). 1160 1161 It also suffers from erratum 38545 (also present on Marvell's 1162 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1163 spuriously presented to the CPU interface. 1164 1165 If unsure, say Y. 1166 1167config CAVIUM_ERRATUM_27456 1168 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1169 default y 1170 help 1171 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1172 instructions may cause the icache to become corrupted if it 1173 contains data for a non-current ASID. The fix is to 1174 invalidate the icache when changing the mm context. 1175 1176 If unsure, say Y. 1177 1178config CAVIUM_ERRATUM_30115 1179 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1180 default y 1181 help 1182 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1183 1.2, and T83 Pass 1.0, KVM guest execution may disable 1184 interrupts in host. Trapping both GICv3 group-0 and group-1 1185 accesses sidesteps the issue. 1186 1187 If unsure, say Y. 1188 1189config CAVIUM_TX2_ERRATUM_219 1190 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1191 default y 1192 help 1193 On Cavium ThunderX2, a load, store or prefetch instruction between a 1194 TTBR update and the corresponding context synchronizing operation can 1195 cause a spurious Data Abort to be delivered to any hardware thread in 1196 the CPU core. 1197 1198 Work around the issue by avoiding the problematic code sequence and 1199 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1200 trap handler performs the corresponding register access, skips the 1201 instruction and ensures context synchronization by virtue of the 1202 exception return. 1203 1204 If unsure, say Y. 1205 1206config FUJITSU_ERRATUM_010001 1207 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1208 default y 1209 help 1210 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1211 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1212 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1213 This fault occurs under a specific hardware condition when a 1214 load/store instruction performs an address translation using: 1215 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1216 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1217 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1218 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1219 1220 The workaround is to ensure these bits are clear in TCR_ELx. 1221 The workaround only affects the Fujitsu-A64FX. 1222 1223 If unsure, say Y. 1224 1225config HISILICON_ERRATUM_161600802 1226 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1227 default y 1228 help 1229 The HiSilicon Hip07 SoC uses the wrong redistributor base 1230 when issued ITS commands such as VMOVP and VMAPP, and requires 1231 a 128kB offset to be applied to the target address in this commands. 1232 1233 If unsure, say Y. 1234 1235config QCOM_FALKOR_ERRATUM_1003 1236 bool "Falkor E1003: Incorrect translation due to ASID change" 1237 default y 1238 help 1239 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1240 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1241 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1242 then only for entries in the walk cache, since the leaf translation 1243 is unchanged. Work around the erratum by invalidating the walk cache 1244 entries for the trampoline before entering the kernel proper. 1245 1246config QCOM_FALKOR_ERRATUM_1009 1247 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1248 default y 1249 select ARM64_WORKAROUND_REPEAT_TLBI 1250 help 1251 On Falkor v1, the CPU may prematurely complete a DSB following a 1252 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1253 one more time to fix the issue. 1254 1255 If unsure, say Y. 1256 1257config QCOM_QDF2400_ERRATUM_0065 1258 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1259 default y 1260 help 1261 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1262 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1263 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1264 1265 If unsure, say Y. 1266 1267config QCOM_FALKOR_ERRATUM_E1041 1268 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1269 default y 1270 help 1271 Falkor CPU may speculatively fetch instructions from an improper 1272 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1273 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1274 1275 If unsure, say Y. 1276 1277config NVIDIA_CARMEL_CNP_ERRATUM 1278 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1279 default y 1280 help 1281 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1282 invalidate shared TLB entries installed by a different core, as it would 1283 on standard ARM cores. 1284 1285 If unsure, say Y. 1286 1287config ROCKCHIP_ERRATUM_3588001 1288 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1289 default y 1290 help 1291 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1292 This means, that its sharability feature may not be used, even though it 1293 is supported by the IP itself. 1294 1295 If unsure, say Y. 1296 1297config SOCIONEXT_SYNQUACER_PREITS 1298 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1299 default y 1300 help 1301 Socionext Synquacer SoCs implement a separate h/w block to generate 1302 MSI doorbell writes with non-zero values for the device ID. 1303 1304 If unsure, say Y. 1305 1306endmenu # "ARM errata workarounds via the alternatives framework" 1307 1308choice 1309 prompt "Page size" 1310 default ARM64_4K_PAGES 1311 help 1312 Page size (translation granule) configuration. 1313 1314config ARM64_4K_PAGES 1315 bool "4KB" 1316 select HAVE_PAGE_SIZE_4KB 1317 help 1318 This feature enables 4KB pages support. 1319 1320config ARM64_16K_PAGES 1321 bool "16KB" 1322 select HAVE_PAGE_SIZE_16KB 1323 help 1324 The system will use 16KB pages support. AArch32 emulation 1325 requires applications compiled with 16K (or a multiple of 16K) 1326 aligned segments. 1327 1328config ARM64_64K_PAGES 1329 bool "64KB" 1330 select HAVE_PAGE_SIZE_64KB 1331 help 1332 This feature enables 64KB pages support (4KB by default) 1333 allowing only two levels of page tables and faster TLB 1334 look-up. AArch32 emulation requires applications compiled 1335 with 64K aligned segments. 1336 1337endchoice 1338 1339choice 1340 prompt "Virtual address space size" 1341 default ARM64_VA_BITS_52 1342 help 1343 Allows choosing one of multiple possible virtual address 1344 space sizes. The level of translation table is determined by 1345 a combination of page size and virtual address space size. 1346 1347config ARM64_VA_BITS_36 1348 bool "36-bit" if EXPERT 1349 depends on PAGE_SIZE_16KB 1350 1351config ARM64_VA_BITS_39 1352 bool "39-bit" 1353 depends on PAGE_SIZE_4KB 1354 1355config ARM64_VA_BITS_42 1356 bool "42-bit" 1357 depends on PAGE_SIZE_64KB 1358 1359config ARM64_VA_BITS_47 1360 bool "47-bit" 1361 depends on PAGE_SIZE_16KB 1362 1363config ARM64_VA_BITS_48 1364 bool "48-bit" 1365 1366config ARM64_VA_BITS_52 1367 bool "52-bit" 1368 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1369 help 1370 Enable 52-bit virtual addressing for userspace when explicitly 1371 requested via a hint to mmap(). The kernel will also use 52-bit 1372 virtual addresses for its own mappings (provided HW support for 1373 this feature is available, otherwise it reverts to 48-bit). 1374 1375 NOTE: Enabling 52-bit virtual addressing in conjunction with 1376 ARMv8.3 Pointer Authentication will result in the PAC being 1377 reduced from 7 bits to 3 bits, which may have a significant 1378 impact on its susceptibility to brute-force attacks. 1379 1380 If unsure, select 48-bit virtual addressing instead. 1381 1382endchoice 1383 1384config ARM64_FORCE_52BIT 1385 bool "Force 52-bit virtual addresses for userspace" 1386 depends on ARM64_VA_BITS_52 && EXPERT 1387 help 1388 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1389 to maintain compatibility with older software by providing 48-bit VAs 1390 unless a hint is supplied to mmap. 1391 1392 This configuration option disables the 48-bit compatibility logic, and 1393 forces all userspace addresses to be 52-bit on HW that supports it. One 1394 should only enable this configuration option for stress testing userspace 1395 memory management code. If unsure say N here. 1396 1397config ARM64_VA_BITS 1398 int 1399 default 36 if ARM64_VA_BITS_36 1400 default 39 if ARM64_VA_BITS_39 1401 default 42 if ARM64_VA_BITS_42 1402 default 47 if ARM64_VA_BITS_47 1403 default 48 if ARM64_VA_BITS_48 1404 default 52 if ARM64_VA_BITS_52 1405 1406choice 1407 prompt "Physical address space size" 1408 default ARM64_PA_BITS_48 1409 help 1410 Choose the maximum physical address range that the kernel will 1411 support. 1412 1413config ARM64_PA_BITS_48 1414 bool "48-bit" 1415 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1416 1417config ARM64_PA_BITS_52 1418 bool "52-bit" 1419 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1420 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1421 help 1422 Enable support for a 52-bit physical address space, introduced as 1423 part of the ARMv8.2-LPA extension. 1424 1425 With this enabled, the kernel will also continue to work on CPUs that 1426 do not support ARMv8.2-LPA, but with some added memory overhead (and 1427 minor performance overhead). 1428 1429endchoice 1430 1431config ARM64_PA_BITS 1432 int 1433 default 48 if ARM64_PA_BITS_48 1434 default 52 if ARM64_PA_BITS_52 1435 1436config ARM64_LPA2 1437 def_bool y 1438 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1439 1440choice 1441 prompt "Endianness" 1442 default CPU_LITTLE_ENDIAN 1443 help 1444 Select the endianness of data accesses performed by the CPU. Userspace 1445 applications will need to be compiled and linked for the endianness 1446 that is selected here. 1447 1448config CPU_BIG_ENDIAN 1449 bool "Build big-endian kernel" 1450 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1451 depends on AS_IS_GNU || AS_VERSION >= 150000 1452 help 1453 Say Y if you plan on running a kernel with a big-endian userspace. 1454 1455config CPU_LITTLE_ENDIAN 1456 bool "Build little-endian kernel" 1457 help 1458 Say Y if you plan on running a kernel with a little-endian userspace. 1459 This is usually the case for distributions targeting arm64. 1460 1461endchoice 1462 1463config SCHED_MC 1464 bool "Multi-core scheduler support" 1465 help 1466 Multi-core scheduler support improves the CPU scheduler's decision 1467 making when dealing with multi-core CPU chips at a cost of slightly 1468 increased overhead in some places. If unsure say N here. 1469 1470config SCHED_CLUSTER 1471 bool "Cluster scheduler support" 1472 help 1473 Cluster scheduler support improves the CPU scheduler's decision 1474 making when dealing with machines that have clusters of CPUs. 1475 Cluster usually means a couple of CPUs which are placed closely 1476 by sharing mid-level caches, last-level cache tags or internal 1477 busses. 1478 1479config SCHED_SMT 1480 bool "SMT scheduler support" 1481 help 1482 Improves the CPU scheduler's decision making when dealing with 1483 MultiThreading at a cost of slightly increased overhead in some 1484 places. If unsure say N here. 1485 1486config NR_CPUS 1487 int "Maximum number of CPUs (2-4096)" 1488 range 2 4096 1489 default "512" 1490 1491config HOTPLUG_CPU 1492 bool "Support for hot-pluggable CPUs" 1493 select GENERIC_IRQ_MIGRATION 1494 help 1495 Say Y here to experiment with turning CPUs off and on. CPUs 1496 can be controlled through /sys/devices/system/cpu. 1497 1498# Common NUMA Features 1499config NUMA 1500 bool "NUMA Memory Allocation and Scheduler Support" 1501 select GENERIC_ARCH_NUMA 1502 select OF_NUMA 1503 select HAVE_SETUP_PER_CPU_AREA 1504 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1505 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1506 select USE_PERCPU_NUMA_NODE_ID 1507 help 1508 Enable NUMA (Non-Uniform Memory Access) support. 1509 1510 The kernel will try to allocate memory used by a CPU on the 1511 local memory of the CPU and add some more 1512 NUMA awareness to the kernel. 1513 1514config NODES_SHIFT 1515 int "Maximum NUMA Nodes (as a power of 2)" 1516 range 1 10 1517 default "4" 1518 depends on NUMA 1519 help 1520 Specify the maximum number of NUMA Nodes available on the target 1521 system. Increases memory reserved to accommodate various tables. 1522 1523source "kernel/Kconfig.hz" 1524 1525config ARCH_SPARSEMEM_ENABLE 1526 def_bool y 1527 select SPARSEMEM_VMEMMAP_ENABLE 1528 select SPARSEMEM_VMEMMAP 1529 1530config HW_PERF_EVENTS 1531 def_bool y 1532 depends on ARM_PMU 1533 1534# Supported by clang >= 7.0 or GCC >= 12.0.0 1535config CC_HAVE_SHADOW_CALL_STACK 1536 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1537 1538config PARAVIRT 1539 bool "Enable paravirtualization code" 1540 help 1541 This changes the kernel so it can modify itself when it is run 1542 under a hypervisor, potentially improving performance significantly 1543 over full virtualization. 1544 1545config PARAVIRT_TIME_ACCOUNTING 1546 bool "Paravirtual steal time accounting" 1547 select PARAVIRT 1548 help 1549 Select this option to enable fine granularity task steal time 1550 accounting. Time spent executing other tasks in parallel with 1551 the current vCPU is discounted from the vCPU power. To account for 1552 that, there can be a small performance impact. 1553 1554 If in doubt, say N here. 1555 1556config ARCH_SUPPORTS_KEXEC 1557 def_bool PM_SLEEP_SMP 1558 1559config ARCH_SUPPORTS_KEXEC_FILE 1560 def_bool y 1561 1562config ARCH_SELECTS_KEXEC_FILE 1563 def_bool y 1564 depends on KEXEC_FILE 1565 select HAVE_IMA_KEXEC if IMA 1566 1567config ARCH_SUPPORTS_KEXEC_SIG 1568 def_bool y 1569 1570config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1571 def_bool y 1572 1573config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1574 def_bool y 1575 1576config ARCH_SUPPORTS_CRASH_DUMP 1577 def_bool y 1578 1579config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1580 def_bool CRASH_RESERVE 1581 1582config TRANS_TABLE 1583 def_bool y 1584 depends on HIBERNATION || KEXEC_CORE 1585 1586config XEN_DOM0 1587 def_bool y 1588 depends on XEN 1589 1590config XEN 1591 bool "Xen guest support on ARM64" 1592 depends on ARM64 && OF 1593 select SWIOTLB_XEN 1594 select PARAVIRT 1595 help 1596 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1597 1598# include/linux/mmzone.h requires the following to be true: 1599# 1600# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1601# 1602# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1603# 1604# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1605# ----+-------------------+--------------+----------------------+-------------------------+ 1606# 4K | 27 | 12 | 15 | 10 | 1607# 16K | 27 | 14 | 13 | 11 | 1608# 64K | 29 | 16 | 13 | 13 | 1609config ARCH_FORCE_MAX_ORDER 1610 int 1611 default "13" if ARM64_64K_PAGES 1612 default "11" if ARM64_16K_PAGES 1613 default "10" 1614 help 1615 The kernel page allocator limits the size of maximal physically 1616 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1617 defines the maximal power of two of number of pages that can be 1618 allocated as a single contiguous block. This option allows 1619 overriding the default setting when ability to allocate very 1620 large blocks of physically contiguous memory is required. 1621 1622 The maximal size of allocation cannot exceed the size of the 1623 section, so the value of MAX_PAGE_ORDER should satisfy 1624 1625 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1626 1627 Don't change if unsure. 1628 1629config UNMAP_KERNEL_AT_EL0 1630 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1631 default y 1632 help 1633 Speculation attacks against some high-performance processors can 1634 be used to bypass MMU permission checks and leak kernel data to 1635 userspace. This can be defended against by unmapping the kernel 1636 when running in userspace, mapping it back in on exception entry 1637 via a trampoline page in the vector table. 1638 1639 If unsure, say Y. 1640 1641config MITIGATE_SPECTRE_BRANCH_HISTORY 1642 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1643 default y 1644 help 1645 Speculation attacks against some high-performance processors can 1646 make use of branch history to influence future speculation. 1647 When taking an exception from user-space, a sequence of branches 1648 or a firmware call overwrites the branch history. 1649 1650config RODATA_FULL_DEFAULT_ENABLED 1651 bool "Apply r/o permissions of VM areas also to their linear aliases" 1652 default y 1653 help 1654 Apply read-only attributes of VM areas to the linear alias of 1655 the backing pages as well. This prevents code or read-only data 1656 from being modified (inadvertently or intentionally) via another 1657 mapping of the same memory page. This additional enhancement can 1658 be turned off at runtime by passing rodata=[off|on] (and turned on 1659 with rodata=full if this option is set to 'n') 1660 1661 This requires the linear region to be mapped down to pages, 1662 which may adversely affect performance in some cases. 1663 1664config ARM64_SW_TTBR0_PAN 1665 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1666 depends on !KCSAN 1667 help 1668 Enabling this option prevents the kernel from accessing 1669 user-space memory directly by pointing TTBR0_EL1 to a reserved 1670 zeroed area and reserved ASID. The user access routines 1671 restore the valid TTBR0_EL1 temporarily. 1672 1673config ARM64_TAGGED_ADDR_ABI 1674 bool "Enable the tagged user addresses syscall ABI" 1675 default y 1676 help 1677 When this option is enabled, user applications can opt in to a 1678 relaxed ABI via prctl() allowing tagged addresses to be passed 1679 to system calls as pointer arguments. For details, see 1680 Documentation/arch/arm64/tagged-address-abi.rst. 1681 1682menuconfig COMPAT 1683 bool "Kernel support for 32-bit EL0" 1684 depends on ARM64_4K_PAGES || EXPERT 1685 select HAVE_UID16 1686 select OLD_SIGSUSPEND3 1687 select COMPAT_OLD_SIGACTION 1688 help 1689 This option enables support for a 32-bit EL0 running under a 64-bit 1690 kernel at EL1. AArch32-specific components such as system calls, 1691 the user helper functions, VFP support and the ptrace interface are 1692 handled appropriately by the kernel. 1693 1694 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1695 that you will only be able to execute AArch32 binaries that were compiled 1696 with page size aligned segments. 1697 1698 If you want to execute 32-bit userspace applications, say Y. 1699 1700if COMPAT 1701 1702config KUSER_HELPERS 1703 bool "Enable kuser helpers page for 32-bit applications" 1704 default y 1705 help 1706 Warning: disabling this option may break 32-bit user programs. 1707 1708 Provide kuser helpers to compat tasks. The kernel provides 1709 helper code to userspace in read only form at a fixed location 1710 to allow userspace to be independent of the CPU type fitted to 1711 the system. This permits binaries to be run on ARMv4 through 1712 to ARMv8 without modification. 1713 1714 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1715 1716 However, the fixed address nature of these helpers can be used 1717 by ROP (return orientated programming) authors when creating 1718 exploits. 1719 1720 If all of the binaries and libraries which run on your platform 1721 are built specifically for your platform, and make no use of 1722 these helpers, then you can turn this option off to hinder 1723 such exploits. However, in that case, if a binary or library 1724 relying on those helpers is run, it will not function correctly. 1725 1726 Say N here only if you are absolutely certain that you do not 1727 need these helpers; otherwise, the safe option is to say Y. 1728 1729config COMPAT_VDSO 1730 bool "Enable vDSO for 32-bit applications" 1731 depends on !CPU_BIG_ENDIAN 1732 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1733 select GENERIC_COMPAT_VDSO 1734 default y 1735 help 1736 Place in the process address space of 32-bit applications an 1737 ELF shared object providing fast implementations of gettimeofday 1738 and clock_gettime. 1739 1740 You must have a 32-bit build of glibc 2.22 or later for programs 1741 to seamlessly take advantage of this. 1742 1743config THUMB2_COMPAT_VDSO 1744 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1745 depends on COMPAT_VDSO 1746 default y 1747 help 1748 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1749 otherwise with '-marm'. 1750 1751config COMPAT_ALIGNMENT_FIXUPS 1752 bool "Fix up misaligned multi-word loads and stores in user space" 1753 1754menuconfig ARMV8_DEPRECATED 1755 bool "Emulate deprecated/obsolete ARMv8 instructions" 1756 depends on SYSCTL 1757 help 1758 Legacy software support may require certain instructions 1759 that have been deprecated or obsoleted in the architecture. 1760 1761 Enable this config to enable selective emulation of these 1762 features. 1763 1764 If unsure, say Y 1765 1766if ARMV8_DEPRECATED 1767 1768config SWP_EMULATION 1769 bool "Emulate SWP/SWPB instructions" 1770 help 1771 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1772 they are always undefined. Say Y here to enable software 1773 emulation of these instructions for userspace using LDXR/STXR. 1774 This feature can be controlled at runtime with the abi.swp 1775 sysctl which is disabled by default. 1776 1777 In some older versions of glibc [<=2.8] SWP is used during futex 1778 trylock() operations with the assumption that the code will not 1779 be preempted. This invalid assumption may be more likely to fail 1780 with SWP emulation enabled, leading to deadlock of the user 1781 application. 1782 1783 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1784 on an external transaction monitoring block called a global 1785 monitor to maintain update atomicity. If your system does not 1786 implement a global monitor, this option can cause programs that 1787 perform SWP operations to uncached memory to deadlock. 1788 1789 If unsure, say Y 1790 1791config CP15_BARRIER_EMULATION 1792 bool "Emulate CP15 Barrier instructions" 1793 help 1794 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1795 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1796 strongly recommended to use the ISB, DSB, and DMB 1797 instructions instead. 1798 1799 Say Y here to enable software emulation of these 1800 instructions for AArch32 userspace code. When this option is 1801 enabled, CP15 barrier usage is traced which can help 1802 identify software that needs updating. This feature can be 1803 controlled at runtime with the abi.cp15_barrier sysctl. 1804 1805 If unsure, say Y 1806 1807config SETEND_EMULATION 1808 bool "Emulate SETEND instruction" 1809 help 1810 The SETEND instruction alters the data-endianness of the 1811 AArch32 EL0, and is deprecated in ARMv8. 1812 1813 Say Y here to enable software emulation of the instruction 1814 for AArch32 userspace code. This feature can be controlled 1815 at runtime with the abi.setend sysctl. 1816 1817 Note: All the cpus on the system must have mixed endian support at EL0 1818 for this feature to be enabled. If a new CPU - which doesn't support mixed 1819 endian - is hotplugged in after this feature has been enabled, there could 1820 be unexpected results in the applications. 1821 1822 If unsure, say Y 1823endif # ARMV8_DEPRECATED 1824 1825endif # COMPAT 1826 1827menu "ARMv8.1 architectural features" 1828 1829config ARM64_HW_AFDBM 1830 bool "Support for hardware updates of the Access and Dirty page flags" 1831 default y 1832 help 1833 The ARMv8.1 architecture extensions introduce support for 1834 hardware updates of the access and dirty information in page 1835 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1836 capable processors, accesses to pages with PTE_AF cleared will 1837 set this bit instead of raising an access flag fault. 1838 Similarly, writes to read-only pages with the DBM bit set will 1839 clear the read-only bit (AP[2]) instead of raising a 1840 permission fault. 1841 1842 Kernels built with this configuration option enabled continue 1843 to work on pre-ARMv8.1 hardware and the performance impact is 1844 minimal. If unsure, say Y. 1845 1846config ARM64_PAN 1847 bool "Enable support for Privileged Access Never (PAN)" 1848 default y 1849 help 1850 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1851 prevents the kernel or hypervisor from accessing user-space (EL0) 1852 memory directly. 1853 1854 Choosing this option will cause any unprotected (not using 1855 copy_to_user et al) memory access to fail with a permission fault. 1856 1857 The feature is detected at runtime, and will remain as a 'nop' 1858 instruction if the cpu does not implement the feature. 1859 1860config AS_HAS_LSE_ATOMICS 1861 def_bool $(as-instr,.arch_extension lse) 1862 1863config ARM64_LSE_ATOMICS 1864 bool 1865 default ARM64_USE_LSE_ATOMICS 1866 depends on AS_HAS_LSE_ATOMICS 1867 1868config ARM64_USE_LSE_ATOMICS 1869 bool "Atomic instructions" 1870 default y 1871 help 1872 As part of the Large System Extensions, ARMv8.1 introduces new 1873 atomic instructions that are designed specifically to scale in 1874 very large systems. 1875 1876 Say Y here to make use of these instructions for the in-kernel 1877 atomic routines. This incurs a small overhead on CPUs that do 1878 not support these instructions and requires the kernel to be 1879 built with binutils >= 2.25 in order for the new instructions 1880 to be used. 1881 1882endmenu # "ARMv8.1 architectural features" 1883 1884menu "ARMv8.2 architectural features" 1885 1886config AS_HAS_ARMV8_2 1887 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1888 1889config AS_HAS_SHA3 1890 def_bool $(as-instr,.arch armv8.2-a+sha3) 1891 1892config ARM64_PMEM 1893 bool "Enable support for persistent memory" 1894 select ARCH_HAS_PMEM_API 1895 select ARCH_HAS_UACCESS_FLUSHCACHE 1896 help 1897 Say Y to enable support for the persistent memory API based on the 1898 ARMv8.2 DCPoP feature. 1899 1900 The feature is detected at runtime, and the kernel will use DC CVAC 1901 operations if DC CVAP is not supported (following the behaviour of 1902 DC CVAP itself if the system does not define a point of persistence). 1903 1904config ARM64_RAS_EXTN 1905 bool "Enable support for RAS CPU Extensions" 1906 default y 1907 help 1908 CPUs that support the Reliability, Availability and Serviceability 1909 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1910 errors, classify them and report them to software. 1911 1912 On CPUs with these extensions system software can use additional 1913 barriers to determine if faults are pending and read the 1914 classification from a new set of registers. 1915 1916 Selecting this feature will allow the kernel to use these barriers 1917 and access the new registers if the system supports the extension. 1918 Platform RAS features may additionally depend on firmware support. 1919 1920config ARM64_CNP 1921 bool "Enable support for Common Not Private (CNP) translations" 1922 default y 1923 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1924 help 1925 Common Not Private (CNP) allows translation table entries to 1926 be shared between different PEs in the same inner shareable 1927 domain, so the hardware can use this fact to optimise the 1928 caching of such entries in the TLB. 1929 1930 Selecting this option allows the CNP feature to be detected 1931 at runtime, and does not affect PEs that do not implement 1932 this feature. 1933 1934endmenu # "ARMv8.2 architectural features" 1935 1936menu "ARMv8.3 architectural features" 1937 1938config ARM64_PTR_AUTH 1939 bool "Enable support for pointer authentication" 1940 default y 1941 help 1942 Pointer authentication (part of the ARMv8.3 Extensions) provides 1943 instructions for signing and authenticating pointers against secret 1944 keys, which can be used to mitigate Return Oriented Programming (ROP) 1945 and other attacks. 1946 1947 This option enables these instructions at EL0 (i.e. for userspace). 1948 Choosing this option will cause the kernel to initialise secret keys 1949 for each process at exec() time, with these keys being 1950 context-switched along with the process. 1951 1952 The feature is detected at runtime. If the feature is not present in 1953 hardware it will not be advertised to userspace/KVM guest nor will it 1954 be enabled. 1955 1956 If the feature is present on the boot CPU but not on a late CPU, then 1957 the late CPU will be parked. Also, if the boot CPU does not have 1958 address auth and the late CPU has then the late CPU will still boot 1959 but with the feature disabled. On such a system, this option should 1960 not be selected. 1961 1962config ARM64_PTR_AUTH_KERNEL 1963 bool "Use pointer authentication for kernel" 1964 default y 1965 depends on ARM64_PTR_AUTH 1966 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1967 # Modern compilers insert a .note.gnu.property section note for PAC 1968 # which is only understood by binutils starting with version 2.33.1. 1969 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1970 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1971 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1972 help 1973 If the compiler supports the -mbranch-protection or 1974 -msign-return-address flag (e.g. GCC 7 or later), then this option 1975 will cause the kernel itself to be compiled with return address 1976 protection. In this case, and if the target hardware is known to 1977 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1978 disabled with minimal loss of protection. 1979 1980 This feature works with FUNCTION_GRAPH_TRACER option only if 1981 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1982 1983config CC_HAS_BRANCH_PROT_PAC_RET 1984 # GCC 9 or later, clang 8 or later 1985 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1986 1987config CC_HAS_SIGN_RETURN_ADDRESS 1988 # GCC 7, 8 1989 def_bool $(cc-option,-msign-return-address=all) 1990 1991config AS_HAS_ARMV8_3 1992 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1993 1994config AS_HAS_CFI_NEGATE_RA_STATE 1995 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1996 1997config AS_HAS_LDAPR 1998 def_bool $(as-instr,.arch_extension rcpc) 1999 2000endmenu # "ARMv8.3 architectural features" 2001 2002menu "ARMv8.4 architectural features" 2003 2004config ARM64_AMU_EXTN 2005 bool "Enable support for the Activity Monitors Unit CPU extension" 2006 default y 2007 help 2008 The activity monitors extension is an optional extension introduced 2009 by the ARMv8.4 CPU architecture. This enables support for version 1 2010 of the activity monitors architecture, AMUv1. 2011 2012 To enable the use of this extension on CPUs that implement it, say Y. 2013 2014 Note that for architectural reasons, firmware _must_ implement AMU 2015 support when running on CPUs that present the activity monitors 2016 extension. The required support is present in: 2017 * Version 1.5 and later of the ARM Trusted Firmware 2018 2019 For kernels that have this configuration enabled but boot with broken 2020 firmware, you may need to say N here until the firmware is fixed. 2021 Otherwise you may experience firmware panics or lockups when 2022 accessing the counter registers. Even if you are not observing these 2023 symptoms, the values returned by the register reads might not 2024 correctly reflect reality. Most commonly, the value read will be 0, 2025 indicating that the counter is not enabled. 2026 2027config AS_HAS_ARMV8_4 2028 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2029 2030config ARM64_TLB_RANGE 2031 bool "Enable support for tlbi range feature" 2032 default y 2033 depends on AS_HAS_ARMV8_4 2034 help 2035 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2036 range of input addresses. 2037 2038 The feature introduces new assembly instructions, and they were 2039 support when binutils >= 2.30. 2040 2041endmenu # "ARMv8.4 architectural features" 2042 2043menu "ARMv8.5 architectural features" 2044 2045config AS_HAS_ARMV8_5 2046 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2047 2048config ARM64_BTI 2049 bool "Branch Target Identification support" 2050 default y 2051 help 2052 Branch Target Identification (part of the ARMv8.5 Extensions) 2053 provides a mechanism to limit the set of locations to which computed 2054 branch instructions such as BR or BLR can jump. 2055 2056 To make use of BTI on CPUs that support it, say Y. 2057 2058 BTI is intended to provide complementary protection to other control 2059 flow integrity protection mechanisms, such as the Pointer 2060 authentication mechanism provided as part of the ARMv8.3 Extensions. 2061 For this reason, it does not make sense to enable this option without 2062 also enabling support for pointer authentication. Thus, when 2063 enabling this option you should also select ARM64_PTR_AUTH=y. 2064 2065 Userspace binaries must also be specifically compiled to make use of 2066 this mechanism. If you say N here or the hardware does not support 2067 BTI, such binaries can still run, but you get no additional 2068 enforcement of branch destinations. 2069 2070config ARM64_BTI_KERNEL 2071 bool "Use Branch Target Identification for kernel" 2072 default y 2073 depends on ARM64_BTI 2074 depends on ARM64_PTR_AUTH_KERNEL 2075 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2076 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2077 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2078 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2079 depends on !CC_IS_GCC 2080 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2081 help 2082 Build the kernel with Branch Target Identification annotations 2083 and enable enforcement of this for kernel code. When this option 2084 is enabled and the system supports BTI all kernel code including 2085 modular code must have BTI enabled. 2086 2087config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2088 # GCC 9 or later, clang 8 or later 2089 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2090 2091config ARM64_E0PD 2092 bool "Enable support for E0PD" 2093 default y 2094 help 2095 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2096 that EL0 accesses made via TTBR1 always fault in constant time, 2097 providing similar benefits to KASLR as those provided by KPTI, but 2098 with lower overhead and without disrupting legitimate access to 2099 kernel memory such as SPE. 2100 2101 This option enables E0PD for TTBR1 where available. 2102 2103config ARM64_AS_HAS_MTE 2104 # Initial support for MTE went in binutils 2.32.0, checked with 2105 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2106 # as a late addition to the final architecture spec (LDGM/STGM) 2107 # is only supported in the newer 2.32.x and 2.33 binutils 2108 # versions, hence the extra "stgm" instruction check below. 2109 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2110 2111config ARM64_MTE 2112 bool "Memory Tagging Extension support" 2113 default y 2114 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2115 depends on AS_HAS_ARMV8_5 2116 depends on AS_HAS_LSE_ATOMICS 2117 # Required for tag checking in the uaccess routines 2118 depends on ARM64_PAN 2119 select ARCH_HAS_SUBPAGE_FAULTS 2120 select ARCH_USES_HIGH_VMA_FLAGS 2121 select ARCH_USES_PG_ARCH_2 2122 select ARCH_USES_PG_ARCH_3 2123 help 2124 Memory Tagging (part of the ARMv8.5 Extensions) provides 2125 architectural support for run-time, always-on detection of 2126 various classes of memory error to aid with software debugging 2127 to eliminate vulnerabilities arising from memory-unsafe 2128 languages. 2129 2130 This option enables the support for the Memory Tagging 2131 Extension at EL0 (i.e. for userspace). 2132 2133 Selecting this option allows the feature to be detected at 2134 runtime. Any secondary CPU not implementing this feature will 2135 not be allowed a late bring-up. 2136 2137 Userspace binaries that want to use this feature must 2138 explicitly opt in. The mechanism for the userspace is 2139 described in: 2140 2141 Documentation/arch/arm64/memory-tagging-extension.rst. 2142 2143endmenu # "ARMv8.5 architectural features" 2144 2145menu "ARMv8.7 architectural features" 2146 2147config ARM64_EPAN 2148 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2149 default y 2150 depends on ARM64_PAN 2151 help 2152 Enhanced Privileged Access Never (EPAN) allows Privileged 2153 Access Never to be used with Execute-only mappings. 2154 2155 The feature is detected at runtime, and will remain disabled 2156 if the cpu does not implement the feature. 2157endmenu # "ARMv8.7 architectural features" 2158 2159menu "ARMv8.9 architectural features" 2160 2161config ARM64_POE 2162 prompt "Permission Overlay Extension" 2163 def_bool y 2164 select ARCH_USES_HIGH_VMA_FLAGS 2165 select ARCH_HAS_PKEYS 2166 help 2167 The Permission Overlay Extension is used to implement Memory 2168 Protection Keys. Memory Protection Keys provides a mechanism for 2169 enforcing page-based protections, but without requiring modification 2170 of the page tables when an application changes protection domains. 2171 2172 For details, see Documentation/core-api/protection-keys.rst 2173 2174 If unsure, say y. 2175 2176config ARCH_PKEY_BITS 2177 int 2178 default 3 2179 2180endmenu # "ARMv8.9 architectural features" 2181 2182config ARM64_SVE 2183 bool "ARM Scalable Vector Extension support" 2184 default y 2185 help 2186 The Scalable Vector Extension (SVE) is an extension to the AArch64 2187 execution state which complements and extends the SIMD functionality 2188 of the base architecture to support much larger vectors and to enable 2189 additional vectorisation opportunities. 2190 2191 To enable use of this extension on CPUs that implement it, say Y. 2192 2193 On CPUs that support the SVE2 extensions, this option will enable 2194 those too. 2195 2196 Note that for architectural reasons, firmware _must_ implement SVE 2197 support when running on SVE capable hardware. The required support 2198 is present in: 2199 2200 * version 1.5 and later of the ARM Trusted Firmware 2201 * the AArch64 boot wrapper since commit 5e1261e08abf 2202 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2203 2204 For other firmware implementations, consult the firmware documentation 2205 or vendor. 2206 2207 If you need the kernel to boot on SVE-capable hardware with broken 2208 firmware, you may need to say N here until you get your firmware 2209 fixed. Otherwise, you may experience firmware panics or lockups when 2210 booting the kernel. If unsure and you are not observing these 2211 symptoms, you should assume that it is safe to say Y. 2212 2213config ARM64_SME 2214 bool "ARM Scalable Matrix Extension support" 2215 default y 2216 depends on ARM64_SVE 2217 help 2218 The Scalable Matrix Extension (SME) is an extension to the AArch64 2219 execution state which utilises a substantial subset of the SVE 2220 instruction set, together with the addition of new architectural 2221 register state capable of holding two dimensional matrix tiles to 2222 enable various matrix operations. 2223 2224config ARM64_PSEUDO_NMI 2225 bool "Support for NMI-like interrupts" 2226 select ARM_GIC_V3 2227 help 2228 Adds support for mimicking Non-Maskable Interrupts through the use of 2229 GIC interrupt priority. This support requires version 3 or later of 2230 ARM GIC. 2231 2232 This high priority configuration for interrupts needs to be 2233 explicitly enabled by setting the kernel parameter 2234 "irqchip.gicv3_pseudo_nmi" to 1. 2235 2236 If unsure, say N 2237 2238if ARM64_PSEUDO_NMI 2239config ARM64_DEBUG_PRIORITY_MASKING 2240 bool "Debug interrupt priority masking" 2241 help 2242 This adds runtime checks to functions enabling/disabling 2243 interrupts when using priority masking. The additional checks verify 2244 the validity of ICC_PMR_EL1 when calling concerned functions. 2245 2246 If unsure, say N 2247endif # ARM64_PSEUDO_NMI 2248 2249config RELOCATABLE 2250 bool "Build a relocatable kernel image" if EXPERT 2251 select ARCH_HAS_RELR 2252 default y 2253 help 2254 This builds the kernel as a Position Independent Executable (PIE), 2255 which retains all relocation metadata required to relocate the 2256 kernel binary at runtime to a different virtual address than the 2257 address it was linked at. 2258 Since AArch64 uses the RELA relocation format, this requires a 2259 relocation pass at runtime even if the kernel is loaded at the 2260 same address it was linked at. 2261 2262config RANDOMIZE_BASE 2263 bool "Randomize the address of the kernel image" 2264 select RELOCATABLE 2265 help 2266 Randomizes the virtual address at which the kernel image is 2267 loaded, as a security feature that deters exploit attempts 2268 relying on knowledge of the location of kernel internals. 2269 2270 It is the bootloader's job to provide entropy, by passing a 2271 random u64 value in /chosen/kaslr-seed at kernel entry. 2272 2273 When booting via the UEFI stub, it will invoke the firmware's 2274 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2275 to the kernel proper. In addition, it will randomise the physical 2276 location of the kernel Image as well. 2277 2278 If unsure, say N. 2279 2280config RANDOMIZE_MODULE_REGION_FULL 2281 bool "Randomize the module region over a 2 GB range" 2282 depends on RANDOMIZE_BASE 2283 default y 2284 help 2285 Randomizes the location of the module region inside a 2 GB window 2286 covering the core kernel. This way, it is less likely for modules 2287 to leak information about the location of core kernel data structures 2288 but it does imply that function calls between modules and the core 2289 kernel will need to be resolved via veneers in the module PLT. 2290 2291 When this option is not set, the module region will be randomized over 2292 a limited range that contains the [_stext, _etext] interval of the 2293 core kernel, so branch relocations are almost always in range unless 2294 the region is exhausted. In this particular case of region 2295 exhaustion, modules might be able to fall back to a larger 2GB area. 2296 2297config CC_HAVE_STACKPROTECTOR_SYSREG 2298 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2299 2300config STACKPROTECTOR_PER_TASK 2301 def_bool y 2302 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2303 2304config UNWIND_PATCH_PAC_INTO_SCS 2305 bool "Enable shadow call stack dynamically using code patching" 2306 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2307 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2308 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2309 depends on SHADOW_CALL_STACK 2310 select UNWIND_TABLES 2311 select DYNAMIC_SCS 2312 2313config ARM64_CONTPTE 2314 bool "Contiguous PTE mappings for user memory" if EXPERT 2315 depends on TRANSPARENT_HUGEPAGE 2316 default y 2317 help 2318 When enabled, user mappings are configured using the PTE contiguous 2319 bit, for any mappings that meet the size and alignment requirements. 2320 This reduces TLB pressure and improves performance. 2321 2322endmenu # "Kernel Features" 2323 2324menu "Boot options" 2325 2326config ARM64_ACPI_PARKING_PROTOCOL 2327 bool "Enable support for the ARM64 ACPI parking protocol" 2328 depends on ACPI 2329 help 2330 Enable support for the ARM64 ACPI parking protocol. If disabled 2331 the kernel will not allow booting through the ARM64 ACPI parking 2332 protocol even if the corresponding data is present in the ACPI 2333 MADT table. 2334 2335config CMDLINE 2336 string "Default kernel command string" 2337 default "" 2338 help 2339 Provide a set of default command-line options at build time by 2340 entering them here. As a minimum, you should specify the the 2341 root device (e.g. root=/dev/nfs). 2342 2343choice 2344 prompt "Kernel command line type" 2345 depends on CMDLINE != "" 2346 default CMDLINE_FROM_BOOTLOADER 2347 help 2348 Choose how the kernel will handle the provided default kernel 2349 command line string. 2350 2351config CMDLINE_FROM_BOOTLOADER 2352 bool "Use bootloader kernel arguments if available" 2353 help 2354 Uses the command-line options passed by the boot loader. If 2355 the boot loader doesn't provide any, the default kernel command 2356 string provided in CMDLINE will be used. 2357 2358config CMDLINE_FORCE 2359 bool "Always use the default kernel command string" 2360 help 2361 Always use the default kernel command string, even if the boot 2362 loader passes other arguments to the kernel. 2363 This is useful if you cannot or don't want to change the 2364 command-line options your boot loader passes to the kernel. 2365 2366endchoice 2367 2368config EFI_STUB 2369 bool 2370 2371config EFI 2372 bool "UEFI runtime support" 2373 depends on OF && !CPU_BIG_ENDIAN 2374 depends on KERNEL_MODE_NEON 2375 select ARCH_SUPPORTS_ACPI 2376 select LIBFDT 2377 select UCS2_STRING 2378 select EFI_PARAMS_FROM_FDT 2379 select EFI_RUNTIME_WRAPPERS 2380 select EFI_STUB 2381 select EFI_GENERIC_STUB 2382 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2383 default y 2384 help 2385 This option provides support for runtime services provided 2386 by UEFI firmware (such as non-volatile variables, realtime 2387 clock, and platform reset). A UEFI stub is also provided to 2388 allow the kernel to be booted as an EFI application. This 2389 is only useful on systems that have UEFI firmware. 2390 2391config COMPRESSED_INSTALL 2392 bool "Install compressed image by default" 2393 help 2394 This makes the regular "make install" install the compressed 2395 image we built, not the legacy uncompressed one. 2396 2397 You can check that a compressed image works for you by doing 2398 "make zinstall" first, and verifying that everything is fine 2399 in your environment before making "make install" do this for 2400 you. 2401 2402config DMI 2403 bool "Enable support for SMBIOS (DMI) tables" 2404 depends on EFI 2405 default y 2406 help 2407 This enables SMBIOS/DMI feature for systems. 2408 2409 This option is only useful on systems that have UEFI firmware. 2410 However, even with this option, the resultant kernel should 2411 continue to boot on existing non-UEFI platforms. 2412 2413endmenu # "Boot options" 2414 2415menu "Power management options" 2416 2417source "kernel/power/Kconfig" 2418 2419config ARCH_HIBERNATION_POSSIBLE 2420 def_bool y 2421 depends on CPU_PM 2422 2423config ARCH_HIBERNATION_HEADER 2424 def_bool y 2425 depends on HIBERNATION 2426 2427config ARCH_SUSPEND_POSSIBLE 2428 def_bool y 2429 2430endmenu # "Power management options" 2431 2432menu "CPU Power Management" 2433 2434source "drivers/cpuidle/Kconfig" 2435 2436source "drivers/cpufreq/Kconfig" 2437 2438endmenu # "CPU Power Management" 2439 2440source "drivers/acpi/Kconfig" 2441 2442source "arch/arm64/kvm/Kconfig" 2443 2444