1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_IORT if ACPI 9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 10 select ACPI_MCFG if (ACPI && PCI) 11 select ACPI_SPCR_TABLE if ACPI 12 select ACPI_PPTT if ACPI 13 select ARCH_HAS_DEBUG_WX 14 select ARCH_BINFMT_ELF_EXTRA_PHDRS 15 select ARCH_BINFMT_ELF_STATE 16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CURRENT_STACK_POINTER 24 select ARCH_HAS_DEBUG_VIRTUAL 25 select ARCH_HAS_DEBUG_VM_PGTABLE 26 select ARCH_HAS_DMA_PREP_COHERENT 27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 28 select ARCH_HAS_FAST_MULTIPLIER 29 select ARCH_HAS_FORTIFY_SOURCE 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_HAS_GIGANTIC_PAGE 32 select ARCH_HAS_KCOV 33 select ARCH_HAS_KEEPINITRD 34 select ARCH_HAS_MEMBARRIER_SYNC_CORE 35 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 36 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 37 select ARCH_HAS_PTE_DEVMAP 38 select ARCH_HAS_PTE_SPECIAL 39 select ARCH_HAS_SETUP_DMA_OPS 40 select ARCH_HAS_SET_DIRECT_MAP 41 select ARCH_HAS_SET_MEMORY 42 select ARCH_STACKWALK 43 select ARCH_HAS_STRICT_KERNEL_RWX 44 select ARCH_HAS_STRICT_MODULE_RWX 45 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 46 select ARCH_HAS_SYNC_DMA_FOR_CPU 47 select ARCH_HAS_SYSCALL_WRAPPER 48 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 49 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 50 select ARCH_HAS_ZONE_DMA_SET if EXPERT 51 select ARCH_HAVE_ELF_PROT 52 select ARCH_HAVE_NMI_SAFE_CMPXCHG 53 select ARCH_HAVE_TRACE_MMIO_ACCESS 54 select ARCH_INLINE_READ_LOCK if !PREEMPTION 55 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 56 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 57 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 64 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 70 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 71 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 74 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 75 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 80 select ARCH_KEEP_MEMBLOCK 81 select ARCH_USE_CMPXCHG_LOCKREF 82 select ARCH_USE_GNU_PROPERTY 83 select ARCH_USE_MEMTEST 84 select ARCH_USE_QUEUED_RWLOCKS 85 select ARCH_USE_QUEUED_SPINLOCKS 86 select ARCH_USE_SYM_ANNOTATIONS 87 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 88 select ARCH_SUPPORTS_HUGETLBFS 89 select ARCH_SUPPORTS_MEMORY_FAILURE 90 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 91 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 92 select ARCH_SUPPORTS_LTO_CLANG_THIN 93 select ARCH_SUPPORTS_CFI_CLANG 94 select ARCH_SUPPORTS_ATOMIC_RMW 95 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 96 select ARCH_SUPPORTS_NUMA_BALANCING 97 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 98 select ARCH_SUPPORTS_PER_VMA_LOCK 99 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 100 select ARCH_WANT_DEFAULT_BPF_JIT 101 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 102 select ARCH_WANT_FRAME_POINTERS 103 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 104 select ARCH_WANT_LD_ORPHAN_WARN 105 select ARCH_WANTS_NO_INSTR 106 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 107 select ARCH_HAS_UBSAN_SANITIZE_ALL 108 select ARM_AMBA 109 select ARM_ARCH_TIMER 110 select ARM_GIC 111 select AUDIT_ARCH_COMPAT_GENERIC 112 select ARM_GIC_V2M if PCI 113 select ARM_GIC_V3 114 select ARM_GIC_V3_ITS if PCI 115 select ARM_PSCI_FW 116 select BUILDTIME_TABLE_SORT 117 select CLONE_BACKWARDS 118 select COMMON_CLK 119 select CPU_PM if (SUSPEND || CPU_IDLE) 120 select CRC32 121 select DCACHE_WORD_ACCESS 122 select DYNAMIC_FTRACE if FUNCTION_TRACER 123 select DMA_BOUNCE_UNALIGNED_KMALLOC 124 select DMA_DIRECT_REMAP 125 select EDAC_SUPPORT 126 select FRAME_POINTER 127 select FUNCTION_ALIGNMENT_4B 128 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 129 select GENERIC_ALLOCATOR 130 select GENERIC_ARCH_TOPOLOGY 131 select GENERIC_CLOCKEVENTS_BROADCAST 132 select GENERIC_CPU_AUTOPROBE 133 select GENERIC_CPU_VULNERABILITIES 134 select GENERIC_EARLY_IOREMAP 135 select GENERIC_IDLE_POLL_SETUP 136 select GENERIC_IOREMAP 137 select GENERIC_IRQ_IPI 138 select GENERIC_IRQ_PROBE 139 select GENERIC_IRQ_SHOW 140 select GENERIC_IRQ_SHOW_LEVEL 141 select GENERIC_LIB_DEVMEM_IS_ALLOWED 142 select GENERIC_PCI_IOMAP 143 select GENERIC_PTDUMP 144 select GENERIC_SCHED_CLOCK 145 select GENERIC_SMP_IDLE_THREAD 146 select GENERIC_TIME_VSYSCALL 147 select GENERIC_GETTIMEOFDAY 148 select GENERIC_VDSO_TIME_NS 149 select HARDIRQS_SW_RESEND 150 select HAS_IOPORT 151 select HAVE_MOVE_PMD 152 select HAVE_MOVE_PUD 153 select HAVE_PCI 154 select HAVE_ACPI_APEI if (ACPI && EFI) 155 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 156 select HAVE_ARCH_AUDITSYSCALL 157 select HAVE_ARCH_BITREVERSE 158 select HAVE_ARCH_COMPILER_H 159 select HAVE_ARCH_HUGE_VMALLOC 160 select HAVE_ARCH_HUGE_VMAP 161 select HAVE_ARCH_JUMP_LABEL 162 select HAVE_ARCH_JUMP_LABEL_RELATIVE 163 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 164 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 165 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 166 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 167 # Some instrumentation may be unsound, hence EXPERT 168 select HAVE_ARCH_KCSAN if EXPERT 169 select HAVE_ARCH_KFENCE 170 select HAVE_ARCH_KGDB 171 select HAVE_ARCH_MMAP_RND_BITS 172 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 173 select HAVE_ARCH_PREL32_RELOCATIONS 174 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 175 select HAVE_ARCH_SECCOMP_FILTER 176 select HAVE_ARCH_STACKLEAK 177 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 178 select HAVE_ARCH_TRACEHOOK 179 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 180 select HAVE_ARCH_VMAP_STACK 181 select HAVE_ARM_SMCCC 182 select HAVE_ASM_MODVERSIONS 183 select HAVE_EBPF_JIT 184 select HAVE_C_RECORDMCOUNT 185 select HAVE_CMPXCHG_DOUBLE 186 select HAVE_CMPXCHG_LOCAL 187 select HAVE_CONTEXT_TRACKING_USER 188 select HAVE_DEBUG_KMEMLEAK 189 select HAVE_DMA_CONTIGUOUS 190 select HAVE_DYNAMIC_FTRACE 191 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 192 if $(cc-option,-fpatchable-function-entry=2) 193 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 194 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 195 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 196 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 197 !CC_OPTIMIZE_FOR_SIZE) 198 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 199 if DYNAMIC_FTRACE_WITH_ARGS 200 select HAVE_SAMPLE_FTRACE_DIRECT 201 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 202 select HAVE_EFFICIENT_UNALIGNED_ACCESS 203 select HAVE_FAST_GUP 204 select HAVE_FTRACE_MCOUNT_RECORD 205 select HAVE_FUNCTION_TRACER 206 select HAVE_FUNCTION_ERROR_INJECTION 207 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 208 select HAVE_FUNCTION_GRAPH_TRACER 209 select HAVE_GCC_PLUGINS 210 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 211 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 212 select HAVE_HW_BREAKPOINT if PERF_EVENTS 213 select HAVE_IOREMAP_PROT 214 select HAVE_IRQ_TIME_ACCOUNTING 215 select HAVE_KVM 216 select HAVE_MOD_ARCH_SPECIFIC 217 select HAVE_NMI 218 select HAVE_PERF_EVENTS 219 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 220 select HAVE_PERF_REGS 221 select HAVE_PERF_USER_STACK_DUMP 222 select HAVE_PREEMPT_DYNAMIC_KEY 223 select HAVE_REGS_AND_STACK_ACCESS_API 224 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 225 select HAVE_FUNCTION_ARG_ACCESS_API 226 select MMU_GATHER_RCU_TABLE_FREE 227 select HAVE_RSEQ 228 select HAVE_STACKPROTECTOR 229 select HAVE_SYSCALL_TRACEPOINTS 230 select HAVE_KPROBES 231 select HAVE_KRETPROBES 232 select HAVE_GENERIC_VDSO 233 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 234 select IRQ_DOMAIN 235 select IRQ_FORCED_THREADING 236 select KASAN_VMALLOC if KASAN 237 select LOCK_MM_AND_FIND_VMA 238 select MODULES_USE_ELF_RELA 239 select NEED_DMA_MAP_STATE 240 select NEED_SG_DMA_LENGTH 241 select OF 242 select OF_EARLY_FLATTREE 243 select PCI_DOMAINS_GENERIC if PCI 244 select PCI_ECAM if (ACPI && PCI) 245 select PCI_SYSCALL if PCI 246 select POWER_RESET 247 select POWER_SUPPLY 248 select SPARSE_IRQ 249 select SWIOTLB 250 select SYSCTL_EXCEPTION_TRACE 251 select THREAD_INFO_IN_TASK 252 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 253 select TRACE_IRQFLAGS_SUPPORT 254 select TRACE_IRQFLAGS_NMI_SUPPORT 255 select HAVE_SOFTIRQ_ON_OWN_STACK 256 help 257 ARM 64-bit (AArch64) Linux support. 258 259config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 260 def_bool CC_IS_CLANG 261 # https://github.com/ClangBuiltLinux/linux/issues/1507 262 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 263 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 264 265config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 266 def_bool CC_IS_GCC 267 depends on $(cc-option,-fpatchable-function-entry=2) 268 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 269 270config 64BIT 271 def_bool y 272 273config MMU 274 def_bool y 275 276config ARM64_PAGE_SHIFT 277 int 278 default 16 if ARM64_64K_PAGES 279 default 14 if ARM64_16K_PAGES 280 default 12 281 282config ARM64_CONT_PTE_SHIFT 283 int 284 default 5 if ARM64_64K_PAGES 285 default 7 if ARM64_16K_PAGES 286 default 4 287 288config ARM64_CONT_PMD_SHIFT 289 int 290 default 5 if ARM64_64K_PAGES 291 default 5 if ARM64_16K_PAGES 292 default 4 293 294config ARCH_MMAP_RND_BITS_MIN 295 default 14 if ARM64_64K_PAGES 296 default 16 if ARM64_16K_PAGES 297 default 18 298 299# max bits determined by the following formula: 300# VA_BITS - PAGE_SHIFT - 3 301config ARCH_MMAP_RND_BITS_MAX 302 default 19 if ARM64_VA_BITS=36 303 default 24 if ARM64_VA_BITS=39 304 default 27 if ARM64_VA_BITS=42 305 default 30 if ARM64_VA_BITS=47 306 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 307 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 308 default 33 if ARM64_VA_BITS=48 309 default 14 if ARM64_64K_PAGES 310 default 16 if ARM64_16K_PAGES 311 default 18 312 313config ARCH_MMAP_RND_COMPAT_BITS_MIN 314 default 7 if ARM64_64K_PAGES 315 default 9 if ARM64_16K_PAGES 316 default 11 317 318config ARCH_MMAP_RND_COMPAT_BITS_MAX 319 default 16 320 321config NO_IOPORT_MAP 322 def_bool y if !PCI 323 324config STACKTRACE_SUPPORT 325 def_bool y 326 327config ILLEGAL_POINTER_VALUE 328 hex 329 default 0xdead000000000000 330 331config LOCKDEP_SUPPORT 332 def_bool y 333 334config GENERIC_BUG 335 def_bool y 336 depends on BUG 337 338config GENERIC_BUG_RELATIVE_POINTERS 339 def_bool y 340 depends on GENERIC_BUG 341 342config GENERIC_HWEIGHT 343 def_bool y 344 345config GENERIC_CSUM 346 def_bool y 347 348config GENERIC_CALIBRATE_DELAY 349 def_bool y 350 351config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 352 def_bool y 353 354config SMP 355 def_bool y 356 357config KERNEL_MODE_NEON 358 def_bool y 359 360config FIX_EARLYCON_MEM 361 def_bool y 362 363config PGTABLE_LEVELS 364 int 365 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 366 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 367 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 368 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 369 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 370 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 371 372config ARCH_SUPPORTS_UPROBES 373 def_bool y 374 375config ARCH_PROC_KCORE_TEXT 376 def_bool y 377 378config BROKEN_GAS_INST 379 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 380 381config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 382 bool 383 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0 384 # https://reviews.llvm.org/D75044 385 default y if CC_IS_CLANG && (CLANG_VERSION >= 120000) 386 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 387 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 388 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 389 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 390 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 391 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 392 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 393 default n 394 395config KASAN_SHADOW_OFFSET 396 hex 397 depends on KASAN_GENERIC || KASAN_SW_TAGS 398 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 399 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 400 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 401 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 402 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 403 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 404 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 405 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 406 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 407 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 408 default 0xffffffffffffffff 409 410config UNWIND_TABLES 411 bool 412 413source "arch/arm64/Kconfig.platforms" 414 415menu "Kernel Features" 416 417menu "ARM errata workarounds via the alternatives framework" 418 419config AMPERE_ERRATUM_AC03_CPU_38 420 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 421 default y 422 help 423 This option adds an alternative code sequence to work around Ampere 424 erratum AC03_CPU_38 on AmpereOne. 425 426 The affected design reports FEAT_HAFDBS as not implemented in 427 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 428 as required by the architecture. The unadvertised HAFDBS 429 implementation suffers from an additional erratum where hardware 430 A/D updates can occur after a PTE has been marked invalid. 431 432 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 433 which avoids enabling unadvertised hardware Access Flag management 434 at stage-2. 435 436 If unsure, say Y. 437 438config ARM64_WORKAROUND_CLEAN_CACHE 439 bool 440 441config ARM64_ERRATUM_826319 442 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 443 default y 444 select ARM64_WORKAROUND_CLEAN_CACHE 445 help 446 This option adds an alternative code sequence to work around ARM 447 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 448 AXI master interface and an L2 cache. 449 450 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 451 and is unable to accept a certain write via this interface, it will 452 not progress on read data presented on the read data channel and the 453 system can deadlock. 454 455 The workaround promotes data cache clean instructions to 456 data cache clean-and-invalidate. 457 Please note that this does not necessarily enable the workaround, 458 as it depends on the alternative framework, which will only patch 459 the kernel if an affected CPU is detected. 460 461 If unsure, say Y. 462 463config ARM64_ERRATUM_827319 464 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 465 default y 466 select ARM64_WORKAROUND_CLEAN_CACHE 467 help 468 This option adds an alternative code sequence to work around ARM 469 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 470 master interface and an L2 cache. 471 472 Under certain conditions this erratum can cause a clean line eviction 473 to occur at the same time as another transaction to the same address 474 on the AMBA 5 CHI interface, which can cause data corruption if the 475 interconnect reorders the two transactions. 476 477 The workaround promotes data cache clean instructions to 478 data cache clean-and-invalidate. 479 Please note that this does not necessarily enable the workaround, 480 as it depends on the alternative framework, which will only patch 481 the kernel if an affected CPU is detected. 482 483 If unsure, say Y. 484 485config ARM64_ERRATUM_824069 486 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 487 default y 488 select ARM64_WORKAROUND_CLEAN_CACHE 489 help 490 This option adds an alternative code sequence to work around ARM 491 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 492 to a coherent interconnect. 493 494 If a Cortex-A53 processor is executing a store or prefetch for 495 write instruction at the same time as a processor in another 496 cluster is executing a cache maintenance operation to the same 497 address, then this erratum might cause a clean cache line to be 498 incorrectly marked as dirty. 499 500 The workaround promotes data cache clean instructions to 501 data cache clean-and-invalidate. 502 Please note that this option does not necessarily enable the 503 workaround, as it depends on the alternative framework, which will 504 only patch the kernel if an affected CPU is detected. 505 506 If unsure, say Y. 507 508config ARM64_ERRATUM_819472 509 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 510 default y 511 select ARM64_WORKAROUND_CLEAN_CACHE 512 help 513 This option adds an alternative code sequence to work around ARM 514 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 515 present when it is connected to a coherent interconnect. 516 517 If the processor is executing a load and store exclusive sequence at 518 the same time as a processor in another cluster is executing a cache 519 maintenance operation to the same address, then this erratum might 520 cause data corruption. 521 522 The workaround promotes data cache clean instructions to 523 data cache clean-and-invalidate. 524 Please note that this does not necessarily enable the workaround, 525 as it depends on the alternative framework, which will only patch 526 the kernel if an affected CPU is detected. 527 528 If unsure, say Y. 529 530config ARM64_ERRATUM_832075 531 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 532 default y 533 help 534 This option adds an alternative code sequence to work around ARM 535 erratum 832075 on Cortex-A57 parts up to r1p2. 536 537 Affected Cortex-A57 parts might deadlock when exclusive load/store 538 instructions to Write-Back memory are mixed with Device loads. 539 540 The workaround is to promote device loads to use Load-Acquire 541 semantics. 542 Please note that this does not necessarily enable the workaround, 543 as it depends on the alternative framework, which will only patch 544 the kernel if an affected CPU is detected. 545 546 If unsure, say Y. 547 548config ARM64_ERRATUM_834220 549 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 550 depends on KVM 551 default y 552 help 553 This option adds an alternative code sequence to work around ARM 554 erratum 834220 on Cortex-A57 parts up to r1p2. 555 556 Affected Cortex-A57 parts might report a Stage 2 translation 557 fault as the result of a Stage 1 fault for load crossing a 558 page boundary when there is a permission or device memory 559 alignment fault at Stage 1 and a translation fault at Stage 2. 560 561 The workaround is to verify that the Stage 1 translation 562 doesn't generate a fault before handling the Stage 2 fault. 563 Please note that this does not necessarily enable the workaround, 564 as it depends on the alternative framework, which will only patch 565 the kernel if an affected CPU is detected. 566 567 If unsure, say Y. 568 569config ARM64_ERRATUM_1742098 570 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 571 depends on COMPAT 572 default y 573 help 574 This option removes the AES hwcap for aarch32 user-space to 575 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 576 577 Affected parts may corrupt the AES state if an interrupt is 578 taken between a pair of AES instructions. These instructions 579 are only present if the cryptography extensions are present. 580 All software should have a fallback implementation for CPUs 581 that don't implement the cryptography extensions. 582 583 If unsure, say Y. 584 585config ARM64_ERRATUM_845719 586 bool "Cortex-A53: 845719: a load might read incorrect data" 587 depends on COMPAT 588 default y 589 help 590 This option adds an alternative code sequence to work around ARM 591 erratum 845719 on Cortex-A53 parts up to r0p4. 592 593 When running a compat (AArch32) userspace on an affected Cortex-A53 594 part, a load at EL0 from a virtual address that matches the bottom 32 595 bits of the virtual address used by a recent load at (AArch64) EL1 596 might return incorrect data. 597 598 The workaround is to write the contextidr_el1 register on exception 599 return to a 32-bit task. 600 Please note that this does not necessarily enable the workaround, 601 as it depends on the alternative framework, which will only patch 602 the kernel if an affected CPU is detected. 603 604 If unsure, say Y. 605 606config ARM64_ERRATUM_843419 607 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 608 default y 609 help 610 This option links the kernel with '--fix-cortex-a53-843419' and 611 enables PLT support to replace certain ADRP instructions, which can 612 cause subsequent memory accesses to use an incorrect address on 613 Cortex-A53 parts up to r0p4. 614 615 If unsure, say Y. 616 617config ARM64_LD_HAS_FIX_ERRATUM_843419 618 def_bool $(ld-option,--fix-cortex-a53-843419) 619 620config ARM64_ERRATUM_1024718 621 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 622 default y 623 help 624 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 625 626 Affected Cortex-A55 cores (all revisions) could cause incorrect 627 update of the hardware dirty bit when the DBM/AP bits are updated 628 without a break-before-make. The workaround is to disable the usage 629 of hardware DBM locally on the affected cores. CPUs not affected by 630 this erratum will continue to use the feature. 631 632 If unsure, say Y. 633 634config ARM64_ERRATUM_1418040 635 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 636 default y 637 depends on COMPAT 638 help 639 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 640 errata 1188873 and 1418040. 641 642 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 643 cause register corruption when accessing the timer registers 644 from AArch32 userspace. 645 646 If unsure, say Y. 647 648config ARM64_WORKAROUND_SPECULATIVE_AT 649 bool 650 651config ARM64_ERRATUM_1165522 652 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 653 default y 654 select ARM64_WORKAROUND_SPECULATIVE_AT 655 help 656 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 657 658 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 659 corrupted TLBs by speculating an AT instruction during a guest 660 context switch. 661 662 If unsure, say Y. 663 664config ARM64_ERRATUM_1319367 665 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 666 default y 667 select ARM64_WORKAROUND_SPECULATIVE_AT 668 help 669 This option adds work arounds for ARM Cortex-A57 erratum 1319537 670 and A72 erratum 1319367 671 672 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 673 speculating an AT instruction during a guest context switch. 674 675 If unsure, say Y. 676 677config ARM64_ERRATUM_1530923 678 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 679 default y 680 select ARM64_WORKAROUND_SPECULATIVE_AT 681 help 682 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 683 684 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 685 corrupted TLBs by speculating an AT instruction during a guest 686 context switch. 687 688 If unsure, say Y. 689 690config ARM64_WORKAROUND_REPEAT_TLBI 691 bool 692 693config ARM64_ERRATUM_2441007 694 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 695 default y 696 select ARM64_WORKAROUND_REPEAT_TLBI 697 help 698 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 699 700 Under very rare circumstances, affected Cortex-A55 CPUs 701 may not handle a race between a break-before-make sequence on one 702 CPU, and another CPU accessing the same page. This could allow a 703 store to a page that has been unmapped. 704 705 Work around this by adding the affected CPUs to the list that needs 706 TLB sequences to be done twice. 707 708 If unsure, say Y. 709 710config ARM64_ERRATUM_1286807 711 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 712 default y 713 select ARM64_WORKAROUND_REPEAT_TLBI 714 help 715 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 716 717 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 718 address for a cacheable mapping of a location is being 719 accessed by a core while another core is remapping the virtual 720 address to a new physical page using the recommended 721 break-before-make sequence, then under very rare circumstances 722 TLBI+DSB completes before a read using the translation being 723 invalidated has been observed by other observers. The 724 workaround repeats the TLBI+DSB operation. 725 726config ARM64_ERRATUM_1463225 727 bool "Cortex-A76: Software Step might prevent interrupt recognition" 728 default y 729 help 730 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 731 732 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 733 of a system call instruction (SVC) can prevent recognition of 734 subsequent interrupts when software stepping is disabled in the 735 exception handler of the system call and either kernel debugging 736 is enabled or VHE is in use. 737 738 Work around the erratum by triggering a dummy step exception 739 when handling a system call from a task that is being stepped 740 in a VHE configuration of the kernel. 741 742 If unsure, say Y. 743 744config ARM64_ERRATUM_1542419 745 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 746 default y 747 help 748 This option adds a workaround for ARM Neoverse-N1 erratum 749 1542419. 750 751 Affected Neoverse-N1 cores could execute a stale instruction when 752 modified by another CPU. The workaround depends on a firmware 753 counterpart. 754 755 Workaround the issue by hiding the DIC feature from EL0. This 756 forces user-space to perform cache maintenance. 757 758 If unsure, say Y. 759 760config ARM64_ERRATUM_1508412 761 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 762 default y 763 help 764 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 765 766 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 767 of a store-exclusive or read of PAR_EL1 and a load with device or 768 non-cacheable memory attributes. The workaround depends on a firmware 769 counterpart. 770 771 KVM guests must also have the workaround implemented or they can 772 deadlock the system. 773 774 Work around the issue by inserting DMB SY barriers around PAR_EL1 775 register reads and warning KVM users. The DMB barrier is sufficient 776 to prevent a speculative PAR_EL1 read. 777 778 If unsure, say Y. 779 780config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 781 bool 782 783config ARM64_ERRATUM_2051678 784 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 785 default y 786 help 787 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 788 Affected Cortex-A510 might not respect the ordering rules for 789 hardware update of the page table's dirty bit. The workaround 790 is to not enable the feature on affected CPUs. 791 792 If unsure, say Y. 793 794config ARM64_ERRATUM_2077057 795 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 796 default y 797 help 798 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 799 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 800 expected, but a Pointer Authentication trap is taken instead. The 801 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 802 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 803 804 This can only happen when EL2 is stepping EL1. 805 806 When these conditions occur, the SPSR_EL2 value is unchanged from the 807 previous guest entry, and can be restored from the in-memory copy. 808 809 If unsure, say Y. 810 811config ARM64_ERRATUM_2658417 812 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 813 default y 814 help 815 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 816 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 817 BFMMLA or VMMLA instructions in rare circumstances when a pair of 818 A510 CPUs are using shared neon hardware. As the sharing is not 819 discoverable by the kernel, hide the BF16 HWCAP to indicate that 820 user-space should not be using these instructions. 821 822 If unsure, say Y. 823 824config ARM64_ERRATUM_2119858 825 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 826 default y 827 depends on CORESIGHT_TRBE 828 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 829 help 830 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 831 832 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 833 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 834 the event of a WRAP event. 835 836 Work around the issue by always making sure we move the TRBPTR_EL1 by 837 256 bytes before enabling the buffer and filling the first 256 bytes of 838 the buffer with ETM ignore packets upon disabling. 839 840 If unsure, say Y. 841 842config ARM64_ERRATUM_2139208 843 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 844 default y 845 depends on CORESIGHT_TRBE 846 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 847 help 848 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 849 850 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 851 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 852 the event of a WRAP event. 853 854 Work around the issue by always making sure we move the TRBPTR_EL1 by 855 256 bytes before enabling the buffer and filling the first 256 bytes of 856 the buffer with ETM ignore packets upon disabling. 857 858 If unsure, say Y. 859 860config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 861 bool 862 863config ARM64_ERRATUM_2054223 864 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 865 default y 866 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 867 help 868 Enable workaround for ARM Cortex-A710 erratum 2054223 869 870 Affected cores may fail to flush the trace data on a TSB instruction, when 871 the PE is in trace prohibited state. This will cause losing a few bytes 872 of the trace cached. 873 874 Workaround is to issue two TSB consecutively on affected cores. 875 876 If unsure, say Y. 877 878config ARM64_ERRATUM_2067961 879 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 880 default y 881 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 882 help 883 Enable workaround for ARM Neoverse-N2 erratum 2067961 884 885 Affected cores may fail to flush the trace data on a TSB instruction, when 886 the PE is in trace prohibited state. This will cause losing a few bytes 887 of the trace cached. 888 889 Workaround is to issue two TSB consecutively on affected cores. 890 891 If unsure, say Y. 892 893config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 894 bool 895 896config ARM64_ERRATUM_2253138 897 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 898 depends on CORESIGHT_TRBE 899 default y 900 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 901 help 902 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 903 904 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 905 for TRBE. Under some conditions, the TRBE might generate a write to the next 906 virtually addressed page following the last page of the TRBE address space 907 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 908 909 Work around this in the driver by always making sure that there is a 910 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 911 912 If unsure, say Y. 913 914config ARM64_ERRATUM_2224489 915 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 916 depends on CORESIGHT_TRBE 917 default y 918 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 919 help 920 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 921 922 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 923 for TRBE. Under some conditions, the TRBE might generate a write to the next 924 virtually addressed page following the last page of the TRBE address space 925 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 926 927 Work around this in the driver by always making sure that there is a 928 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 929 930 If unsure, say Y. 931 932config ARM64_ERRATUM_2441009 933 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 934 default y 935 select ARM64_WORKAROUND_REPEAT_TLBI 936 help 937 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 938 939 Under very rare circumstances, affected Cortex-A510 CPUs 940 may not handle a race between a break-before-make sequence on one 941 CPU, and another CPU accessing the same page. This could allow a 942 store to a page that has been unmapped. 943 944 Work around this by adding the affected CPUs to the list that needs 945 TLB sequences to be done twice. 946 947 If unsure, say Y. 948 949config ARM64_ERRATUM_2064142 950 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 951 depends on CORESIGHT_TRBE 952 default y 953 help 954 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 955 956 Affected Cortex-A510 core might fail to write into system registers after the 957 TRBE has been disabled. Under some conditions after the TRBE has been disabled 958 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 959 and TRBTRG_EL1 will be ignored and will not be effected. 960 961 Work around this in the driver by executing TSB CSYNC and DSB after collection 962 is stopped and before performing a system register write to one of the affected 963 registers. 964 965 If unsure, say Y. 966 967config ARM64_ERRATUM_2038923 968 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 969 depends on CORESIGHT_TRBE 970 default y 971 help 972 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 973 974 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 975 prohibited within the CPU. As a result, the trace buffer or trace buffer state 976 might be corrupted. This happens after TRBE buffer has been enabled by setting 977 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 978 execution changes from a context, in which trace is prohibited to one where it 979 isn't, or vice versa. In these mentioned conditions, the view of whether trace 980 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 981 the trace buffer state might be corrupted. 982 983 Work around this in the driver by preventing an inconsistent view of whether the 984 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 985 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 986 two ISB instructions if no ERET is to take place. 987 988 If unsure, say Y. 989 990config ARM64_ERRATUM_1902691 991 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 992 depends on CORESIGHT_TRBE 993 default y 994 help 995 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 996 997 Affected Cortex-A510 core might cause trace data corruption, when being written 998 into the memory. Effectively TRBE is broken and hence cannot be used to capture 999 trace data. 1000 1001 Work around this problem in the driver by just preventing TRBE initialization on 1002 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1003 on such implementations. This will cover the kernel for any firmware that doesn't 1004 do this already. 1005 1006 If unsure, say Y. 1007 1008config ARM64_ERRATUM_2457168 1009 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1010 depends on ARM64_AMU_EXTN 1011 default y 1012 help 1013 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1014 1015 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1016 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1017 incorrectly giving a significantly higher output value. 1018 1019 Work around this problem by returning 0 when reading the affected counter in 1020 key locations that results in disabling all users of this counter. This effect 1021 is the same to firmware disabling affected counters. 1022 1023 If unsure, say Y. 1024 1025config ARM64_ERRATUM_2645198 1026 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1027 default y 1028 help 1029 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1030 1031 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1032 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1033 next instruction abort caused by permission fault. 1034 1035 Only user-space does executable to non-executable permission transition via 1036 mprotect() system call. Workaround the problem by doing a break-before-make 1037 TLB invalidation, for all changes to executable user space mappings. 1038 1039 If unsure, say Y. 1040 1041config CAVIUM_ERRATUM_22375 1042 bool "Cavium erratum 22375, 24313" 1043 default y 1044 help 1045 Enable workaround for errata 22375 and 24313. 1046 1047 This implements two gicv3-its errata workarounds for ThunderX. Both 1048 with a small impact affecting only ITS table allocation. 1049 1050 erratum 22375: only alloc 8MB table size 1051 erratum 24313: ignore memory access type 1052 1053 The fixes are in ITS initialization and basically ignore memory access 1054 type and table size provided by the TYPER and BASER registers. 1055 1056 If unsure, say Y. 1057 1058config CAVIUM_ERRATUM_23144 1059 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1060 depends on NUMA 1061 default y 1062 help 1063 ITS SYNC command hang for cross node io and collections/cpu mapping. 1064 1065 If unsure, say Y. 1066 1067config CAVIUM_ERRATUM_23154 1068 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1069 default y 1070 help 1071 The ThunderX GICv3 implementation requires a modified version for 1072 reading the IAR status to ensure data synchronization 1073 (access to icc_iar1_el1 is not sync'ed before and after). 1074 1075 It also suffers from erratum 38545 (also present on Marvell's 1076 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1077 spuriously presented to the CPU interface. 1078 1079 If unsure, say Y. 1080 1081config CAVIUM_ERRATUM_27456 1082 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1083 default y 1084 help 1085 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1086 instructions may cause the icache to become corrupted if it 1087 contains data for a non-current ASID. The fix is to 1088 invalidate the icache when changing the mm context. 1089 1090 If unsure, say Y. 1091 1092config CAVIUM_ERRATUM_30115 1093 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1094 default y 1095 help 1096 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1097 1.2, and T83 Pass 1.0, KVM guest execution may disable 1098 interrupts in host. Trapping both GICv3 group-0 and group-1 1099 accesses sidesteps the issue. 1100 1101 If unsure, say Y. 1102 1103config CAVIUM_TX2_ERRATUM_219 1104 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1105 default y 1106 help 1107 On Cavium ThunderX2, a load, store or prefetch instruction between a 1108 TTBR update and the corresponding context synchronizing operation can 1109 cause a spurious Data Abort to be delivered to any hardware thread in 1110 the CPU core. 1111 1112 Work around the issue by avoiding the problematic code sequence and 1113 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1114 trap handler performs the corresponding register access, skips the 1115 instruction and ensures context synchronization by virtue of the 1116 exception return. 1117 1118 If unsure, say Y. 1119 1120config FUJITSU_ERRATUM_010001 1121 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1122 default y 1123 help 1124 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1125 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1126 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1127 This fault occurs under a specific hardware condition when a 1128 load/store instruction performs an address translation using: 1129 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1130 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1131 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1132 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1133 1134 The workaround is to ensure these bits are clear in TCR_ELx. 1135 The workaround only affects the Fujitsu-A64FX. 1136 1137 If unsure, say Y. 1138 1139config HISILICON_ERRATUM_161600802 1140 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1141 default y 1142 help 1143 The HiSilicon Hip07 SoC uses the wrong redistributor base 1144 when issued ITS commands such as VMOVP and VMAPP, and requires 1145 a 128kB offset to be applied to the target address in this commands. 1146 1147 If unsure, say Y. 1148 1149config QCOM_FALKOR_ERRATUM_1003 1150 bool "Falkor E1003: Incorrect translation due to ASID change" 1151 default y 1152 help 1153 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1154 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1155 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1156 then only for entries in the walk cache, since the leaf translation 1157 is unchanged. Work around the erratum by invalidating the walk cache 1158 entries for the trampoline before entering the kernel proper. 1159 1160config QCOM_FALKOR_ERRATUM_1009 1161 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1162 default y 1163 select ARM64_WORKAROUND_REPEAT_TLBI 1164 help 1165 On Falkor v1, the CPU may prematurely complete a DSB following a 1166 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1167 one more time to fix the issue. 1168 1169 If unsure, say Y. 1170 1171config QCOM_QDF2400_ERRATUM_0065 1172 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1173 default y 1174 help 1175 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1176 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1177 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1178 1179 If unsure, say Y. 1180 1181config QCOM_FALKOR_ERRATUM_E1041 1182 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1183 default y 1184 help 1185 Falkor CPU may speculatively fetch instructions from an improper 1186 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1187 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1188 1189 If unsure, say Y. 1190 1191config NVIDIA_CARMEL_CNP_ERRATUM 1192 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1193 default y 1194 help 1195 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1196 invalidate shared TLB entries installed by a different core, as it would 1197 on standard ARM cores. 1198 1199 If unsure, say Y. 1200 1201config ROCKCHIP_ERRATUM_3588001 1202 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1203 default y 1204 help 1205 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1206 This means, that its sharability feature may not be used, even though it 1207 is supported by the IP itself. 1208 1209 If unsure, say Y. 1210 1211config SOCIONEXT_SYNQUACER_PREITS 1212 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1213 default y 1214 help 1215 Socionext Synquacer SoCs implement a separate h/w block to generate 1216 MSI doorbell writes with non-zero values for the device ID. 1217 1218 If unsure, say Y. 1219 1220endmenu # "ARM errata workarounds via the alternatives framework" 1221 1222choice 1223 prompt "Page size" 1224 default ARM64_4K_PAGES 1225 help 1226 Page size (translation granule) configuration. 1227 1228config ARM64_4K_PAGES 1229 bool "4KB" 1230 help 1231 This feature enables 4KB pages support. 1232 1233config ARM64_16K_PAGES 1234 bool "16KB" 1235 help 1236 The system will use 16KB pages support. AArch32 emulation 1237 requires applications compiled with 16K (or a multiple of 16K) 1238 aligned segments. 1239 1240config ARM64_64K_PAGES 1241 bool "64KB" 1242 help 1243 This feature enables 64KB pages support (4KB by default) 1244 allowing only two levels of page tables and faster TLB 1245 look-up. AArch32 emulation requires applications compiled 1246 with 64K aligned segments. 1247 1248endchoice 1249 1250choice 1251 prompt "Virtual address space size" 1252 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1253 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1254 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1255 help 1256 Allows choosing one of multiple possible virtual address 1257 space sizes. The level of translation table is determined by 1258 a combination of page size and virtual address space size. 1259 1260config ARM64_VA_BITS_36 1261 bool "36-bit" if EXPERT 1262 depends on ARM64_16K_PAGES 1263 1264config ARM64_VA_BITS_39 1265 bool "39-bit" 1266 depends on ARM64_4K_PAGES 1267 1268config ARM64_VA_BITS_42 1269 bool "42-bit" 1270 depends on ARM64_64K_PAGES 1271 1272config ARM64_VA_BITS_47 1273 bool "47-bit" 1274 depends on ARM64_16K_PAGES 1275 1276config ARM64_VA_BITS_48 1277 bool "48-bit" 1278 1279config ARM64_VA_BITS_52 1280 bool "52-bit" 1281 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1282 help 1283 Enable 52-bit virtual addressing for userspace when explicitly 1284 requested via a hint to mmap(). The kernel will also use 52-bit 1285 virtual addresses for its own mappings (provided HW support for 1286 this feature is available, otherwise it reverts to 48-bit). 1287 1288 NOTE: Enabling 52-bit virtual addressing in conjunction with 1289 ARMv8.3 Pointer Authentication will result in the PAC being 1290 reduced from 7 bits to 3 bits, which may have a significant 1291 impact on its susceptibility to brute-force attacks. 1292 1293 If unsure, select 48-bit virtual addressing instead. 1294 1295endchoice 1296 1297config ARM64_FORCE_52BIT 1298 bool "Force 52-bit virtual addresses for userspace" 1299 depends on ARM64_VA_BITS_52 && EXPERT 1300 help 1301 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1302 to maintain compatibility with older software by providing 48-bit VAs 1303 unless a hint is supplied to mmap. 1304 1305 This configuration option disables the 48-bit compatibility logic, and 1306 forces all userspace addresses to be 52-bit on HW that supports it. One 1307 should only enable this configuration option for stress testing userspace 1308 memory management code. If unsure say N here. 1309 1310config ARM64_VA_BITS 1311 int 1312 default 36 if ARM64_VA_BITS_36 1313 default 39 if ARM64_VA_BITS_39 1314 default 42 if ARM64_VA_BITS_42 1315 default 47 if ARM64_VA_BITS_47 1316 default 48 if ARM64_VA_BITS_48 1317 default 52 if ARM64_VA_BITS_52 1318 1319choice 1320 prompt "Physical address space size" 1321 default ARM64_PA_BITS_48 1322 help 1323 Choose the maximum physical address range that the kernel will 1324 support. 1325 1326config ARM64_PA_BITS_48 1327 bool "48-bit" 1328 1329config ARM64_PA_BITS_52 1330 bool "52-bit (ARMv8.2)" 1331 depends on ARM64_64K_PAGES 1332 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1333 help 1334 Enable support for a 52-bit physical address space, introduced as 1335 part of the ARMv8.2-LPA extension. 1336 1337 With this enabled, the kernel will also continue to work on CPUs that 1338 do not support ARMv8.2-LPA, but with some added memory overhead (and 1339 minor performance overhead). 1340 1341endchoice 1342 1343config ARM64_PA_BITS 1344 int 1345 default 48 if ARM64_PA_BITS_48 1346 default 52 if ARM64_PA_BITS_52 1347 1348choice 1349 prompt "Endianness" 1350 default CPU_LITTLE_ENDIAN 1351 help 1352 Select the endianness of data accesses performed by the CPU. Userspace 1353 applications will need to be compiled and linked for the endianness 1354 that is selected here. 1355 1356config CPU_BIG_ENDIAN 1357 bool "Build big-endian kernel" 1358 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1359 help 1360 Say Y if you plan on running a kernel with a big-endian userspace. 1361 1362config CPU_LITTLE_ENDIAN 1363 bool "Build little-endian kernel" 1364 help 1365 Say Y if you plan on running a kernel with a little-endian userspace. 1366 This is usually the case for distributions targeting arm64. 1367 1368endchoice 1369 1370config SCHED_MC 1371 bool "Multi-core scheduler support" 1372 help 1373 Multi-core scheduler support improves the CPU scheduler's decision 1374 making when dealing with multi-core CPU chips at a cost of slightly 1375 increased overhead in some places. If unsure say N here. 1376 1377config SCHED_CLUSTER 1378 bool "Cluster scheduler support" 1379 help 1380 Cluster scheduler support improves the CPU scheduler's decision 1381 making when dealing with machines that have clusters of CPUs. 1382 Cluster usually means a couple of CPUs which are placed closely 1383 by sharing mid-level caches, last-level cache tags or internal 1384 busses. 1385 1386config SCHED_SMT 1387 bool "SMT scheduler support" 1388 help 1389 Improves the CPU scheduler's decision making when dealing with 1390 MultiThreading at a cost of slightly increased overhead in some 1391 places. If unsure say N here. 1392 1393config NR_CPUS 1394 int "Maximum number of CPUs (2-4096)" 1395 range 2 4096 1396 default "256" 1397 1398config HOTPLUG_CPU 1399 bool "Support for hot-pluggable CPUs" 1400 select GENERIC_IRQ_MIGRATION 1401 help 1402 Say Y here to experiment with turning CPUs off and on. CPUs 1403 can be controlled through /sys/devices/system/cpu. 1404 1405# Common NUMA Features 1406config NUMA 1407 bool "NUMA Memory Allocation and Scheduler Support" 1408 select GENERIC_ARCH_NUMA 1409 select ACPI_NUMA if ACPI 1410 select OF_NUMA 1411 select HAVE_SETUP_PER_CPU_AREA 1412 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1413 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1414 select USE_PERCPU_NUMA_NODE_ID 1415 help 1416 Enable NUMA (Non-Uniform Memory Access) support. 1417 1418 The kernel will try to allocate memory used by a CPU on the 1419 local memory of the CPU and add some more 1420 NUMA awareness to the kernel. 1421 1422config NODES_SHIFT 1423 int "Maximum NUMA Nodes (as a power of 2)" 1424 range 1 10 1425 default "4" 1426 depends on NUMA 1427 help 1428 Specify the maximum number of NUMA Nodes available on the target 1429 system. Increases memory reserved to accommodate various tables. 1430 1431source "kernel/Kconfig.hz" 1432 1433config ARCH_SPARSEMEM_ENABLE 1434 def_bool y 1435 select SPARSEMEM_VMEMMAP_ENABLE 1436 select SPARSEMEM_VMEMMAP 1437 1438config HW_PERF_EVENTS 1439 def_bool y 1440 depends on ARM_PMU 1441 1442# Supported by clang >= 7.0 or GCC >= 12.0.0 1443config CC_HAVE_SHADOW_CALL_STACK 1444 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1445 1446config PARAVIRT 1447 bool "Enable paravirtualization code" 1448 help 1449 This changes the kernel so it can modify itself when it is run 1450 under a hypervisor, potentially improving performance significantly 1451 over full virtualization. 1452 1453config PARAVIRT_TIME_ACCOUNTING 1454 bool "Paravirtual steal time accounting" 1455 select PARAVIRT 1456 help 1457 Select this option to enable fine granularity task steal time 1458 accounting. Time spent executing other tasks in parallel with 1459 the current vCPU is discounted from the vCPU power. To account for 1460 that, there can be a small performance impact. 1461 1462 If in doubt, say N here. 1463 1464config KEXEC 1465 depends on PM_SLEEP_SMP 1466 select KEXEC_CORE 1467 bool "kexec system call" 1468 help 1469 kexec is a system call that implements the ability to shutdown your 1470 current kernel, and to start another kernel. It is like a reboot 1471 but it is independent of the system firmware. And like a reboot 1472 you can start any kernel with it, not just Linux. 1473 1474config KEXEC_FILE 1475 bool "kexec file based system call" 1476 select KEXEC_CORE 1477 select HAVE_IMA_KEXEC if IMA 1478 help 1479 This is new version of kexec system call. This system call is 1480 file based and takes file descriptors as system call argument 1481 for kernel and initramfs as opposed to list of segments as 1482 accepted by previous system call. 1483 1484config KEXEC_SIG 1485 bool "Verify kernel signature during kexec_file_load() syscall" 1486 depends on KEXEC_FILE 1487 help 1488 Select this option to verify a signature with loaded kernel 1489 image. If configured, any attempt of loading a image without 1490 valid signature will fail. 1491 1492 In addition to that option, you need to enable signature 1493 verification for the corresponding kernel image type being 1494 loaded in order for this to work. 1495 1496config KEXEC_IMAGE_VERIFY_SIG 1497 bool "Enable Image signature verification support" 1498 default y 1499 depends on KEXEC_SIG 1500 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1501 help 1502 Enable Image signature verification support. 1503 1504comment "Support for PE file signature verification disabled" 1505 depends on KEXEC_SIG 1506 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1507 1508config CRASH_DUMP 1509 bool "Build kdump crash kernel" 1510 help 1511 Generate crash dump after being started by kexec. This should 1512 be normally only set in special crash dump kernels which are 1513 loaded in the main kernel with kexec-tools into a specially 1514 reserved region and then later executed after a crash by 1515 kdump/kexec. 1516 1517 For more details see Documentation/admin-guide/kdump/kdump.rst 1518 1519config TRANS_TABLE 1520 def_bool y 1521 depends on HIBERNATION || KEXEC_CORE 1522 1523config XEN_DOM0 1524 def_bool y 1525 depends on XEN 1526 1527config XEN 1528 bool "Xen guest support on ARM64" 1529 depends on ARM64 && OF 1530 select SWIOTLB_XEN 1531 select PARAVIRT 1532 help 1533 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1534 1535# include/linux/mmzone.h requires the following to be true: 1536# 1537# MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1538# 1539# so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1540# 1541# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_ORDER | default MAX_ORDER | 1542# ----+-------------------+--------------+-----------------+--------------------+ 1543# 4K | 27 | 12 | 15 | 10 | 1544# 16K | 27 | 14 | 13 | 11 | 1545# 64K | 29 | 16 | 13 | 13 | 1546config ARCH_FORCE_MAX_ORDER 1547 int 1548 default "13" if ARM64_64K_PAGES 1549 default "11" if ARM64_16K_PAGES 1550 default "10" 1551 help 1552 The kernel page allocator limits the size of maximal physically 1553 contiguous allocations. The limit is called MAX_ORDER and it 1554 defines the maximal power of two of number of pages that can be 1555 allocated as a single contiguous block. This option allows 1556 overriding the default setting when ability to allocate very 1557 large blocks of physically contiguous memory is required. 1558 1559 The maximal size of allocation cannot exceed the size of the 1560 section, so the value of MAX_ORDER should satisfy 1561 1562 MAX_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1563 1564 Don't change if unsure. 1565 1566config UNMAP_KERNEL_AT_EL0 1567 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1568 default y 1569 help 1570 Speculation attacks against some high-performance processors can 1571 be used to bypass MMU permission checks and leak kernel data to 1572 userspace. This can be defended against by unmapping the kernel 1573 when running in userspace, mapping it back in on exception entry 1574 via a trampoline page in the vector table. 1575 1576 If unsure, say Y. 1577 1578config MITIGATE_SPECTRE_BRANCH_HISTORY 1579 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1580 default y 1581 help 1582 Speculation attacks against some high-performance processors can 1583 make use of branch history to influence future speculation. 1584 When taking an exception from user-space, a sequence of branches 1585 or a firmware call overwrites the branch history. 1586 1587config RODATA_FULL_DEFAULT_ENABLED 1588 bool "Apply r/o permissions of VM areas also to their linear aliases" 1589 default y 1590 help 1591 Apply read-only attributes of VM areas to the linear alias of 1592 the backing pages as well. This prevents code or read-only data 1593 from being modified (inadvertently or intentionally) via another 1594 mapping of the same memory page. This additional enhancement can 1595 be turned off at runtime by passing rodata=[off|on] (and turned on 1596 with rodata=full if this option is set to 'n') 1597 1598 This requires the linear region to be mapped down to pages, 1599 which may adversely affect performance in some cases. 1600 1601config ARM64_SW_TTBR0_PAN 1602 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1603 help 1604 Enabling this option prevents the kernel from accessing 1605 user-space memory directly by pointing TTBR0_EL1 to a reserved 1606 zeroed area and reserved ASID. The user access routines 1607 restore the valid TTBR0_EL1 temporarily. 1608 1609config ARM64_TAGGED_ADDR_ABI 1610 bool "Enable the tagged user addresses syscall ABI" 1611 default y 1612 help 1613 When this option is enabled, user applications can opt in to a 1614 relaxed ABI via prctl() allowing tagged addresses to be passed 1615 to system calls as pointer arguments. For details, see 1616 Documentation/arch/arm64/tagged-address-abi.rst. 1617 1618menuconfig COMPAT 1619 bool "Kernel support for 32-bit EL0" 1620 depends on ARM64_4K_PAGES || EXPERT 1621 select HAVE_UID16 1622 select OLD_SIGSUSPEND3 1623 select COMPAT_OLD_SIGACTION 1624 help 1625 This option enables support for a 32-bit EL0 running under a 64-bit 1626 kernel at EL1. AArch32-specific components such as system calls, 1627 the user helper functions, VFP support and the ptrace interface are 1628 handled appropriately by the kernel. 1629 1630 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1631 that you will only be able to execute AArch32 binaries that were compiled 1632 with page size aligned segments. 1633 1634 If you want to execute 32-bit userspace applications, say Y. 1635 1636if COMPAT 1637 1638config KUSER_HELPERS 1639 bool "Enable kuser helpers page for 32-bit applications" 1640 default y 1641 help 1642 Warning: disabling this option may break 32-bit user programs. 1643 1644 Provide kuser helpers to compat tasks. The kernel provides 1645 helper code to userspace in read only form at a fixed location 1646 to allow userspace to be independent of the CPU type fitted to 1647 the system. This permits binaries to be run on ARMv4 through 1648 to ARMv8 without modification. 1649 1650 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1651 1652 However, the fixed address nature of these helpers can be used 1653 by ROP (return orientated programming) authors when creating 1654 exploits. 1655 1656 If all of the binaries and libraries which run on your platform 1657 are built specifically for your platform, and make no use of 1658 these helpers, then you can turn this option off to hinder 1659 such exploits. However, in that case, if a binary or library 1660 relying on those helpers is run, it will not function correctly. 1661 1662 Say N here only if you are absolutely certain that you do not 1663 need these helpers; otherwise, the safe option is to say Y. 1664 1665config COMPAT_VDSO 1666 bool "Enable vDSO for 32-bit applications" 1667 depends on !CPU_BIG_ENDIAN 1668 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1669 select GENERIC_COMPAT_VDSO 1670 default y 1671 help 1672 Place in the process address space of 32-bit applications an 1673 ELF shared object providing fast implementations of gettimeofday 1674 and clock_gettime. 1675 1676 You must have a 32-bit build of glibc 2.22 or later for programs 1677 to seamlessly take advantage of this. 1678 1679config THUMB2_COMPAT_VDSO 1680 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1681 depends on COMPAT_VDSO 1682 default y 1683 help 1684 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1685 otherwise with '-marm'. 1686 1687config COMPAT_ALIGNMENT_FIXUPS 1688 bool "Fix up misaligned multi-word loads and stores in user space" 1689 1690menuconfig ARMV8_DEPRECATED 1691 bool "Emulate deprecated/obsolete ARMv8 instructions" 1692 depends on SYSCTL 1693 help 1694 Legacy software support may require certain instructions 1695 that have been deprecated or obsoleted in the architecture. 1696 1697 Enable this config to enable selective emulation of these 1698 features. 1699 1700 If unsure, say Y 1701 1702if ARMV8_DEPRECATED 1703 1704config SWP_EMULATION 1705 bool "Emulate SWP/SWPB instructions" 1706 help 1707 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1708 they are always undefined. Say Y here to enable software 1709 emulation of these instructions for userspace using LDXR/STXR. 1710 This feature can be controlled at runtime with the abi.swp 1711 sysctl which is disabled by default. 1712 1713 In some older versions of glibc [<=2.8] SWP is used during futex 1714 trylock() operations with the assumption that the code will not 1715 be preempted. This invalid assumption may be more likely to fail 1716 with SWP emulation enabled, leading to deadlock of the user 1717 application. 1718 1719 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1720 on an external transaction monitoring block called a global 1721 monitor to maintain update atomicity. If your system does not 1722 implement a global monitor, this option can cause programs that 1723 perform SWP operations to uncached memory to deadlock. 1724 1725 If unsure, say Y 1726 1727config CP15_BARRIER_EMULATION 1728 bool "Emulate CP15 Barrier instructions" 1729 help 1730 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1731 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1732 strongly recommended to use the ISB, DSB, and DMB 1733 instructions instead. 1734 1735 Say Y here to enable software emulation of these 1736 instructions for AArch32 userspace code. When this option is 1737 enabled, CP15 barrier usage is traced which can help 1738 identify software that needs updating. This feature can be 1739 controlled at runtime with the abi.cp15_barrier sysctl. 1740 1741 If unsure, say Y 1742 1743config SETEND_EMULATION 1744 bool "Emulate SETEND instruction" 1745 help 1746 The SETEND instruction alters the data-endianness of the 1747 AArch32 EL0, and is deprecated in ARMv8. 1748 1749 Say Y here to enable software emulation of the instruction 1750 for AArch32 userspace code. This feature can be controlled 1751 at runtime with the abi.setend sysctl. 1752 1753 Note: All the cpus on the system must have mixed endian support at EL0 1754 for this feature to be enabled. If a new CPU - which doesn't support mixed 1755 endian - is hotplugged in after this feature has been enabled, there could 1756 be unexpected results in the applications. 1757 1758 If unsure, say Y 1759endif # ARMV8_DEPRECATED 1760 1761endif # COMPAT 1762 1763menu "ARMv8.1 architectural features" 1764 1765config ARM64_HW_AFDBM 1766 bool "Support for hardware updates of the Access and Dirty page flags" 1767 default y 1768 help 1769 The ARMv8.1 architecture extensions introduce support for 1770 hardware updates of the access and dirty information in page 1771 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1772 capable processors, accesses to pages with PTE_AF cleared will 1773 set this bit instead of raising an access flag fault. 1774 Similarly, writes to read-only pages with the DBM bit set will 1775 clear the read-only bit (AP[2]) instead of raising a 1776 permission fault. 1777 1778 Kernels built with this configuration option enabled continue 1779 to work on pre-ARMv8.1 hardware and the performance impact is 1780 minimal. If unsure, say Y. 1781 1782config ARM64_PAN 1783 bool "Enable support for Privileged Access Never (PAN)" 1784 default y 1785 help 1786 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1787 prevents the kernel or hypervisor from accessing user-space (EL0) 1788 memory directly. 1789 1790 Choosing this option will cause any unprotected (not using 1791 copy_to_user et al) memory access to fail with a permission fault. 1792 1793 The feature is detected at runtime, and will remain as a 'nop' 1794 instruction if the cpu does not implement the feature. 1795 1796config AS_HAS_LDAPR 1797 def_bool $(as-instr,.arch_extension rcpc) 1798 1799config AS_HAS_LSE_ATOMICS 1800 def_bool $(as-instr,.arch_extension lse) 1801 1802config ARM64_LSE_ATOMICS 1803 bool 1804 default ARM64_USE_LSE_ATOMICS 1805 depends on AS_HAS_LSE_ATOMICS 1806 1807config ARM64_USE_LSE_ATOMICS 1808 bool "Atomic instructions" 1809 default y 1810 help 1811 As part of the Large System Extensions, ARMv8.1 introduces new 1812 atomic instructions that are designed specifically to scale in 1813 very large systems. 1814 1815 Say Y here to make use of these instructions for the in-kernel 1816 atomic routines. This incurs a small overhead on CPUs that do 1817 not support these instructions and requires the kernel to be 1818 built with binutils >= 2.25 in order for the new instructions 1819 to be used. 1820 1821endmenu # "ARMv8.1 architectural features" 1822 1823menu "ARMv8.2 architectural features" 1824 1825config AS_HAS_ARMV8_2 1826 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1827 1828config AS_HAS_SHA3 1829 def_bool $(as-instr,.arch armv8.2-a+sha3) 1830 1831config ARM64_PMEM 1832 bool "Enable support for persistent memory" 1833 select ARCH_HAS_PMEM_API 1834 select ARCH_HAS_UACCESS_FLUSHCACHE 1835 help 1836 Say Y to enable support for the persistent memory API based on the 1837 ARMv8.2 DCPoP feature. 1838 1839 The feature is detected at runtime, and the kernel will use DC CVAC 1840 operations if DC CVAP is not supported (following the behaviour of 1841 DC CVAP itself if the system does not define a point of persistence). 1842 1843config ARM64_RAS_EXTN 1844 bool "Enable support for RAS CPU Extensions" 1845 default y 1846 help 1847 CPUs that support the Reliability, Availability and Serviceability 1848 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1849 errors, classify them and report them to software. 1850 1851 On CPUs with these extensions system software can use additional 1852 barriers to determine if faults are pending and read the 1853 classification from a new set of registers. 1854 1855 Selecting this feature will allow the kernel to use these barriers 1856 and access the new registers if the system supports the extension. 1857 Platform RAS features may additionally depend on firmware support. 1858 1859config ARM64_CNP 1860 bool "Enable support for Common Not Private (CNP) translations" 1861 default y 1862 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1863 help 1864 Common Not Private (CNP) allows translation table entries to 1865 be shared between different PEs in the same inner shareable 1866 domain, so the hardware can use this fact to optimise the 1867 caching of such entries in the TLB. 1868 1869 Selecting this option allows the CNP feature to be detected 1870 at runtime, and does not affect PEs that do not implement 1871 this feature. 1872 1873endmenu # "ARMv8.2 architectural features" 1874 1875menu "ARMv8.3 architectural features" 1876 1877config ARM64_PTR_AUTH 1878 bool "Enable support for pointer authentication" 1879 default y 1880 help 1881 Pointer authentication (part of the ARMv8.3 Extensions) provides 1882 instructions for signing and authenticating pointers against secret 1883 keys, which can be used to mitigate Return Oriented Programming (ROP) 1884 and other attacks. 1885 1886 This option enables these instructions at EL0 (i.e. for userspace). 1887 Choosing this option will cause the kernel to initialise secret keys 1888 for each process at exec() time, with these keys being 1889 context-switched along with the process. 1890 1891 The feature is detected at runtime. If the feature is not present in 1892 hardware it will not be advertised to userspace/KVM guest nor will it 1893 be enabled. 1894 1895 If the feature is present on the boot CPU but not on a late CPU, then 1896 the late CPU will be parked. Also, if the boot CPU does not have 1897 address auth and the late CPU has then the late CPU will still boot 1898 but with the feature disabled. On such a system, this option should 1899 not be selected. 1900 1901config ARM64_PTR_AUTH_KERNEL 1902 bool "Use pointer authentication for kernel" 1903 default y 1904 depends on ARM64_PTR_AUTH 1905 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1906 # Modern compilers insert a .note.gnu.property section note for PAC 1907 # which is only understood by binutils starting with version 2.33.1. 1908 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1909 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1910 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1911 help 1912 If the compiler supports the -mbranch-protection or 1913 -msign-return-address flag (e.g. GCC 7 or later), then this option 1914 will cause the kernel itself to be compiled with return address 1915 protection. In this case, and if the target hardware is known to 1916 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1917 disabled with minimal loss of protection. 1918 1919 This feature works with FUNCTION_GRAPH_TRACER option only if 1920 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1921 1922config CC_HAS_BRANCH_PROT_PAC_RET 1923 # GCC 9 or later, clang 8 or later 1924 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1925 1926config CC_HAS_SIGN_RETURN_ADDRESS 1927 # GCC 7, 8 1928 def_bool $(cc-option,-msign-return-address=all) 1929 1930config AS_HAS_ARMV8_3 1931 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1932 1933config AS_HAS_CFI_NEGATE_RA_STATE 1934 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1935 1936endmenu # "ARMv8.3 architectural features" 1937 1938menu "ARMv8.4 architectural features" 1939 1940config ARM64_AMU_EXTN 1941 bool "Enable support for the Activity Monitors Unit CPU extension" 1942 default y 1943 help 1944 The activity monitors extension is an optional extension introduced 1945 by the ARMv8.4 CPU architecture. This enables support for version 1 1946 of the activity monitors architecture, AMUv1. 1947 1948 To enable the use of this extension on CPUs that implement it, say Y. 1949 1950 Note that for architectural reasons, firmware _must_ implement AMU 1951 support when running on CPUs that present the activity monitors 1952 extension. The required support is present in: 1953 * Version 1.5 and later of the ARM Trusted Firmware 1954 1955 For kernels that have this configuration enabled but boot with broken 1956 firmware, you may need to say N here until the firmware is fixed. 1957 Otherwise you may experience firmware panics or lockups when 1958 accessing the counter registers. Even if you are not observing these 1959 symptoms, the values returned by the register reads might not 1960 correctly reflect reality. Most commonly, the value read will be 0, 1961 indicating that the counter is not enabled. 1962 1963config AS_HAS_ARMV8_4 1964 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1965 1966config ARM64_TLB_RANGE 1967 bool "Enable support for tlbi range feature" 1968 default y 1969 depends on AS_HAS_ARMV8_4 1970 help 1971 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1972 range of input addresses. 1973 1974 The feature introduces new assembly instructions, and they were 1975 support when binutils >= 2.30. 1976 1977endmenu # "ARMv8.4 architectural features" 1978 1979menu "ARMv8.5 architectural features" 1980 1981config AS_HAS_ARMV8_5 1982 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1983 1984config ARM64_BTI 1985 bool "Branch Target Identification support" 1986 default y 1987 help 1988 Branch Target Identification (part of the ARMv8.5 Extensions) 1989 provides a mechanism to limit the set of locations to which computed 1990 branch instructions such as BR or BLR can jump. 1991 1992 To make use of BTI on CPUs that support it, say Y. 1993 1994 BTI is intended to provide complementary protection to other control 1995 flow integrity protection mechanisms, such as the Pointer 1996 authentication mechanism provided as part of the ARMv8.3 Extensions. 1997 For this reason, it does not make sense to enable this option without 1998 also enabling support for pointer authentication. Thus, when 1999 enabling this option you should also select ARM64_PTR_AUTH=y. 2000 2001 Userspace binaries must also be specifically compiled to make use of 2002 this mechanism. If you say N here or the hardware does not support 2003 BTI, such binaries can still run, but you get no additional 2004 enforcement of branch destinations. 2005 2006config ARM64_BTI_KERNEL 2007 bool "Use Branch Target Identification for kernel" 2008 default y 2009 depends on ARM64_BTI 2010 depends on ARM64_PTR_AUTH_KERNEL 2011 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2012 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2013 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2014 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2015 depends on !CC_IS_GCC 2016 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 2017 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 2018 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2019 help 2020 Build the kernel with Branch Target Identification annotations 2021 and enable enforcement of this for kernel code. When this option 2022 is enabled and the system supports BTI all kernel code including 2023 modular code must have BTI enabled. 2024 2025config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2026 # GCC 9 or later, clang 8 or later 2027 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2028 2029config ARM64_E0PD 2030 bool "Enable support for E0PD" 2031 default y 2032 help 2033 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2034 that EL0 accesses made via TTBR1 always fault in constant time, 2035 providing similar benefits to KASLR as those provided by KPTI, but 2036 with lower overhead and without disrupting legitimate access to 2037 kernel memory such as SPE. 2038 2039 This option enables E0PD for TTBR1 where available. 2040 2041config ARM64_AS_HAS_MTE 2042 # Initial support for MTE went in binutils 2.32.0, checked with 2043 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2044 # as a late addition to the final architecture spec (LDGM/STGM) 2045 # is only supported in the newer 2.32.x and 2.33 binutils 2046 # versions, hence the extra "stgm" instruction check below. 2047 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2048 2049config ARM64_MTE 2050 bool "Memory Tagging Extension support" 2051 default y 2052 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2053 depends on AS_HAS_ARMV8_5 2054 depends on AS_HAS_LSE_ATOMICS 2055 # Required for tag checking in the uaccess routines 2056 depends on ARM64_PAN 2057 select ARCH_HAS_SUBPAGE_FAULTS 2058 select ARCH_USES_HIGH_VMA_FLAGS 2059 select ARCH_USES_PG_ARCH_X 2060 help 2061 Memory Tagging (part of the ARMv8.5 Extensions) provides 2062 architectural support for run-time, always-on detection of 2063 various classes of memory error to aid with software debugging 2064 to eliminate vulnerabilities arising from memory-unsafe 2065 languages. 2066 2067 This option enables the support for the Memory Tagging 2068 Extension at EL0 (i.e. for userspace). 2069 2070 Selecting this option allows the feature to be detected at 2071 runtime. Any secondary CPU not implementing this feature will 2072 not be allowed a late bring-up. 2073 2074 Userspace binaries that want to use this feature must 2075 explicitly opt in. The mechanism for the userspace is 2076 described in: 2077 2078 Documentation/arch/arm64/memory-tagging-extension.rst. 2079 2080endmenu # "ARMv8.5 architectural features" 2081 2082menu "ARMv8.7 architectural features" 2083 2084config ARM64_EPAN 2085 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2086 default y 2087 depends on ARM64_PAN 2088 help 2089 Enhanced Privileged Access Never (EPAN) allows Privileged 2090 Access Never to be used with Execute-only mappings. 2091 2092 The feature is detected at runtime, and will remain disabled 2093 if the cpu does not implement the feature. 2094endmenu # "ARMv8.7 architectural features" 2095 2096config ARM64_SVE 2097 bool "ARM Scalable Vector Extension support" 2098 default y 2099 help 2100 The Scalable Vector Extension (SVE) is an extension to the AArch64 2101 execution state which complements and extends the SIMD functionality 2102 of the base architecture to support much larger vectors and to enable 2103 additional vectorisation opportunities. 2104 2105 To enable use of this extension on CPUs that implement it, say Y. 2106 2107 On CPUs that support the SVE2 extensions, this option will enable 2108 those too. 2109 2110 Note that for architectural reasons, firmware _must_ implement SVE 2111 support when running on SVE capable hardware. The required support 2112 is present in: 2113 2114 * version 1.5 and later of the ARM Trusted Firmware 2115 * the AArch64 boot wrapper since commit 5e1261e08abf 2116 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2117 2118 For other firmware implementations, consult the firmware documentation 2119 or vendor. 2120 2121 If you need the kernel to boot on SVE-capable hardware with broken 2122 firmware, you may need to say N here until you get your firmware 2123 fixed. Otherwise, you may experience firmware panics or lockups when 2124 booting the kernel. If unsure and you are not observing these 2125 symptoms, you should assume that it is safe to say Y. 2126 2127config ARM64_SME 2128 bool "ARM Scalable Matrix Extension support" 2129 default y 2130 depends on ARM64_SVE 2131 help 2132 The Scalable Matrix Extension (SME) is an extension to the AArch64 2133 execution state which utilises a substantial subset of the SVE 2134 instruction set, together with the addition of new architectural 2135 register state capable of holding two dimensional matrix tiles to 2136 enable various matrix operations. 2137 2138config ARM64_PSEUDO_NMI 2139 bool "Support for NMI-like interrupts" 2140 select ARM_GIC_V3 2141 help 2142 Adds support for mimicking Non-Maskable Interrupts through the use of 2143 GIC interrupt priority. This support requires version 3 or later of 2144 ARM GIC. 2145 2146 This high priority configuration for interrupts needs to be 2147 explicitly enabled by setting the kernel parameter 2148 "irqchip.gicv3_pseudo_nmi" to 1. 2149 2150 If unsure, say N 2151 2152if ARM64_PSEUDO_NMI 2153config ARM64_DEBUG_PRIORITY_MASKING 2154 bool "Debug interrupt priority masking" 2155 help 2156 This adds runtime checks to functions enabling/disabling 2157 interrupts when using priority masking. The additional checks verify 2158 the validity of ICC_PMR_EL1 when calling concerned functions. 2159 2160 If unsure, say N 2161endif # ARM64_PSEUDO_NMI 2162 2163config RELOCATABLE 2164 bool "Build a relocatable kernel image" if EXPERT 2165 select ARCH_HAS_RELR 2166 default y 2167 help 2168 This builds the kernel as a Position Independent Executable (PIE), 2169 which retains all relocation metadata required to relocate the 2170 kernel binary at runtime to a different virtual address than the 2171 address it was linked at. 2172 Since AArch64 uses the RELA relocation format, this requires a 2173 relocation pass at runtime even if the kernel is loaded at the 2174 same address it was linked at. 2175 2176config RANDOMIZE_BASE 2177 bool "Randomize the address of the kernel image" 2178 select RELOCATABLE 2179 help 2180 Randomizes the virtual address at which the kernel image is 2181 loaded, as a security feature that deters exploit attempts 2182 relying on knowledge of the location of kernel internals. 2183 2184 It is the bootloader's job to provide entropy, by passing a 2185 random u64 value in /chosen/kaslr-seed at kernel entry. 2186 2187 When booting via the UEFI stub, it will invoke the firmware's 2188 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2189 to the kernel proper. In addition, it will randomise the physical 2190 location of the kernel Image as well. 2191 2192 If unsure, say N. 2193 2194config RANDOMIZE_MODULE_REGION_FULL 2195 bool "Randomize the module region over a 2 GB range" 2196 depends on RANDOMIZE_BASE 2197 default y 2198 help 2199 Randomizes the location of the module region inside a 2 GB window 2200 covering the core kernel. This way, it is less likely for modules 2201 to leak information about the location of core kernel data structures 2202 but it does imply that function calls between modules and the core 2203 kernel will need to be resolved via veneers in the module PLT. 2204 2205 When this option is not set, the module region will be randomized over 2206 a limited range that contains the [_stext, _etext] interval of the 2207 core kernel, so branch relocations are almost always in range unless 2208 the region is exhausted. In this particular case of region 2209 exhaustion, modules might be able to fall back to a larger 2GB area. 2210 2211config CC_HAVE_STACKPROTECTOR_SYSREG 2212 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2213 2214config STACKPROTECTOR_PER_TASK 2215 def_bool y 2216 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2217 2218config UNWIND_PATCH_PAC_INTO_SCS 2219 bool "Enable shadow call stack dynamically using code patching" 2220 # needs Clang with https://reviews.llvm.org/D111780 incorporated 2221 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2222 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2223 depends on SHADOW_CALL_STACK 2224 select UNWIND_TABLES 2225 select DYNAMIC_SCS 2226 2227endmenu # "Kernel Features" 2228 2229menu "Boot options" 2230 2231config ARM64_ACPI_PARKING_PROTOCOL 2232 bool "Enable support for the ARM64 ACPI parking protocol" 2233 depends on ACPI 2234 help 2235 Enable support for the ARM64 ACPI parking protocol. If disabled 2236 the kernel will not allow booting through the ARM64 ACPI parking 2237 protocol even if the corresponding data is present in the ACPI 2238 MADT table. 2239 2240config CMDLINE 2241 string "Default kernel command string" 2242 default "" 2243 help 2244 Provide a set of default command-line options at build time by 2245 entering them here. As a minimum, you should specify the the 2246 root device (e.g. root=/dev/nfs). 2247 2248choice 2249 prompt "Kernel command line type" if CMDLINE != "" 2250 default CMDLINE_FROM_BOOTLOADER 2251 help 2252 Choose how the kernel will handle the provided default kernel 2253 command line string. 2254 2255config CMDLINE_FROM_BOOTLOADER 2256 bool "Use bootloader kernel arguments if available" 2257 help 2258 Uses the command-line options passed by the boot loader. If 2259 the boot loader doesn't provide any, the default kernel command 2260 string provided in CMDLINE will be used. 2261 2262config CMDLINE_FORCE 2263 bool "Always use the default kernel command string" 2264 help 2265 Always use the default kernel command string, even if the boot 2266 loader passes other arguments to the kernel. 2267 This is useful if you cannot or don't want to change the 2268 command-line options your boot loader passes to the kernel. 2269 2270endchoice 2271 2272config EFI_STUB 2273 bool 2274 2275config EFI 2276 bool "UEFI runtime support" 2277 depends on OF && !CPU_BIG_ENDIAN 2278 depends on KERNEL_MODE_NEON 2279 select ARCH_SUPPORTS_ACPI 2280 select LIBFDT 2281 select UCS2_STRING 2282 select EFI_PARAMS_FROM_FDT 2283 select EFI_RUNTIME_WRAPPERS 2284 select EFI_STUB 2285 select EFI_GENERIC_STUB 2286 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2287 default y 2288 help 2289 This option provides support for runtime services provided 2290 by UEFI firmware (such as non-volatile variables, realtime 2291 clock, and platform reset). A UEFI stub is also provided to 2292 allow the kernel to be booted as an EFI application. This 2293 is only useful on systems that have UEFI firmware. 2294 2295config DMI 2296 bool "Enable support for SMBIOS (DMI) tables" 2297 depends on EFI 2298 default y 2299 help 2300 This enables SMBIOS/DMI feature for systems. 2301 2302 This option is only useful on systems that have UEFI firmware. 2303 However, even with this option, the resultant kernel should 2304 continue to boot on existing non-UEFI platforms. 2305 2306endmenu # "Boot options" 2307 2308menu "Power management options" 2309 2310source "kernel/power/Kconfig" 2311 2312config ARCH_HIBERNATION_POSSIBLE 2313 def_bool y 2314 depends on CPU_PM 2315 2316config ARCH_HIBERNATION_HEADER 2317 def_bool y 2318 depends on HIBERNATION 2319 2320config ARCH_SUSPEND_POSSIBLE 2321 def_bool y 2322 2323endmenu # "Power management options" 2324 2325menu "CPU Power Management" 2326 2327source "drivers/cpuidle/Kconfig" 2328 2329source "drivers/cpufreq/Kconfig" 2330 2331endmenu # "CPU Power Management" 2332 2333source "drivers/acpi/Kconfig" 2334 2335source "arch/arm64/kvm/Kconfig" 2336 2337