1config ARM64 2 def_bool y 3 select ACPI_CCA_REQUIRED if ACPI 4 select ACPI_GENERIC_GSI if ACPI 5 select ACPI_GTDT if ACPI 6 select ACPI_IORT if ACPI 7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 8 select ACPI_MCFG if (ACPI && PCI) 9 select ACPI_SPCR_TABLE if ACPI 10 select ACPI_PPTT if ACPI 11 select ARCH_CLOCKSOURCE_DATA 12 select ARCH_HAS_DEBUG_VIRTUAL 13 select ARCH_HAS_DEVMEM_IS_ALLOWED 14 select ARCH_HAS_DMA_COHERENT_TO_PFN 15 select ARCH_HAS_DMA_MMAP_PGPROT 16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 17 select ARCH_HAS_ELF_RANDOMIZE 18 select ARCH_HAS_FAST_MULTIPLIER 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA 22 select ARCH_HAS_KCOV 23 select ARCH_HAS_MEMBARRIER_SYNC_CORE 24 select ARCH_HAS_PTE_SPECIAL 25 select ARCH_HAS_SET_MEMORY 26 select ARCH_HAS_SG_CHAIN 27 select ARCH_HAS_STRICT_KERNEL_RWX 28 select ARCH_HAS_STRICT_MODULE_RWX 29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 30 select ARCH_HAS_SYNC_DMA_FOR_CPU 31 select ARCH_HAS_SYSCALL_WRAPPER 32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 33 select ARCH_HAVE_NMI_SAFE_CMPXCHG 34 select ARCH_INLINE_READ_LOCK if !PREEMPT 35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT 36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT 37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT 38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT 39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT 40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT 41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT 42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT 43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT 44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT 45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT 46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT 47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT 48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT 49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT 50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT 51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT 52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT 53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT 54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT 55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT 56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT 57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT 58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT 59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT 60 select ARCH_USE_CMPXCHG_LOCKREF 61 select ARCH_USE_QUEUED_RWLOCKS 62 select ARCH_USE_QUEUED_SPINLOCKS 63 select ARCH_SUPPORTS_MEMORY_FAILURE 64 select ARCH_SUPPORTS_ATOMIC_RMW 65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG 66 select ARCH_SUPPORTS_NUMA_BALANCING 67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION 68 select ARCH_WANT_FRAME_POINTERS 69 select ARCH_HAS_UBSAN_SANITIZE_ALL 70 select ARM_AMBA 71 select ARM_ARCH_TIMER 72 select ARM_GIC 73 select AUDIT_ARCH_COMPAT_GENERIC 74 select ARM_GIC_V2M if PCI 75 select ARM_GIC_V3 76 select ARM_GIC_V3_ITS if PCI 77 select ARM_PSCI_FW 78 select BUILDTIME_EXTABLE_SORT 79 select CLONE_BACKWARDS 80 select COMMON_CLK 81 select CPU_PM if (SUSPEND || CPU_IDLE) 82 select CRC32 83 select DCACHE_WORD_ACCESS 84 select DMA_DIRECT_OPS 85 select EDAC_SUPPORT 86 select FRAME_POINTER 87 select GENERIC_ALLOCATOR 88 select GENERIC_ARCH_TOPOLOGY 89 select GENERIC_CLOCKEVENTS 90 select GENERIC_CLOCKEVENTS_BROADCAST 91 select GENERIC_CPU_AUTOPROBE 92 select GENERIC_EARLY_IOREMAP 93 select GENERIC_IDLE_POLL_SETUP 94 select GENERIC_IRQ_MULTI_HANDLER 95 select GENERIC_IRQ_PROBE 96 select GENERIC_IRQ_SHOW 97 select GENERIC_IRQ_SHOW_LEVEL 98 select GENERIC_PCI_IOMAP 99 select GENERIC_SCHED_CLOCK 100 select GENERIC_SMP_IDLE_THREAD 101 select GENERIC_STRNCPY_FROM_USER 102 select GENERIC_STRNLEN_USER 103 select GENERIC_TIME_VSYSCALL 104 select HANDLE_DOMAIN_IRQ 105 select HARDIRQS_SW_RESEND 106 select HAVE_ACPI_APEI if (ACPI && EFI) 107 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 108 select HAVE_ARCH_AUDITSYSCALL 109 select HAVE_ARCH_BITREVERSE 110 select HAVE_ARCH_HUGE_VMAP 111 select HAVE_ARCH_JUMP_LABEL 112 select HAVE_ARCH_JUMP_LABEL_RELATIVE 113 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 114 select HAVE_ARCH_KGDB 115 select HAVE_ARCH_MMAP_RND_BITS 116 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 117 select HAVE_ARCH_PREL32_RELOCATIONS 118 select HAVE_ARCH_SECCOMP_FILTER 119 select HAVE_ARCH_STACKLEAK 120 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 121 select HAVE_ARCH_TRACEHOOK 122 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 123 select HAVE_ARCH_VMAP_STACK 124 select HAVE_ARM_SMCCC 125 select HAVE_EBPF_JIT 126 select HAVE_C_RECORDMCOUNT 127 select HAVE_CMPXCHG_DOUBLE 128 select HAVE_CMPXCHG_LOCAL 129 select HAVE_CONTEXT_TRACKING 130 select HAVE_DEBUG_BUGVERBOSE 131 select HAVE_DEBUG_KMEMLEAK 132 select HAVE_DMA_CONTIGUOUS 133 select HAVE_DYNAMIC_FTRACE 134 select HAVE_EFFICIENT_UNALIGNED_ACCESS 135 select HAVE_FTRACE_MCOUNT_RECORD 136 select HAVE_FUNCTION_TRACER 137 select HAVE_FUNCTION_GRAPH_TRACER 138 select HAVE_GCC_PLUGINS 139 select HAVE_GENERIC_DMA_COHERENT 140 select HAVE_HW_BREAKPOINT if PERF_EVENTS 141 select HAVE_IRQ_TIME_ACCOUNTING 142 select HAVE_MEMBLOCK_NODE_MAP if NUMA 143 select HAVE_NMI 144 select HAVE_PATA_PLATFORM 145 select HAVE_PERF_EVENTS 146 select HAVE_PERF_REGS 147 select HAVE_PERF_USER_STACK_DUMP 148 select HAVE_REGS_AND_STACK_ACCESS_API 149 select HAVE_RCU_TABLE_FREE 150 select HAVE_RCU_TABLE_INVALIDATE 151 select HAVE_RSEQ 152 select HAVE_STACKPROTECTOR 153 select HAVE_SYSCALL_TRACEPOINTS 154 select HAVE_KPROBES 155 select HAVE_KRETPROBES 156 select IOMMU_DMA if IOMMU_SUPPORT 157 select IRQ_DOMAIN 158 select IRQ_FORCED_THREADING 159 select MODULES_USE_ELF_RELA 160 select MULTI_IRQ_HANDLER 161 select NEED_DMA_MAP_STATE 162 select NEED_SG_DMA_LENGTH 163 select OF 164 select OF_EARLY_FLATTREE 165 select OF_RESERVED_MEM 166 select PCI_ECAM if (ACPI && PCI) 167 select POWER_RESET 168 select POWER_SUPPLY 169 select REFCOUNT_FULL 170 select SPARSE_IRQ 171 select SWIOTLB 172 select SYSCTL_EXCEPTION_TRACE 173 select THREAD_INFO_IN_TASK 174 help 175 ARM 64-bit (AArch64) Linux support. 176 177config 64BIT 178 def_bool y 179 180config MMU 181 def_bool y 182 183config ARM64_PAGE_SHIFT 184 int 185 default 16 if ARM64_64K_PAGES 186 default 14 if ARM64_16K_PAGES 187 default 12 188 189config ARM64_CONT_SHIFT 190 int 191 default 5 if ARM64_64K_PAGES 192 default 7 if ARM64_16K_PAGES 193 default 4 194 195config ARCH_MMAP_RND_BITS_MIN 196 default 14 if ARM64_64K_PAGES 197 default 16 if ARM64_16K_PAGES 198 default 18 199 200# max bits determined by the following formula: 201# VA_BITS - PAGE_SHIFT - 3 202config ARCH_MMAP_RND_BITS_MAX 203 default 19 if ARM64_VA_BITS=36 204 default 24 if ARM64_VA_BITS=39 205 default 27 if ARM64_VA_BITS=42 206 default 30 if ARM64_VA_BITS=47 207 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 208 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 209 default 33 if ARM64_VA_BITS=48 210 default 14 if ARM64_64K_PAGES 211 default 16 if ARM64_16K_PAGES 212 default 18 213 214config ARCH_MMAP_RND_COMPAT_BITS_MIN 215 default 7 if ARM64_64K_PAGES 216 default 9 if ARM64_16K_PAGES 217 default 11 218 219config ARCH_MMAP_RND_COMPAT_BITS_MAX 220 default 16 221 222config NO_IOPORT_MAP 223 def_bool y if !PCI 224 225config STACKTRACE_SUPPORT 226 def_bool y 227 228config ILLEGAL_POINTER_VALUE 229 hex 230 default 0xdead000000000000 231 232config LOCKDEP_SUPPORT 233 def_bool y 234 235config TRACE_IRQFLAGS_SUPPORT 236 def_bool y 237 238config RWSEM_XCHGADD_ALGORITHM 239 def_bool y 240 241config GENERIC_BUG 242 def_bool y 243 depends on BUG 244 245config GENERIC_BUG_RELATIVE_POINTERS 246 def_bool y 247 depends on GENERIC_BUG 248 249config GENERIC_HWEIGHT 250 def_bool y 251 252config GENERIC_CSUM 253 def_bool y 254 255config GENERIC_CALIBRATE_DELAY 256 def_bool y 257 258config ZONE_DMA32 259 def_bool y 260 261config HAVE_GENERIC_GUP 262 def_bool y 263 264config SMP 265 def_bool y 266 267config KERNEL_MODE_NEON 268 def_bool y 269 270config FIX_EARLYCON_MEM 271 def_bool y 272 273config PGTABLE_LEVELS 274 int 275 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 276 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 277 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 278 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 279 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 280 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 281 282config ARCH_SUPPORTS_UPROBES 283 def_bool y 284 285config ARCH_PROC_KCORE_TEXT 286 def_bool y 287 288source "arch/arm64/Kconfig.platforms" 289 290menu "Bus support" 291 292config PCI 293 bool "PCI support" 294 help 295 This feature enables support for PCI bus system. If you say Y 296 here, the kernel will include drivers and infrastructure code 297 to support PCI bus devices. 298 299config PCI_DOMAINS 300 def_bool PCI 301 302config PCI_DOMAINS_GENERIC 303 def_bool PCI 304 305config PCI_SYSCALL 306 def_bool PCI 307 308source "drivers/pci/Kconfig" 309 310endmenu 311 312menu "Kernel Features" 313 314menu "ARM errata workarounds via the alternatives framework" 315 316config ARM64_ERRATUM_826319 317 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 318 default y 319 help 320 This option adds an alternative code sequence to work around ARM 321 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 322 AXI master interface and an L2 cache. 323 324 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 325 and is unable to accept a certain write via this interface, it will 326 not progress on read data presented on the read data channel and the 327 system can deadlock. 328 329 The workaround promotes data cache clean instructions to 330 data cache clean-and-invalidate. 331 Please note that this does not necessarily enable the workaround, 332 as it depends on the alternative framework, which will only patch 333 the kernel if an affected CPU is detected. 334 335 If unsure, say Y. 336 337config ARM64_ERRATUM_827319 338 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 339 default y 340 help 341 This option adds an alternative code sequence to work around ARM 342 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 343 master interface and an L2 cache. 344 345 Under certain conditions this erratum can cause a clean line eviction 346 to occur at the same time as another transaction to the same address 347 on the AMBA 5 CHI interface, which can cause data corruption if the 348 interconnect reorders the two transactions. 349 350 The workaround promotes data cache clean instructions to 351 data cache clean-and-invalidate. 352 Please note that this does not necessarily enable the workaround, 353 as it depends on the alternative framework, which will only patch 354 the kernel if an affected CPU is detected. 355 356 If unsure, say Y. 357 358config ARM64_ERRATUM_824069 359 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 360 default y 361 help 362 This option adds an alternative code sequence to work around ARM 363 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 364 to a coherent interconnect. 365 366 If a Cortex-A53 processor is executing a store or prefetch for 367 write instruction at the same time as a processor in another 368 cluster is executing a cache maintenance operation to the same 369 address, then this erratum might cause a clean cache line to be 370 incorrectly marked as dirty. 371 372 The workaround promotes data cache clean instructions to 373 data cache clean-and-invalidate. 374 Please note that this option does not necessarily enable the 375 workaround, as it depends on the alternative framework, which will 376 only patch the kernel if an affected CPU is detected. 377 378 If unsure, say Y. 379 380config ARM64_ERRATUM_819472 381 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 382 default y 383 help 384 This option adds an alternative code sequence to work around ARM 385 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 386 present when it is connected to a coherent interconnect. 387 388 If the processor is executing a load and store exclusive sequence at 389 the same time as a processor in another cluster is executing a cache 390 maintenance operation to the same address, then this erratum might 391 cause data corruption. 392 393 The workaround promotes data cache clean instructions to 394 data cache clean-and-invalidate. 395 Please note that this does not necessarily enable the workaround, 396 as it depends on the alternative framework, which will only patch 397 the kernel if an affected CPU is detected. 398 399 If unsure, say Y. 400 401config ARM64_ERRATUM_832075 402 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 403 default y 404 help 405 This option adds an alternative code sequence to work around ARM 406 erratum 832075 on Cortex-A57 parts up to r1p2. 407 408 Affected Cortex-A57 parts might deadlock when exclusive load/store 409 instructions to Write-Back memory are mixed with Device loads. 410 411 The workaround is to promote device loads to use Load-Acquire 412 semantics. 413 Please note that this does not necessarily enable the workaround, 414 as it depends on the alternative framework, which will only patch 415 the kernel if an affected CPU is detected. 416 417 If unsure, say Y. 418 419config ARM64_ERRATUM_834220 420 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 421 depends on KVM 422 default y 423 help 424 This option adds an alternative code sequence to work around ARM 425 erratum 834220 on Cortex-A57 parts up to r1p2. 426 427 Affected Cortex-A57 parts might report a Stage 2 translation 428 fault as the result of a Stage 1 fault for load crossing a 429 page boundary when there is a permission or device memory 430 alignment fault at Stage 1 and a translation fault at Stage 2. 431 432 The workaround is to verify that the Stage 1 translation 433 doesn't generate a fault before handling the Stage 2 fault. 434 Please note that this does not necessarily enable the workaround, 435 as it depends on the alternative framework, which will only patch 436 the kernel if an affected CPU is detected. 437 438 If unsure, say Y. 439 440config ARM64_ERRATUM_845719 441 bool "Cortex-A53: 845719: a load might read incorrect data" 442 depends on COMPAT 443 default y 444 help 445 This option adds an alternative code sequence to work around ARM 446 erratum 845719 on Cortex-A53 parts up to r0p4. 447 448 When running a compat (AArch32) userspace on an affected Cortex-A53 449 part, a load at EL0 from a virtual address that matches the bottom 32 450 bits of the virtual address used by a recent load at (AArch64) EL1 451 might return incorrect data. 452 453 The workaround is to write the contextidr_el1 register on exception 454 return to a 32-bit task. 455 Please note that this does not necessarily enable the workaround, 456 as it depends on the alternative framework, which will only patch 457 the kernel if an affected CPU is detected. 458 459 If unsure, say Y. 460 461config ARM64_ERRATUM_843419 462 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 463 default y 464 select ARM64_MODULE_PLTS if MODULES 465 help 466 This option links the kernel with '--fix-cortex-a53-843419' and 467 enables PLT support to replace certain ADRP instructions, which can 468 cause subsequent memory accesses to use an incorrect address on 469 Cortex-A53 parts up to r0p4. 470 471 If unsure, say Y. 472 473config ARM64_ERRATUM_1024718 474 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 475 default y 476 help 477 This option adds work around for Arm Cortex-A55 Erratum 1024718. 478 479 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect 480 update of the hardware dirty bit when the DBM/AP bits are updated 481 without a break-before-make. The work around is to disable the usage 482 of hardware DBM locally on the affected cores. CPUs not affected by 483 erratum will continue to use the feature. 484 485 If unsure, say Y. 486 487config ARM64_ERRATUM_1188873 488 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 489 default y 490 select ARM_ARCH_TIMER_OOL_WORKAROUND 491 help 492 This option adds work arounds for ARM Cortex-A76 erratum 1188873 493 494 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause 495 register corruption when accessing the timer registers from 496 AArch32 userspace. 497 498 If unsure, say Y. 499 500config ARM64_ERRATUM_1286807 501 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 502 default y 503 select ARM64_WORKAROUND_REPEAT_TLBI 504 help 505 This option adds workaround for ARM Cortex-A76 erratum 1286807 506 507 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 508 address for a cacheable mapping of a location is being 509 accessed by a core while another core is remapping the virtual 510 address to a new physical page using the recommended 511 break-before-make sequence, then under very rare circumstances 512 TLBI+DSB completes before a read using the translation being 513 invalidated has been observed by other observers. The 514 workaround repeats the TLBI+DSB operation. 515 516 If unsure, say Y. 517 518config CAVIUM_ERRATUM_22375 519 bool "Cavium erratum 22375, 24313" 520 default y 521 help 522 Enable workaround for erratum 22375, 24313. 523 524 This implements two gicv3-its errata workarounds for ThunderX. Both 525 with small impact affecting only ITS table allocation. 526 527 erratum 22375: only alloc 8MB table size 528 erratum 24313: ignore memory access type 529 530 The fixes are in ITS initialization and basically ignore memory access 531 type and table size provided by the TYPER and BASER registers. 532 533 If unsure, say Y. 534 535config CAVIUM_ERRATUM_23144 536 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 537 depends on NUMA 538 default y 539 help 540 ITS SYNC command hang for cross node io and collections/cpu mapping. 541 542 If unsure, say Y. 543 544config CAVIUM_ERRATUM_23154 545 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed" 546 default y 547 help 548 The gicv3 of ThunderX requires a modified version for 549 reading the IAR status to ensure data synchronization 550 (access to icc_iar1_el1 is not sync'ed before and after). 551 552 If unsure, say Y. 553 554config CAVIUM_ERRATUM_27456 555 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 556 default y 557 help 558 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 559 instructions may cause the icache to become corrupted if it 560 contains data for a non-current ASID. The fix is to 561 invalidate the icache when changing the mm context. 562 563 If unsure, say Y. 564 565config CAVIUM_ERRATUM_30115 566 bool "Cavium erratum 30115: Guest may disable interrupts in host" 567 default y 568 help 569 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 570 1.2, and T83 Pass 1.0, KVM guest execution may disable 571 interrupts in host. Trapping both GICv3 group-0 and group-1 572 accesses sidesteps the issue. 573 574 If unsure, say Y. 575 576config QCOM_FALKOR_ERRATUM_1003 577 bool "Falkor E1003: Incorrect translation due to ASID change" 578 default y 579 help 580 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 581 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 582 in TTBR1_EL1, this situation only occurs in the entry trampoline and 583 then only for entries in the walk cache, since the leaf translation 584 is unchanged. Work around the erratum by invalidating the walk cache 585 entries for the trampoline before entering the kernel proper. 586 587config ARM64_WORKAROUND_REPEAT_TLBI 588 bool 589 help 590 Enable the repeat TLBI workaround for Falkor erratum 1009 and 591 Cortex-A76 erratum 1286807. 592 593config QCOM_FALKOR_ERRATUM_1009 594 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 595 default y 596 select ARM64_WORKAROUND_REPEAT_TLBI 597 help 598 On Falkor v1, the CPU may prematurely complete a DSB following a 599 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 600 one more time to fix the issue. 601 602 If unsure, say Y. 603 604config QCOM_QDF2400_ERRATUM_0065 605 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 606 default y 607 help 608 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 609 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 610 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 611 612 If unsure, say Y. 613 614config SOCIONEXT_SYNQUACER_PREITS 615 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 616 default y 617 help 618 Socionext Synquacer SoCs implement a separate h/w block to generate 619 MSI doorbell writes with non-zero values for the device ID. 620 621 If unsure, say Y. 622 623config HISILICON_ERRATUM_161600802 624 bool "Hip07 161600802: Erroneous redistributor VLPI base" 625 default y 626 help 627 The HiSilicon Hip07 SoC usees the wrong redistributor base 628 when issued ITS commands such as VMOVP and VMAPP, and requires 629 a 128kB offset to be applied to the target address in this commands. 630 631 If unsure, say Y. 632 633config QCOM_FALKOR_ERRATUM_E1041 634 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 635 default y 636 help 637 Falkor CPU may speculatively fetch instructions from an improper 638 memory location when MMU translation is changed from SCTLR_ELn[M]=1 639 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 640 641 If unsure, say Y. 642 643endmenu 644 645 646choice 647 prompt "Page size" 648 default ARM64_4K_PAGES 649 help 650 Page size (translation granule) configuration. 651 652config ARM64_4K_PAGES 653 bool "4KB" 654 help 655 This feature enables 4KB pages support. 656 657config ARM64_16K_PAGES 658 bool "16KB" 659 help 660 The system will use 16KB pages support. AArch32 emulation 661 requires applications compiled with 16K (or a multiple of 16K) 662 aligned segments. 663 664config ARM64_64K_PAGES 665 bool "64KB" 666 help 667 This feature enables 64KB pages support (4KB by default) 668 allowing only two levels of page tables and faster TLB 669 look-up. AArch32 emulation requires applications compiled 670 with 64K aligned segments. 671 672endchoice 673 674choice 675 prompt "Virtual address space size" 676 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 677 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 678 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 679 help 680 Allows choosing one of multiple possible virtual address 681 space sizes. The level of translation table is determined by 682 a combination of page size and virtual address space size. 683 684config ARM64_VA_BITS_36 685 bool "36-bit" if EXPERT 686 depends on ARM64_16K_PAGES 687 688config ARM64_VA_BITS_39 689 bool "39-bit" 690 depends on ARM64_4K_PAGES 691 692config ARM64_VA_BITS_42 693 bool "42-bit" 694 depends on ARM64_64K_PAGES 695 696config ARM64_VA_BITS_47 697 bool "47-bit" 698 depends on ARM64_16K_PAGES 699 700config ARM64_VA_BITS_48 701 bool "48-bit" 702 703endchoice 704 705config ARM64_VA_BITS 706 int 707 default 36 if ARM64_VA_BITS_36 708 default 39 if ARM64_VA_BITS_39 709 default 42 if ARM64_VA_BITS_42 710 default 47 if ARM64_VA_BITS_47 711 default 48 if ARM64_VA_BITS_48 712 713choice 714 prompt "Physical address space size" 715 default ARM64_PA_BITS_48 716 help 717 Choose the maximum physical address range that the kernel will 718 support. 719 720config ARM64_PA_BITS_48 721 bool "48-bit" 722 723config ARM64_PA_BITS_52 724 bool "52-bit (ARMv8.2)" 725 depends on ARM64_64K_PAGES 726 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 727 help 728 Enable support for a 52-bit physical address space, introduced as 729 part of the ARMv8.2-LPA extension. 730 731 With this enabled, the kernel will also continue to work on CPUs that 732 do not support ARMv8.2-LPA, but with some added memory overhead (and 733 minor performance overhead). 734 735endchoice 736 737config ARM64_PA_BITS 738 int 739 default 48 if ARM64_PA_BITS_48 740 default 52 if ARM64_PA_BITS_52 741 742config CPU_BIG_ENDIAN 743 bool "Build big-endian kernel" 744 help 745 Say Y if you plan on running a kernel in big-endian mode. 746 747config SCHED_MC 748 bool "Multi-core scheduler support" 749 help 750 Multi-core scheduler support improves the CPU scheduler's decision 751 making when dealing with multi-core CPU chips at a cost of slightly 752 increased overhead in some places. If unsure say N here. 753 754config SCHED_SMT 755 bool "SMT scheduler support" 756 help 757 Improves the CPU scheduler's decision making when dealing with 758 MultiThreading at a cost of slightly increased overhead in some 759 places. If unsure say N here. 760 761config NR_CPUS 762 int "Maximum number of CPUs (2-4096)" 763 range 2 4096 764 # These have to remain sorted largest to smallest 765 default "64" 766 767config HOTPLUG_CPU 768 bool "Support for hot-pluggable CPUs" 769 select GENERIC_IRQ_MIGRATION 770 help 771 Say Y here to experiment with turning CPUs off and on. CPUs 772 can be controlled through /sys/devices/system/cpu. 773 774# Common NUMA Features 775config NUMA 776 bool "Numa Memory Allocation and Scheduler Support" 777 select ACPI_NUMA if ACPI 778 select OF_NUMA 779 help 780 Enable NUMA (Non Uniform Memory Access) support. 781 782 The kernel will try to allocate memory used by a CPU on the 783 local memory of the CPU and add some more 784 NUMA awareness to the kernel. 785 786config NODES_SHIFT 787 int "Maximum NUMA Nodes (as a power of 2)" 788 range 1 10 789 default "2" 790 depends on NEED_MULTIPLE_NODES 791 help 792 Specify the maximum number of NUMA Nodes available on the target 793 system. Increases memory reserved to accommodate various tables. 794 795config USE_PERCPU_NUMA_NODE_ID 796 def_bool y 797 depends on NUMA 798 799config HAVE_SETUP_PER_CPU_AREA 800 def_bool y 801 depends on NUMA 802 803config NEED_PER_CPU_EMBED_FIRST_CHUNK 804 def_bool y 805 depends on NUMA 806 807config HOLES_IN_ZONE 808 def_bool y 809 810source kernel/Kconfig.hz 811 812config ARCH_SUPPORTS_DEBUG_PAGEALLOC 813 def_bool y 814 815config ARCH_SPARSEMEM_ENABLE 816 def_bool y 817 select SPARSEMEM_VMEMMAP_ENABLE 818 819config ARCH_SPARSEMEM_DEFAULT 820 def_bool ARCH_SPARSEMEM_ENABLE 821 822config ARCH_SELECT_MEMORY_MODEL 823 def_bool ARCH_SPARSEMEM_ENABLE 824 825config ARCH_FLATMEM_ENABLE 826 def_bool !NUMA 827 828config HAVE_ARCH_PFN_VALID 829 def_bool y 830 831config HW_PERF_EVENTS 832 def_bool y 833 depends on ARM_PMU 834 835config SYS_SUPPORTS_HUGETLBFS 836 def_bool y 837 838config ARCH_WANT_HUGE_PMD_SHARE 839 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 840 841config ARCH_HAS_CACHE_LINE_SIZE 842 def_bool y 843 844config SECCOMP 845 bool "Enable seccomp to safely compute untrusted bytecode" 846 ---help--- 847 This kernel feature is useful for number crunching applications 848 that may need to compute untrusted bytecode during their 849 execution. By using pipes or other transports made available to 850 the process as file descriptors supporting the read/write 851 syscalls, it's possible to isolate those applications in 852 their own address space using seccomp. Once seccomp is 853 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 854 and the task is only allowed to execute a few safe syscalls 855 defined by each seccomp mode. 856 857config PARAVIRT 858 bool "Enable paravirtualization code" 859 help 860 This changes the kernel so it can modify itself when it is run 861 under a hypervisor, potentially improving performance significantly 862 over full virtualization. 863 864config PARAVIRT_TIME_ACCOUNTING 865 bool "Paravirtual steal time accounting" 866 select PARAVIRT 867 default n 868 help 869 Select this option to enable fine granularity task steal time 870 accounting. Time spent executing other tasks in parallel with 871 the current vCPU is discounted from the vCPU power. To account for 872 that, there can be a small performance impact. 873 874 If in doubt, say N here. 875 876config KEXEC 877 depends on PM_SLEEP_SMP 878 select KEXEC_CORE 879 bool "kexec system call" 880 ---help--- 881 kexec is a system call that implements the ability to shutdown your 882 current kernel, and to start another kernel. It is like a reboot 883 but it is independent of the system firmware. And like a reboot 884 you can start any kernel with it, not just Linux. 885 886config CRASH_DUMP 887 bool "Build kdump crash kernel" 888 help 889 Generate crash dump after being started by kexec. This should 890 be normally only set in special crash dump kernels which are 891 loaded in the main kernel with kexec-tools into a specially 892 reserved region and then later executed after a crash by 893 kdump/kexec. 894 895 For more details see Documentation/kdump/kdump.txt 896 897config XEN_DOM0 898 def_bool y 899 depends on XEN 900 901config XEN 902 bool "Xen guest support on ARM64" 903 depends on ARM64 && OF 904 select SWIOTLB_XEN 905 select PARAVIRT 906 help 907 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 908 909config FORCE_MAX_ZONEORDER 910 int 911 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) 912 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE) 913 default "11" 914 help 915 The kernel memory allocator divides physically contiguous memory 916 blocks into "zones", where each zone is a power of two number of 917 pages. This option selects the largest power of two that the kernel 918 keeps in the memory allocator. If you need to allocate very large 919 blocks of physically contiguous memory, then you may need to 920 increase this value. 921 922 This config option is actually maximum order plus one. For example, 923 a value of 11 means that the largest free memory block is 2^10 pages. 924 925 We make sure that we can allocate upto a HugePage size for each configuration. 926 Hence we have : 927 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 928 929 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 930 4M allocations matching the default size used by generic code. 931 932config UNMAP_KERNEL_AT_EL0 933 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 934 default y 935 help 936 Speculation attacks against some high-performance processors can 937 be used to bypass MMU permission checks and leak kernel data to 938 userspace. This can be defended against by unmapping the kernel 939 when running in userspace, mapping it back in on exception entry 940 via a trampoline page in the vector table. 941 942 If unsure, say Y. 943 944config HARDEN_BRANCH_PREDICTOR 945 bool "Harden the branch predictor against aliasing attacks" if EXPERT 946 default y 947 help 948 Speculation attacks against some high-performance processors rely on 949 being able to manipulate the branch predictor for a victim context by 950 executing aliasing branches in the attacker context. Such attacks 951 can be partially mitigated against by clearing internal branch 952 predictor state and limiting the prediction logic in some situations. 953 954 This config option will take CPU-specific actions to harden the 955 branch predictor against aliasing attacks and may rely on specific 956 instruction sequences or control bits being set by the system 957 firmware. 958 959 If unsure, say Y. 960 961config HARDEN_EL2_VECTORS 962 bool "Harden EL2 vector mapping against system register leak" if EXPERT 963 default y 964 help 965 Speculation attacks against some high-performance processors can 966 be used to leak privileged information such as the vector base 967 register, resulting in a potential defeat of the EL2 layout 968 randomization. 969 970 This config option will map the vectors to a fixed location, 971 independent of the EL2 code mapping, so that revealing VBAR_EL2 972 to an attacker does not give away any extra information. This 973 only gets enabled on affected CPUs. 974 975 If unsure, say Y. 976 977config ARM64_SSBD 978 bool "Speculative Store Bypass Disable" if EXPERT 979 default y 980 help 981 This enables mitigation of the bypassing of previous stores 982 by speculative loads. 983 984 If unsure, say Y. 985 986menuconfig ARMV8_DEPRECATED 987 bool "Emulate deprecated/obsolete ARMv8 instructions" 988 depends on COMPAT 989 depends on SYSCTL 990 help 991 Legacy software support may require certain instructions 992 that have been deprecated or obsoleted in the architecture. 993 994 Enable this config to enable selective emulation of these 995 features. 996 997 If unsure, say Y 998 999if ARMV8_DEPRECATED 1000 1001config SWP_EMULATION 1002 bool "Emulate SWP/SWPB instructions" 1003 help 1004 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1005 they are always undefined. Say Y here to enable software 1006 emulation of these instructions for userspace using LDXR/STXR. 1007 1008 In some older versions of glibc [<=2.8] SWP is used during futex 1009 trylock() operations with the assumption that the code will not 1010 be preempted. This invalid assumption may be more likely to fail 1011 with SWP emulation enabled, leading to deadlock of the user 1012 application. 1013 1014 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1015 on an external transaction monitoring block called a global 1016 monitor to maintain update atomicity. If your system does not 1017 implement a global monitor, this option can cause programs that 1018 perform SWP operations to uncached memory to deadlock. 1019 1020 If unsure, say Y 1021 1022config CP15_BARRIER_EMULATION 1023 bool "Emulate CP15 Barrier instructions" 1024 help 1025 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1026 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1027 strongly recommended to use the ISB, DSB, and DMB 1028 instructions instead. 1029 1030 Say Y here to enable software emulation of these 1031 instructions for AArch32 userspace code. When this option is 1032 enabled, CP15 barrier usage is traced which can help 1033 identify software that needs updating. 1034 1035 If unsure, say Y 1036 1037config SETEND_EMULATION 1038 bool "Emulate SETEND instruction" 1039 help 1040 The SETEND instruction alters the data-endianness of the 1041 AArch32 EL0, and is deprecated in ARMv8. 1042 1043 Say Y here to enable software emulation of the instruction 1044 for AArch32 userspace code. 1045 1046 Note: All the cpus on the system must have mixed endian support at EL0 1047 for this feature to be enabled. If a new CPU - which doesn't support mixed 1048 endian - is hotplugged in after this feature has been enabled, there could 1049 be unexpected results in the applications. 1050 1051 If unsure, say Y 1052endif 1053 1054config ARM64_SW_TTBR0_PAN 1055 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1056 help 1057 Enabling this option prevents the kernel from accessing 1058 user-space memory directly by pointing TTBR0_EL1 to a reserved 1059 zeroed area and reserved ASID. The user access routines 1060 restore the valid TTBR0_EL1 temporarily. 1061 1062menu "ARMv8.1 architectural features" 1063 1064config ARM64_HW_AFDBM 1065 bool "Support for hardware updates of the Access and Dirty page flags" 1066 default y 1067 help 1068 The ARMv8.1 architecture extensions introduce support for 1069 hardware updates of the access and dirty information in page 1070 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1071 capable processors, accesses to pages with PTE_AF cleared will 1072 set this bit instead of raising an access flag fault. 1073 Similarly, writes to read-only pages with the DBM bit set will 1074 clear the read-only bit (AP[2]) instead of raising a 1075 permission fault. 1076 1077 Kernels built with this configuration option enabled continue 1078 to work on pre-ARMv8.1 hardware and the performance impact is 1079 minimal. If unsure, say Y. 1080 1081config ARM64_PAN 1082 bool "Enable support for Privileged Access Never (PAN)" 1083 default y 1084 help 1085 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1086 prevents the kernel or hypervisor from accessing user-space (EL0) 1087 memory directly. 1088 1089 Choosing this option will cause any unprotected (not using 1090 copy_to_user et al) memory access to fail with a permission fault. 1091 1092 The feature is detected at runtime, and will remain as a 'nop' 1093 instruction if the cpu does not implement the feature. 1094 1095config ARM64_LSE_ATOMICS 1096 bool "Atomic instructions" 1097 default y 1098 help 1099 As part of the Large System Extensions, ARMv8.1 introduces new 1100 atomic instructions that are designed specifically to scale in 1101 very large systems. 1102 1103 Say Y here to make use of these instructions for the in-kernel 1104 atomic routines. This incurs a small overhead on CPUs that do 1105 not support these instructions and requires the kernel to be 1106 built with binutils >= 2.25 in order for the new instructions 1107 to be used. 1108 1109config ARM64_VHE 1110 bool "Enable support for Virtualization Host Extensions (VHE)" 1111 default y 1112 help 1113 Virtualization Host Extensions (VHE) allow the kernel to run 1114 directly at EL2 (instead of EL1) on processors that support 1115 it. This leads to better performance for KVM, as they reduce 1116 the cost of the world switch. 1117 1118 Selecting this option allows the VHE feature to be detected 1119 at runtime, and does not affect processors that do not 1120 implement this feature. 1121 1122endmenu 1123 1124menu "ARMv8.2 architectural features" 1125 1126config ARM64_UAO 1127 bool "Enable support for User Access Override (UAO)" 1128 default y 1129 help 1130 User Access Override (UAO; part of the ARMv8.2 Extensions) 1131 causes the 'unprivileged' variant of the load/store instructions to 1132 be overridden to be privileged. 1133 1134 This option changes get_user() and friends to use the 'unprivileged' 1135 variant of the load/store instructions. This ensures that user-space 1136 really did have access to the supplied memory. When addr_limit is 1137 set to kernel memory the UAO bit will be set, allowing privileged 1138 access to kernel memory. 1139 1140 Choosing this option will cause copy_to_user() et al to use user-space 1141 memory permissions. 1142 1143 The feature is detected at runtime, the kernel will use the 1144 regular load/store instructions if the cpu does not implement the 1145 feature. 1146 1147config ARM64_PMEM 1148 bool "Enable support for persistent memory" 1149 select ARCH_HAS_PMEM_API 1150 select ARCH_HAS_UACCESS_FLUSHCACHE 1151 help 1152 Say Y to enable support for the persistent memory API based on the 1153 ARMv8.2 DCPoP feature. 1154 1155 The feature is detected at runtime, and the kernel will use DC CVAC 1156 operations if DC CVAP is not supported (following the behaviour of 1157 DC CVAP itself if the system does not define a point of persistence). 1158 1159config ARM64_RAS_EXTN 1160 bool "Enable support for RAS CPU Extensions" 1161 default y 1162 help 1163 CPUs that support the Reliability, Availability and Serviceability 1164 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1165 errors, classify them and report them to software. 1166 1167 On CPUs with these extensions system software can use additional 1168 barriers to determine if faults are pending and read the 1169 classification from a new set of registers. 1170 1171 Selecting this feature will allow the kernel to use these barriers 1172 and access the new registers if the system supports the extension. 1173 Platform RAS features may additionally depend on firmware support. 1174 1175config ARM64_CNP 1176 bool "Enable support for Common Not Private (CNP) translations" 1177 default y 1178 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1179 help 1180 Common Not Private (CNP) allows translation table entries to 1181 be shared between different PEs in the same inner shareable 1182 domain, so the hardware can use this fact to optimise the 1183 caching of such entries in the TLB. 1184 1185 Selecting this option allows the CNP feature to be detected 1186 at runtime, and does not affect PEs that do not implement 1187 this feature. 1188 1189endmenu 1190 1191config ARM64_SVE 1192 bool "ARM Scalable Vector Extension support" 1193 default y 1194 depends on !KVM || ARM64_VHE 1195 help 1196 The Scalable Vector Extension (SVE) is an extension to the AArch64 1197 execution state which complements and extends the SIMD functionality 1198 of the base architecture to support much larger vectors and to enable 1199 additional vectorisation opportunities. 1200 1201 To enable use of this extension on CPUs that implement it, say Y. 1202 1203 Note that for architectural reasons, firmware _must_ implement SVE 1204 support when running on SVE capable hardware. The required support 1205 is present in: 1206 1207 * version 1.5 and later of the ARM Trusted Firmware 1208 * the AArch64 boot wrapper since commit 5e1261e08abf 1209 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1210 1211 For other firmware implementations, consult the firmware documentation 1212 or vendor. 1213 1214 If you need the kernel to boot on SVE-capable hardware with broken 1215 firmware, you may need to say N here until you get your firmware 1216 fixed. Otherwise, you may experience firmware panics or lockups when 1217 booting the kernel. If unsure and you are not observing these 1218 symptoms, you should assume that it is safe to say Y. 1219 1220 CPUs that support SVE are architecturally required to support the 1221 Virtualization Host Extensions (VHE), so the kernel makes no 1222 provision for supporting SVE alongside KVM without VHE enabled. 1223 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support 1224 KVM in the same kernel image. 1225 1226config ARM64_MODULE_PLTS 1227 bool 1228 select HAVE_MOD_ARCH_SPECIFIC 1229 1230config RELOCATABLE 1231 bool 1232 help 1233 This builds the kernel as a Position Independent Executable (PIE), 1234 which retains all relocation metadata required to relocate the 1235 kernel binary at runtime to a different virtual address than the 1236 address it was linked at. 1237 Since AArch64 uses the RELA relocation format, this requires a 1238 relocation pass at runtime even if the kernel is loaded at the 1239 same address it was linked at. 1240 1241config RANDOMIZE_BASE 1242 bool "Randomize the address of the kernel image" 1243 select ARM64_MODULE_PLTS if MODULES 1244 select RELOCATABLE 1245 help 1246 Randomizes the virtual address at which the kernel image is 1247 loaded, as a security feature that deters exploit attempts 1248 relying on knowledge of the location of kernel internals. 1249 1250 It is the bootloader's job to provide entropy, by passing a 1251 random u64 value in /chosen/kaslr-seed at kernel entry. 1252 1253 When booting via the UEFI stub, it will invoke the firmware's 1254 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 1255 to the kernel proper. In addition, it will randomise the physical 1256 location of the kernel Image as well. 1257 1258 If unsure, say N. 1259 1260config RANDOMIZE_MODULE_REGION_FULL 1261 bool "Randomize the module region over a 4 GB range" 1262 depends on RANDOMIZE_BASE 1263 default y 1264 help 1265 Randomizes the location of the module region inside a 4 GB window 1266 covering the core kernel. This way, it is less likely for modules 1267 to leak information about the location of core kernel data structures 1268 but it does imply that function calls between modules and the core 1269 kernel will need to be resolved via veneers in the module PLT. 1270 1271 When this option is not set, the module region will be randomized over 1272 a limited range that contains the [_stext, _etext] interval of the 1273 core kernel, so branch relocations are always in range. 1274 1275endmenu 1276 1277menu "Boot options" 1278 1279config ARM64_ACPI_PARKING_PROTOCOL 1280 bool "Enable support for the ARM64 ACPI parking protocol" 1281 depends on ACPI 1282 help 1283 Enable support for the ARM64 ACPI parking protocol. If disabled 1284 the kernel will not allow booting through the ARM64 ACPI parking 1285 protocol even if the corresponding data is present in the ACPI 1286 MADT table. 1287 1288config CMDLINE 1289 string "Default kernel command string" 1290 default "" 1291 help 1292 Provide a set of default command-line options at build time by 1293 entering them here. As a minimum, you should specify the the 1294 root device (e.g. root=/dev/nfs). 1295 1296config CMDLINE_FORCE 1297 bool "Always use the default kernel command string" 1298 help 1299 Always use the default kernel command string, even if the boot 1300 loader passes other arguments to the kernel. 1301 This is useful if you cannot or don't want to change the 1302 command-line options your boot loader passes to the kernel. 1303 1304config EFI_STUB 1305 bool 1306 1307config EFI 1308 bool "UEFI runtime support" 1309 depends on OF && !CPU_BIG_ENDIAN 1310 depends on KERNEL_MODE_NEON 1311 select ARCH_SUPPORTS_ACPI 1312 select LIBFDT 1313 select UCS2_STRING 1314 select EFI_PARAMS_FROM_FDT 1315 select EFI_RUNTIME_WRAPPERS 1316 select EFI_STUB 1317 select EFI_ARMSTUB 1318 default y 1319 help 1320 This option provides support for runtime services provided 1321 by UEFI firmware (such as non-volatile variables, realtime 1322 clock, and platform reset). A UEFI stub is also provided to 1323 allow the kernel to be booted as an EFI application. This 1324 is only useful on systems that have UEFI firmware. 1325 1326config DMI 1327 bool "Enable support for SMBIOS (DMI) tables" 1328 depends on EFI 1329 default y 1330 help 1331 This enables SMBIOS/DMI feature for systems. 1332 1333 This option is only useful on systems that have UEFI firmware. 1334 However, even with this option, the resultant kernel should 1335 continue to boot on existing non-UEFI platforms. 1336 1337endmenu 1338 1339config COMPAT 1340 bool "Kernel support for 32-bit EL0" 1341 depends on ARM64_4K_PAGES || EXPERT 1342 select COMPAT_BINFMT_ELF if BINFMT_ELF 1343 select HAVE_UID16 1344 select OLD_SIGSUSPEND3 1345 select COMPAT_OLD_SIGACTION 1346 help 1347 This option enables support for a 32-bit EL0 running under a 64-bit 1348 kernel at EL1. AArch32-specific components such as system calls, 1349 the user helper functions, VFP support and the ptrace interface are 1350 handled appropriately by the kernel. 1351 1352 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1353 that you will only be able to execute AArch32 binaries that were compiled 1354 with page size aligned segments. 1355 1356 If you want to execute 32-bit userspace applications, say Y. 1357 1358config SYSVIPC_COMPAT 1359 def_bool y 1360 depends on COMPAT && SYSVIPC 1361 1362menu "Power management options" 1363 1364source "kernel/power/Kconfig" 1365 1366config ARCH_HIBERNATION_POSSIBLE 1367 def_bool y 1368 depends on CPU_PM 1369 1370config ARCH_HIBERNATION_HEADER 1371 def_bool y 1372 depends on HIBERNATION 1373 1374config ARCH_SUSPEND_POSSIBLE 1375 def_bool y 1376 1377endmenu 1378 1379menu "CPU Power Management" 1380 1381source "drivers/cpuidle/Kconfig" 1382 1383source "drivers/cpufreq/Kconfig" 1384 1385endmenu 1386 1387source "drivers/firmware/Kconfig" 1388 1389source "drivers/acpi/Kconfig" 1390 1391source "arch/arm64/kvm/Kconfig" 1392 1393if CRYPTO 1394source "arch/arm64/crypto/Kconfig" 1395endif 1396