1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_IORT if ACPI 9 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 10 select ACPI_MCFG if (ACPI && PCI) 11 select ACPI_SPCR_TABLE if ACPI 12 select ACPI_PPTT if ACPI 13 select ARCH_HAS_DEBUG_WX 14 select ARCH_BINFMT_ELF_EXTRA_PHDRS 15 select ARCH_BINFMT_ELF_STATE 16 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CURRENT_STACK_POINTER 24 select ARCH_HAS_DEBUG_VIRTUAL 25 select ARCH_HAS_DEBUG_VM_PGTABLE 26 select ARCH_HAS_DMA_PREP_COHERENT 27 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 28 select ARCH_HAS_FAST_MULTIPLIER 29 select ARCH_HAS_FORTIFY_SOURCE 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_HAS_GIGANTIC_PAGE 32 select ARCH_HAS_KCOV 33 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 34 select ARCH_HAS_KEEPINITRD 35 select ARCH_HAS_MEMBARRIER_SYNC_CORE 36 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 37 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 38 select ARCH_HAS_PTE_DEVMAP 39 select ARCH_HAS_PTE_SPECIAL 40 select ARCH_HAS_HW_PTE_YOUNG 41 select ARCH_HAS_SETUP_DMA_OPS 42 select ARCH_HAS_SET_DIRECT_MAP 43 select ARCH_HAS_SET_MEMORY 44 select ARCH_STACKWALK 45 select ARCH_HAS_STRICT_KERNEL_RWX 46 select ARCH_HAS_STRICT_MODULE_RWX 47 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 48 select ARCH_HAS_SYNC_DMA_FOR_CPU 49 select ARCH_HAS_SYSCALL_WRAPPER 50 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 51 select ARCH_HAS_ZONE_DMA_SET if EXPERT 52 select ARCH_HAVE_ELF_PROT 53 select ARCH_HAVE_NMI_SAFE_CMPXCHG 54 select ARCH_HAVE_TRACE_MMIO_ACCESS 55 select ARCH_INLINE_READ_LOCK if !PREEMPTION 56 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 57 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 58 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 59 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 60 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 61 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 63 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 64 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 72 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 73 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 74 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 75 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 77 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 78 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 79 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 81 select ARCH_KEEP_MEMBLOCK 82 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 83 select ARCH_USE_CMPXCHG_LOCKREF 84 select ARCH_USE_GNU_PROPERTY 85 select ARCH_USE_MEMTEST 86 select ARCH_USE_QUEUED_RWLOCKS 87 select ARCH_USE_QUEUED_SPINLOCKS 88 select ARCH_USE_SYM_ANNOTATIONS 89 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 90 select ARCH_SUPPORTS_HUGETLBFS 91 select ARCH_SUPPORTS_MEMORY_FAILURE 92 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 93 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 94 select ARCH_SUPPORTS_LTO_CLANG_THIN 95 select ARCH_SUPPORTS_CFI_CLANG 96 select ARCH_SUPPORTS_ATOMIC_RMW 97 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 98 select ARCH_SUPPORTS_NUMA_BALANCING 99 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 100 select ARCH_SUPPORTS_PER_VMA_LOCK 101 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 102 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 103 select ARCH_WANT_DEFAULT_BPF_JIT 104 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 105 select ARCH_WANT_FRAME_POINTERS 106 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 107 select ARCH_WANT_LD_ORPHAN_WARN 108 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 109 select ARCH_WANTS_NO_INSTR 110 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 111 select ARCH_HAS_UBSAN 112 select ARM_AMBA 113 select ARM_ARCH_TIMER 114 select ARM_GIC 115 select AUDIT_ARCH_COMPAT_GENERIC 116 select ARM_GIC_V2M if PCI 117 select ARM_GIC_V3 118 select ARM_GIC_V3_ITS if PCI 119 select ARM_PSCI_FW 120 select BUILDTIME_TABLE_SORT 121 select CLONE_BACKWARDS 122 select COMMON_CLK 123 select CPU_PM if (SUSPEND || CPU_IDLE) 124 select CPUMASK_OFFSTACK if NR_CPUS > 256 125 select CRC32 126 select DCACHE_WORD_ACCESS 127 select DYNAMIC_FTRACE if FUNCTION_TRACER 128 select DMA_BOUNCE_UNALIGNED_KMALLOC 129 select DMA_DIRECT_REMAP 130 select EDAC_SUPPORT 131 select FRAME_POINTER 132 select FUNCTION_ALIGNMENT_4B 133 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 134 select GENERIC_ALLOCATOR 135 select GENERIC_ARCH_TOPOLOGY 136 select GENERIC_CLOCKEVENTS_BROADCAST 137 select GENERIC_CPU_AUTOPROBE 138 select GENERIC_CPU_DEVICES 139 select GENERIC_CPU_VULNERABILITIES 140 select GENERIC_EARLY_IOREMAP 141 select GENERIC_IDLE_POLL_SETUP 142 select GENERIC_IOREMAP 143 select GENERIC_IRQ_IPI 144 select GENERIC_IRQ_PROBE 145 select GENERIC_IRQ_SHOW 146 select GENERIC_IRQ_SHOW_LEVEL 147 select GENERIC_LIB_DEVMEM_IS_ALLOWED 148 select GENERIC_PCI_IOMAP 149 select GENERIC_PTDUMP 150 select GENERIC_SCHED_CLOCK 151 select GENERIC_SMP_IDLE_THREAD 152 select GENERIC_TIME_VSYSCALL 153 select GENERIC_GETTIMEOFDAY 154 select GENERIC_VDSO_TIME_NS 155 select HARDIRQS_SW_RESEND 156 select HAS_IOPORT 157 select HAVE_MOVE_PMD 158 select HAVE_MOVE_PUD 159 select HAVE_PCI 160 select HAVE_ACPI_APEI if (ACPI && EFI) 161 select HAVE_ALIGNED_STRUCT_PAGE 162 select HAVE_ARCH_AUDITSYSCALL 163 select HAVE_ARCH_BITREVERSE 164 select HAVE_ARCH_COMPILER_H 165 select HAVE_ARCH_HUGE_VMALLOC 166 select HAVE_ARCH_HUGE_VMAP 167 select HAVE_ARCH_JUMP_LABEL 168 select HAVE_ARCH_JUMP_LABEL_RELATIVE 169 select HAVE_ARCH_KASAN 170 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 171 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 172 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 173 # Some instrumentation may be unsound, hence EXPERT 174 select HAVE_ARCH_KCSAN if EXPERT 175 select HAVE_ARCH_KFENCE 176 select HAVE_ARCH_KGDB 177 select HAVE_ARCH_MMAP_RND_BITS 178 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 179 select HAVE_ARCH_PREL32_RELOCATIONS 180 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 181 select HAVE_ARCH_SECCOMP_FILTER 182 select HAVE_ARCH_STACKLEAK 183 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 184 select HAVE_ARCH_TRACEHOOK 185 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 186 select HAVE_ARCH_VMAP_STACK 187 select HAVE_ARM_SMCCC 188 select HAVE_ASM_MODVERSIONS 189 select HAVE_EBPF_JIT 190 select HAVE_C_RECORDMCOUNT 191 select HAVE_CMPXCHG_DOUBLE 192 select HAVE_CMPXCHG_LOCAL 193 select HAVE_CONTEXT_TRACKING_USER 194 select HAVE_DEBUG_KMEMLEAK 195 select HAVE_DMA_CONTIGUOUS 196 select HAVE_DYNAMIC_FTRACE 197 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 198 if $(cc-option,-fpatchable-function-entry=2) 199 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 200 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 201 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 202 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 203 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 204 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 205 if DYNAMIC_FTRACE_WITH_ARGS 206 select HAVE_SAMPLE_FTRACE_DIRECT 207 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 208 select HAVE_EFFICIENT_UNALIGNED_ACCESS 209 select HAVE_GUP_FAST 210 select HAVE_FTRACE_MCOUNT_RECORD 211 select HAVE_FUNCTION_TRACER 212 select HAVE_FUNCTION_ERROR_INJECTION 213 select HAVE_FUNCTION_GRAPH_RETVAL if HAVE_FUNCTION_GRAPH_TRACER 214 select HAVE_FUNCTION_GRAPH_TRACER 215 select HAVE_GCC_PLUGINS 216 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 217 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 218 select HAVE_HW_BREAKPOINT if PERF_EVENTS 219 select HAVE_IOREMAP_PROT 220 select HAVE_IRQ_TIME_ACCOUNTING 221 select HAVE_MOD_ARCH_SPECIFIC 222 select HAVE_NMI 223 select HAVE_PERF_EVENTS 224 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 225 select HAVE_PERF_REGS 226 select HAVE_PERF_USER_STACK_DUMP 227 select HAVE_PREEMPT_DYNAMIC_KEY 228 select HAVE_REGS_AND_STACK_ACCESS_API 229 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 230 select HAVE_FUNCTION_ARG_ACCESS_API 231 select MMU_GATHER_RCU_TABLE_FREE 232 select HAVE_RSEQ 233 select HAVE_RUST if CPU_LITTLE_ENDIAN 234 select HAVE_STACKPROTECTOR 235 select HAVE_SYSCALL_TRACEPOINTS 236 select HAVE_KPROBES 237 select HAVE_KRETPROBES 238 select HAVE_GENERIC_VDSO 239 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 240 select IRQ_DOMAIN 241 select IRQ_FORCED_THREADING 242 select KASAN_VMALLOC if KASAN 243 select LOCK_MM_AND_FIND_VMA 244 select MODULES_USE_ELF_RELA 245 select NEED_DMA_MAP_STATE 246 select NEED_SG_DMA_LENGTH 247 select OF 248 select OF_EARLY_FLATTREE 249 select PCI_DOMAINS_GENERIC if PCI 250 select PCI_ECAM if (ACPI && PCI) 251 select PCI_SYSCALL if PCI 252 select POWER_RESET 253 select POWER_SUPPLY 254 select SPARSE_IRQ 255 select SWIOTLB 256 select SYSCTL_EXCEPTION_TRACE 257 select THREAD_INFO_IN_TASK 258 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 259 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 260 select TRACE_IRQFLAGS_SUPPORT 261 select TRACE_IRQFLAGS_NMI_SUPPORT 262 select HAVE_SOFTIRQ_ON_OWN_STACK 263 select USER_STACKTRACE_SUPPORT 264 help 265 ARM 64-bit (AArch64) Linux support. 266 267config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 268 def_bool CC_IS_CLANG 269 # https://github.com/ClangBuiltLinux/linux/issues/1507 270 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 271 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 272 273config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 274 def_bool CC_IS_GCC 275 depends on $(cc-option,-fpatchable-function-entry=2) 276 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 277 278config 64BIT 279 def_bool y 280 281config MMU 282 def_bool y 283 284config ARM64_CONT_PTE_SHIFT 285 int 286 default 5 if PAGE_SIZE_64KB 287 default 7 if PAGE_SIZE_16KB 288 default 4 289 290config ARM64_CONT_PMD_SHIFT 291 int 292 default 5 if PAGE_SIZE_64KB 293 default 5 if PAGE_SIZE_16KB 294 default 4 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 14 if PAGE_SIZE_64KB 298 default 16 if PAGE_SIZE_16KB 299 default 18 300 301# max bits determined by the following formula: 302# VA_BITS - PAGE_SHIFT - 3 303config ARCH_MMAP_RND_BITS_MAX 304 default 19 if ARM64_VA_BITS=36 305 default 24 if ARM64_VA_BITS=39 306 default 27 if ARM64_VA_BITS=42 307 default 30 if ARM64_VA_BITS=47 308 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 309 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 310 default 33 if ARM64_VA_BITS=48 311 default 14 if ARM64_64K_PAGES 312 default 16 if ARM64_16K_PAGES 313 default 18 314 315config ARCH_MMAP_RND_COMPAT_BITS_MIN 316 default 7 if ARM64_64K_PAGES 317 default 9 if ARM64_16K_PAGES 318 default 11 319 320config ARCH_MMAP_RND_COMPAT_BITS_MAX 321 default 16 322 323config NO_IOPORT_MAP 324 def_bool y if !PCI 325 326config STACKTRACE_SUPPORT 327 def_bool y 328 329config ILLEGAL_POINTER_VALUE 330 hex 331 default 0xdead000000000000 332 333config LOCKDEP_SUPPORT 334 def_bool y 335 336config GENERIC_BUG 337 def_bool y 338 depends on BUG 339 340config GENERIC_BUG_RELATIVE_POINTERS 341 def_bool y 342 depends on GENERIC_BUG 343 344config GENERIC_HWEIGHT 345 def_bool y 346 347config GENERIC_CSUM 348 def_bool y 349 350config GENERIC_CALIBRATE_DELAY 351 def_bool y 352 353config SMP 354 def_bool y 355 356config KERNEL_MODE_NEON 357 def_bool y 358 359config FIX_EARLYCON_MEM 360 def_bool y 361 362config PGTABLE_LEVELS 363 int 364 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 365 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 366 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 367 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 368 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 369 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 370 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 371 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 372 373config ARCH_SUPPORTS_UPROBES 374 def_bool y 375 376config ARCH_PROC_KCORE_TEXT 377 def_bool y 378 379config BROKEN_GAS_INST 380 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 381 382config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 383 bool 384 # Clang's __builtin_return_adddress() strips the PAC since 12.0.0 385 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 386 default y if CC_IS_CLANG 387 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 388 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 389 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 390 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 391 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 392 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 393 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 394 default n 395 396config KASAN_SHADOW_OFFSET 397 hex 398 depends on KASAN_GENERIC || KASAN_SW_TAGS 399 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 400 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 401 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 402 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 403 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 404 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 405 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 406 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 407 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 408 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 409 default 0xffffffffffffffff 410 411config UNWIND_TABLES 412 bool 413 414source "arch/arm64/Kconfig.platforms" 415 416menu "Kernel Features" 417 418menu "ARM errata workarounds via the alternatives framework" 419 420config AMPERE_ERRATUM_AC03_CPU_38 421 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 422 default y 423 help 424 This option adds an alternative code sequence to work around Ampere 425 erratum AC03_CPU_38 on AmpereOne. 426 427 The affected design reports FEAT_HAFDBS as not implemented in 428 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 429 as required by the architecture. The unadvertised HAFDBS 430 implementation suffers from an additional erratum where hardware 431 A/D updates can occur after a PTE has been marked invalid. 432 433 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 434 which avoids enabling unadvertised hardware Access Flag management 435 at stage-2. 436 437 If unsure, say Y. 438 439config ARM64_WORKAROUND_CLEAN_CACHE 440 bool 441 442config ARM64_ERRATUM_826319 443 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 444 default y 445 select ARM64_WORKAROUND_CLEAN_CACHE 446 help 447 This option adds an alternative code sequence to work around ARM 448 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 449 AXI master interface and an L2 cache. 450 451 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 452 and is unable to accept a certain write via this interface, it will 453 not progress on read data presented on the read data channel and the 454 system can deadlock. 455 456 The workaround promotes data cache clean instructions to 457 data cache clean-and-invalidate. 458 Please note that this does not necessarily enable the workaround, 459 as it depends on the alternative framework, which will only patch 460 the kernel if an affected CPU is detected. 461 462 If unsure, say Y. 463 464config ARM64_ERRATUM_827319 465 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 466 default y 467 select ARM64_WORKAROUND_CLEAN_CACHE 468 help 469 This option adds an alternative code sequence to work around ARM 470 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 471 master interface and an L2 cache. 472 473 Under certain conditions this erratum can cause a clean line eviction 474 to occur at the same time as another transaction to the same address 475 on the AMBA 5 CHI interface, which can cause data corruption if the 476 interconnect reorders the two transactions. 477 478 The workaround promotes data cache clean instructions to 479 data cache clean-and-invalidate. 480 Please note that this does not necessarily enable the workaround, 481 as it depends on the alternative framework, which will only patch 482 the kernel if an affected CPU is detected. 483 484 If unsure, say Y. 485 486config ARM64_ERRATUM_824069 487 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 488 default y 489 select ARM64_WORKAROUND_CLEAN_CACHE 490 help 491 This option adds an alternative code sequence to work around ARM 492 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 493 to a coherent interconnect. 494 495 If a Cortex-A53 processor is executing a store or prefetch for 496 write instruction at the same time as a processor in another 497 cluster is executing a cache maintenance operation to the same 498 address, then this erratum might cause a clean cache line to be 499 incorrectly marked as dirty. 500 501 The workaround promotes data cache clean instructions to 502 data cache clean-and-invalidate. 503 Please note that this option does not necessarily enable the 504 workaround, as it depends on the alternative framework, which will 505 only patch the kernel if an affected CPU is detected. 506 507 If unsure, say Y. 508 509config ARM64_ERRATUM_819472 510 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 511 default y 512 select ARM64_WORKAROUND_CLEAN_CACHE 513 help 514 This option adds an alternative code sequence to work around ARM 515 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 516 present when it is connected to a coherent interconnect. 517 518 If the processor is executing a load and store exclusive sequence at 519 the same time as a processor in another cluster is executing a cache 520 maintenance operation to the same address, then this erratum might 521 cause data corruption. 522 523 The workaround promotes data cache clean instructions to 524 data cache clean-and-invalidate. 525 Please note that this does not necessarily enable the workaround, 526 as it depends on the alternative framework, which will only patch 527 the kernel if an affected CPU is detected. 528 529 If unsure, say Y. 530 531config ARM64_ERRATUM_832075 532 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 533 default y 534 help 535 This option adds an alternative code sequence to work around ARM 536 erratum 832075 on Cortex-A57 parts up to r1p2. 537 538 Affected Cortex-A57 parts might deadlock when exclusive load/store 539 instructions to Write-Back memory are mixed with Device loads. 540 541 The workaround is to promote device loads to use Load-Acquire 542 semantics. 543 Please note that this does not necessarily enable the workaround, 544 as it depends on the alternative framework, which will only patch 545 the kernel if an affected CPU is detected. 546 547 If unsure, say Y. 548 549config ARM64_ERRATUM_834220 550 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 551 depends on KVM 552 help 553 This option adds an alternative code sequence to work around ARM 554 erratum 834220 on Cortex-A57 parts up to r1p2. 555 556 Affected Cortex-A57 parts might report a Stage 2 translation 557 fault as the result of a Stage 1 fault for load crossing a 558 page boundary when there is a permission or device memory 559 alignment fault at Stage 1 and a translation fault at Stage 2. 560 561 The workaround is to verify that the Stage 1 translation 562 doesn't generate a fault before handling the Stage 2 fault. 563 Please note that this does not necessarily enable the workaround, 564 as it depends on the alternative framework, which will only patch 565 the kernel if an affected CPU is detected. 566 567 If unsure, say N. 568 569config ARM64_ERRATUM_1742098 570 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 571 depends on COMPAT 572 default y 573 help 574 This option removes the AES hwcap for aarch32 user-space to 575 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 576 577 Affected parts may corrupt the AES state if an interrupt is 578 taken between a pair of AES instructions. These instructions 579 are only present if the cryptography extensions are present. 580 All software should have a fallback implementation for CPUs 581 that don't implement the cryptography extensions. 582 583 If unsure, say Y. 584 585config ARM64_ERRATUM_845719 586 bool "Cortex-A53: 845719: a load might read incorrect data" 587 depends on COMPAT 588 default y 589 help 590 This option adds an alternative code sequence to work around ARM 591 erratum 845719 on Cortex-A53 parts up to r0p4. 592 593 When running a compat (AArch32) userspace on an affected Cortex-A53 594 part, a load at EL0 from a virtual address that matches the bottom 32 595 bits of the virtual address used by a recent load at (AArch64) EL1 596 might return incorrect data. 597 598 The workaround is to write the contextidr_el1 register on exception 599 return to a 32-bit task. 600 Please note that this does not necessarily enable the workaround, 601 as it depends on the alternative framework, which will only patch 602 the kernel if an affected CPU is detected. 603 604 If unsure, say Y. 605 606config ARM64_ERRATUM_843419 607 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 608 default y 609 help 610 This option links the kernel with '--fix-cortex-a53-843419' and 611 enables PLT support to replace certain ADRP instructions, which can 612 cause subsequent memory accesses to use an incorrect address on 613 Cortex-A53 parts up to r0p4. 614 615 If unsure, say Y. 616 617config ARM64_LD_HAS_FIX_ERRATUM_843419 618 def_bool $(ld-option,--fix-cortex-a53-843419) 619 620config ARM64_ERRATUM_1024718 621 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 622 default y 623 help 624 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 625 626 Affected Cortex-A55 cores (all revisions) could cause incorrect 627 update of the hardware dirty bit when the DBM/AP bits are updated 628 without a break-before-make. The workaround is to disable the usage 629 of hardware DBM locally on the affected cores. CPUs not affected by 630 this erratum will continue to use the feature. 631 632 If unsure, say Y. 633 634config ARM64_ERRATUM_1418040 635 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 636 default y 637 depends on COMPAT 638 help 639 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 640 errata 1188873 and 1418040. 641 642 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 643 cause register corruption when accessing the timer registers 644 from AArch32 userspace. 645 646 If unsure, say Y. 647 648config ARM64_WORKAROUND_SPECULATIVE_AT 649 bool 650 651config ARM64_ERRATUM_1165522 652 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 653 default y 654 select ARM64_WORKAROUND_SPECULATIVE_AT 655 help 656 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 657 658 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 659 corrupted TLBs by speculating an AT instruction during a guest 660 context switch. 661 662 If unsure, say Y. 663 664config ARM64_ERRATUM_1319367 665 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 666 default y 667 select ARM64_WORKAROUND_SPECULATIVE_AT 668 help 669 This option adds work arounds for ARM Cortex-A57 erratum 1319537 670 and A72 erratum 1319367 671 672 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 673 speculating an AT instruction during a guest context switch. 674 675 If unsure, say Y. 676 677config ARM64_ERRATUM_1530923 678 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 679 default y 680 select ARM64_WORKAROUND_SPECULATIVE_AT 681 help 682 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 683 684 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 685 corrupted TLBs by speculating an AT instruction during a guest 686 context switch. 687 688 If unsure, say Y. 689 690config ARM64_WORKAROUND_REPEAT_TLBI 691 bool 692 693config ARM64_ERRATUM_2441007 694 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 695 select ARM64_WORKAROUND_REPEAT_TLBI 696 help 697 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 698 699 Under very rare circumstances, affected Cortex-A55 CPUs 700 may not handle a race between a break-before-make sequence on one 701 CPU, and another CPU accessing the same page. This could allow a 702 store to a page that has been unmapped. 703 704 Work around this by adding the affected CPUs to the list that needs 705 TLB sequences to be done twice. 706 707 If unsure, say N. 708 709config ARM64_ERRATUM_1286807 710 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 711 select ARM64_WORKAROUND_REPEAT_TLBI 712 help 713 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 714 715 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 716 address for a cacheable mapping of a location is being 717 accessed by a core while another core is remapping the virtual 718 address to a new physical page using the recommended 719 break-before-make sequence, then under very rare circumstances 720 TLBI+DSB completes before a read using the translation being 721 invalidated has been observed by other observers. The 722 workaround repeats the TLBI+DSB operation. 723 724 If unsure, say N. 725 726config ARM64_ERRATUM_1463225 727 bool "Cortex-A76: Software Step might prevent interrupt recognition" 728 default y 729 help 730 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 731 732 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 733 of a system call instruction (SVC) can prevent recognition of 734 subsequent interrupts when software stepping is disabled in the 735 exception handler of the system call and either kernel debugging 736 is enabled or VHE is in use. 737 738 Work around the erratum by triggering a dummy step exception 739 when handling a system call from a task that is being stepped 740 in a VHE configuration of the kernel. 741 742 If unsure, say Y. 743 744config ARM64_ERRATUM_1542419 745 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 746 help 747 This option adds a workaround for ARM Neoverse-N1 erratum 748 1542419. 749 750 Affected Neoverse-N1 cores could execute a stale instruction when 751 modified by another CPU. The workaround depends on a firmware 752 counterpart. 753 754 Workaround the issue by hiding the DIC feature from EL0. This 755 forces user-space to perform cache maintenance. 756 757 If unsure, say N. 758 759config ARM64_ERRATUM_1508412 760 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 761 default y 762 help 763 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 764 765 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 766 of a store-exclusive or read of PAR_EL1 and a load with device or 767 non-cacheable memory attributes. The workaround depends on a firmware 768 counterpart. 769 770 KVM guests must also have the workaround implemented or they can 771 deadlock the system. 772 773 Work around the issue by inserting DMB SY barriers around PAR_EL1 774 register reads and warning KVM users. The DMB barrier is sufficient 775 to prevent a speculative PAR_EL1 read. 776 777 If unsure, say Y. 778 779config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 780 bool 781 782config ARM64_ERRATUM_2051678 783 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 784 default y 785 help 786 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 787 Affected Cortex-A510 might not respect the ordering rules for 788 hardware update of the page table's dirty bit. The workaround 789 is to not enable the feature on affected CPUs. 790 791 If unsure, say Y. 792 793config ARM64_ERRATUM_2077057 794 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 795 default y 796 help 797 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 798 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 799 expected, but a Pointer Authentication trap is taken instead. The 800 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 801 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 802 803 This can only happen when EL2 is stepping EL1. 804 805 When these conditions occur, the SPSR_EL2 value is unchanged from the 806 previous guest entry, and can be restored from the in-memory copy. 807 808 If unsure, say Y. 809 810config ARM64_ERRATUM_2658417 811 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 812 default y 813 help 814 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 815 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 816 BFMMLA or VMMLA instructions in rare circumstances when a pair of 817 A510 CPUs are using shared neon hardware. As the sharing is not 818 discoverable by the kernel, hide the BF16 HWCAP to indicate that 819 user-space should not be using these instructions. 820 821 If unsure, say Y. 822 823config ARM64_ERRATUM_2119858 824 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 825 default y 826 depends on CORESIGHT_TRBE 827 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 828 help 829 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 830 831 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 832 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 833 the event of a WRAP event. 834 835 Work around the issue by always making sure we move the TRBPTR_EL1 by 836 256 bytes before enabling the buffer and filling the first 256 bytes of 837 the buffer with ETM ignore packets upon disabling. 838 839 If unsure, say Y. 840 841config ARM64_ERRATUM_2139208 842 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 843 default y 844 depends on CORESIGHT_TRBE 845 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 846 help 847 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 848 849 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 850 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 851 the event of a WRAP event. 852 853 Work around the issue by always making sure we move the TRBPTR_EL1 by 854 256 bytes before enabling the buffer and filling the first 256 bytes of 855 the buffer with ETM ignore packets upon disabling. 856 857 If unsure, say Y. 858 859config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 860 bool 861 862config ARM64_ERRATUM_2054223 863 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 864 default y 865 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 866 help 867 Enable workaround for ARM Cortex-A710 erratum 2054223 868 869 Affected cores may fail to flush the trace data on a TSB instruction, when 870 the PE is in trace prohibited state. This will cause losing a few bytes 871 of the trace cached. 872 873 Workaround is to issue two TSB consecutively on affected cores. 874 875 If unsure, say Y. 876 877config ARM64_ERRATUM_2067961 878 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 879 default y 880 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 881 help 882 Enable workaround for ARM Neoverse-N2 erratum 2067961 883 884 Affected cores may fail to flush the trace data on a TSB instruction, when 885 the PE is in trace prohibited state. This will cause losing a few bytes 886 of the trace cached. 887 888 Workaround is to issue two TSB consecutively on affected cores. 889 890 If unsure, say Y. 891 892config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 893 bool 894 895config ARM64_ERRATUM_2253138 896 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 897 depends on CORESIGHT_TRBE 898 default y 899 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 900 help 901 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 902 903 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 904 for TRBE. Under some conditions, the TRBE might generate a write to the next 905 virtually addressed page following the last page of the TRBE address space 906 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 907 908 Work around this in the driver by always making sure that there is a 909 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 910 911 If unsure, say Y. 912 913config ARM64_ERRATUM_2224489 914 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 915 depends on CORESIGHT_TRBE 916 default y 917 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 918 help 919 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 920 921 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 922 for TRBE. Under some conditions, the TRBE might generate a write to the next 923 virtually addressed page following the last page of the TRBE address space 924 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 925 926 Work around this in the driver by always making sure that there is a 927 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 928 929 If unsure, say Y. 930 931config ARM64_ERRATUM_2441009 932 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 933 select ARM64_WORKAROUND_REPEAT_TLBI 934 help 935 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 936 937 Under very rare circumstances, affected Cortex-A510 CPUs 938 may not handle a race between a break-before-make sequence on one 939 CPU, and another CPU accessing the same page. This could allow a 940 store to a page that has been unmapped. 941 942 Work around this by adding the affected CPUs to the list that needs 943 TLB sequences to be done twice. 944 945 If unsure, say N. 946 947config ARM64_ERRATUM_2064142 948 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 949 depends on CORESIGHT_TRBE 950 default y 951 help 952 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 953 954 Affected Cortex-A510 core might fail to write into system registers after the 955 TRBE has been disabled. Under some conditions after the TRBE has been disabled 956 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 957 and TRBTRG_EL1 will be ignored and will not be effected. 958 959 Work around this in the driver by executing TSB CSYNC and DSB after collection 960 is stopped and before performing a system register write to one of the affected 961 registers. 962 963 If unsure, say Y. 964 965config ARM64_ERRATUM_2038923 966 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 967 depends on CORESIGHT_TRBE 968 default y 969 help 970 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 971 972 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 973 prohibited within the CPU. As a result, the trace buffer or trace buffer state 974 might be corrupted. This happens after TRBE buffer has been enabled by setting 975 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 976 execution changes from a context, in which trace is prohibited to one where it 977 isn't, or vice versa. In these mentioned conditions, the view of whether trace 978 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 979 the trace buffer state might be corrupted. 980 981 Work around this in the driver by preventing an inconsistent view of whether the 982 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 983 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 984 two ISB instructions if no ERET is to take place. 985 986 If unsure, say Y. 987 988config ARM64_ERRATUM_1902691 989 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 990 depends on CORESIGHT_TRBE 991 default y 992 help 993 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 994 995 Affected Cortex-A510 core might cause trace data corruption, when being written 996 into the memory. Effectively TRBE is broken and hence cannot be used to capture 997 trace data. 998 999 Work around this problem in the driver by just preventing TRBE initialization on 1000 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1001 on such implementations. This will cover the kernel for any firmware that doesn't 1002 do this already. 1003 1004 If unsure, say Y. 1005 1006config ARM64_ERRATUM_2457168 1007 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1008 depends on ARM64_AMU_EXTN 1009 default y 1010 help 1011 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1012 1013 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1014 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1015 incorrectly giving a significantly higher output value. 1016 1017 Work around this problem by returning 0 when reading the affected counter in 1018 key locations that results in disabling all users of this counter. This effect 1019 is the same to firmware disabling affected counters. 1020 1021 If unsure, say Y. 1022 1023config ARM64_ERRATUM_2645198 1024 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1025 default y 1026 help 1027 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1028 1029 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1030 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1031 next instruction abort caused by permission fault. 1032 1033 Only user-space does executable to non-executable permission transition via 1034 mprotect() system call. Workaround the problem by doing a break-before-make 1035 TLB invalidation, for all changes to executable user space mappings. 1036 1037 If unsure, say Y. 1038 1039config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1040 bool 1041 1042config ARM64_ERRATUM_2966298 1043 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1044 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1045 default y 1046 help 1047 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1048 1049 On an affected Cortex-A520 core, a speculatively executed unprivileged 1050 load might leak data from a privileged level via a cache side channel. 1051 1052 Work around this problem by executing a TLBI before returning to EL0. 1053 1054 If unsure, say Y. 1055 1056config ARM64_ERRATUM_3117295 1057 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1058 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1059 default y 1060 help 1061 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1062 1063 On an affected Cortex-A510 core, a speculatively executed unprivileged 1064 load might leak data from a privileged level via a cache side channel. 1065 1066 Work around this problem by executing a TLBI before returning to EL0. 1067 1068 If unsure, say Y. 1069 1070config ARM64_WORKAROUND_SPECULATIVE_SSBS 1071 bool 1072 1073config ARM64_ERRATUM_3194386 1074 bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing" 1075 select ARM64_WORKAROUND_SPECULATIVE_SSBS 1076 default y 1077 help 1078 This option adds the workaround for ARM Cortex-X4 erratum 3194386. 1079 1080 On affected cores "MSR SSBS, #0" instructions may not affect 1081 subsequent speculative instructions, which may permit unexepected 1082 speculative store bypassing. 1083 1084 Work around this problem by placing a speculation barrier after 1085 kernel changes to SSBS. The presence of the SSBS special-purpose 1086 register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such 1087 that userspace will use the PR_SPEC_STORE_BYPASS prctl to change 1088 SSBS. 1089 1090 If unsure, say Y. 1091 1092config ARM64_ERRATUM_3312417 1093 bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing" 1094 select ARM64_WORKAROUND_SPECULATIVE_SSBS 1095 default y 1096 help 1097 This option adds the workaround for ARM Neoverse-V3 erratum 3312417. 1098 1099 On affected cores "MSR SSBS, #0" instructions may not affect 1100 subsequent speculative instructions, which may permit unexepected 1101 speculative store bypassing. 1102 1103 Work around this problem by placing a speculation barrier after 1104 kernel changes to SSBS. The presence of the SSBS special-purpose 1105 register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such 1106 that userspace will use the PR_SPEC_STORE_BYPASS prctl to change 1107 SSBS. 1108 1109 If unsure, say Y. 1110 1111 1112config CAVIUM_ERRATUM_22375 1113 bool "Cavium erratum 22375, 24313" 1114 default y 1115 help 1116 Enable workaround for errata 22375 and 24313. 1117 1118 This implements two gicv3-its errata workarounds for ThunderX. Both 1119 with a small impact affecting only ITS table allocation. 1120 1121 erratum 22375: only alloc 8MB table size 1122 erratum 24313: ignore memory access type 1123 1124 The fixes are in ITS initialization and basically ignore memory access 1125 type and table size provided by the TYPER and BASER registers. 1126 1127 If unsure, say Y. 1128 1129config CAVIUM_ERRATUM_23144 1130 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1131 depends on NUMA 1132 default y 1133 help 1134 ITS SYNC command hang for cross node io and collections/cpu mapping. 1135 1136 If unsure, say Y. 1137 1138config CAVIUM_ERRATUM_23154 1139 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1140 default y 1141 help 1142 The ThunderX GICv3 implementation requires a modified version for 1143 reading the IAR status to ensure data synchronization 1144 (access to icc_iar1_el1 is not sync'ed before and after). 1145 1146 It also suffers from erratum 38545 (also present on Marvell's 1147 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1148 spuriously presented to the CPU interface. 1149 1150 If unsure, say Y. 1151 1152config CAVIUM_ERRATUM_27456 1153 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1154 default y 1155 help 1156 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1157 instructions may cause the icache to become corrupted if it 1158 contains data for a non-current ASID. The fix is to 1159 invalidate the icache when changing the mm context. 1160 1161 If unsure, say Y. 1162 1163config CAVIUM_ERRATUM_30115 1164 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1165 default y 1166 help 1167 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1168 1.2, and T83 Pass 1.0, KVM guest execution may disable 1169 interrupts in host. Trapping both GICv3 group-0 and group-1 1170 accesses sidesteps the issue. 1171 1172 If unsure, say Y. 1173 1174config CAVIUM_TX2_ERRATUM_219 1175 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1176 default y 1177 help 1178 On Cavium ThunderX2, a load, store or prefetch instruction between a 1179 TTBR update and the corresponding context synchronizing operation can 1180 cause a spurious Data Abort to be delivered to any hardware thread in 1181 the CPU core. 1182 1183 Work around the issue by avoiding the problematic code sequence and 1184 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1185 trap handler performs the corresponding register access, skips the 1186 instruction and ensures context synchronization by virtue of the 1187 exception return. 1188 1189 If unsure, say Y. 1190 1191config FUJITSU_ERRATUM_010001 1192 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1193 default y 1194 help 1195 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1196 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1197 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1198 This fault occurs under a specific hardware condition when a 1199 load/store instruction performs an address translation using: 1200 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1201 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1202 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1203 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1204 1205 The workaround is to ensure these bits are clear in TCR_ELx. 1206 The workaround only affects the Fujitsu-A64FX. 1207 1208 If unsure, say Y. 1209 1210config HISILICON_ERRATUM_161600802 1211 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1212 default y 1213 help 1214 The HiSilicon Hip07 SoC uses the wrong redistributor base 1215 when issued ITS commands such as VMOVP and VMAPP, and requires 1216 a 128kB offset to be applied to the target address in this commands. 1217 1218 If unsure, say Y. 1219 1220config QCOM_FALKOR_ERRATUM_1003 1221 bool "Falkor E1003: Incorrect translation due to ASID change" 1222 default y 1223 help 1224 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1225 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1226 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1227 then only for entries in the walk cache, since the leaf translation 1228 is unchanged. Work around the erratum by invalidating the walk cache 1229 entries for the trampoline before entering the kernel proper. 1230 1231config QCOM_FALKOR_ERRATUM_1009 1232 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1233 default y 1234 select ARM64_WORKAROUND_REPEAT_TLBI 1235 help 1236 On Falkor v1, the CPU may prematurely complete a DSB following a 1237 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1238 one more time to fix the issue. 1239 1240 If unsure, say Y. 1241 1242config QCOM_QDF2400_ERRATUM_0065 1243 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1244 default y 1245 help 1246 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1247 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1248 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1249 1250 If unsure, say Y. 1251 1252config QCOM_FALKOR_ERRATUM_E1041 1253 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1254 default y 1255 help 1256 Falkor CPU may speculatively fetch instructions from an improper 1257 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1258 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1259 1260 If unsure, say Y. 1261 1262config NVIDIA_CARMEL_CNP_ERRATUM 1263 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1264 default y 1265 help 1266 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1267 invalidate shared TLB entries installed by a different core, as it would 1268 on standard ARM cores. 1269 1270 If unsure, say Y. 1271 1272config ROCKCHIP_ERRATUM_3588001 1273 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1274 default y 1275 help 1276 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1277 This means, that its sharability feature may not be used, even though it 1278 is supported by the IP itself. 1279 1280 If unsure, say Y. 1281 1282config SOCIONEXT_SYNQUACER_PREITS 1283 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1284 default y 1285 help 1286 Socionext Synquacer SoCs implement a separate h/w block to generate 1287 MSI doorbell writes with non-zero values for the device ID. 1288 1289 If unsure, say Y. 1290 1291endmenu # "ARM errata workarounds via the alternatives framework" 1292 1293choice 1294 prompt "Page size" 1295 default ARM64_4K_PAGES 1296 help 1297 Page size (translation granule) configuration. 1298 1299config ARM64_4K_PAGES 1300 bool "4KB" 1301 select HAVE_PAGE_SIZE_4KB 1302 help 1303 This feature enables 4KB pages support. 1304 1305config ARM64_16K_PAGES 1306 bool "16KB" 1307 select HAVE_PAGE_SIZE_16KB 1308 help 1309 The system will use 16KB pages support. AArch32 emulation 1310 requires applications compiled with 16K (or a multiple of 16K) 1311 aligned segments. 1312 1313config ARM64_64K_PAGES 1314 bool "64KB" 1315 select HAVE_PAGE_SIZE_64KB 1316 help 1317 This feature enables 64KB pages support (4KB by default) 1318 allowing only two levels of page tables and faster TLB 1319 look-up. AArch32 emulation requires applications compiled 1320 with 64K aligned segments. 1321 1322endchoice 1323 1324choice 1325 prompt "Virtual address space size" 1326 default ARM64_VA_BITS_52 1327 help 1328 Allows choosing one of multiple possible virtual address 1329 space sizes. The level of translation table is determined by 1330 a combination of page size and virtual address space size. 1331 1332config ARM64_VA_BITS_36 1333 bool "36-bit" if EXPERT 1334 depends on PAGE_SIZE_16KB 1335 1336config ARM64_VA_BITS_39 1337 bool "39-bit" 1338 depends on PAGE_SIZE_4KB 1339 1340config ARM64_VA_BITS_42 1341 bool "42-bit" 1342 depends on PAGE_SIZE_64KB 1343 1344config ARM64_VA_BITS_47 1345 bool "47-bit" 1346 depends on PAGE_SIZE_16KB 1347 1348config ARM64_VA_BITS_48 1349 bool "48-bit" 1350 1351config ARM64_VA_BITS_52 1352 bool "52-bit" 1353 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1354 help 1355 Enable 52-bit virtual addressing for userspace when explicitly 1356 requested via a hint to mmap(). The kernel will also use 52-bit 1357 virtual addresses for its own mappings (provided HW support for 1358 this feature is available, otherwise it reverts to 48-bit). 1359 1360 NOTE: Enabling 52-bit virtual addressing in conjunction with 1361 ARMv8.3 Pointer Authentication will result in the PAC being 1362 reduced from 7 bits to 3 bits, which may have a significant 1363 impact on its susceptibility to brute-force attacks. 1364 1365 If unsure, select 48-bit virtual addressing instead. 1366 1367endchoice 1368 1369config ARM64_FORCE_52BIT 1370 bool "Force 52-bit virtual addresses for userspace" 1371 depends on ARM64_VA_BITS_52 && EXPERT 1372 help 1373 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1374 to maintain compatibility with older software by providing 48-bit VAs 1375 unless a hint is supplied to mmap. 1376 1377 This configuration option disables the 48-bit compatibility logic, and 1378 forces all userspace addresses to be 52-bit on HW that supports it. One 1379 should only enable this configuration option for stress testing userspace 1380 memory management code. If unsure say N here. 1381 1382config ARM64_VA_BITS 1383 int 1384 default 36 if ARM64_VA_BITS_36 1385 default 39 if ARM64_VA_BITS_39 1386 default 42 if ARM64_VA_BITS_42 1387 default 47 if ARM64_VA_BITS_47 1388 default 48 if ARM64_VA_BITS_48 1389 default 52 if ARM64_VA_BITS_52 1390 1391choice 1392 prompt "Physical address space size" 1393 default ARM64_PA_BITS_48 1394 help 1395 Choose the maximum physical address range that the kernel will 1396 support. 1397 1398config ARM64_PA_BITS_48 1399 bool "48-bit" 1400 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1401 1402config ARM64_PA_BITS_52 1403 bool "52-bit" 1404 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1405 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1406 help 1407 Enable support for a 52-bit physical address space, introduced as 1408 part of the ARMv8.2-LPA extension. 1409 1410 With this enabled, the kernel will also continue to work on CPUs that 1411 do not support ARMv8.2-LPA, but with some added memory overhead (and 1412 minor performance overhead). 1413 1414endchoice 1415 1416config ARM64_PA_BITS 1417 int 1418 default 48 if ARM64_PA_BITS_48 1419 default 52 if ARM64_PA_BITS_52 1420 1421config ARM64_LPA2 1422 def_bool y 1423 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1424 1425choice 1426 prompt "Endianness" 1427 default CPU_LITTLE_ENDIAN 1428 help 1429 Select the endianness of data accesses performed by the CPU. Userspace 1430 applications will need to be compiled and linked for the endianness 1431 that is selected here. 1432 1433config CPU_BIG_ENDIAN 1434 bool "Build big-endian kernel" 1435 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1436 depends on AS_IS_GNU || AS_VERSION >= 150000 1437 help 1438 Say Y if you plan on running a kernel with a big-endian userspace. 1439 1440config CPU_LITTLE_ENDIAN 1441 bool "Build little-endian kernel" 1442 help 1443 Say Y if you plan on running a kernel with a little-endian userspace. 1444 This is usually the case for distributions targeting arm64. 1445 1446endchoice 1447 1448config SCHED_MC 1449 bool "Multi-core scheduler support" 1450 help 1451 Multi-core scheduler support improves the CPU scheduler's decision 1452 making when dealing with multi-core CPU chips at a cost of slightly 1453 increased overhead in some places. If unsure say N here. 1454 1455config SCHED_CLUSTER 1456 bool "Cluster scheduler support" 1457 help 1458 Cluster scheduler support improves the CPU scheduler's decision 1459 making when dealing with machines that have clusters of CPUs. 1460 Cluster usually means a couple of CPUs which are placed closely 1461 by sharing mid-level caches, last-level cache tags or internal 1462 busses. 1463 1464config SCHED_SMT 1465 bool "SMT scheduler support" 1466 help 1467 Improves the CPU scheduler's decision making when dealing with 1468 MultiThreading at a cost of slightly increased overhead in some 1469 places. If unsure say N here. 1470 1471config NR_CPUS 1472 int "Maximum number of CPUs (2-4096)" 1473 range 2 4096 1474 default "512" 1475 1476config HOTPLUG_CPU 1477 bool "Support for hot-pluggable CPUs" 1478 select GENERIC_IRQ_MIGRATION 1479 help 1480 Say Y here to experiment with turning CPUs off and on. CPUs 1481 can be controlled through /sys/devices/system/cpu. 1482 1483# Common NUMA Features 1484config NUMA 1485 bool "NUMA Memory Allocation and Scheduler Support" 1486 select GENERIC_ARCH_NUMA 1487 select ACPI_NUMA if ACPI 1488 select OF_NUMA 1489 select HAVE_SETUP_PER_CPU_AREA 1490 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1491 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1492 select USE_PERCPU_NUMA_NODE_ID 1493 help 1494 Enable NUMA (Non-Uniform Memory Access) support. 1495 1496 The kernel will try to allocate memory used by a CPU on the 1497 local memory of the CPU and add some more 1498 NUMA awareness to the kernel. 1499 1500config NODES_SHIFT 1501 int "Maximum NUMA Nodes (as a power of 2)" 1502 range 1 10 1503 default "4" 1504 depends on NUMA 1505 help 1506 Specify the maximum number of NUMA Nodes available on the target 1507 system. Increases memory reserved to accommodate various tables. 1508 1509source "kernel/Kconfig.hz" 1510 1511config ARCH_SPARSEMEM_ENABLE 1512 def_bool y 1513 select SPARSEMEM_VMEMMAP_ENABLE 1514 select SPARSEMEM_VMEMMAP 1515 1516config HW_PERF_EVENTS 1517 def_bool y 1518 depends on ARM_PMU 1519 1520# Supported by clang >= 7.0 or GCC >= 12.0.0 1521config CC_HAVE_SHADOW_CALL_STACK 1522 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1523 1524config PARAVIRT 1525 bool "Enable paravirtualization code" 1526 help 1527 This changes the kernel so it can modify itself when it is run 1528 under a hypervisor, potentially improving performance significantly 1529 over full virtualization. 1530 1531config PARAVIRT_TIME_ACCOUNTING 1532 bool "Paravirtual steal time accounting" 1533 select PARAVIRT 1534 help 1535 Select this option to enable fine granularity task steal time 1536 accounting. Time spent executing other tasks in parallel with 1537 the current vCPU is discounted from the vCPU power. To account for 1538 that, there can be a small performance impact. 1539 1540 If in doubt, say N here. 1541 1542config ARCH_SUPPORTS_KEXEC 1543 def_bool PM_SLEEP_SMP 1544 1545config ARCH_SUPPORTS_KEXEC_FILE 1546 def_bool y 1547 1548config ARCH_SELECTS_KEXEC_FILE 1549 def_bool y 1550 depends on KEXEC_FILE 1551 select HAVE_IMA_KEXEC if IMA 1552 1553config ARCH_SUPPORTS_KEXEC_SIG 1554 def_bool y 1555 1556config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1557 def_bool y 1558 1559config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1560 def_bool y 1561 1562config ARCH_SUPPORTS_CRASH_DUMP 1563 def_bool y 1564 1565config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1566 def_bool CRASH_RESERVE 1567 1568config TRANS_TABLE 1569 def_bool y 1570 depends on HIBERNATION || KEXEC_CORE 1571 1572config XEN_DOM0 1573 def_bool y 1574 depends on XEN 1575 1576config XEN 1577 bool "Xen guest support on ARM64" 1578 depends on ARM64 && OF 1579 select SWIOTLB_XEN 1580 select PARAVIRT 1581 help 1582 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1583 1584# include/linux/mmzone.h requires the following to be true: 1585# 1586# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1587# 1588# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1589# 1590# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1591# ----+-------------------+--------------+----------------------+-------------------------+ 1592# 4K | 27 | 12 | 15 | 10 | 1593# 16K | 27 | 14 | 13 | 11 | 1594# 64K | 29 | 16 | 13 | 13 | 1595config ARCH_FORCE_MAX_ORDER 1596 int 1597 default "13" if ARM64_64K_PAGES 1598 default "11" if ARM64_16K_PAGES 1599 default "10" 1600 help 1601 The kernel page allocator limits the size of maximal physically 1602 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1603 defines the maximal power of two of number of pages that can be 1604 allocated as a single contiguous block. This option allows 1605 overriding the default setting when ability to allocate very 1606 large blocks of physically contiguous memory is required. 1607 1608 The maximal size of allocation cannot exceed the size of the 1609 section, so the value of MAX_PAGE_ORDER should satisfy 1610 1611 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1612 1613 Don't change if unsure. 1614 1615config UNMAP_KERNEL_AT_EL0 1616 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1617 default y 1618 help 1619 Speculation attacks against some high-performance processors can 1620 be used to bypass MMU permission checks and leak kernel data to 1621 userspace. This can be defended against by unmapping the kernel 1622 when running in userspace, mapping it back in on exception entry 1623 via a trampoline page in the vector table. 1624 1625 If unsure, say Y. 1626 1627config MITIGATE_SPECTRE_BRANCH_HISTORY 1628 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1629 default y 1630 help 1631 Speculation attacks against some high-performance processors can 1632 make use of branch history to influence future speculation. 1633 When taking an exception from user-space, a sequence of branches 1634 or a firmware call overwrites the branch history. 1635 1636config RODATA_FULL_DEFAULT_ENABLED 1637 bool "Apply r/o permissions of VM areas also to their linear aliases" 1638 default y 1639 help 1640 Apply read-only attributes of VM areas to the linear alias of 1641 the backing pages as well. This prevents code or read-only data 1642 from being modified (inadvertently or intentionally) via another 1643 mapping of the same memory page. This additional enhancement can 1644 be turned off at runtime by passing rodata=[off|on] (and turned on 1645 with rodata=full if this option is set to 'n') 1646 1647 This requires the linear region to be mapped down to pages, 1648 which may adversely affect performance in some cases. 1649 1650config ARM64_SW_TTBR0_PAN 1651 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1652 depends on !KCSAN 1653 help 1654 Enabling this option prevents the kernel from accessing 1655 user-space memory directly by pointing TTBR0_EL1 to a reserved 1656 zeroed area and reserved ASID. The user access routines 1657 restore the valid TTBR0_EL1 temporarily. 1658 1659config ARM64_TAGGED_ADDR_ABI 1660 bool "Enable the tagged user addresses syscall ABI" 1661 default y 1662 help 1663 When this option is enabled, user applications can opt in to a 1664 relaxed ABI via prctl() allowing tagged addresses to be passed 1665 to system calls as pointer arguments. For details, see 1666 Documentation/arch/arm64/tagged-address-abi.rst. 1667 1668menuconfig COMPAT 1669 bool "Kernel support for 32-bit EL0" 1670 depends on ARM64_4K_PAGES || EXPERT 1671 select HAVE_UID16 1672 select OLD_SIGSUSPEND3 1673 select COMPAT_OLD_SIGACTION 1674 help 1675 This option enables support for a 32-bit EL0 running under a 64-bit 1676 kernel at EL1. AArch32-specific components such as system calls, 1677 the user helper functions, VFP support and the ptrace interface are 1678 handled appropriately by the kernel. 1679 1680 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1681 that you will only be able to execute AArch32 binaries that were compiled 1682 with page size aligned segments. 1683 1684 If you want to execute 32-bit userspace applications, say Y. 1685 1686if COMPAT 1687 1688config KUSER_HELPERS 1689 bool "Enable kuser helpers page for 32-bit applications" 1690 default y 1691 help 1692 Warning: disabling this option may break 32-bit user programs. 1693 1694 Provide kuser helpers to compat tasks. The kernel provides 1695 helper code to userspace in read only form at a fixed location 1696 to allow userspace to be independent of the CPU type fitted to 1697 the system. This permits binaries to be run on ARMv4 through 1698 to ARMv8 without modification. 1699 1700 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1701 1702 However, the fixed address nature of these helpers can be used 1703 by ROP (return orientated programming) authors when creating 1704 exploits. 1705 1706 If all of the binaries and libraries which run on your platform 1707 are built specifically for your platform, and make no use of 1708 these helpers, then you can turn this option off to hinder 1709 such exploits. However, in that case, if a binary or library 1710 relying on those helpers is run, it will not function correctly. 1711 1712 Say N here only if you are absolutely certain that you do not 1713 need these helpers; otherwise, the safe option is to say Y. 1714 1715config COMPAT_VDSO 1716 bool "Enable vDSO for 32-bit applications" 1717 depends on !CPU_BIG_ENDIAN 1718 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1719 select GENERIC_COMPAT_VDSO 1720 default y 1721 help 1722 Place in the process address space of 32-bit applications an 1723 ELF shared object providing fast implementations of gettimeofday 1724 and clock_gettime. 1725 1726 You must have a 32-bit build of glibc 2.22 or later for programs 1727 to seamlessly take advantage of this. 1728 1729config THUMB2_COMPAT_VDSO 1730 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1731 depends on COMPAT_VDSO 1732 default y 1733 help 1734 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1735 otherwise with '-marm'. 1736 1737config COMPAT_ALIGNMENT_FIXUPS 1738 bool "Fix up misaligned multi-word loads and stores in user space" 1739 1740menuconfig ARMV8_DEPRECATED 1741 bool "Emulate deprecated/obsolete ARMv8 instructions" 1742 depends on SYSCTL 1743 help 1744 Legacy software support may require certain instructions 1745 that have been deprecated or obsoleted in the architecture. 1746 1747 Enable this config to enable selective emulation of these 1748 features. 1749 1750 If unsure, say Y 1751 1752if ARMV8_DEPRECATED 1753 1754config SWP_EMULATION 1755 bool "Emulate SWP/SWPB instructions" 1756 help 1757 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1758 they are always undefined. Say Y here to enable software 1759 emulation of these instructions for userspace using LDXR/STXR. 1760 This feature can be controlled at runtime with the abi.swp 1761 sysctl which is disabled by default. 1762 1763 In some older versions of glibc [<=2.8] SWP is used during futex 1764 trylock() operations with the assumption that the code will not 1765 be preempted. This invalid assumption may be more likely to fail 1766 with SWP emulation enabled, leading to deadlock of the user 1767 application. 1768 1769 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1770 on an external transaction monitoring block called a global 1771 monitor to maintain update atomicity. If your system does not 1772 implement a global monitor, this option can cause programs that 1773 perform SWP operations to uncached memory to deadlock. 1774 1775 If unsure, say Y 1776 1777config CP15_BARRIER_EMULATION 1778 bool "Emulate CP15 Barrier instructions" 1779 help 1780 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1781 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1782 strongly recommended to use the ISB, DSB, and DMB 1783 instructions instead. 1784 1785 Say Y here to enable software emulation of these 1786 instructions for AArch32 userspace code. When this option is 1787 enabled, CP15 barrier usage is traced which can help 1788 identify software that needs updating. This feature can be 1789 controlled at runtime with the abi.cp15_barrier sysctl. 1790 1791 If unsure, say Y 1792 1793config SETEND_EMULATION 1794 bool "Emulate SETEND instruction" 1795 help 1796 The SETEND instruction alters the data-endianness of the 1797 AArch32 EL0, and is deprecated in ARMv8. 1798 1799 Say Y here to enable software emulation of the instruction 1800 for AArch32 userspace code. This feature can be controlled 1801 at runtime with the abi.setend sysctl. 1802 1803 Note: All the cpus on the system must have mixed endian support at EL0 1804 for this feature to be enabled. If a new CPU - which doesn't support mixed 1805 endian - is hotplugged in after this feature has been enabled, there could 1806 be unexpected results in the applications. 1807 1808 If unsure, say Y 1809endif # ARMV8_DEPRECATED 1810 1811endif # COMPAT 1812 1813menu "ARMv8.1 architectural features" 1814 1815config ARM64_HW_AFDBM 1816 bool "Support for hardware updates of the Access and Dirty page flags" 1817 default y 1818 help 1819 The ARMv8.1 architecture extensions introduce support for 1820 hardware updates of the access and dirty information in page 1821 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1822 capable processors, accesses to pages with PTE_AF cleared will 1823 set this bit instead of raising an access flag fault. 1824 Similarly, writes to read-only pages with the DBM bit set will 1825 clear the read-only bit (AP[2]) instead of raising a 1826 permission fault. 1827 1828 Kernels built with this configuration option enabled continue 1829 to work on pre-ARMv8.1 hardware and the performance impact is 1830 minimal. If unsure, say Y. 1831 1832config ARM64_PAN 1833 bool "Enable support for Privileged Access Never (PAN)" 1834 default y 1835 help 1836 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1837 prevents the kernel or hypervisor from accessing user-space (EL0) 1838 memory directly. 1839 1840 Choosing this option will cause any unprotected (not using 1841 copy_to_user et al) memory access to fail with a permission fault. 1842 1843 The feature is detected at runtime, and will remain as a 'nop' 1844 instruction if the cpu does not implement the feature. 1845 1846config AS_HAS_LSE_ATOMICS 1847 def_bool $(as-instr,.arch_extension lse) 1848 1849config ARM64_LSE_ATOMICS 1850 bool 1851 default ARM64_USE_LSE_ATOMICS 1852 depends on AS_HAS_LSE_ATOMICS 1853 1854config ARM64_USE_LSE_ATOMICS 1855 bool "Atomic instructions" 1856 default y 1857 help 1858 As part of the Large System Extensions, ARMv8.1 introduces new 1859 atomic instructions that are designed specifically to scale in 1860 very large systems. 1861 1862 Say Y here to make use of these instructions for the in-kernel 1863 atomic routines. This incurs a small overhead on CPUs that do 1864 not support these instructions and requires the kernel to be 1865 built with binutils >= 2.25 in order for the new instructions 1866 to be used. 1867 1868endmenu # "ARMv8.1 architectural features" 1869 1870menu "ARMv8.2 architectural features" 1871 1872config AS_HAS_ARMV8_2 1873 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1874 1875config AS_HAS_SHA3 1876 def_bool $(as-instr,.arch armv8.2-a+sha3) 1877 1878config ARM64_PMEM 1879 bool "Enable support for persistent memory" 1880 select ARCH_HAS_PMEM_API 1881 select ARCH_HAS_UACCESS_FLUSHCACHE 1882 help 1883 Say Y to enable support for the persistent memory API based on the 1884 ARMv8.2 DCPoP feature. 1885 1886 The feature is detected at runtime, and the kernel will use DC CVAC 1887 operations if DC CVAP is not supported (following the behaviour of 1888 DC CVAP itself if the system does not define a point of persistence). 1889 1890config ARM64_RAS_EXTN 1891 bool "Enable support for RAS CPU Extensions" 1892 default y 1893 help 1894 CPUs that support the Reliability, Availability and Serviceability 1895 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1896 errors, classify them and report them to software. 1897 1898 On CPUs with these extensions system software can use additional 1899 barriers to determine if faults are pending and read the 1900 classification from a new set of registers. 1901 1902 Selecting this feature will allow the kernel to use these barriers 1903 and access the new registers if the system supports the extension. 1904 Platform RAS features may additionally depend on firmware support. 1905 1906config ARM64_CNP 1907 bool "Enable support for Common Not Private (CNP) translations" 1908 default y 1909 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1910 help 1911 Common Not Private (CNP) allows translation table entries to 1912 be shared between different PEs in the same inner shareable 1913 domain, so the hardware can use this fact to optimise the 1914 caching of such entries in the TLB. 1915 1916 Selecting this option allows the CNP feature to be detected 1917 at runtime, and does not affect PEs that do not implement 1918 this feature. 1919 1920endmenu # "ARMv8.2 architectural features" 1921 1922menu "ARMv8.3 architectural features" 1923 1924config ARM64_PTR_AUTH 1925 bool "Enable support for pointer authentication" 1926 default y 1927 help 1928 Pointer authentication (part of the ARMv8.3 Extensions) provides 1929 instructions for signing and authenticating pointers against secret 1930 keys, which can be used to mitigate Return Oriented Programming (ROP) 1931 and other attacks. 1932 1933 This option enables these instructions at EL0 (i.e. for userspace). 1934 Choosing this option will cause the kernel to initialise secret keys 1935 for each process at exec() time, with these keys being 1936 context-switched along with the process. 1937 1938 The feature is detected at runtime. If the feature is not present in 1939 hardware it will not be advertised to userspace/KVM guest nor will it 1940 be enabled. 1941 1942 If the feature is present on the boot CPU but not on a late CPU, then 1943 the late CPU will be parked. Also, if the boot CPU does not have 1944 address auth and the late CPU has then the late CPU will still boot 1945 but with the feature disabled. On such a system, this option should 1946 not be selected. 1947 1948config ARM64_PTR_AUTH_KERNEL 1949 bool "Use pointer authentication for kernel" 1950 default y 1951 depends on ARM64_PTR_AUTH 1952 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1953 # Modern compilers insert a .note.gnu.property section note for PAC 1954 # which is only understood by binutils starting with version 2.33.1. 1955 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1956 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1957 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1958 help 1959 If the compiler supports the -mbranch-protection or 1960 -msign-return-address flag (e.g. GCC 7 or later), then this option 1961 will cause the kernel itself to be compiled with return address 1962 protection. In this case, and if the target hardware is known to 1963 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1964 disabled with minimal loss of protection. 1965 1966 This feature works with FUNCTION_GRAPH_TRACER option only if 1967 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1968 1969config CC_HAS_BRANCH_PROT_PAC_RET 1970 # GCC 9 or later, clang 8 or later 1971 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1972 1973config CC_HAS_SIGN_RETURN_ADDRESS 1974 # GCC 7, 8 1975 def_bool $(cc-option,-msign-return-address=all) 1976 1977config AS_HAS_ARMV8_3 1978 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1979 1980config AS_HAS_CFI_NEGATE_RA_STATE 1981 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1982 1983config AS_HAS_LDAPR 1984 def_bool $(as-instr,.arch_extension rcpc) 1985 1986endmenu # "ARMv8.3 architectural features" 1987 1988menu "ARMv8.4 architectural features" 1989 1990config ARM64_AMU_EXTN 1991 bool "Enable support for the Activity Monitors Unit CPU extension" 1992 default y 1993 help 1994 The activity monitors extension is an optional extension introduced 1995 by the ARMv8.4 CPU architecture. This enables support for version 1 1996 of the activity monitors architecture, AMUv1. 1997 1998 To enable the use of this extension on CPUs that implement it, say Y. 1999 2000 Note that for architectural reasons, firmware _must_ implement AMU 2001 support when running on CPUs that present the activity monitors 2002 extension. The required support is present in: 2003 * Version 1.5 and later of the ARM Trusted Firmware 2004 2005 For kernels that have this configuration enabled but boot with broken 2006 firmware, you may need to say N here until the firmware is fixed. 2007 Otherwise you may experience firmware panics or lockups when 2008 accessing the counter registers. Even if you are not observing these 2009 symptoms, the values returned by the register reads might not 2010 correctly reflect reality. Most commonly, the value read will be 0, 2011 indicating that the counter is not enabled. 2012 2013config AS_HAS_ARMV8_4 2014 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2015 2016config ARM64_TLB_RANGE 2017 bool "Enable support for tlbi range feature" 2018 default y 2019 depends on AS_HAS_ARMV8_4 2020 help 2021 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2022 range of input addresses. 2023 2024 The feature introduces new assembly instructions, and they were 2025 support when binutils >= 2.30. 2026 2027endmenu # "ARMv8.4 architectural features" 2028 2029menu "ARMv8.5 architectural features" 2030 2031config AS_HAS_ARMV8_5 2032 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2033 2034config ARM64_BTI 2035 bool "Branch Target Identification support" 2036 default y 2037 help 2038 Branch Target Identification (part of the ARMv8.5 Extensions) 2039 provides a mechanism to limit the set of locations to which computed 2040 branch instructions such as BR or BLR can jump. 2041 2042 To make use of BTI on CPUs that support it, say Y. 2043 2044 BTI is intended to provide complementary protection to other control 2045 flow integrity protection mechanisms, such as the Pointer 2046 authentication mechanism provided as part of the ARMv8.3 Extensions. 2047 For this reason, it does not make sense to enable this option without 2048 also enabling support for pointer authentication. Thus, when 2049 enabling this option you should also select ARM64_PTR_AUTH=y. 2050 2051 Userspace binaries must also be specifically compiled to make use of 2052 this mechanism. If you say N here or the hardware does not support 2053 BTI, such binaries can still run, but you get no additional 2054 enforcement of branch destinations. 2055 2056config ARM64_BTI_KERNEL 2057 bool "Use Branch Target Identification for kernel" 2058 default y 2059 depends on ARM64_BTI 2060 depends on ARM64_PTR_AUTH_KERNEL 2061 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2062 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2063 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2064 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2065 depends on !CC_IS_GCC 2066 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2067 help 2068 Build the kernel with Branch Target Identification annotations 2069 and enable enforcement of this for kernel code. When this option 2070 is enabled and the system supports BTI all kernel code including 2071 modular code must have BTI enabled. 2072 2073config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2074 # GCC 9 or later, clang 8 or later 2075 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2076 2077config ARM64_E0PD 2078 bool "Enable support for E0PD" 2079 default y 2080 help 2081 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2082 that EL0 accesses made via TTBR1 always fault in constant time, 2083 providing similar benefits to KASLR as those provided by KPTI, but 2084 with lower overhead and without disrupting legitimate access to 2085 kernel memory such as SPE. 2086 2087 This option enables E0PD for TTBR1 where available. 2088 2089config ARM64_AS_HAS_MTE 2090 # Initial support for MTE went in binutils 2.32.0, checked with 2091 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2092 # as a late addition to the final architecture spec (LDGM/STGM) 2093 # is only supported in the newer 2.32.x and 2.33 binutils 2094 # versions, hence the extra "stgm" instruction check below. 2095 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2096 2097config ARM64_MTE 2098 bool "Memory Tagging Extension support" 2099 default y 2100 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2101 depends on AS_HAS_ARMV8_5 2102 depends on AS_HAS_LSE_ATOMICS 2103 # Required for tag checking in the uaccess routines 2104 depends on ARM64_PAN 2105 select ARCH_HAS_SUBPAGE_FAULTS 2106 select ARCH_USES_HIGH_VMA_FLAGS 2107 select ARCH_USES_PG_ARCH_X 2108 help 2109 Memory Tagging (part of the ARMv8.5 Extensions) provides 2110 architectural support for run-time, always-on detection of 2111 various classes of memory error to aid with software debugging 2112 to eliminate vulnerabilities arising from memory-unsafe 2113 languages. 2114 2115 This option enables the support for the Memory Tagging 2116 Extension at EL0 (i.e. for userspace). 2117 2118 Selecting this option allows the feature to be detected at 2119 runtime. Any secondary CPU not implementing this feature will 2120 not be allowed a late bring-up. 2121 2122 Userspace binaries that want to use this feature must 2123 explicitly opt in. The mechanism for the userspace is 2124 described in: 2125 2126 Documentation/arch/arm64/memory-tagging-extension.rst. 2127 2128endmenu # "ARMv8.5 architectural features" 2129 2130menu "ARMv8.7 architectural features" 2131 2132config ARM64_EPAN 2133 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2134 default y 2135 depends on ARM64_PAN 2136 help 2137 Enhanced Privileged Access Never (EPAN) allows Privileged 2138 Access Never to be used with Execute-only mappings. 2139 2140 The feature is detected at runtime, and will remain disabled 2141 if the cpu does not implement the feature. 2142endmenu # "ARMv8.7 architectural features" 2143 2144config ARM64_SVE 2145 bool "ARM Scalable Vector Extension support" 2146 default y 2147 help 2148 The Scalable Vector Extension (SVE) is an extension to the AArch64 2149 execution state which complements and extends the SIMD functionality 2150 of the base architecture to support much larger vectors and to enable 2151 additional vectorisation opportunities. 2152 2153 To enable use of this extension on CPUs that implement it, say Y. 2154 2155 On CPUs that support the SVE2 extensions, this option will enable 2156 those too. 2157 2158 Note that for architectural reasons, firmware _must_ implement SVE 2159 support when running on SVE capable hardware. The required support 2160 is present in: 2161 2162 * version 1.5 and later of the ARM Trusted Firmware 2163 * the AArch64 boot wrapper since commit 5e1261e08abf 2164 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2165 2166 For other firmware implementations, consult the firmware documentation 2167 or vendor. 2168 2169 If you need the kernel to boot on SVE-capable hardware with broken 2170 firmware, you may need to say N here until you get your firmware 2171 fixed. Otherwise, you may experience firmware panics or lockups when 2172 booting the kernel. If unsure and you are not observing these 2173 symptoms, you should assume that it is safe to say Y. 2174 2175config ARM64_SME 2176 bool "ARM Scalable Matrix Extension support" 2177 default y 2178 depends on ARM64_SVE 2179 help 2180 The Scalable Matrix Extension (SME) is an extension to the AArch64 2181 execution state which utilises a substantial subset of the SVE 2182 instruction set, together with the addition of new architectural 2183 register state capable of holding two dimensional matrix tiles to 2184 enable various matrix operations. 2185 2186config ARM64_PSEUDO_NMI 2187 bool "Support for NMI-like interrupts" 2188 select ARM_GIC_V3 2189 help 2190 Adds support for mimicking Non-Maskable Interrupts through the use of 2191 GIC interrupt priority. This support requires version 3 or later of 2192 ARM GIC. 2193 2194 This high priority configuration for interrupts needs to be 2195 explicitly enabled by setting the kernel parameter 2196 "irqchip.gicv3_pseudo_nmi" to 1. 2197 2198 If unsure, say N 2199 2200if ARM64_PSEUDO_NMI 2201config ARM64_DEBUG_PRIORITY_MASKING 2202 bool "Debug interrupt priority masking" 2203 help 2204 This adds runtime checks to functions enabling/disabling 2205 interrupts when using priority masking. The additional checks verify 2206 the validity of ICC_PMR_EL1 when calling concerned functions. 2207 2208 If unsure, say N 2209endif # ARM64_PSEUDO_NMI 2210 2211config RELOCATABLE 2212 bool "Build a relocatable kernel image" if EXPERT 2213 select ARCH_HAS_RELR 2214 default y 2215 help 2216 This builds the kernel as a Position Independent Executable (PIE), 2217 which retains all relocation metadata required to relocate the 2218 kernel binary at runtime to a different virtual address than the 2219 address it was linked at. 2220 Since AArch64 uses the RELA relocation format, this requires a 2221 relocation pass at runtime even if the kernel is loaded at the 2222 same address it was linked at. 2223 2224config RANDOMIZE_BASE 2225 bool "Randomize the address of the kernel image" 2226 select RELOCATABLE 2227 help 2228 Randomizes the virtual address at which the kernel image is 2229 loaded, as a security feature that deters exploit attempts 2230 relying on knowledge of the location of kernel internals. 2231 2232 It is the bootloader's job to provide entropy, by passing a 2233 random u64 value in /chosen/kaslr-seed at kernel entry. 2234 2235 When booting via the UEFI stub, it will invoke the firmware's 2236 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2237 to the kernel proper. In addition, it will randomise the physical 2238 location of the kernel Image as well. 2239 2240 If unsure, say N. 2241 2242config RANDOMIZE_MODULE_REGION_FULL 2243 bool "Randomize the module region over a 2 GB range" 2244 depends on RANDOMIZE_BASE 2245 default y 2246 help 2247 Randomizes the location of the module region inside a 2 GB window 2248 covering the core kernel. This way, it is less likely for modules 2249 to leak information about the location of core kernel data structures 2250 but it does imply that function calls between modules and the core 2251 kernel will need to be resolved via veneers in the module PLT. 2252 2253 When this option is not set, the module region will be randomized over 2254 a limited range that contains the [_stext, _etext] interval of the 2255 core kernel, so branch relocations are almost always in range unless 2256 the region is exhausted. In this particular case of region 2257 exhaustion, modules might be able to fall back to a larger 2GB area. 2258 2259config CC_HAVE_STACKPROTECTOR_SYSREG 2260 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2261 2262config STACKPROTECTOR_PER_TASK 2263 def_bool y 2264 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2265 2266config UNWIND_PATCH_PAC_INTO_SCS 2267 bool "Enable shadow call stack dynamically using code patching" 2268 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2269 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2270 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2271 depends on SHADOW_CALL_STACK 2272 select UNWIND_TABLES 2273 select DYNAMIC_SCS 2274 2275config ARM64_CONTPTE 2276 bool "Contiguous PTE mappings for user memory" if EXPERT 2277 depends on TRANSPARENT_HUGEPAGE 2278 default y 2279 help 2280 When enabled, user mappings are configured using the PTE contiguous 2281 bit, for any mappings that meet the size and alignment requirements. 2282 This reduces TLB pressure and improves performance. 2283 2284endmenu # "Kernel Features" 2285 2286menu "Boot options" 2287 2288config ARM64_ACPI_PARKING_PROTOCOL 2289 bool "Enable support for the ARM64 ACPI parking protocol" 2290 depends on ACPI 2291 help 2292 Enable support for the ARM64 ACPI parking protocol. If disabled 2293 the kernel will not allow booting through the ARM64 ACPI parking 2294 protocol even if the corresponding data is present in the ACPI 2295 MADT table. 2296 2297config CMDLINE 2298 string "Default kernel command string" 2299 default "" 2300 help 2301 Provide a set of default command-line options at build time by 2302 entering them here. As a minimum, you should specify the the 2303 root device (e.g. root=/dev/nfs). 2304 2305choice 2306 prompt "Kernel command line type" if CMDLINE != "" 2307 default CMDLINE_FROM_BOOTLOADER 2308 help 2309 Choose how the kernel will handle the provided default kernel 2310 command line string. 2311 2312config CMDLINE_FROM_BOOTLOADER 2313 bool "Use bootloader kernel arguments if available" 2314 help 2315 Uses the command-line options passed by the boot loader. If 2316 the boot loader doesn't provide any, the default kernel command 2317 string provided in CMDLINE will be used. 2318 2319config CMDLINE_FORCE 2320 bool "Always use the default kernel command string" 2321 help 2322 Always use the default kernel command string, even if the boot 2323 loader passes other arguments to the kernel. 2324 This is useful if you cannot or don't want to change the 2325 command-line options your boot loader passes to the kernel. 2326 2327endchoice 2328 2329config EFI_STUB 2330 bool 2331 2332config EFI 2333 bool "UEFI runtime support" 2334 depends on OF && !CPU_BIG_ENDIAN 2335 depends on KERNEL_MODE_NEON 2336 select ARCH_SUPPORTS_ACPI 2337 select LIBFDT 2338 select UCS2_STRING 2339 select EFI_PARAMS_FROM_FDT 2340 select EFI_RUNTIME_WRAPPERS 2341 select EFI_STUB 2342 select EFI_GENERIC_STUB 2343 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2344 default y 2345 help 2346 This option provides support for runtime services provided 2347 by UEFI firmware (such as non-volatile variables, realtime 2348 clock, and platform reset). A UEFI stub is also provided to 2349 allow the kernel to be booted as an EFI application. This 2350 is only useful on systems that have UEFI firmware. 2351 2352config DMI 2353 bool "Enable support for SMBIOS (DMI) tables" 2354 depends on EFI 2355 default y 2356 help 2357 This enables SMBIOS/DMI feature for systems. 2358 2359 This option is only useful on systems that have UEFI firmware. 2360 However, even with this option, the resultant kernel should 2361 continue to boot on existing non-UEFI platforms. 2362 2363endmenu # "Boot options" 2364 2365menu "Power management options" 2366 2367source "kernel/power/Kconfig" 2368 2369config ARCH_HIBERNATION_POSSIBLE 2370 def_bool y 2371 depends on CPU_PM 2372 2373config ARCH_HIBERNATION_HEADER 2374 def_bool y 2375 depends on HIBERNATION 2376 2377config ARCH_SUSPEND_POSSIBLE 2378 def_bool y 2379 2380endmenu # "Power management options" 2381 2382menu "CPU Power Management" 2383 2384source "drivers/cpuidle/Kconfig" 2385 2386source "drivers/cpufreq/Kconfig" 2387 2388endmenu # "CPU Power Management" 2389 2390source "drivers/acpi/Kconfig" 2391 2392source "arch/arm64/kvm/Kconfig" 2393 2394