1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 18 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 19 select ARCH_ENABLE_MEMORY_HOTPLUG 20 select ARCH_ENABLE_MEMORY_HOTREMOVE 21 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 22 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 23 select ARCH_HAS_CACHE_LINE_SIZE 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_MEMBARRIER_SYNC_CORE 38 select ARCH_HAS_MEM_ENCRYPT 39 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 40 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 41 select ARCH_HAS_PTE_DEVMAP 42 select ARCH_HAS_PTE_SPECIAL 43 select ARCH_HAS_HW_PTE_YOUNG 44 select ARCH_HAS_SETUP_DMA_OPS 45 select ARCH_HAS_SET_DIRECT_MAP 46 select ARCH_HAS_SET_MEMORY 47 select ARCH_STACKWALK 48 select ARCH_HAS_STRICT_KERNEL_RWX 49 select ARCH_HAS_STRICT_MODULE_RWX 50 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 51 select ARCH_HAS_SYNC_DMA_FOR_CPU 52 select ARCH_HAS_SYSCALL_WRAPPER 53 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 54 select ARCH_HAS_ZONE_DMA_SET if EXPERT 55 select ARCH_HAVE_ELF_PROT 56 select ARCH_HAVE_NMI_SAFE_CMPXCHG 57 select ARCH_HAVE_TRACE_MMIO_ACCESS 58 select ARCH_INLINE_READ_LOCK if !PREEMPTION 59 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 60 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 61 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 62 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 63 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 64 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 65 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 66 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 67 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 68 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 69 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 70 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 71 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 72 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 73 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 74 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 75 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 76 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 77 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 78 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 79 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 80 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 81 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 82 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 83 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 84 select ARCH_KEEP_MEMBLOCK 85 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 86 select ARCH_USE_CMPXCHG_LOCKREF 87 select ARCH_USE_GNU_PROPERTY 88 select ARCH_USE_MEMTEST 89 select ARCH_USE_QUEUED_RWLOCKS 90 select ARCH_USE_QUEUED_SPINLOCKS 91 select ARCH_USE_SYM_ANNOTATIONS 92 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 93 select ARCH_SUPPORTS_HUGETLBFS 94 select ARCH_SUPPORTS_MEMORY_FAILURE 95 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 96 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 97 select ARCH_SUPPORTS_LTO_CLANG_THIN 98 select ARCH_SUPPORTS_CFI_CLANG 99 select ARCH_SUPPORTS_ATOMIC_RMW 100 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 101 select ARCH_SUPPORTS_NUMA_BALANCING 102 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 103 select ARCH_SUPPORTS_PER_VMA_LOCK 104 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 105 select ARCH_SUPPORTS_RT 106 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 107 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 108 select ARCH_WANT_DEFAULT_BPF_JIT 109 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 110 select ARCH_WANT_FRAME_POINTERS 111 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 112 select ARCH_WANT_LD_ORPHAN_WARN 113 select ARCH_WANTS_EXECMEM_LATE if EXECMEM 114 select ARCH_WANTS_NO_INSTR 115 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 116 select ARCH_HAS_UBSAN 117 select ARM_AMBA 118 select ARM_ARCH_TIMER 119 select ARM_GIC 120 select AUDIT_ARCH_COMPAT_GENERIC 121 select ARM_GIC_V2M if PCI 122 select ARM_GIC_V3 123 select ARM_GIC_V3_ITS if PCI 124 select ARM_PSCI_FW 125 select BUILDTIME_TABLE_SORT 126 select CLONE_BACKWARDS 127 select COMMON_CLK 128 select CPU_PM if (SUSPEND || CPU_IDLE) 129 select CPUMASK_OFFSTACK if NR_CPUS > 256 130 select CRC32 131 select DCACHE_WORD_ACCESS 132 select DYNAMIC_FTRACE if FUNCTION_TRACER 133 select DMA_BOUNCE_UNALIGNED_KMALLOC 134 select DMA_DIRECT_REMAP 135 select EDAC_SUPPORT 136 select FRAME_POINTER 137 select FUNCTION_ALIGNMENT_4B 138 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 139 select GENERIC_ALLOCATOR 140 select GENERIC_ARCH_TOPOLOGY 141 select GENERIC_CLOCKEVENTS_BROADCAST 142 select GENERIC_CPU_AUTOPROBE 143 select GENERIC_CPU_DEVICES 144 select GENERIC_CPU_VULNERABILITIES 145 select GENERIC_EARLY_IOREMAP 146 select GENERIC_IDLE_POLL_SETUP 147 select GENERIC_IOREMAP 148 select GENERIC_IRQ_IPI 149 select GENERIC_IRQ_PROBE 150 select GENERIC_IRQ_SHOW 151 select GENERIC_IRQ_SHOW_LEVEL 152 select GENERIC_LIB_DEVMEM_IS_ALLOWED 153 select GENERIC_PCI_IOMAP 154 select GENERIC_PTDUMP 155 select GENERIC_SCHED_CLOCK 156 select GENERIC_SMP_IDLE_THREAD 157 select GENERIC_TIME_VSYSCALL 158 select GENERIC_GETTIMEOFDAY 159 select GENERIC_VDSO_TIME_NS 160 select HARDIRQS_SW_RESEND 161 select HAS_IOPORT 162 select HAVE_MOVE_PMD 163 select HAVE_MOVE_PUD 164 select HAVE_PCI 165 select HAVE_ACPI_APEI if (ACPI && EFI) 166 select HAVE_ALIGNED_STRUCT_PAGE 167 select HAVE_ARCH_AUDITSYSCALL 168 select HAVE_ARCH_BITREVERSE 169 select HAVE_ARCH_COMPILER_H 170 select HAVE_ARCH_HUGE_VMALLOC 171 select HAVE_ARCH_HUGE_VMAP 172 select HAVE_ARCH_JUMP_LABEL 173 select HAVE_ARCH_JUMP_LABEL_RELATIVE 174 select HAVE_ARCH_KASAN 175 select HAVE_ARCH_KASAN_VMALLOC 176 select HAVE_ARCH_KASAN_SW_TAGS 177 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 178 # Some instrumentation may be unsound, hence EXPERT 179 select HAVE_ARCH_KCSAN if EXPERT 180 select HAVE_ARCH_KFENCE 181 select HAVE_ARCH_KGDB 182 select HAVE_ARCH_MMAP_RND_BITS 183 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 184 select HAVE_ARCH_PREL32_RELOCATIONS 185 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 186 select HAVE_ARCH_SECCOMP_FILTER 187 select HAVE_ARCH_STACKLEAK 188 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 189 select HAVE_ARCH_TRACEHOOK 190 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 191 select HAVE_ARCH_VMAP_STACK 192 select HAVE_ARM_SMCCC 193 select HAVE_ASM_MODVERSIONS 194 select HAVE_EBPF_JIT 195 select HAVE_C_RECORDMCOUNT 196 select HAVE_CMPXCHG_DOUBLE 197 select HAVE_CMPXCHG_LOCAL 198 select HAVE_CONTEXT_TRACKING_USER 199 select HAVE_DEBUG_KMEMLEAK 200 select HAVE_DMA_CONTIGUOUS 201 select HAVE_DYNAMIC_FTRACE 202 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 203 if $(cc-option,-fpatchable-function-entry=2) 204 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 205 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 206 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 207 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 208 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 209 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 210 if DYNAMIC_FTRACE_WITH_ARGS 211 select HAVE_SAMPLE_FTRACE_DIRECT 212 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 213 select HAVE_EFFICIENT_UNALIGNED_ACCESS 214 select HAVE_GUP_FAST 215 select HAVE_FTRACE_MCOUNT_RECORD 216 select HAVE_FUNCTION_TRACER 217 select HAVE_FUNCTION_ERROR_INJECTION 218 select HAVE_FUNCTION_GRAPH_TRACER 219 select HAVE_FUNCTION_GRAPH_RETVAL 220 select HAVE_GCC_PLUGINS 221 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 222 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 223 select HAVE_HW_BREAKPOINT if PERF_EVENTS 224 select HAVE_IOREMAP_PROT 225 select HAVE_IRQ_TIME_ACCOUNTING 226 select HAVE_MOD_ARCH_SPECIFIC 227 select HAVE_NMI 228 select HAVE_PERF_EVENTS 229 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 230 select HAVE_PERF_REGS 231 select HAVE_PERF_USER_STACK_DUMP 232 select HAVE_PREEMPT_DYNAMIC_KEY 233 select HAVE_REGS_AND_STACK_ACCESS_API 234 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 235 select HAVE_FUNCTION_ARG_ACCESS_API 236 select MMU_GATHER_RCU_TABLE_FREE 237 select HAVE_RSEQ 238 select HAVE_RUST if CPU_LITTLE_ENDIAN 239 select HAVE_STACKPROTECTOR 240 select HAVE_SYSCALL_TRACEPOINTS 241 select HAVE_KPROBES 242 select HAVE_KRETPROBES 243 select HAVE_GENERIC_VDSO 244 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 245 select IRQ_DOMAIN 246 select IRQ_FORCED_THREADING 247 select KASAN_VMALLOC if KASAN 248 select LOCK_MM_AND_FIND_VMA 249 select MODULES_USE_ELF_RELA 250 select NEED_DMA_MAP_STATE 251 select NEED_SG_DMA_LENGTH 252 select OF 253 select OF_EARLY_FLATTREE 254 select PCI_DOMAINS_GENERIC if PCI 255 select PCI_ECAM if (ACPI && PCI) 256 select PCI_SYSCALL if PCI 257 select POWER_RESET 258 select POWER_SUPPLY 259 select SPARSE_IRQ 260 select SWIOTLB 261 select SYSCTL_EXCEPTION_TRACE 262 select THREAD_INFO_IN_TASK 263 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 264 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 265 select TRACE_IRQFLAGS_SUPPORT 266 select TRACE_IRQFLAGS_NMI_SUPPORT 267 select HAVE_SOFTIRQ_ON_OWN_STACK 268 select USER_STACKTRACE_SUPPORT 269 select VDSO_GETRANDOM 270 help 271 ARM 64-bit (AArch64) Linux support. 272 273config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 274 def_bool CC_IS_CLANG 275 # https://github.com/ClangBuiltLinux/linux/issues/1507 276 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 277 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 278 279config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 280 def_bool CC_IS_GCC 281 depends on $(cc-option,-fpatchable-function-entry=2) 282 select HAVE_DYNAMIC_FTRACE_WITH_ARGS 283 284config 64BIT 285 def_bool y 286 287config MMU 288 def_bool y 289 290config ARM64_CONT_PTE_SHIFT 291 int 292 default 5 if PAGE_SIZE_64KB 293 default 7 if PAGE_SIZE_16KB 294 default 4 295 296config ARM64_CONT_PMD_SHIFT 297 int 298 default 5 if PAGE_SIZE_64KB 299 default 5 if PAGE_SIZE_16KB 300 default 4 301 302config ARCH_MMAP_RND_BITS_MIN 303 default 14 if PAGE_SIZE_64KB 304 default 16 if PAGE_SIZE_16KB 305 default 18 306 307# max bits determined by the following formula: 308# VA_BITS - PAGE_SHIFT - 3 309config ARCH_MMAP_RND_BITS_MAX 310 default 19 if ARM64_VA_BITS=36 311 default 24 if ARM64_VA_BITS=39 312 default 27 if ARM64_VA_BITS=42 313 default 30 if ARM64_VA_BITS=47 314 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 315 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 316 default 33 if ARM64_VA_BITS=48 317 default 14 if ARM64_64K_PAGES 318 default 16 if ARM64_16K_PAGES 319 default 18 320 321config ARCH_MMAP_RND_COMPAT_BITS_MIN 322 default 7 if ARM64_64K_PAGES 323 default 9 if ARM64_16K_PAGES 324 default 11 325 326config ARCH_MMAP_RND_COMPAT_BITS_MAX 327 default 16 328 329config NO_IOPORT_MAP 330 def_bool y if !PCI 331 332config STACKTRACE_SUPPORT 333 def_bool y 334 335config ILLEGAL_POINTER_VALUE 336 hex 337 default 0xdead000000000000 338 339config LOCKDEP_SUPPORT 340 def_bool y 341 342config GENERIC_BUG 343 def_bool y 344 depends on BUG 345 346config GENERIC_BUG_RELATIVE_POINTERS 347 def_bool y 348 depends on GENERIC_BUG 349 350config GENERIC_HWEIGHT 351 def_bool y 352 353config GENERIC_CSUM 354 def_bool y 355 356config GENERIC_CALIBRATE_DELAY 357 def_bool y 358 359config SMP 360 def_bool y 361 362config KERNEL_MODE_NEON 363 def_bool y 364 365config FIX_EARLYCON_MEM 366 def_bool y 367 368config PGTABLE_LEVELS 369 int 370 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 371 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 372 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 373 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 374 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 375 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 376 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 377 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 378 379config ARCH_SUPPORTS_UPROBES 380 def_bool y 381 382config ARCH_PROC_KCORE_TEXT 383 def_bool y 384 385config BROKEN_GAS_INST 386 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 387 388config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 389 bool 390 # Clang's __builtin_return_address() strips the PAC since 12.0.0 391 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 392 default y if CC_IS_CLANG 393 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 394 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 395 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 396 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 397 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 398 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 399 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 400 default n 401 402config KASAN_SHADOW_OFFSET 403 hex 404 depends on KASAN_GENERIC || KASAN_SW_TAGS 405 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 406 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 407 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 408 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 409 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 410 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 411 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 412 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 413 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 414 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 415 default 0xffffffffffffffff 416 417config UNWIND_TABLES 418 bool 419 420source "arch/arm64/Kconfig.platforms" 421 422menu "Kernel Features" 423 424menu "ARM errata workarounds via the alternatives framework" 425 426config AMPERE_ERRATUM_AC03_CPU_38 427 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 428 default y 429 help 430 This option adds an alternative code sequence to work around Ampere 431 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 432 433 The affected design reports FEAT_HAFDBS as not implemented in 434 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 435 as required by the architecture. The unadvertised HAFDBS 436 implementation suffers from an additional erratum where hardware 437 A/D updates can occur after a PTE has been marked invalid. 438 439 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 440 which avoids enabling unadvertised hardware Access Flag management 441 at stage-2. 442 443 If unsure, say Y. 444 445config ARM64_WORKAROUND_CLEAN_CACHE 446 bool 447 448config ARM64_ERRATUM_826319 449 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 450 default y 451 select ARM64_WORKAROUND_CLEAN_CACHE 452 help 453 This option adds an alternative code sequence to work around ARM 454 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 455 AXI master interface and an L2 cache. 456 457 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 458 and is unable to accept a certain write via this interface, it will 459 not progress on read data presented on the read data channel and the 460 system can deadlock. 461 462 The workaround promotes data cache clean instructions to 463 data cache clean-and-invalidate. 464 Please note that this does not necessarily enable the workaround, 465 as it depends on the alternative framework, which will only patch 466 the kernel if an affected CPU is detected. 467 468 If unsure, say Y. 469 470config ARM64_ERRATUM_827319 471 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 472 default y 473 select ARM64_WORKAROUND_CLEAN_CACHE 474 help 475 This option adds an alternative code sequence to work around ARM 476 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 477 master interface and an L2 cache. 478 479 Under certain conditions this erratum can cause a clean line eviction 480 to occur at the same time as another transaction to the same address 481 on the AMBA 5 CHI interface, which can cause data corruption if the 482 interconnect reorders the two transactions. 483 484 The workaround promotes data cache clean instructions to 485 data cache clean-and-invalidate. 486 Please note that this does not necessarily enable the workaround, 487 as it depends on the alternative framework, which will only patch 488 the kernel if an affected CPU is detected. 489 490 If unsure, say Y. 491 492config ARM64_ERRATUM_824069 493 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 494 default y 495 select ARM64_WORKAROUND_CLEAN_CACHE 496 help 497 This option adds an alternative code sequence to work around ARM 498 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 499 to a coherent interconnect. 500 501 If a Cortex-A53 processor is executing a store or prefetch for 502 write instruction at the same time as a processor in another 503 cluster is executing a cache maintenance operation to the same 504 address, then this erratum might cause a clean cache line to be 505 incorrectly marked as dirty. 506 507 The workaround promotes data cache clean instructions to 508 data cache clean-and-invalidate. 509 Please note that this option does not necessarily enable the 510 workaround, as it depends on the alternative framework, which will 511 only patch the kernel if an affected CPU is detected. 512 513 If unsure, say Y. 514 515config ARM64_ERRATUM_819472 516 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 517 default y 518 select ARM64_WORKAROUND_CLEAN_CACHE 519 help 520 This option adds an alternative code sequence to work around ARM 521 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 522 present when it is connected to a coherent interconnect. 523 524 If the processor is executing a load and store exclusive sequence at 525 the same time as a processor in another cluster is executing a cache 526 maintenance operation to the same address, then this erratum might 527 cause data corruption. 528 529 The workaround promotes data cache clean instructions to 530 data cache clean-and-invalidate. 531 Please note that this does not necessarily enable the workaround, 532 as it depends on the alternative framework, which will only patch 533 the kernel if an affected CPU is detected. 534 535 If unsure, say Y. 536 537config ARM64_ERRATUM_832075 538 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 539 default y 540 help 541 This option adds an alternative code sequence to work around ARM 542 erratum 832075 on Cortex-A57 parts up to r1p2. 543 544 Affected Cortex-A57 parts might deadlock when exclusive load/store 545 instructions to Write-Back memory are mixed with Device loads. 546 547 The workaround is to promote device loads to use Load-Acquire 548 semantics. 549 Please note that this does not necessarily enable the workaround, 550 as it depends on the alternative framework, which will only patch 551 the kernel if an affected CPU is detected. 552 553 If unsure, say Y. 554 555config ARM64_ERRATUM_834220 556 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 557 depends on KVM 558 help 559 This option adds an alternative code sequence to work around ARM 560 erratum 834220 on Cortex-A57 parts up to r1p2. 561 562 Affected Cortex-A57 parts might report a Stage 2 translation 563 fault as the result of a Stage 1 fault for load crossing a 564 page boundary when there is a permission or device memory 565 alignment fault at Stage 1 and a translation fault at Stage 2. 566 567 The workaround is to verify that the Stage 1 translation 568 doesn't generate a fault before handling the Stage 2 fault. 569 Please note that this does not necessarily enable the workaround, 570 as it depends on the alternative framework, which will only patch 571 the kernel if an affected CPU is detected. 572 573 If unsure, say N. 574 575config ARM64_ERRATUM_1742098 576 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 577 depends on COMPAT 578 default y 579 help 580 This option removes the AES hwcap for aarch32 user-space to 581 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 582 583 Affected parts may corrupt the AES state if an interrupt is 584 taken between a pair of AES instructions. These instructions 585 are only present if the cryptography extensions are present. 586 All software should have a fallback implementation for CPUs 587 that don't implement the cryptography extensions. 588 589 If unsure, say Y. 590 591config ARM64_ERRATUM_845719 592 bool "Cortex-A53: 845719: a load might read incorrect data" 593 depends on COMPAT 594 default y 595 help 596 This option adds an alternative code sequence to work around ARM 597 erratum 845719 on Cortex-A53 parts up to r0p4. 598 599 When running a compat (AArch32) userspace on an affected Cortex-A53 600 part, a load at EL0 from a virtual address that matches the bottom 32 601 bits of the virtual address used by a recent load at (AArch64) EL1 602 might return incorrect data. 603 604 The workaround is to write the contextidr_el1 register on exception 605 return to a 32-bit task. 606 Please note that this does not necessarily enable the workaround, 607 as it depends on the alternative framework, which will only patch 608 the kernel if an affected CPU is detected. 609 610 If unsure, say Y. 611 612config ARM64_ERRATUM_843419 613 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 614 default y 615 help 616 This option links the kernel with '--fix-cortex-a53-843419' and 617 enables PLT support to replace certain ADRP instructions, which can 618 cause subsequent memory accesses to use an incorrect address on 619 Cortex-A53 parts up to r0p4. 620 621 If unsure, say Y. 622 623config ARM64_LD_HAS_FIX_ERRATUM_843419 624 def_bool $(ld-option,--fix-cortex-a53-843419) 625 626config ARM64_ERRATUM_1024718 627 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 628 default y 629 help 630 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 631 632 Affected Cortex-A55 cores (all revisions) could cause incorrect 633 update of the hardware dirty bit when the DBM/AP bits are updated 634 without a break-before-make. The workaround is to disable the usage 635 of hardware DBM locally on the affected cores. CPUs not affected by 636 this erratum will continue to use the feature. 637 638 If unsure, say Y. 639 640config ARM64_ERRATUM_1418040 641 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 642 default y 643 depends on COMPAT 644 help 645 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 646 errata 1188873 and 1418040. 647 648 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 649 cause register corruption when accessing the timer registers 650 from AArch32 userspace. 651 652 If unsure, say Y. 653 654config ARM64_WORKAROUND_SPECULATIVE_AT 655 bool 656 657config ARM64_ERRATUM_1165522 658 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 659 default y 660 select ARM64_WORKAROUND_SPECULATIVE_AT 661 help 662 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 663 664 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 665 corrupted TLBs by speculating an AT instruction during a guest 666 context switch. 667 668 If unsure, say Y. 669 670config ARM64_ERRATUM_1319367 671 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 672 default y 673 select ARM64_WORKAROUND_SPECULATIVE_AT 674 help 675 This option adds work arounds for ARM Cortex-A57 erratum 1319537 676 and A72 erratum 1319367 677 678 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 679 speculating an AT instruction during a guest context switch. 680 681 If unsure, say Y. 682 683config ARM64_ERRATUM_1530923 684 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 685 default y 686 select ARM64_WORKAROUND_SPECULATIVE_AT 687 help 688 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 689 690 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 691 corrupted TLBs by speculating an AT instruction during a guest 692 context switch. 693 694 If unsure, say Y. 695 696config ARM64_WORKAROUND_REPEAT_TLBI 697 bool 698 699config ARM64_ERRATUM_2441007 700 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 701 select ARM64_WORKAROUND_REPEAT_TLBI 702 help 703 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 704 705 Under very rare circumstances, affected Cortex-A55 CPUs 706 may not handle a race between a break-before-make sequence on one 707 CPU, and another CPU accessing the same page. This could allow a 708 store to a page that has been unmapped. 709 710 Work around this by adding the affected CPUs to the list that needs 711 TLB sequences to be done twice. 712 713 If unsure, say N. 714 715config ARM64_ERRATUM_1286807 716 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 717 select ARM64_WORKAROUND_REPEAT_TLBI 718 help 719 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 720 721 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 722 address for a cacheable mapping of a location is being 723 accessed by a core while another core is remapping the virtual 724 address to a new physical page using the recommended 725 break-before-make sequence, then under very rare circumstances 726 TLBI+DSB completes before a read using the translation being 727 invalidated has been observed by other observers. The 728 workaround repeats the TLBI+DSB operation. 729 730 If unsure, say N. 731 732config ARM64_ERRATUM_1463225 733 bool "Cortex-A76: Software Step might prevent interrupt recognition" 734 default y 735 help 736 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 737 738 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 739 of a system call instruction (SVC) can prevent recognition of 740 subsequent interrupts when software stepping is disabled in the 741 exception handler of the system call and either kernel debugging 742 is enabled or VHE is in use. 743 744 Work around the erratum by triggering a dummy step exception 745 when handling a system call from a task that is being stepped 746 in a VHE configuration of the kernel. 747 748 If unsure, say Y. 749 750config ARM64_ERRATUM_1542419 751 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 752 help 753 This option adds a workaround for ARM Neoverse-N1 erratum 754 1542419. 755 756 Affected Neoverse-N1 cores could execute a stale instruction when 757 modified by another CPU. The workaround depends on a firmware 758 counterpart. 759 760 Workaround the issue by hiding the DIC feature from EL0. This 761 forces user-space to perform cache maintenance. 762 763 If unsure, say N. 764 765config ARM64_ERRATUM_1508412 766 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 767 default y 768 help 769 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 770 771 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 772 of a store-exclusive or read of PAR_EL1 and a load with device or 773 non-cacheable memory attributes. The workaround depends on a firmware 774 counterpart. 775 776 KVM guests must also have the workaround implemented or they can 777 deadlock the system. 778 779 Work around the issue by inserting DMB SY barriers around PAR_EL1 780 register reads and warning KVM users. The DMB barrier is sufficient 781 to prevent a speculative PAR_EL1 read. 782 783 If unsure, say Y. 784 785config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 786 bool 787 788config ARM64_ERRATUM_2051678 789 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 790 default y 791 help 792 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 793 Affected Cortex-A510 might not respect the ordering rules for 794 hardware update of the page table's dirty bit. The workaround 795 is to not enable the feature on affected CPUs. 796 797 If unsure, say Y. 798 799config ARM64_ERRATUM_2077057 800 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 801 default y 802 help 803 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 804 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 805 expected, but a Pointer Authentication trap is taken instead. The 806 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 807 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 808 809 This can only happen when EL2 is stepping EL1. 810 811 When these conditions occur, the SPSR_EL2 value is unchanged from the 812 previous guest entry, and can be restored from the in-memory copy. 813 814 If unsure, say Y. 815 816config ARM64_ERRATUM_2658417 817 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 818 default y 819 help 820 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 821 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 822 BFMMLA or VMMLA instructions in rare circumstances when a pair of 823 A510 CPUs are using shared neon hardware. As the sharing is not 824 discoverable by the kernel, hide the BF16 HWCAP to indicate that 825 user-space should not be using these instructions. 826 827 If unsure, say Y. 828 829config ARM64_ERRATUM_2119858 830 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 831 default y 832 depends on CORESIGHT_TRBE 833 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 834 help 835 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 836 837 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 838 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 839 the event of a WRAP event. 840 841 Work around the issue by always making sure we move the TRBPTR_EL1 by 842 256 bytes before enabling the buffer and filling the first 256 bytes of 843 the buffer with ETM ignore packets upon disabling. 844 845 If unsure, say Y. 846 847config ARM64_ERRATUM_2139208 848 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 849 default y 850 depends on CORESIGHT_TRBE 851 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 852 help 853 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 854 855 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 856 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 857 the event of a WRAP event. 858 859 Work around the issue by always making sure we move the TRBPTR_EL1 by 860 256 bytes before enabling the buffer and filling the first 256 bytes of 861 the buffer with ETM ignore packets upon disabling. 862 863 If unsure, say Y. 864 865config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 866 bool 867 868config ARM64_ERRATUM_2054223 869 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 870 default y 871 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 872 help 873 Enable workaround for ARM Cortex-A710 erratum 2054223 874 875 Affected cores may fail to flush the trace data on a TSB instruction, when 876 the PE is in trace prohibited state. This will cause losing a few bytes 877 of the trace cached. 878 879 Workaround is to issue two TSB consecutively on affected cores. 880 881 If unsure, say Y. 882 883config ARM64_ERRATUM_2067961 884 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 885 default y 886 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 887 help 888 Enable workaround for ARM Neoverse-N2 erratum 2067961 889 890 Affected cores may fail to flush the trace data on a TSB instruction, when 891 the PE is in trace prohibited state. This will cause losing a few bytes 892 of the trace cached. 893 894 Workaround is to issue two TSB consecutively on affected cores. 895 896 If unsure, say Y. 897 898config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 899 bool 900 901config ARM64_ERRATUM_2253138 902 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 903 depends on CORESIGHT_TRBE 904 default y 905 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 906 help 907 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 908 909 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 910 for TRBE. Under some conditions, the TRBE might generate a write to the next 911 virtually addressed page following the last page of the TRBE address space 912 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 913 914 Work around this in the driver by always making sure that there is a 915 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 916 917 If unsure, say Y. 918 919config ARM64_ERRATUM_2224489 920 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 921 depends on CORESIGHT_TRBE 922 default y 923 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 924 help 925 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 926 927 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 928 for TRBE. Under some conditions, the TRBE might generate a write to the next 929 virtually addressed page following the last page of the TRBE address space 930 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 931 932 Work around this in the driver by always making sure that there is a 933 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 934 935 If unsure, say Y. 936 937config ARM64_ERRATUM_2441009 938 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 939 select ARM64_WORKAROUND_REPEAT_TLBI 940 help 941 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 942 943 Under very rare circumstances, affected Cortex-A510 CPUs 944 may not handle a race between a break-before-make sequence on one 945 CPU, and another CPU accessing the same page. This could allow a 946 store to a page that has been unmapped. 947 948 Work around this by adding the affected CPUs to the list that needs 949 TLB sequences to be done twice. 950 951 If unsure, say N. 952 953config ARM64_ERRATUM_2064142 954 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 955 depends on CORESIGHT_TRBE 956 default y 957 help 958 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 959 960 Affected Cortex-A510 core might fail to write into system registers after the 961 TRBE has been disabled. Under some conditions after the TRBE has been disabled 962 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 963 and TRBTRG_EL1 will be ignored and will not be effected. 964 965 Work around this in the driver by executing TSB CSYNC and DSB after collection 966 is stopped and before performing a system register write to one of the affected 967 registers. 968 969 If unsure, say Y. 970 971config ARM64_ERRATUM_2038923 972 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 973 depends on CORESIGHT_TRBE 974 default y 975 help 976 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 977 978 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 979 prohibited within the CPU. As a result, the trace buffer or trace buffer state 980 might be corrupted. This happens after TRBE buffer has been enabled by setting 981 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 982 execution changes from a context, in which trace is prohibited to one where it 983 isn't, or vice versa. In these mentioned conditions, the view of whether trace 984 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 985 the trace buffer state might be corrupted. 986 987 Work around this in the driver by preventing an inconsistent view of whether the 988 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 989 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 990 two ISB instructions if no ERET is to take place. 991 992 If unsure, say Y. 993 994config ARM64_ERRATUM_1902691 995 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 996 depends on CORESIGHT_TRBE 997 default y 998 help 999 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1000 1001 Affected Cortex-A510 core might cause trace data corruption, when being written 1002 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1003 trace data. 1004 1005 Work around this problem in the driver by just preventing TRBE initialization on 1006 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1007 on such implementations. This will cover the kernel for any firmware that doesn't 1008 do this already. 1009 1010 If unsure, say Y. 1011 1012config ARM64_ERRATUM_2457168 1013 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1014 depends on ARM64_AMU_EXTN 1015 default y 1016 help 1017 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1018 1019 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1020 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1021 incorrectly giving a significantly higher output value. 1022 1023 Work around this problem by returning 0 when reading the affected counter in 1024 key locations that results in disabling all users of this counter. This effect 1025 is the same to firmware disabling affected counters. 1026 1027 If unsure, say Y. 1028 1029config ARM64_ERRATUM_2645198 1030 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1031 default y 1032 help 1033 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1034 1035 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1036 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1037 next instruction abort caused by permission fault. 1038 1039 Only user-space does executable to non-executable permission transition via 1040 mprotect() system call. Workaround the problem by doing a break-before-make 1041 TLB invalidation, for all changes to executable user space mappings. 1042 1043 If unsure, say Y. 1044 1045config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1046 bool 1047 1048config ARM64_ERRATUM_2966298 1049 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1050 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1051 default y 1052 help 1053 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1054 1055 On an affected Cortex-A520 core, a speculatively executed unprivileged 1056 load might leak data from a privileged level via a cache side channel. 1057 1058 Work around this problem by executing a TLBI before returning to EL0. 1059 1060 If unsure, say Y. 1061 1062config ARM64_ERRATUM_3117295 1063 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1064 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1065 default y 1066 help 1067 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1068 1069 On an affected Cortex-A510 core, a speculatively executed unprivileged 1070 load might leak data from a privileged level via a cache side channel. 1071 1072 Work around this problem by executing a TLBI before returning to EL0. 1073 1074 If unsure, say Y. 1075 1076config ARM64_ERRATUM_3194386 1077 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1078 default y 1079 help 1080 This option adds the workaround for the following errata: 1081 1082 * ARM Cortex-A76 erratum 3324349 1083 * ARM Cortex-A77 erratum 3324348 1084 * ARM Cortex-A78 erratum 3324344 1085 * ARM Cortex-A78C erratum 3324346 1086 * ARM Cortex-A78C erratum 3324347 1087 * ARM Cortex-A710 erratam 3324338 1088 * ARM Cortex-A720 erratum 3456091 1089 * ARM Cortex-A725 erratum 3456106 1090 * ARM Cortex-X1 erratum 3324344 1091 * ARM Cortex-X1C erratum 3324346 1092 * ARM Cortex-X2 erratum 3324338 1093 * ARM Cortex-X3 erratum 3324335 1094 * ARM Cortex-X4 erratum 3194386 1095 * ARM Cortex-X925 erratum 3324334 1096 * ARM Neoverse-N1 erratum 3324349 1097 * ARM Neoverse N2 erratum 3324339 1098 * ARM Neoverse-V1 erratum 3324341 1099 * ARM Neoverse V2 erratum 3324336 1100 * ARM Neoverse-V3 erratum 3312417 1101 1102 On affected cores "MSR SSBS, #0" instructions may not affect 1103 subsequent speculative instructions, which may permit unexepected 1104 speculative store bypassing. 1105 1106 Work around this problem by placing a Speculation Barrier (SB) or 1107 Instruction Synchronization Barrier (ISB) after kernel changes to 1108 SSBS. The presence of the SSBS special-purpose register is hidden 1109 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1110 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1111 1112 If unsure, say Y. 1113 1114config CAVIUM_ERRATUM_22375 1115 bool "Cavium erratum 22375, 24313" 1116 default y 1117 help 1118 Enable workaround for errata 22375 and 24313. 1119 1120 This implements two gicv3-its errata workarounds for ThunderX. Both 1121 with a small impact affecting only ITS table allocation. 1122 1123 erratum 22375: only alloc 8MB table size 1124 erratum 24313: ignore memory access type 1125 1126 The fixes are in ITS initialization and basically ignore memory access 1127 type and table size provided by the TYPER and BASER registers. 1128 1129 If unsure, say Y. 1130 1131config CAVIUM_ERRATUM_23144 1132 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1133 depends on NUMA 1134 default y 1135 help 1136 ITS SYNC command hang for cross node io and collections/cpu mapping. 1137 1138 If unsure, say Y. 1139 1140config CAVIUM_ERRATUM_23154 1141 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1142 default y 1143 help 1144 The ThunderX GICv3 implementation requires a modified version for 1145 reading the IAR status to ensure data synchronization 1146 (access to icc_iar1_el1 is not sync'ed before and after). 1147 1148 It also suffers from erratum 38545 (also present on Marvell's 1149 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1150 spuriously presented to the CPU interface. 1151 1152 If unsure, say Y. 1153 1154config CAVIUM_ERRATUM_27456 1155 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1156 default y 1157 help 1158 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1159 instructions may cause the icache to become corrupted if it 1160 contains data for a non-current ASID. The fix is to 1161 invalidate the icache when changing the mm context. 1162 1163 If unsure, say Y. 1164 1165config CAVIUM_ERRATUM_30115 1166 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1167 default y 1168 help 1169 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1170 1.2, and T83 Pass 1.0, KVM guest execution may disable 1171 interrupts in host. Trapping both GICv3 group-0 and group-1 1172 accesses sidesteps the issue. 1173 1174 If unsure, say Y. 1175 1176config CAVIUM_TX2_ERRATUM_219 1177 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1178 default y 1179 help 1180 On Cavium ThunderX2, a load, store or prefetch instruction between a 1181 TTBR update and the corresponding context synchronizing operation can 1182 cause a spurious Data Abort to be delivered to any hardware thread in 1183 the CPU core. 1184 1185 Work around the issue by avoiding the problematic code sequence and 1186 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1187 trap handler performs the corresponding register access, skips the 1188 instruction and ensures context synchronization by virtue of the 1189 exception return. 1190 1191 If unsure, say Y. 1192 1193config FUJITSU_ERRATUM_010001 1194 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1195 default y 1196 help 1197 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1198 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1199 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1200 This fault occurs under a specific hardware condition when a 1201 load/store instruction performs an address translation using: 1202 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1203 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1204 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1205 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1206 1207 The workaround is to ensure these bits are clear in TCR_ELx. 1208 The workaround only affects the Fujitsu-A64FX. 1209 1210 If unsure, say Y. 1211 1212config HISILICON_ERRATUM_161600802 1213 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1214 default y 1215 help 1216 The HiSilicon Hip07 SoC uses the wrong redistributor base 1217 when issued ITS commands such as VMOVP and VMAPP, and requires 1218 a 128kB offset to be applied to the target address in this commands. 1219 1220 If unsure, say Y. 1221 1222config QCOM_FALKOR_ERRATUM_1003 1223 bool "Falkor E1003: Incorrect translation due to ASID change" 1224 default y 1225 help 1226 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1227 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1228 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1229 then only for entries in the walk cache, since the leaf translation 1230 is unchanged. Work around the erratum by invalidating the walk cache 1231 entries for the trampoline before entering the kernel proper. 1232 1233config QCOM_FALKOR_ERRATUM_1009 1234 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1235 default y 1236 select ARM64_WORKAROUND_REPEAT_TLBI 1237 help 1238 On Falkor v1, the CPU may prematurely complete a DSB following a 1239 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1240 one more time to fix the issue. 1241 1242 If unsure, say Y. 1243 1244config QCOM_QDF2400_ERRATUM_0065 1245 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1246 default y 1247 help 1248 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1249 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1250 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1251 1252 If unsure, say Y. 1253 1254config QCOM_FALKOR_ERRATUM_E1041 1255 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1256 default y 1257 help 1258 Falkor CPU may speculatively fetch instructions from an improper 1259 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1260 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1261 1262 If unsure, say Y. 1263 1264config NVIDIA_CARMEL_CNP_ERRATUM 1265 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1266 default y 1267 help 1268 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1269 invalidate shared TLB entries installed by a different core, as it would 1270 on standard ARM cores. 1271 1272 If unsure, say Y. 1273 1274config ROCKCHIP_ERRATUM_3588001 1275 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1276 default y 1277 help 1278 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1279 This means, that its sharability feature may not be used, even though it 1280 is supported by the IP itself. 1281 1282 If unsure, say Y. 1283 1284config SOCIONEXT_SYNQUACER_PREITS 1285 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1286 default y 1287 help 1288 Socionext Synquacer SoCs implement a separate h/w block to generate 1289 MSI doorbell writes with non-zero values for the device ID. 1290 1291 If unsure, say Y. 1292 1293endmenu # "ARM errata workarounds via the alternatives framework" 1294 1295choice 1296 prompt "Page size" 1297 default ARM64_4K_PAGES 1298 help 1299 Page size (translation granule) configuration. 1300 1301config ARM64_4K_PAGES 1302 bool "4KB" 1303 select HAVE_PAGE_SIZE_4KB 1304 help 1305 This feature enables 4KB pages support. 1306 1307config ARM64_16K_PAGES 1308 bool "16KB" 1309 select HAVE_PAGE_SIZE_16KB 1310 help 1311 The system will use 16KB pages support. AArch32 emulation 1312 requires applications compiled with 16K (or a multiple of 16K) 1313 aligned segments. 1314 1315config ARM64_64K_PAGES 1316 bool "64KB" 1317 select HAVE_PAGE_SIZE_64KB 1318 help 1319 This feature enables 64KB pages support (4KB by default) 1320 allowing only two levels of page tables and faster TLB 1321 look-up. AArch32 emulation requires applications compiled 1322 with 64K aligned segments. 1323 1324endchoice 1325 1326choice 1327 prompt "Virtual address space size" 1328 default ARM64_VA_BITS_52 1329 help 1330 Allows choosing one of multiple possible virtual address 1331 space sizes. The level of translation table is determined by 1332 a combination of page size and virtual address space size. 1333 1334config ARM64_VA_BITS_36 1335 bool "36-bit" if EXPERT 1336 depends on PAGE_SIZE_16KB 1337 1338config ARM64_VA_BITS_39 1339 bool "39-bit" 1340 depends on PAGE_SIZE_4KB 1341 1342config ARM64_VA_BITS_42 1343 bool "42-bit" 1344 depends on PAGE_SIZE_64KB 1345 1346config ARM64_VA_BITS_47 1347 bool "47-bit" 1348 depends on PAGE_SIZE_16KB 1349 1350config ARM64_VA_BITS_48 1351 bool "48-bit" 1352 1353config ARM64_VA_BITS_52 1354 bool "52-bit" 1355 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1356 help 1357 Enable 52-bit virtual addressing for userspace when explicitly 1358 requested via a hint to mmap(). The kernel will also use 52-bit 1359 virtual addresses for its own mappings (provided HW support for 1360 this feature is available, otherwise it reverts to 48-bit). 1361 1362 NOTE: Enabling 52-bit virtual addressing in conjunction with 1363 ARMv8.3 Pointer Authentication will result in the PAC being 1364 reduced from 7 bits to 3 bits, which may have a significant 1365 impact on its susceptibility to brute-force attacks. 1366 1367 If unsure, select 48-bit virtual addressing instead. 1368 1369endchoice 1370 1371config ARM64_FORCE_52BIT 1372 bool "Force 52-bit virtual addresses for userspace" 1373 depends on ARM64_VA_BITS_52 && EXPERT 1374 help 1375 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1376 to maintain compatibility with older software by providing 48-bit VAs 1377 unless a hint is supplied to mmap. 1378 1379 This configuration option disables the 48-bit compatibility logic, and 1380 forces all userspace addresses to be 52-bit on HW that supports it. One 1381 should only enable this configuration option for stress testing userspace 1382 memory management code. If unsure say N here. 1383 1384config ARM64_VA_BITS 1385 int 1386 default 36 if ARM64_VA_BITS_36 1387 default 39 if ARM64_VA_BITS_39 1388 default 42 if ARM64_VA_BITS_42 1389 default 47 if ARM64_VA_BITS_47 1390 default 48 if ARM64_VA_BITS_48 1391 default 52 if ARM64_VA_BITS_52 1392 1393choice 1394 prompt "Physical address space size" 1395 default ARM64_PA_BITS_48 1396 help 1397 Choose the maximum physical address range that the kernel will 1398 support. 1399 1400config ARM64_PA_BITS_48 1401 bool "48-bit" 1402 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1403 1404config ARM64_PA_BITS_52 1405 bool "52-bit" 1406 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1407 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1408 help 1409 Enable support for a 52-bit physical address space, introduced as 1410 part of the ARMv8.2-LPA extension. 1411 1412 With this enabled, the kernel will also continue to work on CPUs that 1413 do not support ARMv8.2-LPA, but with some added memory overhead (and 1414 minor performance overhead). 1415 1416endchoice 1417 1418config ARM64_PA_BITS 1419 int 1420 default 48 if ARM64_PA_BITS_48 1421 default 52 if ARM64_PA_BITS_52 1422 1423config ARM64_LPA2 1424 def_bool y 1425 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1426 1427choice 1428 prompt "Endianness" 1429 default CPU_LITTLE_ENDIAN 1430 help 1431 Select the endianness of data accesses performed by the CPU. Userspace 1432 applications will need to be compiled and linked for the endianness 1433 that is selected here. 1434 1435config CPU_BIG_ENDIAN 1436 bool "Build big-endian kernel" 1437 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1438 depends on AS_IS_GNU || AS_VERSION >= 150000 1439 help 1440 Say Y if you plan on running a kernel with a big-endian userspace. 1441 1442config CPU_LITTLE_ENDIAN 1443 bool "Build little-endian kernel" 1444 help 1445 Say Y if you plan on running a kernel with a little-endian userspace. 1446 This is usually the case for distributions targeting arm64. 1447 1448endchoice 1449 1450config SCHED_MC 1451 bool "Multi-core scheduler support" 1452 help 1453 Multi-core scheduler support improves the CPU scheduler's decision 1454 making when dealing with multi-core CPU chips at a cost of slightly 1455 increased overhead in some places. If unsure say N here. 1456 1457config SCHED_CLUSTER 1458 bool "Cluster scheduler support" 1459 help 1460 Cluster scheduler support improves the CPU scheduler's decision 1461 making when dealing with machines that have clusters of CPUs. 1462 Cluster usually means a couple of CPUs which are placed closely 1463 by sharing mid-level caches, last-level cache tags or internal 1464 busses. 1465 1466config SCHED_SMT 1467 bool "SMT scheduler support" 1468 help 1469 Improves the CPU scheduler's decision making when dealing with 1470 MultiThreading at a cost of slightly increased overhead in some 1471 places. If unsure say N here. 1472 1473config NR_CPUS 1474 int "Maximum number of CPUs (2-4096)" 1475 range 2 4096 1476 default "512" 1477 1478config HOTPLUG_CPU 1479 bool "Support for hot-pluggable CPUs" 1480 select GENERIC_IRQ_MIGRATION 1481 help 1482 Say Y here to experiment with turning CPUs off and on. CPUs 1483 can be controlled through /sys/devices/system/cpu. 1484 1485# Common NUMA Features 1486config NUMA 1487 bool "NUMA Memory Allocation and Scheduler Support" 1488 select GENERIC_ARCH_NUMA 1489 select OF_NUMA 1490 select HAVE_SETUP_PER_CPU_AREA 1491 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1492 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1493 select USE_PERCPU_NUMA_NODE_ID 1494 help 1495 Enable NUMA (Non-Uniform Memory Access) support. 1496 1497 The kernel will try to allocate memory used by a CPU on the 1498 local memory of the CPU and add some more 1499 NUMA awareness to the kernel. 1500 1501config NODES_SHIFT 1502 int "Maximum NUMA Nodes (as a power of 2)" 1503 range 1 10 1504 default "4" 1505 depends on NUMA 1506 help 1507 Specify the maximum number of NUMA Nodes available on the target 1508 system. Increases memory reserved to accommodate various tables. 1509 1510source "kernel/Kconfig.hz" 1511 1512config ARCH_SPARSEMEM_ENABLE 1513 def_bool y 1514 select SPARSEMEM_VMEMMAP_ENABLE 1515 select SPARSEMEM_VMEMMAP 1516 1517config HW_PERF_EVENTS 1518 def_bool y 1519 depends on ARM_PMU 1520 1521# Supported by clang >= 7.0 or GCC >= 12.0.0 1522config CC_HAVE_SHADOW_CALL_STACK 1523 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1524 1525config PARAVIRT 1526 bool "Enable paravirtualization code" 1527 help 1528 This changes the kernel so it can modify itself when it is run 1529 under a hypervisor, potentially improving performance significantly 1530 over full virtualization. 1531 1532config PARAVIRT_TIME_ACCOUNTING 1533 bool "Paravirtual steal time accounting" 1534 select PARAVIRT 1535 help 1536 Select this option to enable fine granularity task steal time 1537 accounting. Time spent executing other tasks in parallel with 1538 the current vCPU is discounted from the vCPU power. To account for 1539 that, there can be a small performance impact. 1540 1541 If in doubt, say N here. 1542 1543config ARCH_SUPPORTS_KEXEC 1544 def_bool PM_SLEEP_SMP 1545 1546config ARCH_SUPPORTS_KEXEC_FILE 1547 def_bool y 1548 1549config ARCH_SELECTS_KEXEC_FILE 1550 def_bool y 1551 depends on KEXEC_FILE 1552 select HAVE_IMA_KEXEC if IMA 1553 1554config ARCH_SUPPORTS_KEXEC_SIG 1555 def_bool y 1556 1557config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1558 def_bool y 1559 1560config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1561 def_bool y 1562 1563config ARCH_SUPPORTS_CRASH_DUMP 1564 def_bool y 1565 1566config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1567 def_bool CRASH_RESERVE 1568 1569config TRANS_TABLE 1570 def_bool y 1571 depends on HIBERNATION || KEXEC_CORE 1572 1573config XEN_DOM0 1574 def_bool y 1575 depends on XEN 1576 1577config XEN 1578 bool "Xen guest support on ARM64" 1579 depends on ARM64 && OF 1580 select SWIOTLB_XEN 1581 select PARAVIRT 1582 help 1583 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1584 1585# include/linux/mmzone.h requires the following to be true: 1586# 1587# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1588# 1589# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1590# 1591# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1592# ----+-------------------+--------------+----------------------+-------------------------+ 1593# 4K | 27 | 12 | 15 | 10 | 1594# 16K | 27 | 14 | 13 | 11 | 1595# 64K | 29 | 16 | 13 | 13 | 1596config ARCH_FORCE_MAX_ORDER 1597 int 1598 default "13" if ARM64_64K_PAGES 1599 default "11" if ARM64_16K_PAGES 1600 default "10" 1601 help 1602 The kernel page allocator limits the size of maximal physically 1603 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1604 defines the maximal power of two of number of pages that can be 1605 allocated as a single contiguous block. This option allows 1606 overriding the default setting when ability to allocate very 1607 large blocks of physically contiguous memory is required. 1608 1609 The maximal size of allocation cannot exceed the size of the 1610 section, so the value of MAX_PAGE_ORDER should satisfy 1611 1612 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1613 1614 Don't change if unsure. 1615 1616config UNMAP_KERNEL_AT_EL0 1617 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1618 default y 1619 help 1620 Speculation attacks against some high-performance processors can 1621 be used to bypass MMU permission checks and leak kernel data to 1622 userspace. This can be defended against by unmapping the kernel 1623 when running in userspace, mapping it back in on exception entry 1624 via a trampoline page in the vector table. 1625 1626 If unsure, say Y. 1627 1628config MITIGATE_SPECTRE_BRANCH_HISTORY 1629 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1630 default y 1631 help 1632 Speculation attacks against some high-performance processors can 1633 make use of branch history to influence future speculation. 1634 When taking an exception from user-space, a sequence of branches 1635 or a firmware call overwrites the branch history. 1636 1637config RODATA_FULL_DEFAULT_ENABLED 1638 bool "Apply r/o permissions of VM areas also to their linear aliases" 1639 default y 1640 help 1641 Apply read-only attributes of VM areas to the linear alias of 1642 the backing pages as well. This prevents code or read-only data 1643 from being modified (inadvertently or intentionally) via another 1644 mapping of the same memory page. This additional enhancement can 1645 be turned off at runtime by passing rodata=[off|on] (and turned on 1646 with rodata=full if this option is set to 'n') 1647 1648 This requires the linear region to be mapped down to pages, 1649 which may adversely affect performance in some cases. 1650 1651config ARM64_SW_TTBR0_PAN 1652 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1653 depends on !KCSAN 1654 help 1655 Enabling this option prevents the kernel from accessing 1656 user-space memory directly by pointing TTBR0_EL1 to a reserved 1657 zeroed area and reserved ASID. The user access routines 1658 restore the valid TTBR0_EL1 temporarily. 1659 1660config ARM64_TAGGED_ADDR_ABI 1661 bool "Enable the tagged user addresses syscall ABI" 1662 default y 1663 help 1664 When this option is enabled, user applications can opt in to a 1665 relaxed ABI via prctl() allowing tagged addresses to be passed 1666 to system calls as pointer arguments. For details, see 1667 Documentation/arch/arm64/tagged-address-abi.rst. 1668 1669menuconfig COMPAT 1670 bool "Kernel support for 32-bit EL0" 1671 depends on ARM64_4K_PAGES || EXPERT 1672 select HAVE_UID16 1673 select OLD_SIGSUSPEND3 1674 select COMPAT_OLD_SIGACTION 1675 help 1676 This option enables support for a 32-bit EL0 running under a 64-bit 1677 kernel at EL1. AArch32-specific components such as system calls, 1678 the user helper functions, VFP support and the ptrace interface are 1679 handled appropriately by the kernel. 1680 1681 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1682 that you will only be able to execute AArch32 binaries that were compiled 1683 with page size aligned segments. 1684 1685 If you want to execute 32-bit userspace applications, say Y. 1686 1687if COMPAT 1688 1689config KUSER_HELPERS 1690 bool "Enable kuser helpers page for 32-bit applications" 1691 default y 1692 help 1693 Warning: disabling this option may break 32-bit user programs. 1694 1695 Provide kuser helpers to compat tasks. The kernel provides 1696 helper code to userspace in read only form at a fixed location 1697 to allow userspace to be independent of the CPU type fitted to 1698 the system. This permits binaries to be run on ARMv4 through 1699 to ARMv8 without modification. 1700 1701 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1702 1703 However, the fixed address nature of these helpers can be used 1704 by ROP (return orientated programming) authors when creating 1705 exploits. 1706 1707 If all of the binaries and libraries which run on your platform 1708 are built specifically for your platform, and make no use of 1709 these helpers, then you can turn this option off to hinder 1710 such exploits. However, in that case, if a binary or library 1711 relying on those helpers is run, it will not function correctly. 1712 1713 Say N here only if you are absolutely certain that you do not 1714 need these helpers; otherwise, the safe option is to say Y. 1715 1716config COMPAT_VDSO 1717 bool "Enable vDSO for 32-bit applications" 1718 depends on !CPU_BIG_ENDIAN 1719 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1720 select GENERIC_COMPAT_VDSO 1721 default y 1722 help 1723 Place in the process address space of 32-bit applications an 1724 ELF shared object providing fast implementations of gettimeofday 1725 and clock_gettime. 1726 1727 You must have a 32-bit build of glibc 2.22 or later for programs 1728 to seamlessly take advantage of this. 1729 1730config THUMB2_COMPAT_VDSO 1731 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1732 depends on COMPAT_VDSO 1733 default y 1734 help 1735 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1736 otherwise with '-marm'. 1737 1738config COMPAT_ALIGNMENT_FIXUPS 1739 bool "Fix up misaligned multi-word loads and stores in user space" 1740 1741menuconfig ARMV8_DEPRECATED 1742 bool "Emulate deprecated/obsolete ARMv8 instructions" 1743 depends on SYSCTL 1744 help 1745 Legacy software support may require certain instructions 1746 that have been deprecated or obsoleted in the architecture. 1747 1748 Enable this config to enable selective emulation of these 1749 features. 1750 1751 If unsure, say Y 1752 1753if ARMV8_DEPRECATED 1754 1755config SWP_EMULATION 1756 bool "Emulate SWP/SWPB instructions" 1757 help 1758 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1759 they are always undefined. Say Y here to enable software 1760 emulation of these instructions for userspace using LDXR/STXR. 1761 This feature can be controlled at runtime with the abi.swp 1762 sysctl which is disabled by default. 1763 1764 In some older versions of glibc [<=2.8] SWP is used during futex 1765 trylock() operations with the assumption that the code will not 1766 be preempted. This invalid assumption may be more likely to fail 1767 with SWP emulation enabled, leading to deadlock of the user 1768 application. 1769 1770 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1771 on an external transaction monitoring block called a global 1772 monitor to maintain update atomicity. If your system does not 1773 implement a global monitor, this option can cause programs that 1774 perform SWP operations to uncached memory to deadlock. 1775 1776 If unsure, say Y 1777 1778config CP15_BARRIER_EMULATION 1779 bool "Emulate CP15 Barrier instructions" 1780 help 1781 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1782 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1783 strongly recommended to use the ISB, DSB, and DMB 1784 instructions instead. 1785 1786 Say Y here to enable software emulation of these 1787 instructions for AArch32 userspace code. When this option is 1788 enabled, CP15 barrier usage is traced which can help 1789 identify software that needs updating. This feature can be 1790 controlled at runtime with the abi.cp15_barrier sysctl. 1791 1792 If unsure, say Y 1793 1794config SETEND_EMULATION 1795 bool "Emulate SETEND instruction" 1796 help 1797 The SETEND instruction alters the data-endianness of the 1798 AArch32 EL0, and is deprecated in ARMv8. 1799 1800 Say Y here to enable software emulation of the instruction 1801 for AArch32 userspace code. This feature can be controlled 1802 at runtime with the abi.setend sysctl. 1803 1804 Note: All the cpus on the system must have mixed endian support at EL0 1805 for this feature to be enabled. If a new CPU - which doesn't support mixed 1806 endian - is hotplugged in after this feature has been enabled, there could 1807 be unexpected results in the applications. 1808 1809 If unsure, say Y 1810endif # ARMV8_DEPRECATED 1811 1812endif # COMPAT 1813 1814menu "ARMv8.1 architectural features" 1815 1816config ARM64_HW_AFDBM 1817 bool "Support for hardware updates of the Access and Dirty page flags" 1818 default y 1819 help 1820 The ARMv8.1 architecture extensions introduce support for 1821 hardware updates of the access and dirty information in page 1822 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1823 capable processors, accesses to pages with PTE_AF cleared will 1824 set this bit instead of raising an access flag fault. 1825 Similarly, writes to read-only pages with the DBM bit set will 1826 clear the read-only bit (AP[2]) instead of raising a 1827 permission fault. 1828 1829 Kernels built with this configuration option enabled continue 1830 to work on pre-ARMv8.1 hardware and the performance impact is 1831 minimal. If unsure, say Y. 1832 1833config ARM64_PAN 1834 bool "Enable support for Privileged Access Never (PAN)" 1835 default y 1836 help 1837 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1838 prevents the kernel or hypervisor from accessing user-space (EL0) 1839 memory directly. 1840 1841 Choosing this option will cause any unprotected (not using 1842 copy_to_user et al) memory access to fail with a permission fault. 1843 1844 The feature is detected at runtime, and will remain as a 'nop' 1845 instruction if the cpu does not implement the feature. 1846 1847config AS_HAS_LSE_ATOMICS 1848 def_bool $(as-instr,.arch_extension lse) 1849 1850config ARM64_LSE_ATOMICS 1851 bool 1852 default ARM64_USE_LSE_ATOMICS 1853 depends on AS_HAS_LSE_ATOMICS 1854 1855config ARM64_USE_LSE_ATOMICS 1856 bool "Atomic instructions" 1857 default y 1858 help 1859 As part of the Large System Extensions, ARMv8.1 introduces new 1860 atomic instructions that are designed specifically to scale in 1861 very large systems. 1862 1863 Say Y here to make use of these instructions for the in-kernel 1864 atomic routines. This incurs a small overhead on CPUs that do 1865 not support these instructions and requires the kernel to be 1866 built with binutils >= 2.25 in order for the new instructions 1867 to be used. 1868 1869endmenu # "ARMv8.1 architectural features" 1870 1871menu "ARMv8.2 architectural features" 1872 1873config AS_HAS_ARMV8_2 1874 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1875 1876config AS_HAS_SHA3 1877 def_bool $(as-instr,.arch armv8.2-a+sha3) 1878 1879config ARM64_PMEM 1880 bool "Enable support for persistent memory" 1881 select ARCH_HAS_PMEM_API 1882 select ARCH_HAS_UACCESS_FLUSHCACHE 1883 help 1884 Say Y to enable support for the persistent memory API based on the 1885 ARMv8.2 DCPoP feature. 1886 1887 The feature is detected at runtime, and the kernel will use DC CVAC 1888 operations if DC CVAP is not supported (following the behaviour of 1889 DC CVAP itself if the system does not define a point of persistence). 1890 1891config ARM64_RAS_EXTN 1892 bool "Enable support for RAS CPU Extensions" 1893 default y 1894 help 1895 CPUs that support the Reliability, Availability and Serviceability 1896 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1897 errors, classify them and report them to software. 1898 1899 On CPUs with these extensions system software can use additional 1900 barriers to determine if faults are pending and read the 1901 classification from a new set of registers. 1902 1903 Selecting this feature will allow the kernel to use these barriers 1904 and access the new registers if the system supports the extension. 1905 Platform RAS features may additionally depend on firmware support. 1906 1907config ARM64_CNP 1908 bool "Enable support for Common Not Private (CNP) translations" 1909 default y 1910 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1911 help 1912 Common Not Private (CNP) allows translation table entries to 1913 be shared between different PEs in the same inner shareable 1914 domain, so the hardware can use this fact to optimise the 1915 caching of such entries in the TLB. 1916 1917 Selecting this option allows the CNP feature to be detected 1918 at runtime, and does not affect PEs that do not implement 1919 this feature. 1920 1921endmenu # "ARMv8.2 architectural features" 1922 1923menu "ARMv8.3 architectural features" 1924 1925config ARM64_PTR_AUTH 1926 bool "Enable support for pointer authentication" 1927 default y 1928 help 1929 Pointer authentication (part of the ARMv8.3 Extensions) provides 1930 instructions for signing and authenticating pointers against secret 1931 keys, which can be used to mitigate Return Oriented Programming (ROP) 1932 and other attacks. 1933 1934 This option enables these instructions at EL0 (i.e. for userspace). 1935 Choosing this option will cause the kernel to initialise secret keys 1936 for each process at exec() time, with these keys being 1937 context-switched along with the process. 1938 1939 The feature is detected at runtime. If the feature is not present in 1940 hardware it will not be advertised to userspace/KVM guest nor will it 1941 be enabled. 1942 1943 If the feature is present on the boot CPU but not on a late CPU, then 1944 the late CPU will be parked. Also, if the boot CPU does not have 1945 address auth and the late CPU has then the late CPU will still boot 1946 but with the feature disabled. On such a system, this option should 1947 not be selected. 1948 1949config ARM64_PTR_AUTH_KERNEL 1950 bool "Use pointer authentication for kernel" 1951 default y 1952 depends on ARM64_PTR_AUTH 1953 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1954 # Modern compilers insert a .note.gnu.property section note for PAC 1955 # which is only understood by binutils starting with version 2.33.1. 1956 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1957 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1958 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1959 help 1960 If the compiler supports the -mbranch-protection or 1961 -msign-return-address flag (e.g. GCC 7 or later), then this option 1962 will cause the kernel itself to be compiled with return address 1963 protection. In this case, and if the target hardware is known to 1964 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1965 disabled with minimal loss of protection. 1966 1967 This feature works with FUNCTION_GRAPH_TRACER option only if 1968 DYNAMIC_FTRACE_WITH_ARGS is enabled. 1969 1970config CC_HAS_BRANCH_PROT_PAC_RET 1971 # GCC 9 or later, clang 8 or later 1972 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1973 1974config CC_HAS_SIGN_RETURN_ADDRESS 1975 # GCC 7, 8 1976 def_bool $(cc-option,-msign-return-address=all) 1977 1978config AS_HAS_ARMV8_3 1979 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1980 1981config AS_HAS_CFI_NEGATE_RA_STATE 1982 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1983 1984config AS_HAS_LDAPR 1985 def_bool $(as-instr,.arch_extension rcpc) 1986 1987endmenu # "ARMv8.3 architectural features" 1988 1989menu "ARMv8.4 architectural features" 1990 1991config ARM64_AMU_EXTN 1992 bool "Enable support for the Activity Monitors Unit CPU extension" 1993 default y 1994 help 1995 The activity monitors extension is an optional extension introduced 1996 by the ARMv8.4 CPU architecture. This enables support for version 1 1997 of the activity monitors architecture, AMUv1. 1998 1999 To enable the use of this extension on CPUs that implement it, say Y. 2000 2001 Note that for architectural reasons, firmware _must_ implement AMU 2002 support when running on CPUs that present the activity monitors 2003 extension. The required support is present in: 2004 * Version 1.5 and later of the ARM Trusted Firmware 2005 2006 For kernels that have this configuration enabled but boot with broken 2007 firmware, you may need to say N here until the firmware is fixed. 2008 Otherwise you may experience firmware panics or lockups when 2009 accessing the counter registers. Even if you are not observing these 2010 symptoms, the values returned by the register reads might not 2011 correctly reflect reality. Most commonly, the value read will be 0, 2012 indicating that the counter is not enabled. 2013 2014config AS_HAS_ARMV8_4 2015 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2016 2017config ARM64_TLB_RANGE 2018 bool "Enable support for tlbi range feature" 2019 default y 2020 depends on AS_HAS_ARMV8_4 2021 help 2022 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2023 range of input addresses. 2024 2025 The feature introduces new assembly instructions, and they were 2026 support when binutils >= 2.30. 2027 2028endmenu # "ARMv8.4 architectural features" 2029 2030menu "ARMv8.5 architectural features" 2031 2032config AS_HAS_ARMV8_5 2033 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2034 2035config ARM64_BTI 2036 bool "Branch Target Identification support" 2037 default y 2038 help 2039 Branch Target Identification (part of the ARMv8.5 Extensions) 2040 provides a mechanism to limit the set of locations to which computed 2041 branch instructions such as BR or BLR can jump. 2042 2043 To make use of BTI on CPUs that support it, say Y. 2044 2045 BTI is intended to provide complementary protection to other control 2046 flow integrity protection mechanisms, such as the Pointer 2047 authentication mechanism provided as part of the ARMv8.3 Extensions. 2048 For this reason, it does not make sense to enable this option without 2049 also enabling support for pointer authentication. Thus, when 2050 enabling this option you should also select ARM64_PTR_AUTH=y. 2051 2052 Userspace binaries must also be specifically compiled to make use of 2053 this mechanism. If you say N here or the hardware does not support 2054 BTI, such binaries can still run, but you get no additional 2055 enforcement of branch destinations. 2056 2057config ARM64_BTI_KERNEL 2058 bool "Use Branch Target Identification for kernel" 2059 default y 2060 depends on ARM64_BTI 2061 depends on ARM64_PTR_AUTH_KERNEL 2062 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2063 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2064 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2065 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2066 depends on !CC_IS_GCC 2067 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2068 help 2069 Build the kernel with Branch Target Identification annotations 2070 and enable enforcement of this for kernel code. When this option 2071 is enabled and the system supports BTI all kernel code including 2072 modular code must have BTI enabled. 2073 2074config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2075 # GCC 9 or later, clang 8 or later 2076 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2077 2078config ARM64_E0PD 2079 bool "Enable support for E0PD" 2080 default y 2081 help 2082 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2083 that EL0 accesses made via TTBR1 always fault in constant time, 2084 providing similar benefits to KASLR as those provided by KPTI, but 2085 with lower overhead and without disrupting legitimate access to 2086 kernel memory such as SPE. 2087 2088 This option enables E0PD for TTBR1 where available. 2089 2090config ARM64_AS_HAS_MTE 2091 # Initial support for MTE went in binutils 2.32.0, checked with 2092 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2093 # as a late addition to the final architecture spec (LDGM/STGM) 2094 # is only supported in the newer 2.32.x and 2.33 binutils 2095 # versions, hence the extra "stgm" instruction check below. 2096 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2097 2098config ARM64_MTE 2099 bool "Memory Tagging Extension support" 2100 default y 2101 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2102 depends on AS_HAS_ARMV8_5 2103 depends on AS_HAS_LSE_ATOMICS 2104 # Required for tag checking in the uaccess routines 2105 depends on ARM64_PAN 2106 select ARCH_HAS_SUBPAGE_FAULTS 2107 select ARCH_USES_HIGH_VMA_FLAGS 2108 select ARCH_USES_PG_ARCH_2 2109 select ARCH_USES_PG_ARCH_3 2110 help 2111 Memory Tagging (part of the ARMv8.5 Extensions) provides 2112 architectural support for run-time, always-on detection of 2113 various classes of memory error to aid with software debugging 2114 to eliminate vulnerabilities arising from memory-unsafe 2115 languages. 2116 2117 This option enables the support for the Memory Tagging 2118 Extension at EL0 (i.e. for userspace). 2119 2120 Selecting this option allows the feature to be detected at 2121 runtime. Any secondary CPU not implementing this feature will 2122 not be allowed a late bring-up. 2123 2124 Userspace binaries that want to use this feature must 2125 explicitly opt in. The mechanism for the userspace is 2126 described in: 2127 2128 Documentation/arch/arm64/memory-tagging-extension.rst. 2129 2130endmenu # "ARMv8.5 architectural features" 2131 2132menu "ARMv8.7 architectural features" 2133 2134config ARM64_EPAN 2135 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2136 default y 2137 depends on ARM64_PAN 2138 help 2139 Enhanced Privileged Access Never (EPAN) allows Privileged 2140 Access Never to be used with Execute-only mappings. 2141 2142 The feature is detected at runtime, and will remain disabled 2143 if the cpu does not implement the feature. 2144endmenu # "ARMv8.7 architectural features" 2145 2146menu "ARMv8.9 architectural features" 2147 2148config ARM64_POE 2149 prompt "Permission Overlay Extension" 2150 def_bool y 2151 select ARCH_USES_HIGH_VMA_FLAGS 2152 select ARCH_HAS_PKEYS 2153 help 2154 The Permission Overlay Extension is used to implement Memory 2155 Protection Keys. Memory Protection Keys provides a mechanism for 2156 enforcing page-based protections, but without requiring modification 2157 of the page tables when an application changes protection domains. 2158 2159 For details, see Documentation/core-api/protection-keys.rst 2160 2161 If unsure, say y. 2162 2163config ARCH_PKEY_BITS 2164 int 2165 default 3 2166 2167endmenu # "ARMv8.9 architectural features" 2168 2169config ARM64_SVE 2170 bool "ARM Scalable Vector Extension support" 2171 default y 2172 help 2173 The Scalable Vector Extension (SVE) is an extension to the AArch64 2174 execution state which complements and extends the SIMD functionality 2175 of the base architecture to support much larger vectors and to enable 2176 additional vectorisation opportunities. 2177 2178 To enable use of this extension on CPUs that implement it, say Y. 2179 2180 On CPUs that support the SVE2 extensions, this option will enable 2181 those too. 2182 2183 Note that for architectural reasons, firmware _must_ implement SVE 2184 support when running on SVE capable hardware. The required support 2185 is present in: 2186 2187 * version 1.5 and later of the ARM Trusted Firmware 2188 * the AArch64 boot wrapper since commit 5e1261e08abf 2189 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2190 2191 For other firmware implementations, consult the firmware documentation 2192 or vendor. 2193 2194 If you need the kernel to boot on SVE-capable hardware with broken 2195 firmware, you may need to say N here until you get your firmware 2196 fixed. Otherwise, you may experience firmware panics or lockups when 2197 booting the kernel. If unsure and you are not observing these 2198 symptoms, you should assume that it is safe to say Y. 2199 2200config ARM64_SME 2201 bool "ARM Scalable Matrix Extension support" 2202 default y 2203 depends on ARM64_SVE 2204 help 2205 The Scalable Matrix Extension (SME) is an extension to the AArch64 2206 execution state which utilises a substantial subset of the SVE 2207 instruction set, together with the addition of new architectural 2208 register state capable of holding two dimensional matrix tiles to 2209 enable various matrix operations. 2210 2211config ARM64_PSEUDO_NMI 2212 bool "Support for NMI-like interrupts" 2213 select ARM_GIC_V3 2214 help 2215 Adds support for mimicking Non-Maskable Interrupts through the use of 2216 GIC interrupt priority. This support requires version 3 or later of 2217 ARM GIC. 2218 2219 This high priority configuration for interrupts needs to be 2220 explicitly enabled by setting the kernel parameter 2221 "irqchip.gicv3_pseudo_nmi" to 1. 2222 2223 If unsure, say N 2224 2225if ARM64_PSEUDO_NMI 2226config ARM64_DEBUG_PRIORITY_MASKING 2227 bool "Debug interrupt priority masking" 2228 help 2229 This adds runtime checks to functions enabling/disabling 2230 interrupts when using priority masking. The additional checks verify 2231 the validity of ICC_PMR_EL1 when calling concerned functions. 2232 2233 If unsure, say N 2234endif # ARM64_PSEUDO_NMI 2235 2236config RELOCATABLE 2237 bool "Build a relocatable kernel image" if EXPERT 2238 select ARCH_HAS_RELR 2239 default y 2240 help 2241 This builds the kernel as a Position Independent Executable (PIE), 2242 which retains all relocation metadata required to relocate the 2243 kernel binary at runtime to a different virtual address than the 2244 address it was linked at. 2245 Since AArch64 uses the RELA relocation format, this requires a 2246 relocation pass at runtime even if the kernel is loaded at the 2247 same address it was linked at. 2248 2249config RANDOMIZE_BASE 2250 bool "Randomize the address of the kernel image" 2251 select RELOCATABLE 2252 help 2253 Randomizes the virtual address at which the kernel image is 2254 loaded, as a security feature that deters exploit attempts 2255 relying on knowledge of the location of kernel internals. 2256 2257 It is the bootloader's job to provide entropy, by passing a 2258 random u64 value in /chosen/kaslr-seed at kernel entry. 2259 2260 When booting via the UEFI stub, it will invoke the firmware's 2261 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2262 to the kernel proper. In addition, it will randomise the physical 2263 location of the kernel Image as well. 2264 2265 If unsure, say N. 2266 2267config RANDOMIZE_MODULE_REGION_FULL 2268 bool "Randomize the module region over a 2 GB range" 2269 depends on RANDOMIZE_BASE 2270 default y 2271 help 2272 Randomizes the location of the module region inside a 2 GB window 2273 covering the core kernel. This way, it is less likely for modules 2274 to leak information about the location of core kernel data structures 2275 but it does imply that function calls between modules and the core 2276 kernel will need to be resolved via veneers in the module PLT. 2277 2278 When this option is not set, the module region will be randomized over 2279 a limited range that contains the [_stext, _etext] interval of the 2280 core kernel, so branch relocations are almost always in range unless 2281 the region is exhausted. In this particular case of region 2282 exhaustion, modules might be able to fall back to a larger 2GB area. 2283 2284config CC_HAVE_STACKPROTECTOR_SYSREG 2285 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2286 2287config STACKPROTECTOR_PER_TASK 2288 def_bool y 2289 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2290 2291config UNWIND_PATCH_PAC_INTO_SCS 2292 bool "Enable shadow call stack dynamically using code patching" 2293 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2294 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2295 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2296 depends on SHADOW_CALL_STACK 2297 select UNWIND_TABLES 2298 select DYNAMIC_SCS 2299 2300config ARM64_CONTPTE 2301 bool "Contiguous PTE mappings for user memory" if EXPERT 2302 depends on TRANSPARENT_HUGEPAGE 2303 default y 2304 help 2305 When enabled, user mappings are configured using the PTE contiguous 2306 bit, for any mappings that meet the size and alignment requirements. 2307 This reduces TLB pressure and improves performance. 2308 2309endmenu # "Kernel Features" 2310 2311menu "Boot options" 2312 2313config ARM64_ACPI_PARKING_PROTOCOL 2314 bool "Enable support for the ARM64 ACPI parking protocol" 2315 depends on ACPI 2316 help 2317 Enable support for the ARM64 ACPI parking protocol. If disabled 2318 the kernel will not allow booting through the ARM64 ACPI parking 2319 protocol even if the corresponding data is present in the ACPI 2320 MADT table. 2321 2322config CMDLINE 2323 string "Default kernel command string" 2324 default "" 2325 help 2326 Provide a set of default command-line options at build time by 2327 entering them here. As a minimum, you should specify the the 2328 root device (e.g. root=/dev/nfs). 2329 2330choice 2331 prompt "Kernel command line type" 2332 depends on CMDLINE != "" 2333 default CMDLINE_FROM_BOOTLOADER 2334 help 2335 Choose how the kernel will handle the provided default kernel 2336 command line string. 2337 2338config CMDLINE_FROM_BOOTLOADER 2339 bool "Use bootloader kernel arguments if available" 2340 help 2341 Uses the command-line options passed by the boot loader. If 2342 the boot loader doesn't provide any, the default kernel command 2343 string provided in CMDLINE will be used. 2344 2345config CMDLINE_FORCE 2346 bool "Always use the default kernel command string" 2347 help 2348 Always use the default kernel command string, even if the boot 2349 loader passes other arguments to the kernel. 2350 This is useful if you cannot or don't want to change the 2351 command-line options your boot loader passes to the kernel. 2352 2353endchoice 2354 2355config EFI_STUB 2356 bool 2357 2358config EFI 2359 bool "UEFI runtime support" 2360 depends on OF && !CPU_BIG_ENDIAN 2361 depends on KERNEL_MODE_NEON 2362 select ARCH_SUPPORTS_ACPI 2363 select LIBFDT 2364 select UCS2_STRING 2365 select EFI_PARAMS_FROM_FDT 2366 select EFI_RUNTIME_WRAPPERS 2367 select EFI_STUB 2368 select EFI_GENERIC_STUB 2369 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2370 default y 2371 help 2372 This option provides support for runtime services provided 2373 by UEFI firmware (such as non-volatile variables, realtime 2374 clock, and platform reset). A UEFI stub is also provided to 2375 allow the kernel to be booted as an EFI application. This 2376 is only useful on systems that have UEFI firmware. 2377 2378config COMPRESSED_INSTALL 2379 bool "Install compressed image by default" 2380 help 2381 This makes the regular "make install" install the compressed 2382 image we built, not the legacy uncompressed one. 2383 2384 You can check that a compressed image works for you by doing 2385 "make zinstall" first, and verifying that everything is fine 2386 in your environment before making "make install" do this for 2387 you. 2388 2389config DMI 2390 bool "Enable support for SMBIOS (DMI) tables" 2391 depends on EFI 2392 default y 2393 help 2394 This enables SMBIOS/DMI feature for systems. 2395 2396 This option is only useful on systems that have UEFI firmware. 2397 However, even with this option, the resultant kernel should 2398 continue to boot on existing non-UEFI platforms. 2399 2400endmenu # "Boot options" 2401 2402menu "Power management options" 2403 2404source "kernel/power/Kconfig" 2405 2406config ARCH_HIBERNATION_POSSIBLE 2407 def_bool y 2408 depends on CPU_PM 2409 2410config ARCH_HIBERNATION_HEADER 2411 def_bool y 2412 depends on HIBERNATION 2413 2414config ARCH_SUSPEND_POSSIBLE 2415 def_bool y 2416 2417endmenu # "Power management options" 2418 2419menu "CPU Power Management" 2420 2421source "drivers/cpuidle/Kconfig" 2422 2423source "drivers/cpufreq/Kconfig" 2424 2425endmenu # "CPU Power Management" 2426 2427source "drivers/acpi/Kconfig" 2428 2429source "arch/arm64/kvm/Kconfig" 2430 2431