1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CC_PLATFORM 23 select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION 24 select ARCH_HAS_CURRENT_STACK_POINTER 25 select ARCH_HAS_DEBUG_VIRTUAL 26 select ARCH_HAS_DEBUG_VM_PGTABLE 27 select ARCH_HAS_DMA_OPS if XEN 28 select ARCH_HAS_DMA_PREP_COHERENT 29 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 30 select ARCH_HAS_FAST_MULTIPLIER 31 select ARCH_HAS_FORTIFY_SOURCE 32 select ARCH_HAS_GCOV_PROFILE_ALL 33 select ARCH_HAS_GIGANTIC_PAGE 34 select ARCH_HAS_KCOV 35 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 36 select ARCH_HAS_KEEPINITRD 37 select ARCH_HAS_LAZY_MMU_MODE 38 select ARCH_HAS_MEMBARRIER_SYNC_CORE 39 select ARCH_HAS_MEM_ENCRYPT 40 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PREEMPT_LAZY 45 select ARCH_HAS_PTDUMP 46 select ARCH_HAS_PTE_SPECIAL 47 select ARCH_HAS_HW_PTE_YOUNG 48 select ARCH_HAS_SETUP_DMA_OPS 49 select ARCH_HAS_SET_DIRECT_MAP 50 select ARCH_HAS_SET_MEMORY 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_BATCHED_DMA_SYNC 58 select ARCH_HAS_SYSCALL_WRAPPER 59 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 60 select ARCH_HAS_ZONE_DMA_SET if EXPERT 61 select ARCH_HAVE_ELF_PROT 62 select ARCH_HAVE_NMI_SAFE_CMPXCHG 63 select ARCH_HAVE_TRACE_MMIO_ACCESS 64 select ARCH_KEEP_MEMBLOCK 65 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 66 select ARCH_USE_CMPXCHG_LOCKREF 67 select ARCH_USE_GNU_PROPERTY 68 select ARCH_USE_MEMTEST 69 select ARCH_USE_QUEUED_RWLOCKS 70 select ARCH_USE_QUEUED_SPINLOCKS 71 select ARCH_USE_SYM_ANNOTATIONS 72 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 73 select ARCH_SUPPORTS_HUGETLBFS 74 select ARCH_SUPPORTS_MEMORY_FAILURE 75 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 76 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 77 select ARCH_SUPPORTS_LTO_CLANG_THIN 78 select ARCH_SUPPORTS_CFI 79 select ARCH_SUPPORTS_ATOMIC_RMW 80 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 81 select ARCH_SUPPORTS_NUMA_BALANCING 82 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 83 select ARCH_SUPPORTS_PER_VMA_LOCK 84 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 85 select ARCH_SUPPORTS_RT 86 select ARCH_SUPPORTS_SCHED_SMT 87 select ARCH_SUPPORTS_SCHED_CLUSTER 88 select ARCH_SUPPORTS_SCHED_MC 89 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 90 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 91 select ARCH_WANT_DEFAULT_BPF_JIT 92 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 93 select ARCH_WANT_FRAME_POINTERS 94 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 95 select ARCH_WANT_LD_ORPHAN_WARN 96 select ARCH_WANTS_EXECMEM_LATE 97 select ARCH_WANTS_NO_INSTR 98 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 99 select ARCH_HAS_UBSAN 100 select ARM_AMBA 101 select ARM_ARCH_TIMER 102 select ARM_GIC 103 select AUDIT_ARCH_COMPAT_GENERIC 104 select ARM_GIC_V2M if PCI 105 select ARM_GIC_V3 106 select ARM_GIC_V3_ITS if PCI 107 select ARM_GIC_V5 108 select ARM_PSCI_FW 109 select BUILDTIME_TABLE_SORT 110 select CLONE_BACKWARDS 111 select COMMON_CLK 112 select CPU_PM if (SUSPEND || CPU_IDLE) 113 select CPUMASK_OFFSTACK if NR_CPUS > 256 114 select DCACHE_WORD_ACCESS 115 select HAVE_EXTRA_IPI_TRACEPOINTS 116 select DYNAMIC_FTRACE if FUNCTION_TRACER 117 select DMA_BOUNCE_UNALIGNED_KMALLOC 118 select DMA_DIRECT_REMAP 119 select EDAC_SUPPORT 120 select FRAME_POINTER 121 select FUNCTION_ALIGNMENT_4B 122 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 123 select GENERIC_ALLOCATOR 124 select GENERIC_ARCH_TOPOLOGY 125 select GENERIC_CLOCKEVENTS_BROADCAST 126 select GENERIC_CPU_AUTOPROBE 127 select GENERIC_CPU_CACHE_MAINTENANCE 128 select GENERIC_CPU_DEVICES 129 select GENERIC_CPU_VULNERABILITIES 130 select GENERIC_EARLY_IOREMAP 131 select GENERIC_IDLE_POLL_SETUP 132 select GENERIC_IOREMAP 133 select GENERIC_IRQ_ENTRY 134 select GENERIC_IRQ_IPI 135 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 136 select GENERIC_IRQ_PROBE 137 select GENERIC_IRQ_SHOW 138 select GENERIC_IRQ_SHOW_LEVEL 139 select GENERIC_LIB_DEVMEM_IS_ALLOWED 140 select GENERIC_PCI_IOMAP 141 select GENERIC_SCHED_CLOCK 142 select GENERIC_SMP_IDLE_THREAD 143 select GENERIC_TIME_VSYSCALL 144 select GENERIC_GETTIMEOFDAY 145 select HARDIRQS_SW_RESEND 146 select HAS_IOPORT 147 select HAVE_MOVE_PMD 148 select HAVE_MOVE_PUD 149 select HAVE_PCI 150 select HAVE_ACPI_APEI if (ACPI && EFI) 151 select HAVE_ALIGNED_STRUCT_PAGE 152 select HAVE_ARCH_AUDITSYSCALL 153 select HAVE_ARCH_BITREVERSE 154 select HAVE_ARCH_COMPILER_H 155 select HAVE_ARCH_HUGE_VMALLOC 156 select HAVE_ARCH_HUGE_VMAP 157 select HAVE_ARCH_JUMP_LABEL 158 select HAVE_ARCH_JUMP_LABEL_RELATIVE 159 select HAVE_ARCH_KASAN 160 select HAVE_ARCH_KASAN_VMALLOC 161 select HAVE_ARCH_KASAN_SW_TAGS 162 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 163 # Some instrumentation may be unsound, hence EXPERT 164 select HAVE_ARCH_KCSAN if EXPERT 165 select HAVE_ARCH_KFENCE 166 select HAVE_ARCH_KGDB 167 select HAVE_ARCH_KSTACK_ERASE 168 select HAVE_ARCH_MMAP_RND_BITS 169 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 170 select HAVE_ARCH_PREL32_RELOCATIONS 171 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 172 select HAVE_ARCH_SECCOMP_FILTER 173 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 174 select HAVE_ARCH_TRACEHOOK 175 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 176 select HAVE_ARCH_VMAP_STACK 177 select HAVE_ARM_SMCCC 178 select HAVE_ASM_MODVERSIONS 179 select HAVE_EBPF_JIT 180 select HAVE_C_RECORDMCOUNT 181 select HAVE_CMPXCHG_DOUBLE 182 select HAVE_CMPXCHG_LOCAL 183 select HAVE_CONTEXT_TRACKING_USER 184 select HAVE_DEBUG_KMEMLEAK 185 select HAVE_DMA_CONTIGUOUS 186 select HAVE_DYNAMIC_FTRACE 187 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 188 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 189 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 190 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 191 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 192 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 193 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI && \ 194 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 195 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 196 if DYNAMIC_FTRACE_WITH_ARGS 197 select HAVE_SAMPLE_FTRACE_DIRECT 198 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 199 select HAVE_BUILDTIME_MCOUNT_SORT 200 select HAVE_EFFICIENT_UNALIGNED_ACCESS 201 select HAVE_GUP_FAST 202 select HAVE_FTRACE_GRAPH_FUNC 203 select HAVE_FUNCTION_TRACER 204 select HAVE_FUNCTION_ERROR_INJECTION 205 select HAVE_FUNCTION_GRAPH_FREGS 206 select HAVE_FUNCTION_GRAPH_TRACER 207 select HAVE_GCC_PLUGINS 208 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 209 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 210 select HAVE_HW_BREAKPOINT if PERF_EVENTS 211 select HAVE_IOREMAP_PROT 212 select HAVE_IRQ_TIME_ACCOUNTING 213 select HAVE_LIVEPATCH 214 select HAVE_MOD_ARCH_SPECIFIC 215 select HAVE_NMI 216 select HAVE_PERF_EVENTS 217 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 218 select HAVE_PERF_REGS 219 select HAVE_PERF_USER_STACK_DUMP 220 select HAVE_PREEMPT_DYNAMIC_KEY 221 select HAVE_REGS_AND_STACK_ACCESS_API 222 select HAVE_RELIABLE_STACKTRACE 223 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 224 select HAVE_FUNCTION_ARG_ACCESS_API 225 select MMU_GATHER_RCU_TABLE_FREE 226 select HAVE_RSEQ 227 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 228 select HAVE_STACKPROTECTOR 229 select HAVE_STATIC_CALL if CFI 230 select HAVE_SYSCALL_TRACEPOINTS 231 select HAVE_KPROBES 232 select HAVE_KRETPROBES 233 select HAVE_GENERIC_VDSO 234 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 235 select HOTPLUG_SMT if HOTPLUG_CPU 236 select IRQ_DOMAIN 237 select IRQ_FORCED_THREADING 238 select JUMP_LABEL 239 select KASAN_VMALLOC if KASAN 240 select LOCK_MM_AND_FIND_VMA 241 select MODULES_USE_ELF_RELA 242 select NEED_DMA_MAP_STATE 243 select NEED_SG_DMA_LENGTH 244 select OF 245 select OF_EARLY_FLATTREE 246 select PCI_DOMAINS_GENERIC if PCI 247 select PCI_ECAM if (ACPI && PCI) 248 select PCI_SYSCALL if PCI 249 select POWER_RESET 250 select POWER_SUPPLY 251 select SPARSE_IRQ 252 select SWIOTLB 253 select SYSCTL_EXCEPTION_TRACE 254 select THREAD_INFO_IN_TASK 255 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 256 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 257 select TRACE_IRQFLAGS_SUPPORT 258 select TRACE_IRQFLAGS_NMI_SUPPORT 259 select HAVE_SOFTIRQ_ON_OWN_STACK 260 select USER_STACKTRACE_SUPPORT 261 select VDSO_GETRANDOM 262 select VMAP_STACK 263 help 264 ARM 64-bit (AArch64) Linux support. 265 266config RUSTC_SUPPORTS_ARM64 267 def_bool y 268 depends on CPU_LITTLE_ENDIAN 269 270config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 271 def_bool CC_IS_CLANG 272 # https://github.com/ClangBuiltLinux/linux/issues/1507 273 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 274 275config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 276 def_bool CC_IS_GCC 277 depends on $(cc-option,-fpatchable-function-entry=2) 278 279config 64BIT 280 def_bool y 281 282config MMU 283 def_bool y 284 285config ARM64_CONT_PTE_SHIFT 286 int 287 default 5 if PAGE_SIZE_64KB 288 default 7 if PAGE_SIZE_16KB 289 default 4 290 291config ARM64_CONT_PMD_SHIFT 292 int 293 default 5 if PAGE_SIZE_64KB 294 default 5 if PAGE_SIZE_16KB 295 default 4 296 297config ARCH_MMAP_RND_BITS_MIN 298 default 14 if PAGE_SIZE_64KB 299 default 16 if PAGE_SIZE_16KB 300 default 18 301 302# max bits determined by the following formula: 303# VA_BITS - PTDESC_TABLE_SHIFT 304config ARCH_MMAP_RND_BITS_MAX 305 default 19 if ARM64_VA_BITS=36 306 default 24 if ARM64_VA_BITS=39 307 default 27 if ARM64_VA_BITS=42 308 default 30 if ARM64_VA_BITS=47 309 default 29 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_64K_PAGES 310 default 31 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) && ARM64_16K_PAGES 311 default 33 if (ARM64_VA_BITS=48 || ARM64_VA_BITS=52) 312 default 14 if ARM64_64K_PAGES 313 default 16 if ARM64_16K_PAGES 314 default 18 315 316config ARCH_MMAP_RND_COMPAT_BITS_MIN 317 default 7 if ARM64_64K_PAGES 318 default 9 if ARM64_16K_PAGES 319 default 11 320 321config ARCH_MMAP_RND_COMPAT_BITS_MAX 322 default 16 323 324config NO_IOPORT_MAP 325 def_bool y if !PCI 326 327config STACKTRACE_SUPPORT 328 def_bool y 329 330config ILLEGAL_POINTER_VALUE 331 hex 332 default 0xdead000000000000 333 334config LOCKDEP_SUPPORT 335 def_bool y 336 337config GENERIC_BUG 338 def_bool y 339 depends on BUG 340 341config GENERIC_BUG_RELATIVE_POINTERS 342 def_bool y 343 depends on GENERIC_BUG 344 345config GENERIC_HWEIGHT 346 def_bool y 347 348config GENERIC_CSUM 349 def_bool y 350 351config GENERIC_CALIBRATE_DELAY 352 def_bool y 353 354config SMP 355 def_bool y 356 357config KERNEL_MODE_NEON 358 def_bool y 359 360config FIX_EARLYCON_MEM 361 def_bool y 362 363config PGTABLE_LEVELS 364 int 365 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 366 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 367 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 368 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 369 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 370 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 371 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 372 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 373 374config ARCH_SUPPORTS_UPROBES 375 def_bool y 376 377config ARCH_PROC_KCORE_TEXT 378 def_bool y 379 380config BROKEN_GAS_INST 381 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 382 383config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 384 bool 385 # Clang's __builtin_return_address() strips the PAC since 12.0.0 386 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 387 default y if CC_IS_CLANG 388 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 389 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 390 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 391 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 392 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 393 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 394 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 395 default n 396 397config KASAN_SHADOW_OFFSET 398 hex 399 depends on KASAN_GENERIC || KASAN_SW_TAGS 400 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 401 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 402 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 403 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 404 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 405 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 406 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 407 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 408 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 409 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 410 default 0xffffffffffffffff 411 412config UNWIND_TABLES 413 bool 414 415source "arch/arm64/Kconfig.platforms" 416 417menu "Kernel Features" 418 419menu "ARM errata workarounds via the alternatives framework" 420 421config AMPERE_ERRATUM_AC03_CPU_38 422 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 423 default y 424 help 425 This option adds an alternative code sequence to work around Ampere 426 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 427 428 The affected design reports FEAT_HAFDBS as not implemented in 429 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 430 as required by the architecture. The unadvertised HAFDBS 431 implementation suffers from an additional erratum where hardware 432 A/D updates can occur after a PTE has been marked invalid. 433 434 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 435 which avoids enabling unadvertised hardware Access Flag management 436 at stage-2. 437 438 If unsure, say Y. 439 440config AMPERE_ERRATUM_AC04_CPU_23 441 bool "AmpereOne: AC04_CPU_23: Failure to synchronize writes to HCR_EL2 may corrupt address translations." 442 default y 443 help 444 This option adds an alternative code sequence to work around Ampere 445 errata AC04_CPU_23 on AmpereOne. 446 447 Updates to HCR_EL2 can rarely corrupt simultaneous translations for 448 data addresses initiated by load/store instructions. Only 449 instruction initiated translations are vulnerable, not translations 450 from prefetches for example. A DSB before the store to HCR_EL2 is 451 sufficient to prevent older instructions from hitting the window 452 for corruption, and an ISB after is sufficient to prevent younger 453 instructions from hitting the window for corruption. 454 455 If unsure, say Y. 456 457config ARM64_WORKAROUND_CLEAN_CACHE 458 bool 459 460config ARM64_ERRATUM_826319 461 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 462 default y 463 select ARM64_WORKAROUND_CLEAN_CACHE 464 help 465 This option adds an alternative code sequence to work around ARM 466 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 467 AXI master interface and an L2 cache. 468 469 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 470 and is unable to accept a certain write via this interface, it will 471 not progress on read data presented on the read data channel and the 472 system can deadlock. 473 474 The workaround promotes data cache clean instructions to 475 data cache clean-and-invalidate. 476 Please note that this does not necessarily enable the workaround, 477 as it depends on the alternative framework, which will only patch 478 the kernel if an affected CPU is detected. 479 480 If unsure, say Y. 481 482config ARM64_ERRATUM_827319 483 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 484 default y 485 select ARM64_WORKAROUND_CLEAN_CACHE 486 help 487 This option adds an alternative code sequence to work around ARM 488 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 489 master interface and an L2 cache. 490 491 Under certain conditions this erratum can cause a clean line eviction 492 to occur at the same time as another transaction to the same address 493 on the AMBA 5 CHI interface, which can cause data corruption if the 494 interconnect reorders the two transactions. 495 496 The workaround promotes data cache clean instructions to 497 data cache clean-and-invalidate. 498 Please note that this does not necessarily enable the workaround, 499 as it depends on the alternative framework, which will only patch 500 the kernel if an affected CPU is detected. 501 502 If unsure, say Y. 503 504config ARM64_ERRATUM_824069 505 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 506 default y 507 select ARM64_WORKAROUND_CLEAN_CACHE 508 help 509 This option adds an alternative code sequence to work around ARM 510 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 511 to a coherent interconnect. 512 513 If a Cortex-A53 processor is executing a store or prefetch for 514 write instruction at the same time as a processor in another 515 cluster is executing a cache maintenance operation to the same 516 address, then this erratum might cause a clean cache line to be 517 incorrectly marked as dirty. 518 519 The workaround promotes data cache clean instructions to 520 data cache clean-and-invalidate. 521 Please note that this option does not necessarily enable the 522 workaround, as it depends on the alternative framework, which will 523 only patch the kernel if an affected CPU is detected. 524 525 If unsure, say Y. 526 527config ARM64_ERRATUM_819472 528 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 529 default y 530 select ARM64_WORKAROUND_CLEAN_CACHE 531 help 532 This option adds an alternative code sequence to work around ARM 533 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 534 present when it is connected to a coherent interconnect. 535 536 If the processor is executing a load and store exclusive sequence at 537 the same time as a processor in another cluster is executing a cache 538 maintenance operation to the same address, then this erratum might 539 cause data corruption. 540 541 The workaround promotes data cache clean instructions to 542 data cache clean-and-invalidate. 543 Please note that this does not necessarily enable the workaround, 544 as it depends on the alternative framework, which will only patch 545 the kernel if an affected CPU is detected. 546 547 If unsure, say Y. 548 549config ARM64_ERRATUM_832075 550 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 551 default y 552 help 553 This option adds an alternative code sequence to work around ARM 554 erratum 832075 on Cortex-A57 parts up to r1p2. 555 556 Affected Cortex-A57 parts might deadlock when exclusive load/store 557 instructions to Write-Back memory are mixed with Device loads. 558 559 The workaround is to promote device loads to use Load-Acquire 560 semantics. 561 Please note that this does not necessarily enable the workaround, 562 as it depends on the alternative framework, which will only patch 563 the kernel if an affected CPU is detected. 564 565 If unsure, say Y. 566 567config ARM64_ERRATUM_834220 568 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 569 depends on KVM 570 help 571 This option adds an alternative code sequence to work around ARM 572 erratum 834220 on Cortex-A57 parts up to r1p2. 573 574 Affected Cortex-A57 parts might report a Stage 2 translation 575 fault as the result of a Stage 1 fault for load crossing a 576 page boundary when there is a permission or device memory 577 alignment fault at Stage 1 and a translation fault at Stage 2. 578 579 The workaround is to verify that the Stage 1 translation 580 doesn't generate a fault before handling the Stage 2 fault. 581 Please note that this does not necessarily enable the workaround, 582 as it depends on the alternative framework, which will only patch 583 the kernel if an affected CPU is detected. 584 585 If unsure, say N. 586 587config ARM64_ERRATUM_1742098 588 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 589 depends on COMPAT 590 default y 591 help 592 This option removes the AES hwcap for aarch32 user-space to 593 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 594 595 Affected parts may corrupt the AES state if an interrupt is 596 taken between a pair of AES instructions. These instructions 597 are only present if the cryptography extensions are present. 598 All software should have a fallback implementation for CPUs 599 that don't implement the cryptography extensions. 600 601 If unsure, say Y. 602 603config ARM64_ERRATUM_845719 604 bool "Cortex-A53: 845719: a load might read incorrect data" 605 depends on COMPAT 606 default y 607 help 608 This option adds an alternative code sequence to work around ARM 609 erratum 845719 on Cortex-A53 parts up to r0p4. 610 611 When running a compat (AArch32) userspace on an affected Cortex-A53 612 part, a load at EL0 from a virtual address that matches the bottom 32 613 bits of the virtual address used by a recent load at (AArch64) EL1 614 might return incorrect data. 615 616 The workaround is to write the contextidr_el1 register on exception 617 return to a 32-bit task. 618 Please note that this does not necessarily enable the workaround, 619 as it depends on the alternative framework, which will only patch 620 the kernel if an affected CPU is detected. 621 622 If unsure, say Y. 623 624config ARM64_ERRATUM_843419 625 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 626 default y 627 help 628 This option links the kernel with '--fix-cortex-a53-843419' and 629 enables PLT support to replace certain ADRP instructions, which can 630 cause subsequent memory accesses to use an incorrect address on 631 Cortex-A53 parts up to r0p4. 632 633 If unsure, say Y. 634 635config ARM64_ERRATUM_1024718 636 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 637 default y 638 help 639 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 640 641 Affected Cortex-A55 cores (all revisions) could cause incorrect 642 update of the hardware dirty bit when the DBM/AP bits are updated 643 without a break-before-make. The workaround is to disable the usage 644 of hardware DBM locally on the affected cores. CPUs not affected by 645 this erratum will continue to use the feature. 646 647 If unsure, say Y. 648 649config ARM64_ERRATUM_1418040 650 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 651 default y 652 depends on COMPAT 653 help 654 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 655 errata 1188873 and 1418040. 656 657 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 658 cause register corruption when accessing the timer registers 659 from AArch32 userspace. 660 661 If unsure, say Y. 662 663config ARM64_WORKAROUND_SPECULATIVE_AT 664 bool 665 666config ARM64_ERRATUM_1165522 667 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 668 default y 669 select ARM64_WORKAROUND_SPECULATIVE_AT 670 help 671 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 672 673 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 674 corrupted TLBs by speculating an AT instruction during a guest 675 context switch. 676 677 If unsure, say Y. 678 679config ARM64_ERRATUM_1319367 680 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 681 default y 682 select ARM64_WORKAROUND_SPECULATIVE_AT 683 help 684 This option adds work arounds for ARM Cortex-A57 erratum 1319537 685 and A72 erratum 1319367 686 687 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 688 speculating an AT instruction during a guest context switch. 689 690 If unsure, say Y. 691 692config ARM64_ERRATUM_1530923 693 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 694 default y 695 select ARM64_WORKAROUND_SPECULATIVE_AT 696 help 697 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 698 699 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 700 corrupted TLBs by speculating an AT instruction during a guest 701 context switch. 702 703 If unsure, say Y. 704 705config ARM64_WORKAROUND_REPEAT_TLBI 706 bool 707 708config ARM64_ERRATUM_2441007 709 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 710 select ARM64_WORKAROUND_REPEAT_TLBI 711 help 712 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 713 714 Under very rare circumstances, affected Cortex-A55 CPUs 715 may not handle a race between a break-before-make sequence on one 716 CPU, and another CPU accessing the same page. This could allow a 717 store to a page that has been unmapped. 718 719 Work around this by adding the affected CPUs to the list that needs 720 TLB sequences to be done twice. 721 722 If unsure, say N. 723 724config ARM64_ERRATUM_1286807 725 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 726 select ARM64_WORKAROUND_REPEAT_TLBI 727 help 728 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 729 730 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 731 address for a cacheable mapping of a location is being 732 accessed by a core while another core is remapping the virtual 733 address to a new physical page using the recommended 734 break-before-make sequence, then under very rare circumstances 735 TLBI+DSB completes before a read using the translation being 736 invalidated has been observed by other observers. The 737 workaround repeats the TLBI+DSB operation. 738 739 If unsure, say N. 740 741config ARM64_ERRATUM_1463225 742 bool "Cortex-A76: Software Step might prevent interrupt recognition" 743 default y 744 help 745 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 746 747 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 748 of a system call instruction (SVC) can prevent recognition of 749 subsequent interrupts when software stepping is disabled in the 750 exception handler of the system call and either kernel debugging 751 is enabled or VHE is in use. 752 753 Work around the erratum by triggering a dummy step exception 754 when handling a system call from a task that is being stepped 755 in a VHE configuration of the kernel. 756 757 If unsure, say Y. 758 759config ARM64_ERRATUM_1542419 760 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 761 help 762 This option adds a workaround for ARM Neoverse-N1 erratum 763 1542419. 764 765 Affected Neoverse-N1 cores could execute a stale instruction when 766 modified by another CPU. The workaround depends on a firmware 767 counterpart. 768 769 Workaround the issue by hiding the DIC feature from EL0. This 770 forces user-space to perform cache maintenance. 771 772 If unsure, say N. 773 774config ARM64_ERRATUM_1508412 775 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 776 default y 777 help 778 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 779 780 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 781 of a store-exclusive or read of PAR_EL1 and a load with device or 782 non-cacheable memory attributes. The workaround depends on a firmware 783 counterpart. 784 785 KVM guests must also have the workaround implemented or they can 786 deadlock the system. 787 788 Work around the issue by inserting DMB SY barriers around PAR_EL1 789 register reads and warning KVM users. The DMB barrier is sufficient 790 to prevent a speculative PAR_EL1 read. 791 792 If unsure, say Y. 793 794config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 795 bool 796 797config ARM64_ERRATUM_2051678 798 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 799 default y 800 help 801 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 802 Affected Cortex-A510 might not respect the ordering rules for 803 hardware update of the page table's dirty bit. The workaround 804 is to not enable the feature on affected CPUs. 805 806 If unsure, say Y. 807 808config ARM64_ERRATUM_2077057 809 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 810 default y 811 help 812 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 813 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 814 expected, but a Pointer Authentication trap is taken instead. The 815 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 816 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 817 818 This can only happen when EL2 is stepping EL1. 819 820 When these conditions occur, the SPSR_EL2 value is unchanged from the 821 previous guest entry, and can be restored from the in-memory copy. 822 823 If unsure, say Y. 824 825config ARM64_ERRATUM_2658417 826 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 827 default y 828 help 829 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 830 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 831 BFMMLA or VMMLA instructions in rare circumstances when a pair of 832 A510 CPUs are using shared neon hardware. As the sharing is not 833 discoverable by the kernel, hide the BF16 HWCAP to indicate that 834 user-space should not be using these instructions. 835 836 If unsure, say Y. 837 838config ARM64_ERRATUM_2119858 839 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 840 default y 841 depends on CORESIGHT_TRBE 842 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 843 help 844 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 845 846 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 847 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 848 the event of a WRAP event. 849 850 Work around the issue by always making sure we move the TRBPTR_EL1 by 851 256 bytes before enabling the buffer and filling the first 256 bytes of 852 the buffer with ETM ignore packets upon disabling. 853 854 If unsure, say Y. 855 856config ARM64_ERRATUM_2139208 857 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 858 default y 859 depends on CORESIGHT_TRBE 860 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 861 help 862 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 863 864 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 865 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 866 the event of a WRAP event. 867 868 Work around the issue by always making sure we move the TRBPTR_EL1 by 869 256 bytes before enabling the buffer and filling the first 256 bytes of 870 the buffer with ETM ignore packets upon disabling. 871 872 If unsure, say Y. 873 874config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 875 bool 876 877config ARM64_ERRATUM_2054223 878 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 879 default y 880 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 881 help 882 Enable workaround for ARM Cortex-A710 erratum 2054223 883 884 Affected cores may fail to flush the trace data on a TSB instruction, when 885 the PE is in trace prohibited state. This will cause losing a few bytes 886 of the trace cached. 887 888 Workaround is to issue two TSB consecutively on affected cores. 889 890 If unsure, say Y. 891 892config ARM64_ERRATUM_2067961 893 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 894 default y 895 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 896 help 897 Enable workaround for ARM Neoverse-N2 erratum 2067961 898 899 Affected cores may fail to flush the trace data on a TSB instruction, when 900 the PE is in trace prohibited state. This will cause losing a few bytes 901 of the trace cached. 902 903 Workaround is to issue two TSB consecutively on affected cores. 904 905 If unsure, say Y. 906 907config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 908 bool 909 910config ARM64_ERRATUM_2253138 911 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 912 depends on CORESIGHT_TRBE 913 default y 914 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 915 help 916 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 917 918 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 919 for TRBE. Under some conditions, the TRBE might generate a write to the next 920 virtually addressed page following the last page of the TRBE address space 921 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 922 923 Work around this in the driver by always making sure that there is a 924 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 925 926 If unsure, say Y. 927 928config ARM64_ERRATUM_2224489 929 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 930 depends on CORESIGHT_TRBE 931 default y 932 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 933 help 934 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 935 936 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 937 for TRBE. Under some conditions, the TRBE might generate a write to the next 938 virtually addressed page following the last page of the TRBE address space 939 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 940 941 Work around this in the driver by always making sure that there is a 942 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 943 944 If unsure, say Y. 945 946config ARM64_ERRATUM_2441009 947 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 948 select ARM64_WORKAROUND_REPEAT_TLBI 949 help 950 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 951 952 Under very rare circumstances, affected Cortex-A510 CPUs 953 may not handle a race between a break-before-make sequence on one 954 CPU, and another CPU accessing the same page. This could allow a 955 store to a page that has been unmapped. 956 957 Work around this by adding the affected CPUs to the list that needs 958 TLB sequences to be done twice. 959 960 If unsure, say N. 961 962config ARM64_ERRATUM_2064142 963 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 964 depends on CORESIGHT_TRBE 965 default y 966 help 967 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 968 969 Affected Cortex-A510 core might fail to write into system registers after the 970 TRBE has been disabled. Under some conditions after the TRBE has been disabled 971 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 972 and TRBTRG_EL1 will be ignored and will not be effected. 973 974 Work around this in the driver by executing TSB CSYNC and DSB after collection 975 is stopped and before performing a system register write to one of the affected 976 registers. 977 978 If unsure, say Y. 979 980config ARM64_ERRATUM_2038923 981 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 982 depends on CORESIGHT_TRBE 983 default y 984 help 985 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 986 987 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 988 prohibited within the CPU. As a result, the trace buffer or trace buffer state 989 might be corrupted. This happens after TRBE buffer has been enabled by setting 990 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 991 execution changes from a context, in which trace is prohibited to one where it 992 isn't, or vice versa. In these mentioned conditions, the view of whether trace 993 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 994 the trace buffer state might be corrupted. 995 996 Work around this in the driver by preventing an inconsistent view of whether the 997 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 998 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 999 two ISB instructions if no ERET is to take place. 1000 1001 If unsure, say Y. 1002 1003config ARM64_ERRATUM_1902691 1004 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1005 depends on CORESIGHT_TRBE 1006 default y 1007 help 1008 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1009 1010 Affected Cortex-A510 core might cause trace data corruption, when being written 1011 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1012 trace data. 1013 1014 Work around this problem in the driver by just preventing TRBE initialization on 1015 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1016 on such implementations. This will cover the kernel for any firmware that doesn't 1017 do this already. 1018 1019 If unsure, say Y. 1020 1021config ARM64_ERRATUM_2457168 1022 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1023 depends on ARM64_AMU_EXTN 1024 default y 1025 help 1026 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1027 1028 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1029 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1030 incorrectly giving a significantly higher output value. 1031 1032 Work around this problem by returning 0 when reading the affected counter in 1033 key locations that results in disabling all users of this counter. This effect 1034 is the same to firmware disabling affected counters. 1035 1036 If unsure, say Y. 1037 1038config ARM64_ERRATUM_2645198 1039 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1040 default y 1041 help 1042 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1043 1044 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1045 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1046 next instruction abort caused by permission fault. 1047 1048 Only user-space does executable to non-executable permission transition via 1049 mprotect() system call. Workaround the problem by doing a break-before-make 1050 TLB invalidation, for all changes to executable user space mappings. 1051 1052 If unsure, say Y. 1053 1054config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1055 bool 1056 1057config ARM64_ERRATUM_2966298 1058 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1059 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1060 default y 1061 help 1062 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1063 1064 On an affected Cortex-A520 core, a speculatively executed unprivileged 1065 load might leak data from a privileged level via a cache side channel. 1066 1067 Work around this problem by executing a TLBI before returning to EL0. 1068 1069 If unsure, say Y. 1070 1071config ARM64_ERRATUM_3117295 1072 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1073 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1074 default y 1075 help 1076 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1077 1078 On an affected Cortex-A510 core, a speculatively executed unprivileged 1079 load might leak data from a privileged level via a cache side channel. 1080 1081 Work around this problem by executing a TLBI before returning to EL0. 1082 1083 If unsure, say Y. 1084 1085config ARM64_ERRATUM_3194386 1086 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1087 default y 1088 help 1089 This option adds the workaround for the following errata: 1090 1091 * ARM Cortex-A76 erratum 3324349 1092 * ARM Cortex-A77 erratum 3324348 1093 * ARM Cortex-A78 erratum 3324344 1094 * ARM Cortex-A78C erratum 3324346 1095 * ARM Cortex-A78C erratum 3324347 1096 * ARM Cortex-A710 erratam 3324338 1097 * ARM Cortex-A715 errartum 3456084 1098 * ARM Cortex-A720 erratum 3456091 1099 * ARM Cortex-A725 erratum 3456106 1100 * ARM Cortex-X1 erratum 3324344 1101 * ARM Cortex-X1C erratum 3324346 1102 * ARM Cortex-X2 erratum 3324338 1103 * ARM Cortex-X3 erratum 3324335 1104 * ARM Cortex-X4 erratum 3194386 1105 * ARM Cortex-X925 erratum 3324334 1106 * ARM Neoverse-N1 erratum 3324349 1107 * ARM Neoverse N2 erratum 3324339 1108 * ARM Neoverse-N3 erratum 3456111 1109 * ARM Neoverse-V1 erratum 3324341 1110 * ARM Neoverse V2 erratum 3324336 1111 * ARM Neoverse-V3 erratum 3312417 1112 * ARM Neoverse-V3AE erratum 3312417 1113 1114 On affected cores "MSR SSBS, #0" instructions may not affect 1115 subsequent speculative instructions, which may permit unexepected 1116 speculative store bypassing. 1117 1118 Work around this problem by placing a Speculation Barrier (SB) or 1119 Instruction Synchronization Barrier (ISB) after kernel changes to 1120 SSBS. The presence of the SSBS special-purpose register is hidden 1121 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1122 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1123 1124 If unsure, say Y. 1125 1126config ARM64_ERRATUM_4311569 1127 bool "SI L1: 4311569: workaround for premature CMO completion erratum" 1128 default y 1129 help 1130 This option adds the workaround for ARM SI L1 erratum 4311569. 1131 1132 The erratum of SI L1 can cause an early response to a combined write 1133 and cache maintenance operation (WR+CMO) before the operation is fully 1134 completed to the Point of Serialization (POS). 1135 This can result in a non-I/O coherent agent observing stale data, 1136 potentially leading to system instability or incorrect behavior. 1137 1138 Enabling this option implements a software workaround by inserting a 1139 second loop of Cache Maintenance Operation (CMO) immediately following the 1140 end of function to do CMOs. This ensures that the data is correctly serialized 1141 before the buffer is handed off to a non-coherent agent. 1142 1143 If unsure, say Y. 1144 1145config ARM64_ERRATUM_4193714 1146 bool "C1-Pro: 4193714: SME DVMSync early acknowledgement" 1147 depends on ARM64_SME 1148 default y 1149 help 1150 Enable workaround for C1-Pro acknowledging the DVMSync before 1151 the SME memory accesses are complete. This will cause TLB 1152 maintenance for processes using SME to also issue an IPI to 1153 the affected CPUs. 1154 1155 If unsure, say Y. 1156 1157config ARM64_ERRATUM_4118414 1158 bool "Various: Completion of affected memory accesses might not be guaranteed by completion of a TLBI" 1159 default y 1160 select ARM64_WORKAROUND_REPEAT_TLBI 1161 help 1162 This option adds a workaround for the following errata: 1163 1164 * ARM C1-Premium erratum 4193780 1165 * ARM C1-Ultra erratum 4193780 1166 * ARM Cortex-A76 erratum 4193800 1167 * ARM Cortex-A76AE erratum 4193801 1168 * ARM Cortex-A77 erratum 4193798 1169 * ARM Cortex-A78 erratum 4193791 1170 * ARM Cortex-A78AE erratum 4193793 1171 * ARM Cortex-A78C erratum 4193794 1172 * ARM Cortex-A710 erratum 4193788 1173 * ARM Cortex-X1 erratum 4193791 1174 * ARM Cortex-X1C erratum 4193792 1175 * ARM Cortex-X2 erratum 4193788 1176 * ARM Cortex-X3 erratum 4193786 1177 * ARM Cortex-X4 erratum 4118414 1178 * ARM Cortex-X925 erratum 4193781 1179 * ARM Neoverse-N1 erratum 4193800 1180 * ARM Neoverse-N2 erratum 4193789 1181 * ARM Neoverse-V1 erratum 4193790 1182 * ARM Neoverse-V2 erratum 4193787 1183 * ARM Neoverse-V3 erratum 4193784 1184 * ARM Neoverse-V3AE erratum 4193784 1185 * Microsoft Azure Cobalt 100 4193789 1186 * NVIDIA Olympus erratum T410-OLY-1029 1187 1188 On affected cores, some memory accesses might not be completed by 1189 broadcast TLB invalidation. 1190 1191 This issue is also known as CVE-2025-10263. 1192 1193 If unsure, say Y. 1194 1195config CAVIUM_ERRATUM_22375 1196 bool "Cavium erratum 22375, 24313" 1197 default y 1198 help 1199 Enable workaround for errata 22375 and 24313. 1200 1201 This implements two gicv3-its errata workarounds for ThunderX. Both 1202 with a small impact affecting only ITS table allocation. 1203 1204 erratum 22375: only alloc 8MB table size 1205 erratum 24313: ignore memory access type 1206 1207 The fixes are in ITS initialization and basically ignore memory access 1208 type and table size provided by the TYPER and BASER registers. 1209 1210 If unsure, say Y. 1211 1212config CAVIUM_ERRATUM_23144 1213 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1214 depends on NUMA 1215 default y 1216 help 1217 ITS SYNC command hang for cross node io and collections/cpu mapping. 1218 1219 If unsure, say Y. 1220 1221config CAVIUM_ERRATUM_23154 1222 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1223 default y 1224 help 1225 The ThunderX GICv3 implementation requires a modified version for 1226 reading the IAR status to ensure data synchronization 1227 (access to icc_iar1_el1 is not sync'ed before and after). 1228 1229 It also suffers from erratum 38545 (also present on Marvell's 1230 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1231 spuriously presented to the CPU interface. 1232 1233 If unsure, say Y. 1234 1235config CAVIUM_ERRATUM_27456 1236 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1237 default y 1238 help 1239 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1240 instructions may cause the icache to become corrupted if it 1241 contains data for a non-current ASID. The fix is to 1242 invalidate the icache when changing the mm context. 1243 1244 If unsure, say Y. 1245 1246config CAVIUM_ERRATUM_30115 1247 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1248 default y 1249 help 1250 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1251 1.2, and T83 Pass 1.0, KVM guest execution may disable 1252 interrupts in host. Trapping both GICv3 group-0 and group-1 1253 accesses sidesteps the issue. 1254 1255 If unsure, say Y. 1256 1257config CAVIUM_TX2_ERRATUM_219 1258 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1259 default y 1260 help 1261 On Cavium ThunderX2, a load, store or prefetch instruction between a 1262 TTBR update and the corresponding context synchronizing operation can 1263 cause a spurious Data Abort to be delivered to any hardware thread in 1264 the CPU core. 1265 1266 Work around the issue by avoiding the problematic code sequence and 1267 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1268 trap handler performs the corresponding register access, skips the 1269 instruction and ensures context synchronization by virtue of the 1270 exception return. 1271 1272 If unsure, say Y. 1273 1274config FUJITSU_ERRATUM_010001 1275 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1276 default y 1277 help 1278 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1279 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1280 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1281 This fault occurs under a specific hardware condition when a 1282 load/store instruction performs an address translation using: 1283 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1284 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1285 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1286 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1287 1288 The workaround is to ensure these bits are clear in TCR_ELx. 1289 The workaround only affects the Fujitsu-A64FX. 1290 1291 If unsure, say Y. 1292 1293config HISILICON_ERRATUM_161600802 1294 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1295 default y 1296 help 1297 The HiSilicon Hip07 SoC uses the wrong redistributor base 1298 when issued ITS commands such as VMOVP and VMAPP, and requires 1299 a 128kB offset to be applied to the target address in this commands. 1300 1301 If unsure, say Y. 1302 1303config HISILICON_ERRATUM_162100801 1304 bool "Hip09 162100801 erratum support" 1305 default y 1306 help 1307 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1308 during unmapping operation, which will cause some vSGIs lost. 1309 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1310 after VMOVP. 1311 1312 If unsure, say Y. 1313 1314config HISILICON_ERRATUM_162100125 1315 bool "Hisilicon erratum 162100125" 1316 default y 1317 select ARM64_WORKAROUND_DISABLE_CNP 1318 help 1319 On HiSilicon HIP09, TLB entry matching behavior when CNP 1320 (TTBRx.CNP=1) is enabled differs from the ARM architecture 1321 specification. 1322 1323 TLB entries may be incorrectly shared between CPUs, potentially 1324 causing TLB conflicts and stale mappings. 1325 1326 Disable CNP support for affected HiSilicon HIP09 cores. 1327 1328 If unsure, say Y. 1329 1330config QCOM_FALKOR_ERRATUM_1003 1331 bool "Falkor E1003: Incorrect translation due to ASID change" 1332 default y 1333 help 1334 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1335 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1336 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1337 then only for entries in the walk cache, since the leaf translation 1338 is unchanged. Work around the erratum by invalidating the walk cache 1339 entries for the trampoline before entering the kernel proper. 1340 1341config QCOM_FALKOR_ERRATUM_1009 1342 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1343 default y 1344 select ARM64_WORKAROUND_REPEAT_TLBI 1345 help 1346 On Falkor v1, the CPU may prematurely complete a DSB following a 1347 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1348 one more time to fix the issue. 1349 1350 If unsure, say Y. 1351 1352config QCOM_QDF2400_ERRATUM_0065 1353 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1354 default y 1355 help 1356 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1357 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1358 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1359 1360 If unsure, say Y. 1361 1362config QCOM_FALKOR_ERRATUM_E1041 1363 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1364 default y 1365 help 1366 Falkor CPU may speculatively fetch instructions from an improper 1367 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1368 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1369 1370 If unsure, say Y. 1371 1372config ARM64_WORKAROUND_DISABLE_CNP 1373 bool 1374 1375config NVIDIA_CARMEL_CNP_ERRATUM 1376 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1377 default y 1378 select ARM64_WORKAROUND_DISABLE_CNP 1379 help 1380 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1381 invalidate shared TLB entries installed by a different core, as it would 1382 on standard ARM cores. 1383 1384 If unsure, say Y. 1385 1386config ROCKCHIP_ERRATUM_3568002 1387 bool "Rockchip 3568002: GIC600 can not access physical addresses higher than 4GB" 1388 default y 1389 help 1390 The Rockchip RK3566 and RK3568 GIC600 SoC integrations have AXI 1391 addressing limited to the first 32bit of physical address space. 1392 1393 If unsure, say Y. 1394 1395config ROCKCHIP_ERRATUM_3588001 1396 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1397 default y 1398 help 1399 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1400 This means, that its sharability feature may not be used, even though it 1401 is supported by the IP itself. 1402 1403 If unsure, say Y. 1404 1405config SOCIONEXT_SYNQUACER_PREITS 1406 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1407 default y 1408 help 1409 Socionext Synquacer SoCs implement a separate h/w block to generate 1410 MSI doorbell writes with non-zero values for the device ID. 1411 1412 If unsure, say Y. 1413 1414endmenu # "ARM errata workarounds via the alternatives framework" 1415 1416choice 1417 prompt "Page size" 1418 default ARM64_4K_PAGES 1419 help 1420 Page size (translation granule) configuration. 1421 1422config ARM64_4K_PAGES 1423 bool "4KB" 1424 select HAVE_PAGE_SIZE_4KB 1425 help 1426 This feature enables 4KB pages support. 1427 1428config ARM64_16K_PAGES 1429 bool "16KB" 1430 select HAVE_PAGE_SIZE_16KB 1431 help 1432 The system will use 16KB pages support. AArch32 emulation 1433 requires applications compiled with 16K (or a multiple of 16K) 1434 aligned segments. 1435 1436config ARM64_64K_PAGES 1437 bool "64KB" 1438 select HAVE_PAGE_SIZE_64KB 1439 help 1440 This feature enables 64KB pages support (4KB by default) 1441 allowing only two levels of page tables and faster TLB 1442 look-up. AArch32 emulation requires applications compiled 1443 with 64K aligned segments. 1444 1445endchoice 1446 1447choice 1448 prompt "Virtual address space size" 1449 default ARM64_VA_BITS_52 1450 help 1451 Allows choosing one of multiple possible virtual address 1452 space sizes. The level of translation table is determined by 1453 a combination of page size and virtual address space size. 1454 1455config ARM64_VA_BITS_36 1456 bool "36-bit" if EXPERT 1457 depends on PAGE_SIZE_16KB 1458 1459config ARM64_VA_BITS_39 1460 bool "39-bit" 1461 depends on PAGE_SIZE_4KB 1462 1463config ARM64_VA_BITS_42 1464 bool "42-bit" 1465 depends on PAGE_SIZE_64KB 1466 1467config ARM64_VA_BITS_47 1468 bool "47-bit" 1469 depends on PAGE_SIZE_16KB 1470 1471config ARM64_VA_BITS_48 1472 bool "48-bit" 1473 1474config ARM64_VA_BITS_52 1475 bool "52-bit" 1476 help 1477 Enable 52-bit virtual addressing for userspace when explicitly 1478 requested via a hint to mmap(). The kernel will also use 52-bit 1479 virtual addresses for its own mappings (provided HW support for 1480 this feature is available, otherwise it reverts to 48-bit). 1481 1482 NOTE: Enabling 52-bit virtual addressing in conjunction with 1483 ARMv8.3 Pointer Authentication will result in the PAC being 1484 reduced from 7 bits to 3 bits, which may have a significant 1485 impact on its susceptibility to brute-force attacks. 1486 1487 If unsure, select 48-bit virtual addressing instead. 1488 1489endchoice 1490 1491config ARM64_FORCE_52BIT 1492 bool "Force 52-bit virtual addresses for userspace" 1493 depends on ARM64_VA_BITS_52 && EXPERT 1494 help 1495 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1496 to maintain compatibility with older software by providing 48-bit VAs 1497 unless a hint is supplied to mmap. 1498 1499 This configuration option disables the 48-bit compatibility logic, and 1500 forces all userspace addresses to be 52-bit on HW that supports it. One 1501 should only enable this configuration option for stress testing userspace 1502 memory management code. If unsure say N here. 1503 1504config ARM64_VA_BITS 1505 int 1506 default 36 if ARM64_VA_BITS_36 1507 default 39 if ARM64_VA_BITS_39 1508 default 42 if ARM64_VA_BITS_42 1509 default 47 if ARM64_VA_BITS_47 1510 default 48 if ARM64_VA_BITS_48 1511 default 52 if ARM64_VA_BITS_52 1512 1513choice 1514 prompt "Physical address space size" 1515 default ARM64_PA_BITS_48 1516 help 1517 Choose the maximum physical address range that the kernel will 1518 support. 1519 1520config ARM64_PA_BITS_48 1521 bool "48-bit" 1522 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1523 1524config ARM64_PA_BITS_52 1525 bool "52-bit" 1526 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1527 help 1528 Enable support for a 52-bit physical address space, introduced as 1529 part of the ARMv8.2-LPA extension. 1530 1531 With this enabled, the kernel will also continue to work on CPUs that 1532 do not support ARMv8.2-LPA, but with some added memory overhead (and 1533 minor performance overhead). 1534 1535endchoice 1536 1537config ARM64_PA_BITS 1538 int 1539 default 48 if ARM64_PA_BITS_48 1540 default 52 if ARM64_PA_BITS_52 1541 1542config ARM64_LPA2 1543 def_bool y 1544 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1545 1546choice 1547 prompt "Endianness" 1548 default CPU_LITTLE_ENDIAN 1549 help 1550 Select the endianness of data accesses performed by the CPU. Userspace 1551 applications will need to be compiled and linked for the endianness 1552 that is selected here. 1553 1554config CPU_BIG_ENDIAN 1555 bool "Build big-endian kernel" 1556 depends on BROKEN 1557 help 1558 Say Y if you plan on running a kernel with a big-endian userspace. 1559 1560config CPU_LITTLE_ENDIAN 1561 bool "Build little-endian kernel" 1562 help 1563 Say Y if you plan on running a kernel with a little-endian userspace. 1564 This is usually the case for distributions targeting arm64. 1565 1566endchoice 1567 1568config NR_CPUS 1569 int "Maximum number of CPUs (2-4096)" 1570 range 2 4096 1571 default "512" 1572 1573config HOTPLUG_CPU 1574 bool "Support for hot-pluggable CPUs" 1575 select GENERIC_IRQ_MIGRATION 1576 help 1577 Say Y here to experiment with turning CPUs off and on. CPUs 1578 can be controlled through /sys/devices/system/cpu. 1579 1580# Common NUMA Features 1581config NUMA 1582 bool "NUMA Memory Allocation and Scheduler Support" 1583 select GENERIC_ARCH_NUMA 1584 select OF_NUMA 1585 select HAVE_SETUP_PER_CPU_AREA 1586 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1587 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1588 select USE_PERCPU_NUMA_NODE_ID 1589 help 1590 Enable NUMA (Non-Uniform Memory Access) support. 1591 1592 The kernel will try to allocate memory used by a CPU on the 1593 local memory of the CPU and add some more 1594 NUMA awareness to the kernel. 1595 1596config NODES_SHIFT 1597 int "Maximum NUMA Nodes (as a power of 2)" 1598 range 1 10 1599 default "4" 1600 depends on NUMA 1601 help 1602 Specify the maximum number of NUMA Nodes available on the target 1603 system. Increases memory reserved to accommodate various tables. 1604 1605source "kernel/Kconfig.hz" 1606 1607config ARCH_SPARSEMEM_ENABLE 1608 def_bool y 1609 select SPARSEMEM_VMEMMAP_ENABLE 1610 1611config HW_PERF_EVENTS 1612 def_bool y 1613 depends on ARM_PMU 1614 1615# Supported by clang >= 7.0 or GCC >= 12.0.0 1616config CC_HAVE_SHADOW_CALL_STACK 1617 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1618 1619config PARAVIRT 1620 bool "Enable paravirtualization code" 1621 select HAVE_PV_STEAL_CLOCK_GEN 1622 help 1623 This changes the kernel so it can modify itself when it is run 1624 under a hypervisor, potentially improving performance significantly 1625 over full virtualization. 1626 1627config PARAVIRT_TIME_ACCOUNTING 1628 bool "Paravirtual steal time accounting" 1629 select PARAVIRT 1630 help 1631 Select this option to enable fine granularity task steal time 1632 accounting. Time spent executing other tasks in parallel with 1633 the current vCPU is discounted from the vCPU power. To account for 1634 that, there can be a small performance impact. 1635 1636 If in doubt, say N here. 1637 1638config ARCH_SUPPORTS_KEXEC 1639 def_bool PM_SLEEP_SMP 1640 1641config ARCH_SUPPORTS_KEXEC_FILE 1642 def_bool y 1643 1644config ARCH_SELECTS_KEXEC_FILE 1645 def_bool y 1646 depends on KEXEC_FILE 1647 select HAVE_IMA_KEXEC if IMA 1648 1649config ARCH_SUPPORTS_KEXEC_SIG 1650 def_bool y 1651 1652config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1653 def_bool y 1654 1655config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1656 def_bool y 1657 1658config ARCH_SUPPORTS_KEXEC_HANDOVER 1659 def_bool y 1660 1661config ARCH_SUPPORTS_CRASH_DUMP 1662 def_bool y 1663 1664config ARCH_DEFAULT_CRASH_DUMP 1665 def_bool y 1666 1667config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1668 def_bool CRASH_RESERVE 1669 1670config TRANS_TABLE 1671 def_bool y 1672 depends on HIBERNATION || KEXEC_CORE 1673 1674config XEN_DOM0 1675 def_bool y 1676 depends on XEN 1677 1678config XEN 1679 bool "Xen guest support on ARM64" 1680 depends on ARM64 && OF 1681 select SWIOTLB_XEN 1682 select PARAVIRT 1683 help 1684 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1685 1686# include/linux/mmzone.h requires the following to be true: 1687# 1688# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1689# 1690# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1691# 1692# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1693# ----+-------------------+--------------+----------------------+-------------------------+ 1694# 4K | 27 | 12 | 15 | 10 | 1695# 16K | 27 | 14 | 13 | 11 | 1696# 64K | 29 | 16 | 13 | 13 | 1697config ARCH_FORCE_MAX_ORDER 1698 int 1699 default "13" if ARM64_64K_PAGES 1700 default "11" if ARM64_16K_PAGES 1701 default "10" 1702 help 1703 The kernel page allocator limits the size of maximal physically 1704 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1705 defines the maximal power of two of number of pages that can be 1706 allocated as a single contiguous block. This option allows 1707 overriding the default setting when ability to allocate very 1708 large blocks of physically contiguous memory is required. 1709 1710 The maximal size of allocation cannot exceed the size of the 1711 section, so the value of MAX_PAGE_ORDER should satisfy 1712 1713 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1714 1715 Don't change if unsure. 1716 1717config UNMAP_KERNEL_AT_EL0 1718 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1719 default y 1720 help 1721 Speculation attacks against some high-performance processors can 1722 be used to bypass MMU permission checks and leak kernel data to 1723 userspace. This can be defended against by unmapping the kernel 1724 when running in userspace, mapping it back in on exception entry 1725 via a trampoline page in the vector table. 1726 1727 If unsure, say Y. 1728 1729config MITIGATE_SPECTRE_BRANCH_HISTORY 1730 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1731 default y 1732 help 1733 Speculation attacks against some high-performance processors can 1734 make use of branch history to influence future speculation. 1735 When taking an exception from user-space, a sequence of branches 1736 or a firmware call overwrites the branch history. 1737 1738config ARM64_SW_TTBR0_PAN 1739 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1740 depends on !KCSAN 1741 help 1742 Enabling this option prevents the kernel from accessing 1743 user-space memory directly by pointing TTBR0_EL1 to a reserved 1744 zeroed area and reserved ASID. The user access routines 1745 restore the valid TTBR0_EL1 temporarily. 1746 1747config ARM64_TAGGED_ADDR_ABI 1748 bool "Enable the tagged user addresses syscall ABI" 1749 default y 1750 help 1751 When this option is enabled, user applications can opt in to a 1752 relaxed ABI via prctl() allowing tagged addresses to be passed 1753 to system calls as pointer arguments. For details, see 1754 Documentation/arch/arm64/tagged-address-abi.rst. 1755 1756menuconfig COMPAT 1757 bool "Kernel support for 32-bit EL0" 1758 depends on ARM64_4K_PAGES || EXPERT 1759 select HAVE_UID16 1760 select OLD_SIGSUSPEND3 1761 select COMPAT_OLD_SIGACTION 1762 help 1763 This option enables support for a 32-bit EL0 running under a 64-bit 1764 kernel at EL1. AArch32-specific components such as system calls, 1765 the user helper functions, VFP support and the ptrace interface are 1766 handled appropriately by the kernel. 1767 1768 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1769 that you will only be able to execute AArch32 binaries that were compiled 1770 with page size aligned segments. 1771 1772 If you want to execute 32-bit userspace applications, say Y. 1773 1774if COMPAT 1775 1776config KUSER_HELPERS 1777 bool "Enable kuser helpers page for 32-bit applications" 1778 default y 1779 help 1780 Warning: disabling this option may break 32-bit user programs. 1781 1782 Provide kuser helpers to compat tasks. The kernel provides 1783 helper code to userspace in read only form at a fixed location 1784 to allow userspace to be independent of the CPU type fitted to 1785 the system. This permits binaries to be run on ARMv4 through 1786 to ARMv8 without modification. 1787 1788 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1789 1790 However, the fixed address nature of these helpers can be used 1791 by ROP (return orientated programming) authors when creating 1792 exploits. 1793 1794 If all of the binaries and libraries which run on your platform 1795 are built specifically for your platform, and make no use of 1796 these helpers, then you can turn this option off to hinder 1797 such exploits. However, in that case, if a binary or library 1798 relying on those helpers is run, it will not function correctly. 1799 1800 Say N here only if you are absolutely certain that you do not 1801 need these helpers; otherwise, the safe option is to say Y. 1802 1803config COMPAT_VDSO 1804 bool "Enable vDSO for 32-bit applications" 1805 depends on !CPU_BIG_ENDIAN 1806 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1807 default y 1808 help 1809 Place in the process address space of 32-bit applications an 1810 ELF shared object providing fast implementations of gettimeofday 1811 and clock_gettime. 1812 1813 You must have a 32-bit build of glibc 2.22 or later for programs 1814 to seamlessly take advantage of this. 1815 1816config THUMB2_COMPAT_VDSO 1817 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1818 depends on COMPAT_VDSO 1819 default y 1820 help 1821 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1822 otherwise with '-marm'. 1823 1824config COMPAT_ALIGNMENT_FIXUPS 1825 bool "Fix up misaligned multi-word loads and stores in user space" 1826 1827menuconfig ARMV8_DEPRECATED 1828 bool "Emulate deprecated/obsolete ARMv8 instructions" 1829 depends on SYSCTL 1830 help 1831 Legacy software support may require certain instructions 1832 that have been deprecated or obsoleted in the architecture. 1833 1834 Enable this config to enable selective emulation of these 1835 features. 1836 1837 If unsure, say Y 1838 1839if ARMV8_DEPRECATED 1840 1841config SWP_EMULATION 1842 bool "Emulate SWP/SWPB instructions" 1843 help 1844 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1845 they are always undefined. Say Y here to enable software 1846 emulation of these instructions for userspace using LDXR/STXR. 1847 This feature can be controlled at runtime with the abi.swp 1848 sysctl which is disabled by default. 1849 1850 In some older versions of glibc [<=2.8] SWP is used during futex 1851 trylock() operations with the assumption that the code will not 1852 be preempted. This invalid assumption may be more likely to fail 1853 with SWP emulation enabled, leading to deadlock of the user 1854 application. 1855 1856 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1857 on an external transaction monitoring block called a global 1858 monitor to maintain update atomicity. If your system does not 1859 implement a global monitor, this option can cause programs that 1860 perform SWP operations to uncached memory to deadlock. 1861 1862 If unsure, say Y 1863 1864config CP15_BARRIER_EMULATION 1865 bool "Emulate CP15 Barrier instructions" 1866 help 1867 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1868 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1869 strongly recommended to use the ISB, DSB, and DMB 1870 instructions instead. 1871 1872 Say Y here to enable software emulation of these 1873 instructions for AArch32 userspace code. When this option is 1874 enabled, CP15 barrier usage is traced which can help 1875 identify software that needs updating. This feature can be 1876 controlled at runtime with the abi.cp15_barrier sysctl. 1877 1878 If unsure, say Y 1879 1880config SETEND_EMULATION 1881 bool "Emulate SETEND instruction" 1882 help 1883 The SETEND instruction alters the data-endianness of the 1884 AArch32 EL0, and is deprecated in ARMv8. 1885 1886 Say Y here to enable software emulation of the instruction 1887 for AArch32 userspace code. This feature can be controlled 1888 at runtime with the abi.setend sysctl. 1889 1890 Note: All the cpus on the system must have mixed endian support at EL0 1891 for this feature to be enabled. If a new CPU - which doesn't support mixed 1892 endian - is hotplugged in after this feature has been enabled, there could 1893 be unexpected results in the applications. 1894 1895 If unsure, say Y 1896endif # ARMV8_DEPRECATED 1897 1898endif # COMPAT 1899 1900menu "ARMv8.1 architectural features" 1901 1902config ARM64_HW_AFDBM 1903 bool "Support for hardware updates of the Access and Dirty page flags" 1904 default y 1905 help 1906 The ARMv8.1 architecture extensions introduce support for 1907 hardware updates of the access and dirty information in page 1908 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1909 capable processors, accesses to pages with PTE_AF cleared will 1910 set this bit instead of raising an access flag fault. 1911 Similarly, writes to read-only pages with the DBM bit set will 1912 clear the read-only bit (AP[2]) instead of raising a 1913 permission fault. 1914 1915 Kernels built with this configuration option enabled continue 1916 to work on pre-ARMv8.1 hardware and the performance impact is 1917 minimal. If unsure, say Y. 1918 1919endmenu # "ARMv8.1 architectural features" 1920 1921menu "ARMv8.2 architectural features" 1922 1923config ARM64_PMEM 1924 bool "Enable support for persistent memory" 1925 select ARCH_HAS_PMEM_API 1926 select ARCH_HAS_UACCESS_FLUSHCACHE 1927 help 1928 Say Y to enable support for the persistent memory API based on the 1929 ARMv8.2 DCPoP feature. 1930 1931 The feature is detected at runtime, and the kernel will use DC CVAC 1932 operations if DC CVAP is not supported (following the behaviour of 1933 DC CVAP itself if the system does not define a point of persistence). 1934 1935config ARM64_RAS_EXTN 1936 bool "Enable support for RAS CPU Extensions" 1937 default y 1938 help 1939 CPUs that support the Reliability, Availability and Serviceability 1940 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1941 errors, classify them and report them to software. 1942 1943 On CPUs with these extensions system software can use additional 1944 barriers to determine if faults are pending and read the 1945 classification from a new set of registers. 1946 1947 Selecting this feature will allow the kernel to use these barriers 1948 and access the new registers if the system supports the extension. 1949 Platform RAS features may additionally depend on firmware support. 1950 1951config ARM64_CNP 1952 bool "Enable support for Common Not Private (CNP) translations" 1953 default y 1954 help 1955 Common Not Private (CNP) allows translation table entries to 1956 be shared between different PEs in the same inner shareable 1957 domain, so the hardware can use this fact to optimise the 1958 caching of such entries in the TLB. 1959 1960 Selecting this option allows the CNP feature to be detected 1961 at runtime, and does not affect PEs that do not implement 1962 this feature. 1963 1964endmenu # "ARMv8.2 architectural features" 1965 1966menu "ARMv8.3 architectural features" 1967 1968config ARM64_PTR_AUTH 1969 bool "Enable support for pointer authentication" 1970 default y 1971 help 1972 Pointer authentication (part of the ARMv8.3 Extensions) provides 1973 instructions for signing and authenticating pointers against secret 1974 keys, which can be used to mitigate Return Oriented Programming (ROP) 1975 and other attacks. 1976 1977 This option enables these instructions at EL0 (i.e. for userspace). 1978 Choosing this option will cause the kernel to initialise secret keys 1979 for each process at exec() time, with these keys being 1980 context-switched along with the process. 1981 1982 The feature is detected at runtime. If the feature is not present in 1983 hardware it will not be advertised to userspace/KVM guest nor will it 1984 be enabled. 1985 1986 If the feature is present on the boot CPU but not on a late CPU, then 1987 the late CPU will be parked. Also, if the boot CPU does not have 1988 address auth and the late CPU has then the late CPU will still boot 1989 but with the feature disabled. On such a system, this option should 1990 not be selected. 1991 1992config ARM64_PTR_AUTH_KERNEL 1993 bool "Use pointer authentication for kernel" 1994 default y 1995 depends on ARM64_PTR_AUTH 1996 # Modern compilers insert a .note.gnu.property section note for PAC 1997 # which is only understood by binutils starting with version 2.33.1. 1998 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1999 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 2000 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2001 help 2002 If the compiler supports the -mbranch-protection or 2003 -msign-return-address flag (e.g. GCC 7 or later), then this option 2004 will cause the kernel itself to be compiled with return address 2005 protection. In this case, and if the target hardware is known to 2006 support pointer authentication, then CONFIG_STACKPROTECTOR can be 2007 disabled with minimal loss of protection. 2008 2009 This feature works with FUNCTION_GRAPH_TRACER option only if 2010 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2011 2012config CC_HAS_BRANCH_PROT_PAC_RET 2013 # GCC 9 or later, clang 8 or later 2014 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2015 2016config AS_HAS_CFI_NEGATE_RA_STATE 2017 # binutils 2.34+ 2018 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2019 2020endmenu # "ARMv8.3 architectural features" 2021 2022menu "ARMv8.4 architectural features" 2023 2024config ARM64_AMU_EXTN 2025 bool "Enable support for the Activity Monitors Unit CPU extension" 2026 default y 2027 help 2028 The activity monitors extension is an optional extension introduced 2029 by the ARMv8.4 CPU architecture. This enables support for version 1 2030 of the activity monitors architecture, AMUv1. 2031 2032 To enable the use of this extension on CPUs that implement it, say Y. 2033 2034 Note that for architectural reasons, firmware _must_ implement AMU 2035 support when running on CPUs that present the activity monitors 2036 extension. The required support is present in: 2037 * Version 1.5 and later of the ARM Trusted Firmware 2038 2039 For kernels that have this configuration enabled but boot with broken 2040 firmware, you may need to say N here until the firmware is fixed. 2041 Otherwise you may experience firmware panics or lockups when 2042 accessing the counter registers. Even if you are not observing these 2043 symptoms, the values returned by the register reads might not 2044 correctly reflect reality. Most commonly, the value read will be 0, 2045 indicating that the counter is not enabled. 2046 2047config ARM64_TLB_RANGE 2048 bool "Enable support for tlbi range feature" 2049 default y 2050 help 2051 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2052 range of input addresses. 2053 2054config ARM64_MPAM 2055 bool "Enable support for MPAM" 2056 select ARM64_MPAM_DRIVER 2057 select ARCH_HAS_CPU_RESCTRL 2058 help 2059 Memory System Resource Partitioning and Monitoring (MPAM) is an 2060 optional extension to the Arm architecture that allows each 2061 transaction issued to the memory system to be labelled with a 2062 Partition identifier (PARTID) and Performance Monitoring Group 2063 identifier (PMG). 2064 2065 Memory system components, such as the caches, can be configured with 2066 policies to control how much of various physical resources (such as 2067 memory bandwidth or cache memory) the transactions labelled with each 2068 PARTID can consume. Depending on the capabilities of the hardware, 2069 the PARTID and PMG can also be used as filtering criteria to measure 2070 the memory system resource consumption of different parts of a 2071 workload. 2072 2073 Use of this extension requires CPU support, support in the 2074 Memory System Components (MSC), and a description from firmware 2075 of where the MSCs are in the address space. 2076 2077 MPAM is exposed to user-space via the resctrl pseudo filesystem. 2078 2079 This option enables the extra context switch code. 2080 2081endmenu # "ARMv8.4 architectural features" 2082 2083menu "ARMv8.5 architectural features" 2084 2085config AS_HAS_ARMV8_5 2086 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2087 2088config ARM64_BTI 2089 bool "Branch Target Identification support" 2090 default y 2091 help 2092 Branch Target Identification (part of the ARMv8.5 Extensions) 2093 provides a mechanism to limit the set of locations to which computed 2094 branch instructions such as BR or BLR can jump. 2095 2096 To make use of BTI on CPUs that support it, say Y. 2097 2098 BTI is intended to provide complementary protection to other control 2099 flow integrity protection mechanisms, such as the Pointer 2100 authentication mechanism provided as part of the ARMv8.3 Extensions. 2101 For this reason, it does not make sense to enable this option without 2102 also enabling support for pointer authentication. Thus, when 2103 enabling this option you should also select ARM64_PTR_AUTH=y. 2104 2105 Userspace binaries must also be specifically compiled to make use of 2106 this mechanism. If you say N here or the hardware does not support 2107 BTI, such binaries can still run, but you get no additional 2108 enforcement of branch destinations. 2109 2110config ARM64_BTI_KERNEL 2111 bool "Use Branch Target Identification for kernel" 2112 default y 2113 depends on ARM64_BTI 2114 depends on ARM64_PTR_AUTH_KERNEL 2115 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2116 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2117 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2118 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2119 depends on !CC_IS_GCC 2120 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2121 help 2122 Build the kernel with Branch Target Identification annotations 2123 and enable enforcement of this for kernel code. When this option 2124 is enabled and the system supports BTI all kernel code including 2125 modular code must have BTI enabled. 2126 2127config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2128 # GCC 9 or later, clang 8 or later 2129 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2130 2131config ARM64_E0PD 2132 bool "Enable support for E0PD" 2133 default y 2134 help 2135 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2136 that EL0 accesses made via TTBR1 always fault in constant time, 2137 providing similar benefits to KASLR as those provided by KPTI, but 2138 with lower overhead and without disrupting legitimate access to 2139 kernel memory such as SPE. 2140 2141 This option enables E0PD for TTBR1 where available. 2142 2143config ARM64_AS_HAS_MTE 2144 # Initial support for MTE went in binutils 2.32.0, checked with 2145 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2146 # as a late addition to the final architecture spec (LDGM/STGM) 2147 # is only supported in the newer 2.32.x and 2.33 binutils 2148 # versions, hence the extra "stgm" instruction check below. 2149 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2150 2151config ARM64_MTE 2152 bool "Memory Tagging Extension support" 2153 default y 2154 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2155 depends on AS_HAS_ARMV8_5 2156 # Required for tag checking in the uaccess routines 2157 select ARCH_HAS_SUBPAGE_FAULTS 2158 select ARCH_USES_HIGH_VMA_FLAGS 2159 select ARCH_USES_PG_ARCH_2 2160 select ARCH_USES_PG_ARCH_3 2161 help 2162 Memory Tagging (part of the ARMv8.5 Extensions) provides 2163 architectural support for run-time, always-on detection of 2164 various classes of memory error to aid with software debugging 2165 to eliminate vulnerabilities arising from memory-unsafe 2166 languages. 2167 2168 This option enables the support for the Memory Tagging 2169 Extension at EL0 (i.e. for userspace). 2170 2171 Selecting this option allows the feature to be detected at 2172 runtime. Any secondary CPU not implementing this feature will 2173 not be allowed a late bring-up. 2174 2175 Userspace binaries that want to use this feature must 2176 explicitly opt in. The mechanism for the userspace is 2177 described in: 2178 2179 Documentation/arch/arm64/memory-tagging-extension.rst. 2180 2181endmenu # "ARMv8.5 architectural features" 2182 2183menu "ARMv8.7 architectural features" 2184 2185config ARM64_EPAN 2186 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2187 default y 2188 help 2189 Enhanced Privileged Access Never (EPAN) allows Privileged 2190 Access Never to be used with Execute-only mappings. 2191 2192 The feature is detected at runtime, and will remain disabled 2193 if the cpu does not implement the feature. 2194endmenu # "ARMv8.7 architectural features" 2195 2196config AS_HAS_MOPS 2197 def_bool $(as-instr,.arch_extension mops) 2198 2199menu "ARMv8.9 architectural features" 2200 2201config ARM64_POE 2202 prompt "Permission Overlay Extension" 2203 def_bool y 2204 select ARCH_USES_HIGH_VMA_FLAGS 2205 select ARCH_HAS_PKEYS 2206 help 2207 The Permission Overlay Extension is used to implement Memory 2208 Protection Keys. Memory Protection Keys provides a mechanism for 2209 enforcing page-based protections, but without requiring modification 2210 of the page tables when an application changes protection domains. 2211 2212 For details, see Documentation/core-api/protection-keys.rst 2213 2214 If unsure, say y. 2215 2216config ARCH_PKEY_BITS 2217 int 2218 default 3 2219 2220config ARM64_HAFT 2221 bool "Support for Hardware managed Access Flag for Table Descriptors" 2222 depends on ARM64_HW_AFDBM 2223 default y 2224 help 2225 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2226 Flag for Table descriptors. When enabled an architectural executed 2227 memory access will update the Access Flag in each Table descriptor 2228 which is accessed during the translation table walk and for which 2229 the Access Flag is 0. The Access Flag of the Table descriptor use 2230 the same bit of PTE_AF. 2231 2232 The feature will only be enabled if all the CPUs in the system 2233 support this feature. If unsure, say Y. 2234 2235endmenu # "ARMv8.9 architectural features" 2236 2237menu "ARMv9.4 architectural features" 2238 2239config ARM64_GCS 2240 bool "Enable support for Guarded Control Stack (GCS)" 2241 default y 2242 select ARCH_HAS_USER_SHADOW_STACK 2243 select ARCH_USES_HIGH_VMA_FLAGS 2244 help 2245 Guarded Control Stack (GCS) provides support for a separate 2246 stack with restricted access which contains only return 2247 addresses. This can be used to harden against some attacks 2248 by comparing return address used by the program with what is 2249 stored in the GCS, and may also be used to efficiently obtain 2250 the call stack for applications such as profiling. 2251 2252 The feature is detected at runtime, and will remain disabled 2253 if the system does not implement the feature. 2254 2255endmenu # "ARMv9.4 architectural features" 2256 2257config AS_HAS_LSUI 2258 def_bool $(as-instr,.arch_extension lsui) 2259 help 2260 Supported by LLVM 20+ and binutils 2.45+. 2261 2262menu "ARMv9.6 architectural features" 2263 2264config ARM64_LSUI 2265 bool "Support Unprivileged Load Store Instructions (LSUI)" 2266 default y 2267 depends on AS_HAS_LSUI && !CPU_BIG_ENDIAN 2268 help 2269 The Unprivileged Load Store Instructions (LSUI) provides 2270 variants load/store instructions that access user-space memory 2271 from the kernel without clearing PSTATE.PAN bit. 2272 2273 This feature is supported by LLVM 20+ and binutils 2.45+. 2274 2275endmenu # "ARMv9.6 architectural feature" 2276 2277config ARM64_SVE 2278 bool "ARM Scalable Vector Extension support" 2279 default y 2280 help 2281 The Scalable Vector Extension (SVE) is an extension to the AArch64 2282 execution state which complements and extends the SIMD functionality 2283 of the base architecture to support much larger vectors and to enable 2284 additional vectorisation opportunities. 2285 2286 To enable use of this extension on CPUs that implement it, say Y. 2287 2288 On CPUs that support the SVE2 extensions, this option will enable 2289 those too. 2290 2291 Note that for architectural reasons, firmware _must_ implement SVE 2292 support when running on SVE capable hardware. The required support 2293 is present in: 2294 2295 * version 1.5 and later of the ARM Trusted Firmware 2296 * the AArch64 boot wrapper since commit 5e1261e08abf 2297 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2298 2299 For other firmware implementations, consult the firmware documentation 2300 or vendor. 2301 2302 If you need the kernel to boot on SVE-capable hardware with broken 2303 firmware, you may need to say N here until you get your firmware 2304 fixed. Otherwise, you may experience firmware panics or lockups when 2305 booting the kernel. If unsure and you are not observing these 2306 symptoms, you should assume that it is safe to say Y. 2307 2308config ARM64_SME 2309 bool "ARM Scalable Matrix Extension support" 2310 default y 2311 depends on ARM64_SVE 2312 help 2313 The Scalable Matrix Extension (SME) is an extension to the AArch64 2314 execution state which utilises a substantial subset of the SVE 2315 instruction set, together with the addition of new architectural 2316 register state capable of holding two dimensional matrix tiles to 2317 enable various matrix operations. 2318 2319config ARM64_PSEUDO_NMI 2320 bool "Support for NMI-like interrupts" 2321 select ARM_GIC_V3 2322 help 2323 Adds support for mimicking Non-Maskable Interrupts through the use of 2324 GIC interrupt priority. This support requires version 3 or later of 2325 ARM GIC. 2326 2327 This high priority configuration for interrupts needs to be 2328 explicitly enabled by setting the kernel parameter 2329 "irqchip.gicv3_pseudo_nmi" to 1. 2330 2331 If unsure, say N 2332 2333if ARM64_PSEUDO_NMI 2334config ARM64_DEBUG_PRIORITY_MASKING 2335 bool "Debug interrupt priority masking" 2336 help 2337 This adds runtime checks to functions enabling/disabling 2338 interrupts when using priority masking. The additional checks verify 2339 the validity of ICC_PMR_EL1 when calling concerned functions. 2340 2341 If unsure, say N 2342endif # ARM64_PSEUDO_NMI 2343 2344config RELOCATABLE 2345 bool "Build a relocatable kernel image" if EXPERT 2346 select ARCH_HAS_RELR 2347 default y 2348 help 2349 This builds the kernel as a Position Independent Executable (PIE), 2350 which retains all relocation metadata required to relocate the 2351 kernel binary at runtime to a different virtual address than the 2352 address it was linked at. 2353 Since AArch64 uses the RELA relocation format, this requires a 2354 relocation pass at runtime even if the kernel is loaded at the 2355 same address it was linked at. 2356 2357config RANDOMIZE_BASE 2358 bool "Randomize the address of the kernel image" 2359 select RELOCATABLE 2360 help 2361 Randomizes the virtual address at which the kernel image is 2362 loaded, as a security feature that deters exploit attempts 2363 relying on knowledge of the location of kernel internals. 2364 2365 It is the bootloader's job to provide entropy, by passing a 2366 random u64 value in /chosen/kaslr-seed at kernel entry. 2367 2368 When booting via the UEFI stub, it will invoke the firmware's 2369 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2370 to the kernel proper. In addition, it will randomise the physical 2371 location of the kernel Image as well. 2372 2373 If unsure, say N. 2374 2375config RANDOMIZE_MODULE_REGION_FULL 2376 bool "Randomize the module region over a 2 GB range" 2377 depends on RANDOMIZE_BASE 2378 default y 2379 help 2380 Randomizes the location of the module region inside a 2 GB window 2381 covering the core kernel. This way, it is less likely for modules 2382 to leak information about the location of core kernel data structures 2383 but it does imply that function calls between modules and the core 2384 kernel will need to be resolved via veneers in the module PLT. 2385 2386 When this option is not set, the module region will be randomized over 2387 a limited range that contains the [_stext, _etext] interval of the 2388 core kernel, so branch relocations are almost always in range unless 2389 the region is exhausted. In this particular case of region 2390 exhaustion, modules might be able to fall back to a larger 2GB area. 2391 2392config CC_HAVE_STACKPROTECTOR_SYSREG 2393 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2394 2395config STACKPROTECTOR_PER_TASK 2396 def_bool y 2397 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2398 2399config UNWIND_PATCH_PAC_INTO_SCS 2400 bool "Enable shadow call stack dynamically using code patching" 2401 depends on CC_IS_CLANG 2402 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2403 depends on SHADOW_CALL_STACK 2404 select UNWIND_TABLES 2405 select DYNAMIC_SCS 2406 2407config ARM64_CONTPTE 2408 bool "Contiguous PTE mappings for user memory" if EXPERT 2409 depends on TRANSPARENT_HUGEPAGE 2410 default y 2411 help 2412 When enabled, user mappings are configured using the PTE contiguous 2413 bit, for any mappings that meet the size and alignment requirements. 2414 This reduces TLB pressure and improves performance. 2415 2416endmenu # "Kernel Features" 2417 2418menu "Boot options" 2419 2420config ARM64_ACPI_PARKING_PROTOCOL 2421 bool "Enable support for the ARM64 ACPI parking protocol" 2422 depends on ACPI 2423 help 2424 Enable support for the ARM64 ACPI parking protocol. If disabled 2425 the kernel will not allow booting through the ARM64 ACPI parking 2426 protocol even if the corresponding data is present in the ACPI 2427 MADT table. 2428 2429config CMDLINE 2430 string "Default kernel command string" 2431 default "" 2432 help 2433 Provide a set of default command-line options at build time by 2434 entering them here. As a minimum, you should specify the 2435 root device (e.g. root=/dev/nfs). 2436 2437choice 2438 prompt "Kernel command line type" 2439 depends on CMDLINE != "" 2440 default CMDLINE_FROM_BOOTLOADER 2441 help 2442 Choose how the kernel will handle the provided default kernel 2443 command line string. 2444 2445config CMDLINE_FROM_BOOTLOADER 2446 bool "Use bootloader kernel arguments if available" 2447 help 2448 Uses the command-line options passed by the boot loader. If 2449 the boot loader doesn't provide any, the default kernel command 2450 string provided in CMDLINE will be used. 2451 2452config CMDLINE_FORCE 2453 bool "Always use the default kernel command string" 2454 help 2455 Always use the default kernel command string, even if the boot 2456 loader passes other arguments to the kernel. 2457 This is useful if you cannot or don't want to change the 2458 command-line options your boot loader passes to the kernel. 2459 2460endchoice 2461 2462config EFI_STUB 2463 bool 2464 2465config EFI 2466 bool "UEFI runtime support" 2467 depends on OF && !CPU_BIG_ENDIAN 2468 depends on KERNEL_MODE_NEON 2469 select ARCH_SUPPORTS_ACPI 2470 select LIBFDT 2471 select UCS2_STRING 2472 select EFI_PARAMS_FROM_FDT 2473 select EFI_RUNTIME_WRAPPERS 2474 select EFI_STUB 2475 select EFI_GENERIC_STUB 2476 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2477 default y 2478 help 2479 This option provides support for runtime services provided 2480 by UEFI firmware (such as non-volatile variables, realtime 2481 clock, and platform reset). A UEFI stub is also provided to 2482 allow the kernel to be booted as an EFI application. This 2483 is only useful on systems that have UEFI firmware. 2484 2485config COMPRESSED_INSTALL 2486 bool "Install compressed image by default" 2487 help 2488 This makes the regular "make install" install the compressed 2489 image we built, not the legacy uncompressed one. 2490 2491 You can check that a compressed image works for you by doing 2492 "make zinstall" first, and verifying that everything is fine 2493 in your environment before making "make install" do this for 2494 you. 2495 2496config DMI 2497 bool "Enable support for SMBIOS (DMI) tables" 2498 depends on EFI 2499 default y 2500 help 2501 This enables SMBIOS/DMI feature for systems. 2502 2503 This option is only useful on systems that have UEFI firmware. 2504 However, even with this option, the resultant kernel should 2505 continue to boot on existing non-UEFI platforms. 2506 2507endmenu # "Boot options" 2508 2509menu "Power management options" 2510 2511source "kernel/power/Kconfig" 2512 2513config ARCH_HIBERNATION_POSSIBLE 2514 def_bool y 2515 depends on CPU_PM 2516 2517config ARCH_HIBERNATION_HEADER 2518 def_bool y 2519 depends on HIBERNATION 2520 2521config ARCH_SUSPEND_POSSIBLE 2522 def_bool y 2523 2524endmenu # "Power management options" 2525 2526menu "CPU Power Management" 2527 2528source "drivers/cpuidle/Kconfig" 2529 2530source "drivers/cpufreq/Kconfig" 2531 2532endmenu # "CPU Power Management" 2533 2534source "drivers/acpi/Kconfig" 2535 2536source "arch/arm64/kvm/Kconfig" 2537 2538source "kernel/livepatch/Kconfig" 2539