1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_APMT if ACPI 5 select ACPI_CCA_REQUIRED if ACPI 6 select ACPI_GENERIC_GSI if ACPI 7 select ACPI_GTDT if ACPI 8 select ACPI_HOTPLUG_CPU if ACPI_PROCESSOR && HOTPLUG_CPU 9 select ACPI_IORT if ACPI 10 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 11 select ACPI_MCFG if (ACPI && PCI) 12 select ACPI_SPCR_TABLE if ACPI 13 select ACPI_PPTT if ACPI 14 select ARCH_HAS_DEBUG_WX 15 select ARCH_BINFMT_ELF_EXTRA_PHDRS 16 select ARCH_BINFMT_ELF_STATE 17 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 18 select ARCH_ENABLE_MEMORY_HOTPLUG 19 select ARCH_ENABLE_MEMORY_HOTREMOVE 20 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 21 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 22 select ARCH_HAS_CACHE_LINE_SIZE 23 select ARCH_HAS_CC_PLATFORM 24 select ARCH_HAS_CRC32 25 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON 26 select ARCH_HAS_CURRENT_STACK_POINTER 27 select ARCH_HAS_DEBUG_VIRTUAL 28 select ARCH_HAS_DEBUG_VM_PGTABLE 29 select ARCH_HAS_DMA_OPS if XEN 30 select ARCH_HAS_DMA_PREP_COHERENT 31 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 32 select ARCH_HAS_FAST_MULTIPLIER 33 select ARCH_HAS_FORTIFY_SOURCE 34 select ARCH_HAS_GCOV_PROFILE_ALL 35 select ARCH_HAS_GIGANTIC_PAGE 36 select ARCH_HAS_KCOV 37 select ARCH_HAS_KERNEL_FPU_SUPPORT if KERNEL_MODE_NEON 38 select ARCH_HAS_KEEPINITRD 39 select ARCH_HAS_MEMBARRIER_SYNC_CORE 40 select ARCH_HAS_MEM_ENCRYPT 41 select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS 42 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 43 select ARCH_HAS_NONLEAF_PMD_YOUNG if ARM64_HAFT 44 select ARCH_HAS_PTE_DEVMAP 45 select ARCH_HAS_PTE_SPECIAL 46 select ARCH_HAS_HW_PTE_YOUNG 47 select ARCH_HAS_SETUP_DMA_OPS 48 select ARCH_HAS_SET_DIRECT_MAP 49 select ARCH_HAS_SET_MEMORY 50 select ARCH_HAS_MEM_ENCRYPT 51 select ARCH_HAS_FORCE_DMA_UNENCRYPTED 52 select ARCH_STACKWALK 53 select ARCH_HAS_STRICT_KERNEL_RWX 54 select ARCH_HAS_STRICT_MODULE_RWX 55 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 56 select ARCH_HAS_SYNC_DMA_FOR_CPU 57 select ARCH_HAS_SYSCALL_WRAPPER 58 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 59 select ARCH_HAS_ZONE_DMA_SET if EXPERT 60 select ARCH_HAVE_ELF_PROT 61 select ARCH_HAVE_NMI_SAFE_CMPXCHG 62 select ARCH_HAVE_TRACE_MMIO_ACCESS 63 select ARCH_INLINE_READ_LOCK if !PREEMPTION 64 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 65 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 67 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 68 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 70 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 71 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 72 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 73 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 74 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 75 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 76 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 77 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 78 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 79 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 80 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 81 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 82 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 83 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 84 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 85 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 86 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 87 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 88 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 89 select ARCH_KEEP_MEMBLOCK 90 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 91 select ARCH_USE_CMPXCHG_LOCKREF 92 select ARCH_USE_GNU_PROPERTY 93 select ARCH_USE_MEMTEST 94 select ARCH_USE_QUEUED_RWLOCKS 95 select ARCH_USE_QUEUED_SPINLOCKS 96 select ARCH_USE_SYM_ANNOTATIONS 97 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 98 select ARCH_SUPPORTS_HUGETLBFS 99 select ARCH_SUPPORTS_MEMORY_FAILURE 100 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 101 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 102 select ARCH_SUPPORTS_LTO_CLANG_THIN 103 select ARCH_SUPPORTS_CFI_CLANG 104 select ARCH_SUPPORTS_ATOMIC_RMW 105 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 106 select ARCH_SUPPORTS_NUMA_BALANCING 107 select ARCH_SUPPORTS_PAGE_TABLE_CHECK 108 select ARCH_SUPPORTS_PER_VMA_LOCK 109 select ARCH_SUPPORTS_HUGE_PFNMAP if TRANSPARENT_HUGEPAGE 110 select ARCH_SUPPORTS_RT 111 select ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH 112 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 113 select ARCH_WANT_DEFAULT_BPF_JIT 114 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 115 select ARCH_WANT_FRAME_POINTERS 116 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 117 select ARCH_WANT_LD_ORPHAN_WARN 118 select ARCH_WANTS_EXECMEM_LATE 119 select ARCH_WANTS_NO_INSTR 120 select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES 121 select ARCH_HAS_UBSAN 122 select ARM_AMBA 123 select ARM_ARCH_TIMER 124 select ARM_GIC 125 select AUDIT_ARCH_COMPAT_GENERIC 126 select ARM_GIC_V2M if PCI 127 select ARM_GIC_V3 128 select ARM_GIC_V3_ITS if PCI 129 select ARM_PSCI_FW 130 select BUILDTIME_TABLE_SORT 131 select CLONE_BACKWARDS 132 select COMMON_CLK 133 select CPU_PM if (SUSPEND || CPU_IDLE) 134 select CPUMASK_OFFSTACK if NR_CPUS > 256 135 select CRC32 136 select DCACHE_WORD_ACCESS 137 select DYNAMIC_FTRACE if FUNCTION_TRACER 138 select DMA_BOUNCE_UNALIGNED_KMALLOC 139 select DMA_DIRECT_REMAP 140 select EDAC_SUPPORT 141 select FRAME_POINTER 142 select FUNCTION_ALIGNMENT_4B 143 select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS 144 select GENERIC_ALLOCATOR 145 select GENERIC_ARCH_TOPOLOGY 146 select GENERIC_CLOCKEVENTS_BROADCAST 147 select GENERIC_CPU_AUTOPROBE 148 select GENERIC_CPU_DEVICES 149 select GENERIC_CPU_VULNERABILITIES 150 select GENERIC_EARLY_IOREMAP 151 select GENERIC_IDLE_POLL_SETUP 152 select GENERIC_IOREMAP 153 select GENERIC_IRQ_IPI 154 select GENERIC_IRQ_KEXEC_CLEAR_VM_FORWARD 155 select GENERIC_IRQ_PROBE 156 select GENERIC_IRQ_SHOW 157 select GENERIC_IRQ_SHOW_LEVEL 158 select GENERIC_LIB_DEVMEM_IS_ALLOWED 159 select GENERIC_PCI_IOMAP 160 select GENERIC_PTDUMP 161 select GENERIC_SCHED_CLOCK 162 select GENERIC_SMP_IDLE_THREAD 163 select GENERIC_TIME_VSYSCALL 164 select GENERIC_GETTIMEOFDAY 165 select GENERIC_VDSO_DATA_STORE 166 select GENERIC_VDSO_TIME_NS 167 select HARDIRQS_SW_RESEND 168 select HAS_IOPORT 169 select HAVE_MOVE_PMD 170 select HAVE_MOVE_PUD 171 select HAVE_PCI 172 select HAVE_ACPI_APEI if (ACPI && EFI) 173 select HAVE_ALIGNED_STRUCT_PAGE 174 select HAVE_ARCH_AUDITSYSCALL 175 select HAVE_ARCH_BITREVERSE 176 select HAVE_ARCH_COMPILER_H 177 select HAVE_ARCH_HUGE_VMALLOC 178 select HAVE_ARCH_HUGE_VMAP 179 select HAVE_ARCH_JUMP_LABEL 180 select HAVE_ARCH_JUMP_LABEL_RELATIVE 181 select HAVE_ARCH_KASAN 182 select HAVE_ARCH_KASAN_VMALLOC 183 select HAVE_ARCH_KASAN_SW_TAGS 184 select HAVE_ARCH_KASAN_HW_TAGS if ARM64_MTE 185 # Some instrumentation may be unsound, hence EXPERT 186 select HAVE_ARCH_KCSAN if EXPERT 187 select HAVE_ARCH_KFENCE 188 select HAVE_ARCH_KGDB 189 select HAVE_ARCH_MMAP_RND_BITS 190 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 191 select HAVE_ARCH_PREL32_RELOCATIONS 192 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 193 select HAVE_ARCH_SECCOMP_FILTER 194 select HAVE_ARCH_STACKLEAK 195 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 196 select HAVE_ARCH_TRACEHOOK 197 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 198 select HAVE_ARCH_VMAP_STACK 199 select HAVE_ARM_SMCCC 200 select HAVE_ASM_MODVERSIONS 201 select HAVE_EBPF_JIT 202 select HAVE_C_RECORDMCOUNT 203 select HAVE_CMPXCHG_DOUBLE 204 select HAVE_CMPXCHG_LOCAL 205 select HAVE_CONTEXT_TRACKING_USER 206 select HAVE_DEBUG_KMEMLEAK 207 select HAVE_DMA_CONTIGUOUS 208 select HAVE_DYNAMIC_FTRACE 209 select HAVE_DYNAMIC_FTRACE_WITH_ARGS \ 210 if (GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS || \ 211 CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS) 212 select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS \ 213 if DYNAMIC_FTRACE_WITH_ARGS && DYNAMIC_FTRACE_WITH_CALL_OPS 214 select HAVE_DYNAMIC_FTRACE_WITH_CALL_OPS \ 215 if (DYNAMIC_FTRACE_WITH_ARGS && !CFI_CLANG && \ 216 (CC_IS_CLANG || !CC_OPTIMIZE_FOR_SIZE)) 217 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 218 if DYNAMIC_FTRACE_WITH_ARGS 219 select HAVE_SAMPLE_FTRACE_DIRECT 220 select HAVE_SAMPLE_FTRACE_DIRECT_MULTI 221 select HAVE_EFFICIENT_UNALIGNED_ACCESS 222 select HAVE_GUP_FAST 223 select HAVE_FTRACE_GRAPH_FUNC 224 select HAVE_FTRACE_MCOUNT_RECORD 225 select HAVE_FUNCTION_TRACER 226 select HAVE_FUNCTION_ERROR_INJECTION 227 select HAVE_FUNCTION_GRAPH_FREGS 228 select HAVE_FUNCTION_GRAPH_TRACER 229 select HAVE_FUNCTION_GRAPH_RETVAL 230 select HAVE_GCC_PLUGINS 231 select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && \ 232 HW_PERF_EVENTS && HAVE_PERF_EVENTS_NMI 233 select HAVE_HW_BREAKPOINT if PERF_EVENTS 234 select HAVE_IOREMAP_PROT 235 select HAVE_IRQ_TIME_ACCOUNTING 236 select HAVE_MOD_ARCH_SPECIFIC 237 select HAVE_NMI 238 select HAVE_PERF_EVENTS 239 select HAVE_PERF_EVENTS_NMI if ARM64_PSEUDO_NMI 240 select HAVE_PERF_REGS 241 select HAVE_PERF_USER_STACK_DUMP 242 select HAVE_PREEMPT_DYNAMIC_KEY 243 select HAVE_REGS_AND_STACK_ACCESS_API 244 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 245 select HAVE_FUNCTION_ARG_ACCESS_API 246 select MMU_GATHER_RCU_TABLE_FREE 247 select HAVE_RSEQ 248 select HAVE_RUST if RUSTC_SUPPORTS_ARM64 249 select HAVE_STACKPROTECTOR 250 select HAVE_SYSCALL_TRACEPOINTS 251 select HAVE_KPROBES 252 select HAVE_KRETPROBES 253 select HAVE_GENERIC_VDSO 254 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 255 select IRQ_DOMAIN 256 select IRQ_FORCED_THREADING 257 select KASAN_VMALLOC if KASAN 258 select LOCK_MM_AND_FIND_VMA 259 select MODULES_USE_ELF_RELA 260 select NEED_DMA_MAP_STATE 261 select NEED_SG_DMA_LENGTH 262 select OF 263 select OF_EARLY_FLATTREE 264 select PCI_DOMAINS_GENERIC if PCI 265 select PCI_ECAM if (ACPI && PCI) 266 select PCI_SYSCALL if PCI 267 select POWER_RESET 268 select POWER_SUPPLY 269 select SPARSE_IRQ 270 select SWIOTLB 271 select SYSCTL_EXCEPTION_TRACE 272 select THREAD_INFO_IN_TASK 273 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 274 select HAVE_ARCH_USERFAULTFD_WP if USERFAULTFD 275 select TRACE_IRQFLAGS_SUPPORT 276 select TRACE_IRQFLAGS_NMI_SUPPORT 277 select HAVE_SOFTIRQ_ON_OWN_STACK 278 select USER_STACKTRACE_SUPPORT 279 select VDSO_GETRANDOM 280 help 281 ARM 64-bit (AArch64) Linux support. 282 283config RUSTC_SUPPORTS_ARM64 284 def_bool y 285 depends on CPU_LITTLE_ENDIAN 286 # Shadow call stack is only supported on certain rustc versions. 287 # 288 # When using the UNWIND_PATCH_PAC_INTO_SCS option, rustc version 1.80+ is 289 # required due to use of the -Zfixed-x18 flag. 290 # 291 # Otherwise, rustc version 1.82+ is required due to use of the 292 # -Zsanitizer=shadow-call-stack flag. 293 depends on !SHADOW_CALL_STACK || RUSTC_VERSION >= 108200 || RUSTC_VERSION >= 108000 && UNWIND_PATCH_PAC_INTO_SCS 294 295config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 296 def_bool CC_IS_CLANG 297 # https://github.com/ClangBuiltLinux/linux/issues/1507 298 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 299 300config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS 301 def_bool CC_IS_GCC 302 depends on $(cc-option,-fpatchable-function-entry=2) 303 304config 64BIT 305 def_bool y 306 307config MMU 308 def_bool y 309 310config ARM64_CONT_PTE_SHIFT 311 int 312 default 5 if PAGE_SIZE_64KB 313 default 7 if PAGE_SIZE_16KB 314 default 4 315 316config ARM64_CONT_PMD_SHIFT 317 int 318 default 5 if PAGE_SIZE_64KB 319 default 5 if PAGE_SIZE_16KB 320 default 4 321 322config ARCH_MMAP_RND_BITS_MIN 323 default 14 if PAGE_SIZE_64KB 324 default 16 if PAGE_SIZE_16KB 325 default 18 326 327# max bits determined by the following formula: 328# VA_BITS - PAGE_SHIFT - 3 329config ARCH_MMAP_RND_BITS_MAX 330 default 19 if ARM64_VA_BITS=36 331 default 24 if ARM64_VA_BITS=39 332 default 27 if ARM64_VA_BITS=42 333 default 30 if ARM64_VA_BITS=47 334 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 335 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 336 default 33 if ARM64_VA_BITS=48 337 default 14 if ARM64_64K_PAGES 338 default 16 if ARM64_16K_PAGES 339 default 18 340 341config ARCH_MMAP_RND_COMPAT_BITS_MIN 342 default 7 if ARM64_64K_PAGES 343 default 9 if ARM64_16K_PAGES 344 default 11 345 346config ARCH_MMAP_RND_COMPAT_BITS_MAX 347 default 16 348 349config NO_IOPORT_MAP 350 def_bool y if !PCI 351 352config STACKTRACE_SUPPORT 353 def_bool y 354 355config ILLEGAL_POINTER_VALUE 356 hex 357 default 0xdead000000000000 358 359config LOCKDEP_SUPPORT 360 def_bool y 361 362config GENERIC_BUG 363 def_bool y 364 depends on BUG 365 366config GENERIC_BUG_RELATIVE_POINTERS 367 def_bool y 368 depends on GENERIC_BUG 369 370config GENERIC_HWEIGHT 371 def_bool y 372 373config GENERIC_CSUM 374 def_bool y 375 376config GENERIC_CALIBRATE_DELAY 377 def_bool y 378 379config SMP 380 def_bool y 381 382config KERNEL_MODE_NEON 383 def_bool y 384 385config FIX_EARLYCON_MEM 386 def_bool y 387 388config PGTABLE_LEVELS 389 int 390 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 391 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 392 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 393 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 394 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 395 default 4 if ARM64_16K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 396 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 397 default 5 if ARM64_4K_PAGES && ARM64_VA_BITS_52 398 399config ARCH_SUPPORTS_UPROBES 400 def_bool y 401 402config ARCH_PROC_KCORE_TEXT 403 def_bool y 404 405config BROKEN_GAS_INST 406 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 407 408config BUILTIN_RETURN_ADDRESS_STRIPS_PAC 409 bool 410 # Clang's __builtin_return_address() strips the PAC since 12.0.0 411 # https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2 412 default y if CC_IS_CLANG 413 # GCC's __builtin_return_address() strips the PAC since 11.1.0, 414 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier 415 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94891 416 default y if CC_IS_GCC && (GCC_VERSION >= 110100) 417 default y if CC_IS_GCC && (GCC_VERSION >= 100200) && (GCC_VERSION < 110000) 418 default y if CC_IS_GCC && (GCC_VERSION >= 90400) && (GCC_VERSION < 100000) 419 default y if CC_IS_GCC && (GCC_VERSION >= 80500) && (GCC_VERSION < 90000) 420 default n 421 422config KASAN_SHADOW_OFFSET 423 hex 424 depends on KASAN_GENERIC || KASAN_SW_TAGS 425 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && !KASAN_SW_TAGS 426 default 0xdfffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && !KASAN_SW_TAGS 427 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 428 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 429 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 430 default 0xefff800000000000 if (ARM64_VA_BITS_48 || (ARM64_VA_BITS_52 && !ARM64_16K_PAGES)) && KASAN_SW_TAGS 431 default 0xefffc00000000000 if (ARM64_VA_BITS_47 || ARM64_VA_BITS_52) && ARM64_16K_PAGES && KASAN_SW_TAGS 432 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 433 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 434 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 435 default 0xffffffffffffffff 436 437config UNWIND_TABLES 438 bool 439 440source "arch/arm64/Kconfig.platforms" 441 442menu "Kernel Features" 443 444menu "ARM errata workarounds via the alternatives framework" 445 446config AMPERE_ERRATUM_AC03_CPU_38 447 bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and Translation Control Registers do not follow RES0 semantics" 448 default y 449 help 450 This option adds an alternative code sequence to work around Ampere 451 errata AC03_CPU_38 and AC04_CPU_10 on AmpereOne. 452 453 The affected design reports FEAT_HAFDBS as not implemented in 454 ID_AA64MMFR1_EL1.HAFDBS, but (V)TCR_ELx.{HA,HD} are not RES0 455 as required by the architecture. The unadvertised HAFDBS 456 implementation suffers from an additional erratum where hardware 457 A/D updates can occur after a PTE has been marked invalid. 458 459 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0, 460 which avoids enabling unadvertised hardware Access Flag management 461 at stage-2. 462 463 If unsure, say Y. 464 465config ARM64_WORKAROUND_CLEAN_CACHE 466 bool 467 468config ARM64_ERRATUM_826319 469 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 470 default y 471 select ARM64_WORKAROUND_CLEAN_CACHE 472 help 473 This option adds an alternative code sequence to work around ARM 474 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 475 AXI master interface and an L2 cache. 476 477 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 478 and is unable to accept a certain write via this interface, it will 479 not progress on read data presented on the read data channel and the 480 system can deadlock. 481 482 The workaround promotes data cache clean instructions to 483 data cache clean-and-invalidate. 484 Please note that this does not necessarily enable the workaround, 485 as it depends on the alternative framework, which will only patch 486 the kernel if an affected CPU is detected. 487 488 If unsure, say Y. 489 490config ARM64_ERRATUM_827319 491 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 492 default y 493 select ARM64_WORKAROUND_CLEAN_CACHE 494 help 495 This option adds an alternative code sequence to work around ARM 496 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 497 master interface and an L2 cache. 498 499 Under certain conditions this erratum can cause a clean line eviction 500 to occur at the same time as another transaction to the same address 501 on the AMBA 5 CHI interface, which can cause data corruption if the 502 interconnect reorders the two transactions. 503 504 The workaround promotes data cache clean instructions to 505 data cache clean-and-invalidate. 506 Please note that this does not necessarily enable the workaround, 507 as it depends on the alternative framework, which will only patch 508 the kernel if an affected CPU is detected. 509 510 If unsure, say Y. 511 512config ARM64_ERRATUM_824069 513 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 514 default y 515 select ARM64_WORKAROUND_CLEAN_CACHE 516 help 517 This option adds an alternative code sequence to work around ARM 518 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 519 to a coherent interconnect. 520 521 If a Cortex-A53 processor is executing a store or prefetch for 522 write instruction at the same time as a processor in another 523 cluster is executing a cache maintenance operation to the same 524 address, then this erratum might cause a clean cache line to be 525 incorrectly marked as dirty. 526 527 The workaround promotes data cache clean instructions to 528 data cache clean-and-invalidate. 529 Please note that this option does not necessarily enable the 530 workaround, as it depends on the alternative framework, which will 531 only patch the kernel if an affected CPU is detected. 532 533 If unsure, say Y. 534 535config ARM64_ERRATUM_819472 536 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 537 default y 538 select ARM64_WORKAROUND_CLEAN_CACHE 539 help 540 This option adds an alternative code sequence to work around ARM 541 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 542 present when it is connected to a coherent interconnect. 543 544 If the processor is executing a load and store exclusive sequence at 545 the same time as a processor in another cluster is executing a cache 546 maintenance operation to the same address, then this erratum might 547 cause data corruption. 548 549 The workaround promotes data cache clean instructions to 550 data cache clean-and-invalidate. 551 Please note that this does not necessarily enable the workaround, 552 as it depends on the alternative framework, which will only patch 553 the kernel if an affected CPU is detected. 554 555 If unsure, say Y. 556 557config ARM64_ERRATUM_832075 558 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 559 default y 560 help 561 This option adds an alternative code sequence to work around ARM 562 erratum 832075 on Cortex-A57 parts up to r1p2. 563 564 Affected Cortex-A57 parts might deadlock when exclusive load/store 565 instructions to Write-Back memory are mixed with Device loads. 566 567 The workaround is to promote device loads to use Load-Acquire 568 semantics. 569 Please note that this does not necessarily enable the workaround, 570 as it depends on the alternative framework, which will only patch 571 the kernel if an affected CPU is detected. 572 573 If unsure, say Y. 574 575config ARM64_ERRATUM_834220 576 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)" 577 depends on KVM 578 help 579 This option adds an alternative code sequence to work around ARM 580 erratum 834220 on Cortex-A57 parts up to r1p2. 581 582 Affected Cortex-A57 parts might report a Stage 2 translation 583 fault as the result of a Stage 1 fault for load crossing a 584 page boundary when there is a permission or device memory 585 alignment fault at Stage 1 and a translation fault at Stage 2. 586 587 The workaround is to verify that the Stage 1 translation 588 doesn't generate a fault before handling the Stage 2 fault. 589 Please note that this does not necessarily enable the workaround, 590 as it depends on the alternative framework, which will only patch 591 the kernel if an affected CPU is detected. 592 593 If unsure, say N. 594 595config ARM64_ERRATUM_1742098 596 bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic instructions in a sequence" 597 depends on COMPAT 598 default y 599 help 600 This option removes the AES hwcap for aarch32 user-space to 601 workaround erratum 1742098 on Cortex-A57 and Cortex-A72. 602 603 Affected parts may corrupt the AES state if an interrupt is 604 taken between a pair of AES instructions. These instructions 605 are only present if the cryptography extensions are present. 606 All software should have a fallback implementation for CPUs 607 that don't implement the cryptography extensions. 608 609 If unsure, say Y. 610 611config ARM64_ERRATUM_845719 612 bool "Cortex-A53: 845719: a load might read incorrect data" 613 depends on COMPAT 614 default y 615 help 616 This option adds an alternative code sequence to work around ARM 617 erratum 845719 on Cortex-A53 parts up to r0p4. 618 619 When running a compat (AArch32) userspace on an affected Cortex-A53 620 part, a load at EL0 from a virtual address that matches the bottom 32 621 bits of the virtual address used by a recent load at (AArch64) EL1 622 might return incorrect data. 623 624 The workaround is to write the contextidr_el1 register on exception 625 return to a 32-bit task. 626 Please note that this does not necessarily enable the workaround, 627 as it depends on the alternative framework, which will only patch 628 the kernel if an affected CPU is detected. 629 630 If unsure, say Y. 631 632config ARM64_ERRATUM_843419 633 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 634 default y 635 help 636 This option links the kernel with '--fix-cortex-a53-843419' and 637 enables PLT support to replace certain ADRP instructions, which can 638 cause subsequent memory accesses to use an incorrect address on 639 Cortex-A53 parts up to r0p4. 640 641 If unsure, say Y. 642 643config ARM64_LD_HAS_FIX_ERRATUM_843419 644 def_bool $(ld-option,--fix-cortex-a53-843419) 645 646config ARM64_ERRATUM_1024718 647 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 648 default y 649 help 650 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 651 652 Affected Cortex-A55 cores (all revisions) could cause incorrect 653 update of the hardware dirty bit when the DBM/AP bits are updated 654 without a break-before-make. The workaround is to disable the usage 655 of hardware DBM locally on the affected cores. CPUs not affected by 656 this erratum will continue to use the feature. 657 658 If unsure, say Y. 659 660config ARM64_ERRATUM_1418040 661 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 662 default y 663 depends on COMPAT 664 help 665 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 666 errata 1188873 and 1418040. 667 668 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 669 cause register corruption when accessing the timer registers 670 from AArch32 userspace. 671 672 If unsure, say Y. 673 674config ARM64_WORKAROUND_SPECULATIVE_AT 675 bool 676 677config ARM64_ERRATUM_1165522 678 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 679 default y 680 select ARM64_WORKAROUND_SPECULATIVE_AT 681 help 682 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 683 684 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 685 corrupted TLBs by speculating an AT instruction during a guest 686 context switch. 687 688 If unsure, say Y. 689 690config ARM64_ERRATUM_1319367 691 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 692 default y 693 select ARM64_WORKAROUND_SPECULATIVE_AT 694 help 695 This option adds work arounds for ARM Cortex-A57 erratum 1319537 696 and A72 erratum 1319367 697 698 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 699 speculating an AT instruction during a guest context switch. 700 701 If unsure, say Y. 702 703config ARM64_ERRATUM_1530923 704 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 705 default y 706 select ARM64_WORKAROUND_SPECULATIVE_AT 707 help 708 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 709 710 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 711 corrupted TLBs by speculating an AT instruction during a guest 712 context switch. 713 714 If unsure, say Y. 715 716config ARM64_WORKAROUND_REPEAT_TLBI 717 bool 718 719config ARM64_ERRATUM_2441007 720 bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 721 select ARM64_WORKAROUND_REPEAT_TLBI 722 help 723 This option adds a workaround for ARM Cortex-A55 erratum #2441007. 724 725 Under very rare circumstances, affected Cortex-A55 CPUs 726 may not handle a race between a break-before-make sequence on one 727 CPU, and another CPU accessing the same page. This could allow a 728 store to a page that has been unmapped. 729 730 Work around this by adding the affected CPUs to the list that needs 731 TLB sequences to be done twice. 732 733 If unsure, say N. 734 735config ARM64_ERRATUM_1286807 736 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation (rare)" 737 select ARM64_WORKAROUND_REPEAT_TLBI 738 help 739 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 740 741 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 742 address for a cacheable mapping of a location is being 743 accessed by a core while another core is remapping the virtual 744 address to a new physical page using the recommended 745 break-before-make sequence, then under very rare circumstances 746 TLBI+DSB completes before a read using the translation being 747 invalidated has been observed by other observers. The 748 workaround repeats the TLBI+DSB operation. 749 750 If unsure, say N. 751 752config ARM64_ERRATUM_1463225 753 bool "Cortex-A76: Software Step might prevent interrupt recognition" 754 default y 755 help 756 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 757 758 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 759 of a system call instruction (SVC) can prevent recognition of 760 subsequent interrupts when software stepping is disabled in the 761 exception handler of the system call and either kernel debugging 762 is enabled or VHE is in use. 763 764 Work around the erratum by triggering a dummy step exception 765 when handling a system call from a task that is being stepped 766 in a VHE configuration of the kernel. 767 768 If unsure, say Y. 769 770config ARM64_ERRATUM_1542419 771 bool "Neoverse-N1: workaround mis-ordering of instruction fetches (rare)" 772 help 773 This option adds a workaround for ARM Neoverse-N1 erratum 774 1542419. 775 776 Affected Neoverse-N1 cores could execute a stale instruction when 777 modified by another CPU. The workaround depends on a firmware 778 counterpart. 779 780 Workaround the issue by hiding the DIC feature from EL0. This 781 forces user-space to perform cache maintenance. 782 783 If unsure, say N. 784 785config ARM64_ERRATUM_1508412 786 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 787 default y 788 help 789 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 790 791 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 792 of a store-exclusive or read of PAR_EL1 and a load with device or 793 non-cacheable memory attributes. The workaround depends on a firmware 794 counterpart. 795 796 KVM guests must also have the workaround implemented or they can 797 deadlock the system. 798 799 Work around the issue by inserting DMB SY barriers around PAR_EL1 800 register reads and warning KVM users. The DMB barrier is sufficient 801 to prevent a speculative PAR_EL1 read. 802 803 If unsure, say Y. 804 805config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 806 bool 807 808config ARM64_ERRATUM_2051678 809 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 810 default y 811 help 812 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 813 Affected Cortex-A510 might not respect the ordering rules for 814 hardware update of the page table's dirty bit. The workaround 815 is to not enable the feature on affected CPUs. 816 817 If unsure, say Y. 818 819config ARM64_ERRATUM_2077057 820 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 821 default y 822 help 823 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 824 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 825 expected, but a Pointer Authentication trap is taken instead. The 826 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 827 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 828 829 This can only happen when EL2 is stepping EL1. 830 831 When these conditions occur, the SPSR_EL2 value is unchanged from the 832 previous guest entry, and can be restored from the in-memory copy. 833 834 If unsure, say Y. 835 836config ARM64_ERRATUM_2658417 837 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result" 838 default y 839 help 840 This option adds the workaround for ARM Cortex-A510 erratum 2658417. 841 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for 842 BFMMLA or VMMLA instructions in rare circumstances when a pair of 843 A510 CPUs are using shared neon hardware. As the sharing is not 844 discoverable by the kernel, hide the BF16 HWCAP to indicate that 845 user-space should not be using these instructions. 846 847 If unsure, say Y. 848 849config ARM64_ERRATUM_2119858 850 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 851 default y 852 depends on CORESIGHT_TRBE 853 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 854 help 855 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 856 857 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 858 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 859 the event of a WRAP event. 860 861 Work around the issue by always making sure we move the TRBPTR_EL1 by 862 256 bytes before enabling the buffer and filling the first 256 bytes of 863 the buffer with ETM ignore packets upon disabling. 864 865 If unsure, say Y. 866 867config ARM64_ERRATUM_2139208 868 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 869 default y 870 depends on CORESIGHT_TRBE 871 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 872 help 873 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 874 875 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 876 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 877 the event of a WRAP event. 878 879 Work around the issue by always making sure we move the TRBPTR_EL1 by 880 256 bytes before enabling the buffer and filling the first 256 bytes of 881 the buffer with ETM ignore packets upon disabling. 882 883 If unsure, say Y. 884 885config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 886 bool 887 888config ARM64_ERRATUM_2054223 889 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 890 default y 891 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 892 help 893 Enable workaround for ARM Cortex-A710 erratum 2054223 894 895 Affected cores may fail to flush the trace data on a TSB instruction, when 896 the PE is in trace prohibited state. This will cause losing a few bytes 897 of the trace cached. 898 899 Workaround is to issue two TSB consecutively on affected cores. 900 901 If unsure, say Y. 902 903config ARM64_ERRATUM_2067961 904 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 905 default y 906 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 907 help 908 Enable workaround for ARM Neoverse-N2 erratum 2067961 909 910 Affected cores may fail to flush the trace data on a TSB instruction, when 911 the PE is in trace prohibited state. This will cause losing a few bytes 912 of the trace cached. 913 914 Workaround is to issue two TSB consecutively on affected cores. 915 916 If unsure, say Y. 917 918config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 919 bool 920 921config ARM64_ERRATUM_2253138 922 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 923 depends on CORESIGHT_TRBE 924 default y 925 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 926 help 927 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 928 929 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 930 for TRBE. Under some conditions, the TRBE might generate a write to the next 931 virtually addressed page following the last page of the TRBE address space 932 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 933 934 Work around this in the driver by always making sure that there is a 935 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 936 937 If unsure, say Y. 938 939config ARM64_ERRATUM_2224489 940 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 941 depends on CORESIGHT_TRBE 942 default y 943 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 944 help 945 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 946 947 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 948 for TRBE. Under some conditions, the TRBE might generate a write to the next 949 virtually addressed page following the last page of the TRBE address space 950 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 951 952 Work around this in the driver by always making sure that there is a 953 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 954 955 If unsure, say Y. 956 957config ARM64_ERRATUM_2441009 958 bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of a TLBI (rare)" 959 select ARM64_WORKAROUND_REPEAT_TLBI 960 help 961 This option adds a workaround for ARM Cortex-A510 erratum #2441009. 962 963 Under very rare circumstances, affected Cortex-A510 CPUs 964 may not handle a race between a break-before-make sequence on one 965 CPU, and another CPU accessing the same page. This could allow a 966 store to a page that has been unmapped. 967 968 Work around this by adding the affected CPUs to the list that needs 969 TLB sequences to be done twice. 970 971 If unsure, say N. 972 973config ARM64_ERRATUM_2064142 974 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 975 depends on CORESIGHT_TRBE 976 default y 977 help 978 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 979 980 Affected Cortex-A510 core might fail to write into system registers after the 981 TRBE has been disabled. Under some conditions after the TRBE has been disabled 982 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 983 and TRBTRG_EL1 will be ignored and will not be effected. 984 985 Work around this in the driver by executing TSB CSYNC and DSB after collection 986 is stopped and before performing a system register write to one of the affected 987 registers. 988 989 If unsure, say Y. 990 991config ARM64_ERRATUM_2038923 992 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 993 depends on CORESIGHT_TRBE 994 default y 995 help 996 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 997 998 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 999 prohibited within the CPU. As a result, the trace buffer or trace buffer state 1000 might be corrupted. This happens after TRBE buffer has been enabled by setting 1001 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 1002 execution changes from a context, in which trace is prohibited to one where it 1003 isn't, or vice versa. In these mentioned conditions, the view of whether trace 1004 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 1005 the trace buffer state might be corrupted. 1006 1007 Work around this in the driver by preventing an inconsistent view of whether the 1008 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 1009 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 1010 two ISB instructions if no ERET is to take place. 1011 1012 If unsure, say Y. 1013 1014config ARM64_ERRATUM_1902691 1015 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 1016 depends on CORESIGHT_TRBE 1017 default y 1018 help 1019 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 1020 1021 Affected Cortex-A510 core might cause trace data corruption, when being written 1022 into the memory. Effectively TRBE is broken and hence cannot be used to capture 1023 trace data. 1024 1025 Work around this problem in the driver by just preventing TRBE initialization on 1026 affected cpus. The firmware must have disabled the access to TRBE for the kernel 1027 on such implementations. This will cover the kernel for any firmware that doesn't 1028 do this already. 1029 1030 If unsure, say Y. 1031 1032config ARM64_ERRATUM_2457168 1033 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly" 1034 depends on ARM64_AMU_EXTN 1035 default y 1036 help 1037 This option adds the workaround for ARM Cortex-A510 erratum 2457168. 1038 1039 The AMU counter AMEVCNTR01 (constant counter) should increment at the same rate 1040 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments 1041 incorrectly giving a significantly higher output value. 1042 1043 Work around this problem by returning 0 when reading the affected counter in 1044 key locations that results in disabling all users of this counter. This effect 1045 is the same to firmware disabling affected counters. 1046 1047 If unsure, say Y. 1048 1049config ARM64_ERRATUM_2645198 1050 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption" 1051 default y 1052 help 1053 This option adds the workaround for ARM Cortex-A715 erratum 2645198. 1054 1055 If a Cortex-A715 cpu sees a page mapping permissions change from executable 1056 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the 1057 next instruction abort caused by permission fault. 1058 1059 Only user-space does executable to non-executable permission transition via 1060 mprotect() system call. Workaround the problem by doing a break-before-make 1061 TLB invalidation, for all changes to executable user space mappings. 1062 1063 If unsure, say Y. 1064 1065config ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1066 bool 1067 1068config ARM64_ERRATUM_2966298 1069 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load" 1070 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1071 default y 1072 help 1073 This option adds the workaround for ARM Cortex-A520 erratum 2966298. 1074 1075 On an affected Cortex-A520 core, a speculatively executed unprivileged 1076 load might leak data from a privileged level via a cache side channel. 1077 1078 Work around this problem by executing a TLBI before returning to EL0. 1079 1080 If unsure, say Y. 1081 1082config ARM64_ERRATUM_3117295 1083 bool "Cortex-A510: 3117295: workaround for speculatively executed unprivileged load" 1084 select ARM64_WORKAROUND_SPECULATIVE_UNPRIV_LOAD 1085 default y 1086 help 1087 This option adds the workaround for ARM Cortex-A510 erratum 3117295. 1088 1089 On an affected Cortex-A510 core, a speculatively executed unprivileged 1090 load might leak data from a privileged level via a cache side channel. 1091 1092 Work around this problem by executing a TLBI before returning to EL0. 1093 1094 If unsure, say Y. 1095 1096config ARM64_ERRATUM_3194386 1097 bool "Cortex-*/Neoverse-*: workaround for MSR SSBS not self-synchronizing" 1098 default y 1099 help 1100 This option adds the workaround for the following errata: 1101 1102 * ARM Cortex-A76 erratum 3324349 1103 * ARM Cortex-A77 erratum 3324348 1104 * ARM Cortex-A78 erratum 3324344 1105 * ARM Cortex-A78C erratum 3324346 1106 * ARM Cortex-A78C erratum 3324347 1107 * ARM Cortex-A710 erratam 3324338 1108 * ARM Cortex-A715 errartum 3456084 1109 * ARM Cortex-A720 erratum 3456091 1110 * ARM Cortex-A725 erratum 3456106 1111 * ARM Cortex-X1 erratum 3324344 1112 * ARM Cortex-X1C erratum 3324346 1113 * ARM Cortex-X2 erratum 3324338 1114 * ARM Cortex-X3 erratum 3324335 1115 * ARM Cortex-X4 erratum 3194386 1116 * ARM Cortex-X925 erratum 3324334 1117 * ARM Neoverse-N1 erratum 3324349 1118 * ARM Neoverse N2 erratum 3324339 1119 * ARM Neoverse-N3 erratum 3456111 1120 * ARM Neoverse-V1 erratum 3324341 1121 * ARM Neoverse V2 erratum 3324336 1122 * ARM Neoverse-V3 erratum 3312417 1123 1124 On affected cores "MSR SSBS, #0" instructions may not affect 1125 subsequent speculative instructions, which may permit unexepected 1126 speculative store bypassing. 1127 1128 Work around this problem by placing a Speculation Barrier (SB) or 1129 Instruction Synchronization Barrier (ISB) after kernel changes to 1130 SSBS. The presence of the SSBS special-purpose register is hidden 1131 from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such that userspace 1132 will use the PR_SPEC_STORE_BYPASS prctl to change SSBS. 1133 1134 If unsure, say Y. 1135 1136config CAVIUM_ERRATUM_22375 1137 bool "Cavium erratum 22375, 24313" 1138 default y 1139 help 1140 Enable workaround for errata 22375 and 24313. 1141 1142 This implements two gicv3-its errata workarounds for ThunderX. Both 1143 with a small impact affecting only ITS table allocation. 1144 1145 erratum 22375: only alloc 8MB table size 1146 erratum 24313: ignore memory access type 1147 1148 The fixes are in ITS initialization and basically ignore memory access 1149 type and table size provided by the TYPER and BASER registers. 1150 1151 If unsure, say Y. 1152 1153config CAVIUM_ERRATUM_23144 1154 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 1155 depends on NUMA 1156 default y 1157 help 1158 ITS SYNC command hang for cross node io and collections/cpu mapping. 1159 1160 If unsure, say Y. 1161 1162config CAVIUM_ERRATUM_23154 1163 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 1164 default y 1165 help 1166 The ThunderX GICv3 implementation requires a modified version for 1167 reading the IAR status to ensure data synchronization 1168 (access to icc_iar1_el1 is not sync'ed before and after). 1169 1170 It also suffers from erratum 38545 (also present on Marvell's 1171 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 1172 spuriously presented to the CPU interface. 1173 1174 If unsure, say Y. 1175 1176config CAVIUM_ERRATUM_27456 1177 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 1178 default y 1179 help 1180 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 1181 instructions may cause the icache to become corrupted if it 1182 contains data for a non-current ASID. The fix is to 1183 invalidate the icache when changing the mm context. 1184 1185 If unsure, say Y. 1186 1187config CAVIUM_ERRATUM_30115 1188 bool "Cavium erratum 30115: Guest may disable interrupts in host" 1189 default y 1190 help 1191 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 1192 1.2, and T83 Pass 1.0, KVM guest execution may disable 1193 interrupts in host. Trapping both GICv3 group-0 and group-1 1194 accesses sidesteps the issue. 1195 1196 If unsure, say Y. 1197 1198config CAVIUM_TX2_ERRATUM_219 1199 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 1200 default y 1201 help 1202 On Cavium ThunderX2, a load, store or prefetch instruction between a 1203 TTBR update and the corresponding context synchronizing operation can 1204 cause a spurious Data Abort to be delivered to any hardware thread in 1205 the CPU core. 1206 1207 Work around the issue by avoiding the problematic code sequence and 1208 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 1209 trap handler performs the corresponding register access, skips the 1210 instruction and ensures context synchronization by virtue of the 1211 exception return. 1212 1213 If unsure, say Y. 1214 1215config FUJITSU_ERRATUM_010001 1216 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 1217 default y 1218 help 1219 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 1220 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 1221 accesses may cause undefined fault (Data abort, DFSC=0b111111). 1222 This fault occurs under a specific hardware condition when a 1223 load/store instruction performs an address translation using: 1224 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 1225 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 1226 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 1227 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 1228 1229 The workaround is to ensure these bits are clear in TCR_ELx. 1230 The workaround only affects the Fujitsu-A64FX. 1231 1232 If unsure, say Y. 1233 1234config HISILICON_ERRATUM_161600802 1235 bool "Hip07 161600802: Erroneous redistributor VLPI base" 1236 default y 1237 help 1238 The HiSilicon Hip07 SoC uses the wrong redistributor base 1239 when issued ITS commands such as VMOVP and VMAPP, and requires 1240 a 128kB offset to be applied to the target address in this commands. 1241 1242 If unsure, say Y. 1243 1244config HISILICON_ERRATUM_162100801 1245 bool "Hip09 162100801 erratum support" 1246 default y 1247 help 1248 When enabling GICv4.1 in hip09, VMAPP will fail to clear some caches 1249 during unmapping operation, which will cause some vSGIs lost. 1250 To fix the issue, invalidate related vPE cache through GICR_INVALLR 1251 after VMOVP. 1252 1253 If unsure, say Y. 1254 1255config QCOM_FALKOR_ERRATUM_1003 1256 bool "Falkor E1003: Incorrect translation due to ASID change" 1257 default y 1258 help 1259 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 1260 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 1261 in TTBR1_EL1, this situation only occurs in the entry trampoline and 1262 then only for entries in the walk cache, since the leaf translation 1263 is unchanged. Work around the erratum by invalidating the walk cache 1264 entries for the trampoline before entering the kernel proper. 1265 1266config QCOM_FALKOR_ERRATUM_1009 1267 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1268 default y 1269 select ARM64_WORKAROUND_REPEAT_TLBI 1270 help 1271 On Falkor v1, the CPU may prematurely complete a DSB following a 1272 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1273 one more time to fix the issue. 1274 1275 If unsure, say Y. 1276 1277config QCOM_QDF2400_ERRATUM_0065 1278 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1279 default y 1280 help 1281 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1282 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1283 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1284 1285 If unsure, say Y. 1286 1287config QCOM_FALKOR_ERRATUM_E1041 1288 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1289 default y 1290 help 1291 Falkor CPU may speculatively fetch instructions from an improper 1292 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1293 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1294 1295 If unsure, say Y. 1296 1297config NVIDIA_CARMEL_CNP_ERRATUM 1298 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1299 default y 1300 help 1301 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1302 invalidate shared TLB entries installed by a different core, as it would 1303 on standard ARM cores. 1304 1305 If unsure, say Y. 1306 1307config ROCKCHIP_ERRATUM_3588001 1308 bool "Rockchip 3588001: GIC600 can not support shareability attributes" 1309 default y 1310 help 1311 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite. 1312 This means, that its sharability feature may not be used, even though it 1313 is supported by the IP itself. 1314 1315 If unsure, say Y. 1316 1317config SOCIONEXT_SYNQUACER_PREITS 1318 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1319 default y 1320 help 1321 Socionext Synquacer SoCs implement a separate h/w block to generate 1322 MSI doorbell writes with non-zero values for the device ID. 1323 1324 If unsure, say Y. 1325 1326endmenu # "ARM errata workarounds via the alternatives framework" 1327 1328choice 1329 prompt "Page size" 1330 default ARM64_4K_PAGES 1331 help 1332 Page size (translation granule) configuration. 1333 1334config ARM64_4K_PAGES 1335 bool "4KB" 1336 select HAVE_PAGE_SIZE_4KB 1337 help 1338 This feature enables 4KB pages support. 1339 1340config ARM64_16K_PAGES 1341 bool "16KB" 1342 select HAVE_PAGE_SIZE_16KB 1343 help 1344 The system will use 16KB pages support. AArch32 emulation 1345 requires applications compiled with 16K (or a multiple of 16K) 1346 aligned segments. 1347 1348config ARM64_64K_PAGES 1349 bool "64KB" 1350 select HAVE_PAGE_SIZE_64KB 1351 help 1352 This feature enables 64KB pages support (4KB by default) 1353 allowing only two levels of page tables and faster TLB 1354 look-up. AArch32 emulation requires applications compiled 1355 with 64K aligned segments. 1356 1357endchoice 1358 1359choice 1360 prompt "Virtual address space size" 1361 default ARM64_VA_BITS_52 1362 help 1363 Allows choosing one of multiple possible virtual address 1364 space sizes. The level of translation table is determined by 1365 a combination of page size and virtual address space size. 1366 1367config ARM64_VA_BITS_36 1368 bool "36-bit" if EXPERT 1369 depends on PAGE_SIZE_16KB 1370 1371config ARM64_VA_BITS_39 1372 bool "39-bit" 1373 depends on PAGE_SIZE_4KB 1374 1375config ARM64_VA_BITS_42 1376 bool "42-bit" 1377 depends on PAGE_SIZE_64KB 1378 1379config ARM64_VA_BITS_47 1380 bool "47-bit" 1381 depends on PAGE_SIZE_16KB 1382 1383config ARM64_VA_BITS_48 1384 bool "48-bit" 1385 1386config ARM64_VA_BITS_52 1387 bool "52-bit" 1388 help 1389 Enable 52-bit virtual addressing for userspace when explicitly 1390 requested via a hint to mmap(). The kernel will also use 52-bit 1391 virtual addresses for its own mappings (provided HW support for 1392 this feature is available, otherwise it reverts to 48-bit). 1393 1394 NOTE: Enabling 52-bit virtual addressing in conjunction with 1395 ARMv8.3 Pointer Authentication will result in the PAC being 1396 reduced from 7 bits to 3 bits, which may have a significant 1397 impact on its susceptibility to brute-force attacks. 1398 1399 If unsure, select 48-bit virtual addressing instead. 1400 1401endchoice 1402 1403config ARM64_FORCE_52BIT 1404 bool "Force 52-bit virtual addresses for userspace" 1405 depends on ARM64_VA_BITS_52 && EXPERT 1406 help 1407 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1408 to maintain compatibility with older software by providing 48-bit VAs 1409 unless a hint is supplied to mmap. 1410 1411 This configuration option disables the 48-bit compatibility logic, and 1412 forces all userspace addresses to be 52-bit on HW that supports it. One 1413 should only enable this configuration option for stress testing userspace 1414 memory management code. If unsure say N here. 1415 1416config ARM64_VA_BITS 1417 int 1418 default 36 if ARM64_VA_BITS_36 1419 default 39 if ARM64_VA_BITS_39 1420 default 42 if ARM64_VA_BITS_42 1421 default 47 if ARM64_VA_BITS_47 1422 default 48 if ARM64_VA_BITS_48 1423 default 52 if ARM64_VA_BITS_52 1424 1425choice 1426 prompt "Physical address space size" 1427 default ARM64_PA_BITS_48 1428 help 1429 Choose the maximum physical address range that the kernel will 1430 support. 1431 1432config ARM64_PA_BITS_48 1433 bool "48-bit" 1434 depends on ARM64_64K_PAGES || !ARM64_VA_BITS_52 1435 1436config ARM64_PA_BITS_52 1437 bool "52-bit" 1438 depends on ARM64_64K_PAGES || ARM64_VA_BITS_52 1439 help 1440 Enable support for a 52-bit physical address space, introduced as 1441 part of the ARMv8.2-LPA extension. 1442 1443 With this enabled, the kernel will also continue to work on CPUs that 1444 do not support ARMv8.2-LPA, but with some added memory overhead (and 1445 minor performance overhead). 1446 1447endchoice 1448 1449config ARM64_PA_BITS 1450 int 1451 default 48 if ARM64_PA_BITS_48 1452 default 52 if ARM64_PA_BITS_52 1453 1454config ARM64_LPA2 1455 def_bool y 1456 depends on ARM64_PA_BITS_52 && !ARM64_64K_PAGES 1457 1458choice 1459 prompt "Endianness" 1460 default CPU_LITTLE_ENDIAN 1461 help 1462 Select the endianness of data accesses performed by the CPU. Userspace 1463 applications will need to be compiled and linked for the endianness 1464 that is selected here. 1465 1466config CPU_BIG_ENDIAN 1467 bool "Build big-endian kernel" 1468 # https://github.com/llvm/llvm-project/commit/1379b150991f70a5782e9a143c2ba5308da1161c 1469 depends on AS_IS_GNU || AS_VERSION >= 150000 1470 help 1471 Say Y if you plan on running a kernel with a big-endian userspace. 1472 1473config CPU_LITTLE_ENDIAN 1474 bool "Build little-endian kernel" 1475 help 1476 Say Y if you plan on running a kernel with a little-endian userspace. 1477 This is usually the case for distributions targeting arm64. 1478 1479endchoice 1480 1481config SCHED_MC 1482 bool "Multi-core scheduler support" 1483 help 1484 Multi-core scheduler support improves the CPU scheduler's decision 1485 making when dealing with multi-core CPU chips at a cost of slightly 1486 increased overhead in some places. If unsure say N here. 1487 1488config SCHED_CLUSTER 1489 bool "Cluster scheduler support" 1490 help 1491 Cluster scheduler support improves the CPU scheduler's decision 1492 making when dealing with machines that have clusters of CPUs. 1493 Cluster usually means a couple of CPUs which are placed closely 1494 by sharing mid-level caches, last-level cache tags or internal 1495 busses. 1496 1497config SCHED_SMT 1498 bool "SMT scheduler support" 1499 help 1500 Improves the CPU scheduler's decision making when dealing with 1501 MultiThreading at a cost of slightly increased overhead in some 1502 places. If unsure say N here. 1503 1504config NR_CPUS 1505 int "Maximum number of CPUs (2-4096)" 1506 range 2 4096 1507 default "512" 1508 1509config HOTPLUG_CPU 1510 bool "Support for hot-pluggable CPUs" 1511 select GENERIC_IRQ_MIGRATION 1512 help 1513 Say Y here to experiment with turning CPUs off and on. CPUs 1514 can be controlled through /sys/devices/system/cpu. 1515 1516# Common NUMA Features 1517config NUMA 1518 bool "NUMA Memory Allocation and Scheduler Support" 1519 select GENERIC_ARCH_NUMA 1520 select OF_NUMA 1521 select HAVE_SETUP_PER_CPU_AREA 1522 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1523 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1524 select USE_PERCPU_NUMA_NODE_ID 1525 help 1526 Enable NUMA (Non-Uniform Memory Access) support. 1527 1528 The kernel will try to allocate memory used by a CPU on the 1529 local memory of the CPU and add some more 1530 NUMA awareness to the kernel. 1531 1532config NODES_SHIFT 1533 int "Maximum NUMA Nodes (as a power of 2)" 1534 range 1 10 1535 default "4" 1536 depends on NUMA 1537 help 1538 Specify the maximum number of NUMA Nodes available on the target 1539 system. Increases memory reserved to accommodate various tables. 1540 1541source "kernel/Kconfig.hz" 1542 1543config ARCH_SPARSEMEM_ENABLE 1544 def_bool y 1545 select SPARSEMEM_VMEMMAP_ENABLE 1546 select SPARSEMEM_VMEMMAP 1547 1548config HW_PERF_EVENTS 1549 def_bool y 1550 depends on ARM_PMU 1551 1552# Supported by clang >= 7.0 or GCC >= 12.0.0 1553config CC_HAVE_SHADOW_CALL_STACK 1554 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1555 1556config PARAVIRT 1557 bool "Enable paravirtualization code" 1558 help 1559 This changes the kernel so it can modify itself when it is run 1560 under a hypervisor, potentially improving performance significantly 1561 over full virtualization. 1562 1563config PARAVIRT_TIME_ACCOUNTING 1564 bool "Paravirtual steal time accounting" 1565 select PARAVIRT 1566 help 1567 Select this option to enable fine granularity task steal time 1568 accounting. Time spent executing other tasks in parallel with 1569 the current vCPU is discounted from the vCPU power. To account for 1570 that, there can be a small performance impact. 1571 1572 If in doubt, say N here. 1573 1574config ARCH_SUPPORTS_KEXEC 1575 def_bool PM_SLEEP_SMP 1576 1577config ARCH_SUPPORTS_KEXEC_FILE 1578 def_bool y 1579 1580config ARCH_SELECTS_KEXEC_FILE 1581 def_bool y 1582 depends on KEXEC_FILE 1583 select HAVE_IMA_KEXEC if IMA 1584 1585config ARCH_SUPPORTS_KEXEC_SIG 1586 def_bool y 1587 1588config ARCH_SUPPORTS_KEXEC_IMAGE_VERIFY_SIG 1589 def_bool y 1590 1591config ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG 1592 def_bool y 1593 1594config ARCH_SUPPORTS_CRASH_DUMP 1595 def_bool y 1596 1597config ARCH_DEFAULT_CRASH_DUMP 1598 def_bool y 1599 1600config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION 1601 def_bool CRASH_RESERVE 1602 1603config TRANS_TABLE 1604 def_bool y 1605 depends on HIBERNATION || KEXEC_CORE 1606 1607config XEN_DOM0 1608 def_bool y 1609 depends on XEN 1610 1611config XEN 1612 bool "Xen guest support on ARM64" 1613 depends on ARM64 && OF 1614 select SWIOTLB_XEN 1615 select PARAVIRT 1616 help 1617 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1618 1619# include/linux/mmzone.h requires the following to be true: 1620# 1621# MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1622# 1623# so the maximum value of MAX_PAGE_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT: 1624# 1625# | SECTION_SIZE_BITS | PAGE_SHIFT | max MAX_PAGE_ORDER | default MAX_PAGE_ORDER | 1626# ----+-------------------+--------------+----------------------+-------------------------+ 1627# 4K | 27 | 12 | 15 | 10 | 1628# 16K | 27 | 14 | 13 | 11 | 1629# 64K | 29 | 16 | 13 | 13 | 1630config ARCH_FORCE_MAX_ORDER 1631 int 1632 default "13" if ARM64_64K_PAGES 1633 default "11" if ARM64_16K_PAGES 1634 default "10" 1635 help 1636 The kernel page allocator limits the size of maximal physically 1637 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1638 defines the maximal power of two of number of pages that can be 1639 allocated as a single contiguous block. This option allows 1640 overriding the default setting when ability to allocate very 1641 large blocks of physically contiguous memory is required. 1642 1643 The maximal size of allocation cannot exceed the size of the 1644 section, so the value of MAX_PAGE_ORDER should satisfy 1645 1646 MAX_PAGE_ORDER + PAGE_SHIFT <= SECTION_SIZE_BITS 1647 1648 Don't change if unsure. 1649 1650config UNMAP_KERNEL_AT_EL0 1651 bool "Unmap kernel when running in userspace (KPTI)" if EXPERT 1652 default y 1653 help 1654 Speculation attacks against some high-performance processors can 1655 be used to bypass MMU permission checks and leak kernel data to 1656 userspace. This can be defended against by unmapping the kernel 1657 when running in userspace, mapping it back in on exception entry 1658 via a trampoline page in the vector table. 1659 1660 If unsure, say Y. 1661 1662config MITIGATE_SPECTRE_BRANCH_HISTORY 1663 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1664 default y 1665 help 1666 Speculation attacks against some high-performance processors can 1667 make use of branch history to influence future speculation. 1668 When taking an exception from user-space, a sequence of branches 1669 or a firmware call overwrites the branch history. 1670 1671config RODATA_FULL_DEFAULT_ENABLED 1672 bool "Apply r/o permissions of VM areas also to their linear aliases" 1673 default y 1674 help 1675 Apply read-only attributes of VM areas to the linear alias of 1676 the backing pages as well. This prevents code or read-only data 1677 from being modified (inadvertently or intentionally) via another 1678 mapping of the same memory page. This additional enhancement can 1679 be turned off at runtime by passing rodata=[off|on] (and turned on 1680 with rodata=full if this option is set to 'n') 1681 1682 This requires the linear region to be mapped down to pages, 1683 which may adversely affect performance in some cases. 1684 1685config ARM64_SW_TTBR0_PAN 1686 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1687 depends on !KCSAN 1688 select ARM64_PAN 1689 help 1690 Enabling this option prevents the kernel from accessing 1691 user-space memory directly by pointing TTBR0_EL1 to a reserved 1692 zeroed area and reserved ASID. The user access routines 1693 restore the valid TTBR0_EL1 temporarily. 1694 1695config ARM64_TAGGED_ADDR_ABI 1696 bool "Enable the tagged user addresses syscall ABI" 1697 default y 1698 help 1699 When this option is enabled, user applications can opt in to a 1700 relaxed ABI via prctl() allowing tagged addresses to be passed 1701 to system calls as pointer arguments. For details, see 1702 Documentation/arch/arm64/tagged-address-abi.rst. 1703 1704menuconfig COMPAT 1705 bool "Kernel support for 32-bit EL0" 1706 depends on ARM64_4K_PAGES || EXPERT 1707 select HAVE_UID16 1708 select OLD_SIGSUSPEND3 1709 select COMPAT_OLD_SIGACTION 1710 help 1711 This option enables support for a 32-bit EL0 running under a 64-bit 1712 kernel at EL1. AArch32-specific components such as system calls, 1713 the user helper functions, VFP support and the ptrace interface are 1714 handled appropriately by the kernel. 1715 1716 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1717 that you will only be able to execute AArch32 binaries that were compiled 1718 with page size aligned segments. 1719 1720 If you want to execute 32-bit userspace applications, say Y. 1721 1722if COMPAT 1723 1724config KUSER_HELPERS 1725 bool "Enable kuser helpers page for 32-bit applications" 1726 default y 1727 help 1728 Warning: disabling this option may break 32-bit user programs. 1729 1730 Provide kuser helpers to compat tasks. The kernel provides 1731 helper code to userspace in read only form at a fixed location 1732 to allow userspace to be independent of the CPU type fitted to 1733 the system. This permits binaries to be run on ARMv4 through 1734 to ARMv8 without modification. 1735 1736 See Documentation/arch/arm/kernel_user_helpers.rst for details. 1737 1738 However, the fixed address nature of these helpers can be used 1739 by ROP (return orientated programming) authors when creating 1740 exploits. 1741 1742 If all of the binaries and libraries which run on your platform 1743 are built specifically for your platform, and make no use of 1744 these helpers, then you can turn this option off to hinder 1745 such exploits. However, in that case, if a binary or library 1746 relying on those helpers is run, it will not function correctly. 1747 1748 Say N here only if you are absolutely certain that you do not 1749 need these helpers; otherwise, the safe option is to say Y. 1750 1751config COMPAT_VDSO 1752 bool "Enable vDSO for 32-bit applications" 1753 depends on !CPU_BIG_ENDIAN 1754 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1755 select GENERIC_COMPAT_VDSO 1756 default y 1757 help 1758 Place in the process address space of 32-bit applications an 1759 ELF shared object providing fast implementations of gettimeofday 1760 and clock_gettime. 1761 1762 You must have a 32-bit build of glibc 2.22 or later for programs 1763 to seamlessly take advantage of this. 1764 1765config THUMB2_COMPAT_VDSO 1766 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1767 depends on COMPAT_VDSO 1768 default y 1769 help 1770 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1771 otherwise with '-marm'. 1772 1773config COMPAT_ALIGNMENT_FIXUPS 1774 bool "Fix up misaligned multi-word loads and stores in user space" 1775 1776menuconfig ARMV8_DEPRECATED 1777 bool "Emulate deprecated/obsolete ARMv8 instructions" 1778 depends on SYSCTL 1779 help 1780 Legacy software support may require certain instructions 1781 that have been deprecated or obsoleted in the architecture. 1782 1783 Enable this config to enable selective emulation of these 1784 features. 1785 1786 If unsure, say Y 1787 1788if ARMV8_DEPRECATED 1789 1790config SWP_EMULATION 1791 bool "Emulate SWP/SWPB instructions" 1792 help 1793 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1794 they are always undefined. Say Y here to enable software 1795 emulation of these instructions for userspace using LDXR/STXR. 1796 This feature can be controlled at runtime with the abi.swp 1797 sysctl which is disabled by default. 1798 1799 In some older versions of glibc [<=2.8] SWP is used during futex 1800 trylock() operations with the assumption that the code will not 1801 be preempted. This invalid assumption may be more likely to fail 1802 with SWP emulation enabled, leading to deadlock of the user 1803 application. 1804 1805 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1806 on an external transaction monitoring block called a global 1807 monitor to maintain update atomicity. If your system does not 1808 implement a global monitor, this option can cause programs that 1809 perform SWP operations to uncached memory to deadlock. 1810 1811 If unsure, say Y 1812 1813config CP15_BARRIER_EMULATION 1814 bool "Emulate CP15 Barrier instructions" 1815 help 1816 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1817 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1818 strongly recommended to use the ISB, DSB, and DMB 1819 instructions instead. 1820 1821 Say Y here to enable software emulation of these 1822 instructions for AArch32 userspace code. When this option is 1823 enabled, CP15 barrier usage is traced which can help 1824 identify software that needs updating. This feature can be 1825 controlled at runtime with the abi.cp15_barrier sysctl. 1826 1827 If unsure, say Y 1828 1829config SETEND_EMULATION 1830 bool "Emulate SETEND instruction" 1831 help 1832 The SETEND instruction alters the data-endianness of the 1833 AArch32 EL0, and is deprecated in ARMv8. 1834 1835 Say Y here to enable software emulation of the instruction 1836 for AArch32 userspace code. This feature can be controlled 1837 at runtime with the abi.setend sysctl. 1838 1839 Note: All the cpus on the system must have mixed endian support at EL0 1840 for this feature to be enabled. If a new CPU - which doesn't support mixed 1841 endian - is hotplugged in after this feature has been enabled, there could 1842 be unexpected results in the applications. 1843 1844 If unsure, say Y 1845endif # ARMV8_DEPRECATED 1846 1847endif # COMPAT 1848 1849menu "ARMv8.1 architectural features" 1850 1851config ARM64_HW_AFDBM 1852 bool "Support for hardware updates of the Access and Dirty page flags" 1853 default y 1854 help 1855 The ARMv8.1 architecture extensions introduce support for 1856 hardware updates of the access and dirty information in page 1857 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1858 capable processors, accesses to pages with PTE_AF cleared will 1859 set this bit instead of raising an access flag fault. 1860 Similarly, writes to read-only pages with the DBM bit set will 1861 clear the read-only bit (AP[2]) instead of raising a 1862 permission fault. 1863 1864 Kernels built with this configuration option enabled continue 1865 to work on pre-ARMv8.1 hardware and the performance impact is 1866 minimal. If unsure, say Y. 1867 1868config ARM64_PAN 1869 bool "Enable support for Privileged Access Never (PAN)" 1870 default y 1871 help 1872 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1873 prevents the kernel or hypervisor from accessing user-space (EL0) 1874 memory directly. 1875 1876 Choosing this option will cause any unprotected (not using 1877 copy_to_user et al) memory access to fail with a permission fault. 1878 1879 The feature is detected at runtime, and will remain as a 'nop' 1880 instruction if the cpu does not implement the feature. 1881 1882config AS_HAS_LSE_ATOMICS 1883 def_bool $(as-instr,.arch_extension lse) 1884 1885config ARM64_LSE_ATOMICS 1886 bool 1887 default ARM64_USE_LSE_ATOMICS 1888 depends on AS_HAS_LSE_ATOMICS 1889 1890config ARM64_USE_LSE_ATOMICS 1891 bool "Atomic instructions" 1892 default y 1893 help 1894 As part of the Large System Extensions, ARMv8.1 introduces new 1895 atomic instructions that are designed specifically to scale in 1896 very large systems. 1897 1898 Say Y here to make use of these instructions for the in-kernel 1899 atomic routines. This incurs a small overhead on CPUs that do 1900 not support these instructions and requires the kernel to be 1901 built with binutils >= 2.25 in order for the new instructions 1902 to be used. 1903 1904endmenu # "ARMv8.1 architectural features" 1905 1906menu "ARMv8.2 architectural features" 1907 1908config AS_HAS_ARMV8_2 1909 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1910 1911config AS_HAS_SHA3 1912 def_bool $(as-instr,.arch armv8.2-a+sha3) 1913 1914config ARM64_PMEM 1915 bool "Enable support for persistent memory" 1916 select ARCH_HAS_PMEM_API 1917 select ARCH_HAS_UACCESS_FLUSHCACHE 1918 help 1919 Say Y to enable support for the persistent memory API based on the 1920 ARMv8.2 DCPoP feature. 1921 1922 The feature is detected at runtime, and the kernel will use DC CVAC 1923 operations if DC CVAP is not supported (following the behaviour of 1924 DC CVAP itself if the system does not define a point of persistence). 1925 1926config ARM64_RAS_EXTN 1927 bool "Enable support for RAS CPU Extensions" 1928 default y 1929 help 1930 CPUs that support the Reliability, Availability and Serviceability 1931 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1932 errors, classify them and report them to software. 1933 1934 On CPUs with these extensions system software can use additional 1935 barriers to determine if faults are pending and read the 1936 classification from a new set of registers. 1937 1938 Selecting this feature will allow the kernel to use these barriers 1939 and access the new registers if the system supports the extension. 1940 Platform RAS features may additionally depend on firmware support. 1941 1942config ARM64_CNP 1943 bool "Enable support for Common Not Private (CNP) translations" 1944 default y 1945 help 1946 Common Not Private (CNP) allows translation table entries to 1947 be shared between different PEs in the same inner shareable 1948 domain, so the hardware can use this fact to optimise the 1949 caching of such entries in the TLB. 1950 1951 Selecting this option allows the CNP feature to be detected 1952 at runtime, and does not affect PEs that do not implement 1953 this feature. 1954 1955endmenu # "ARMv8.2 architectural features" 1956 1957menu "ARMv8.3 architectural features" 1958 1959config ARM64_PTR_AUTH 1960 bool "Enable support for pointer authentication" 1961 default y 1962 help 1963 Pointer authentication (part of the ARMv8.3 Extensions) provides 1964 instructions for signing and authenticating pointers against secret 1965 keys, which can be used to mitigate Return Oriented Programming (ROP) 1966 and other attacks. 1967 1968 This option enables these instructions at EL0 (i.e. for userspace). 1969 Choosing this option will cause the kernel to initialise secret keys 1970 for each process at exec() time, with these keys being 1971 context-switched along with the process. 1972 1973 The feature is detected at runtime. If the feature is not present in 1974 hardware it will not be advertised to userspace/KVM guest nor will it 1975 be enabled. 1976 1977 If the feature is present on the boot CPU but not on a late CPU, then 1978 the late CPU will be parked. Also, if the boot CPU does not have 1979 address auth and the late CPU has then the late CPU will still boot 1980 but with the feature disabled. On such a system, this option should 1981 not be selected. 1982 1983config ARM64_PTR_AUTH_KERNEL 1984 bool "Use pointer authentication for kernel" 1985 default y 1986 depends on ARM64_PTR_AUTH 1987 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_ARMV8_3 1988 # Modern compilers insert a .note.gnu.property section note for PAC 1989 # which is only understood by binutils starting with version 2.33.1. 1990 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1991 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1992 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 1993 help 1994 If the compiler supports the -mbranch-protection or 1995 -msign-return-address flag (e.g. GCC 7 or later), then this option 1996 will cause the kernel itself to be compiled with return address 1997 protection. In this case, and if the target hardware is known to 1998 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1999 disabled with minimal loss of protection. 2000 2001 This feature works with FUNCTION_GRAPH_TRACER option only if 2002 DYNAMIC_FTRACE_WITH_ARGS is enabled. 2003 2004config CC_HAS_BRANCH_PROT_PAC_RET 2005 # GCC 9 or later, clang 8 or later 2006 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 2007 2008config CC_HAS_SIGN_RETURN_ADDRESS 2009 # GCC 7, 8 2010 def_bool $(cc-option,-msign-return-address=all) 2011 2012config AS_HAS_ARMV8_3 2013 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 2014 2015config AS_HAS_CFI_NEGATE_RA_STATE 2016 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 2017 2018config AS_HAS_LDAPR 2019 def_bool $(as-instr,.arch_extension rcpc) 2020 2021endmenu # "ARMv8.3 architectural features" 2022 2023menu "ARMv8.4 architectural features" 2024 2025config ARM64_AMU_EXTN 2026 bool "Enable support for the Activity Monitors Unit CPU extension" 2027 default y 2028 help 2029 The activity monitors extension is an optional extension introduced 2030 by the ARMv8.4 CPU architecture. This enables support for version 1 2031 of the activity monitors architecture, AMUv1. 2032 2033 To enable the use of this extension on CPUs that implement it, say Y. 2034 2035 Note that for architectural reasons, firmware _must_ implement AMU 2036 support when running on CPUs that present the activity monitors 2037 extension. The required support is present in: 2038 * Version 1.5 and later of the ARM Trusted Firmware 2039 2040 For kernels that have this configuration enabled but boot with broken 2041 firmware, you may need to say N here until the firmware is fixed. 2042 Otherwise you may experience firmware panics or lockups when 2043 accessing the counter registers. Even if you are not observing these 2044 symptoms, the values returned by the register reads might not 2045 correctly reflect reality. Most commonly, the value read will be 0, 2046 indicating that the counter is not enabled. 2047 2048config AS_HAS_ARMV8_4 2049 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 2050 2051config ARM64_TLB_RANGE 2052 bool "Enable support for tlbi range feature" 2053 default y 2054 depends on AS_HAS_ARMV8_4 2055 help 2056 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 2057 range of input addresses. 2058 2059 The feature introduces new assembly instructions, and they were 2060 support when binutils >= 2.30. 2061 2062endmenu # "ARMv8.4 architectural features" 2063 2064menu "ARMv8.5 architectural features" 2065 2066config AS_HAS_ARMV8_5 2067 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 2068 2069config ARM64_BTI 2070 bool "Branch Target Identification support" 2071 default y 2072 help 2073 Branch Target Identification (part of the ARMv8.5 Extensions) 2074 provides a mechanism to limit the set of locations to which computed 2075 branch instructions such as BR or BLR can jump. 2076 2077 To make use of BTI on CPUs that support it, say Y. 2078 2079 BTI is intended to provide complementary protection to other control 2080 flow integrity protection mechanisms, such as the Pointer 2081 authentication mechanism provided as part of the ARMv8.3 Extensions. 2082 For this reason, it does not make sense to enable this option without 2083 also enabling support for pointer authentication. Thus, when 2084 enabling this option you should also select ARM64_PTR_AUTH=y. 2085 2086 Userspace binaries must also be specifically compiled to make use of 2087 this mechanism. If you say N here or the hardware does not support 2088 BTI, such binaries can still run, but you get no additional 2089 enforcement of branch destinations. 2090 2091config ARM64_BTI_KERNEL 2092 bool "Use Branch Target Identification for kernel" 2093 default y 2094 depends on ARM64_BTI 2095 depends on ARM64_PTR_AUTH_KERNEL 2096 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 2097 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 2098 depends on !CC_IS_GCC || GCC_VERSION >= 100100 2099 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671 2100 depends on !CC_IS_GCC 2101 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_ARGS) 2102 help 2103 Build the kernel with Branch Target Identification annotations 2104 and enable enforcement of this for kernel code. When this option 2105 is enabled and the system supports BTI all kernel code including 2106 modular code must have BTI enabled. 2107 2108config CC_HAS_BRANCH_PROT_PAC_RET_BTI 2109 # GCC 9 or later, clang 8 or later 2110 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 2111 2112config ARM64_E0PD 2113 bool "Enable support for E0PD" 2114 default y 2115 help 2116 E0PD (part of the ARMv8.5 extensions) allows us to ensure 2117 that EL0 accesses made via TTBR1 always fault in constant time, 2118 providing similar benefits to KASLR as those provided by KPTI, but 2119 with lower overhead and without disrupting legitimate access to 2120 kernel memory such as SPE. 2121 2122 This option enables E0PD for TTBR1 where available. 2123 2124config ARM64_AS_HAS_MTE 2125 # Initial support for MTE went in binutils 2.32.0, checked with 2126 # ".arch armv8.5-a+memtag" below. However, this was incomplete 2127 # as a late addition to the final architecture spec (LDGM/STGM) 2128 # is only supported in the newer 2.32.x and 2.33 binutils 2129 # versions, hence the extra "stgm" instruction check below. 2130 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 2131 2132config ARM64_MTE 2133 bool "Memory Tagging Extension support" 2134 default y 2135 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 2136 depends on AS_HAS_ARMV8_5 2137 depends on AS_HAS_LSE_ATOMICS 2138 # Required for tag checking in the uaccess routines 2139 select ARM64_PAN 2140 select ARCH_HAS_SUBPAGE_FAULTS 2141 select ARCH_USES_HIGH_VMA_FLAGS 2142 select ARCH_USES_PG_ARCH_2 2143 select ARCH_USES_PG_ARCH_3 2144 help 2145 Memory Tagging (part of the ARMv8.5 Extensions) provides 2146 architectural support for run-time, always-on detection of 2147 various classes of memory error to aid with software debugging 2148 to eliminate vulnerabilities arising from memory-unsafe 2149 languages. 2150 2151 This option enables the support for the Memory Tagging 2152 Extension at EL0 (i.e. for userspace). 2153 2154 Selecting this option allows the feature to be detected at 2155 runtime. Any secondary CPU not implementing this feature will 2156 not be allowed a late bring-up. 2157 2158 Userspace binaries that want to use this feature must 2159 explicitly opt in. The mechanism for the userspace is 2160 described in: 2161 2162 Documentation/arch/arm64/memory-tagging-extension.rst. 2163 2164endmenu # "ARMv8.5 architectural features" 2165 2166menu "ARMv8.7 architectural features" 2167 2168config ARM64_EPAN 2169 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 2170 default y 2171 depends on ARM64_PAN 2172 help 2173 Enhanced Privileged Access Never (EPAN) allows Privileged 2174 Access Never to be used with Execute-only mappings. 2175 2176 The feature is detected at runtime, and will remain disabled 2177 if the cpu does not implement the feature. 2178endmenu # "ARMv8.7 architectural features" 2179 2180config AS_HAS_MOPS 2181 def_bool $(as-instr,.arch_extension mops) 2182 2183menu "ARMv8.9 architectural features" 2184 2185config ARM64_POE 2186 prompt "Permission Overlay Extension" 2187 def_bool y 2188 select ARCH_USES_HIGH_VMA_FLAGS 2189 select ARCH_HAS_PKEYS 2190 help 2191 The Permission Overlay Extension is used to implement Memory 2192 Protection Keys. Memory Protection Keys provides a mechanism for 2193 enforcing page-based protections, but without requiring modification 2194 of the page tables when an application changes protection domains. 2195 2196 For details, see Documentation/core-api/protection-keys.rst 2197 2198 If unsure, say y. 2199 2200config ARCH_PKEY_BITS 2201 int 2202 default 3 2203 2204config ARM64_HAFT 2205 bool "Support for Hardware managed Access Flag for Table Descriptors" 2206 depends on ARM64_HW_AFDBM 2207 default y 2208 help 2209 The ARMv8.9/ARMv9.5 introduces the feature Hardware managed Access 2210 Flag for Table descriptors. When enabled an architectural executed 2211 memory access will update the Access Flag in each Table descriptor 2212 which is accessed during the translation table walk and for which 2213 the Access Flag is 0. The Access Flag of the Table descriptor use 2214 the same bit of PTE_AF. 2215 2216 The feature will only be enabled if all the CPUs in the system 2217 support this feature. If unsure, say Y. 2218 2219endmenu # "ARMv8.9 architectural features" 2220 2221menu "v9.4 architectural features" 2222 2223config ARM64_GCS 2224 bool "Enable support for Guarded Control Stack (GCS)" 2225 default y 2226 select ARCH_HAS_USER_SHADOW_STACK 2227 select ARCH_USES_HIGH_VMA_FLAGS 2228 depends on !UPROBES 2229 help 2230 Guarded Control Stack (GCS) provides support for a separate 2231 stack with restricted access which contains only return 2232 addresses. This can be used to harden against some attacks 2233 by comparing return address used by the program with what is 2234 stored in the GCS, and may also be used to efficiently obtain 2235 the call stack for applications such as profiling. 2236 2237 The feature is detected at runtime, and will remain disabled 2238 if the system does not implement the feature. 2239 2240endmenu # "v9.4 architectural features" 2241 2242config ARM64_SVE 2243 bool "ARM Scalable Vector Extension support" 2244 default y 2245 help 2246 The Scalable Vector Extension (SVE) is an extension to the AArch64 2247 execution state which complements and extends the SIMD functionality 2248 of the base architecture to support much larger vectors and to enable 2249 additional vectorisation opportunities. 2250 2251 To enable use of this extension on CPUs that implement it, say Y. 2252 2253 On CPUs that support the SVE2 extensions, this option will enable 2254 those too. 2255 2256 Note that for architectural reasons, firmware _must_ implement SVE 2257 support when running on SVE capable hardware. The required support 2258 is present in: 2259 2260 * version 1.5 and later of the ARM Trusted Firmware 2261 * the AArch64 boot wrapper since commit 5e1261e08abf 2262 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 2263 2264 For other firmware implementations, consult the firmware documentation 2265 or vendor. 2266 2267 If you need the kernel to boot on SVE-capable hardware with broken 2268 firmware, you may need to say N here until you get your firmware 2269 fixed. Otherwise, you may experience firmware panics or lockups when 2270 booting the kernel. If unsure and you are not observing these 2271 symptoms, you should assume that it is safe to say Y. 2272 2273config ARM64_SME 2274 bool "ARM Scalable Matrix Extension support" 2275 default y 2276 depends on ARM64_SVE 2277 depends on BROKEN 2278 help 2279 The Scalable Matrix Extension (SME) is an extension to the AArch64 2280 execution state which utilises a substantial subset of the SVE 2281 instruction set, together with the addition of new architectural 2282 register state capable of holding two dimensional matrix tiles to 2283 enable various matrix operations. 2284 2285config ARM64_PSEUDO_NMI 2286 bool "Support for NMI-like interrupts" 2287 select ARM_GIC_V3 2288 help 2289 Adds support for mimicking Non-Maskable Interrupts through the use of 2290 GIC interrupt priority. This support requires version 3 or later of 2291 ARM GIC. 2292 2293 This high priority configuration for interrupts needs to be 2294 explicitly enabled by setting the kernel parameter 2295 "irqchip.gicv3_pseudo_nmi" to 1. 2296 2297 If unsure, say N 2298 2299if ARM64_PSEUDO_NMI 2300config ARM64_DEBUG_PRIORITY_MASKING 2301 bool "Debug interrupt priority masking" 2302 help 2303 This adds runtime checks to functions enabling/disabling 2304 interrupts when using priority masking. The additional checks verify 2305 the validity of ICC_PMR_EL1 when calling concerned functions. 2306 2307 If unsure, say N 2308endif # ARM64_PSEUDO_NMI 2309 2310config RELOCATABLE 2311 bool "Build a relocatable kernel image" if EXPERT 2312 select ARCH_HAS_RELR 2313 default y 2314 help 2315 This builds the kernel as a Position Independent Executable (PIE), 2316 which retains all relocation metadata required to relocate the 2317 kernel binary at runtime to a different virtual address than the 2318 address it was linked at. 2319 Since AArch64 uses the RELA relocation format, this requires a 2320 relocation pass at runtime even if the kernel is loaded at the 2321 same address it was linked at. 2322 2323config RANDOMIZE_BASE 2324 bool "Randomize the address of the kernel image" 2325 select RELOCATABLE 2326 help 2327 Randomizes the virtual address at which the kernel image is 2328 loaded, as a security feature that deters exploit attempts 2329 relying on knowledge of the location of kernel internals. 2330 2331 It is the bootloader's job to provide entropy, by passing a 2332 random u64 value in /chosen/kaslr-seed at kernel entry. 2333 2334 When booting via the UEFI stub, it will invoke the firmware's 2335 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2336 to the kernel proper. In addition, it will randomise the physical 2337 location of the kernel Image as well. 2338 2339 If unsure, say N. 2340 2341config RANDOMIZE_MODULE_REGION_FULL 2342 bool "Randomize the module region over a 2 GB range" 2343 depends on RANDOMIZE_BASE 2344 default y 2345 help 2346 Randomizes the location of the module region inside a 2 GB window 2347 covering the core kernel. This way, it is less likely for modules 2348 to leak information about the location of core kernel data structures 2349 but it does imply that function calls between modules and the core 2350 kernel will need to be resolved via veneers in the module PLT. 2351 2352 When this option is not set, the module region will be randomized over 2353 a limited range that contains the [_stext, _etext] interval of the 2354 core kernel, so branch relocations are almost always in range unless 2355 the region is exhausted. In this particular case of region 2356 exhaustion, modules might be able to fall back to a larger 2GB area. 2357 2358config CC_HAVE_STACKPROTECTOR_SYSREG 2359 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2360 2361config STACKPROTECTOR_PER_TASK 2362 def_bool y 2363 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2364 2365config UNWIND_PATCH_PAC_INTO_SCS 2366 bool "Enable shadow call stack dynamically using code patching" 2367 # needs Clang with https://github.com/llvm/llvm-project/commit/de07cde67b5d205d58690be012106022aea6d2b3 incorporated 2368 depends on CC_IS_CLANG && CLANG_VERSION >= 150000 2369 depends on ARM64_PTR_AUTH_KERNEL && CC_HAS_BRANCH_PROT_PAC_RET 2370 depends on SHADOW_CALL_STACK 2371 select UNWIND_TABLES 2372 select DYNAMIC_SCS 2373 2374config ARM64_CONTPTE 2375 bool "Contiguous PTE mappings for user memory" if EXPERT 2376 depends on TRANSPARENT_HUGEPAGE 2377 default y 2378 help 2379 When enabled, user mappings are configured using the PTE contiguous 2380 bit, for any mappings that meet the size and alignment requirements. 2381 This reduces TLB pressure and improves performance. 2382 2383endmenu # "Kernel Features" 2384 2385menu "Boot options" 2386 2387config ARM64_ACPI_PARKING_PROTOCOL 2388 bool "Enable support for the ARM64 ACPI parking protocol" 2389 depends on ACPI 2390 help 2391 Enable support for the ARM64 ACPI parking protocol. If disabled 2392 the kernel will not allow booting through the ARM64 ACPI parking 2393 protocol even if the corresponding data is present in the ACPI 2394 MADT table. 2395 2396config CMDLINE 2397 string "Default kernel command string" 2398 default "" 2399 help 2400 Provide a set of default command-line options at build time by 2401 entering them here. As a minimum, you should specify the the 2402 root device (e.g. root=/dev/nfs). 2403 2404choice 2405 prompt "Kernel command line type" 2406 depends on CMDLINE != "" 2407 default CMDLINE_FROM_BOOTLOADER 2408 help 2409 Choose how the kernel will handle the provided default kernel 2410 command line string. 2411 2412config CMDLINE_FROM_BOOTLOADER 2413 bool "Use bootloader kernel arguments if available" 2414 help 2415 Uses the command-line options passed by the boot loader. If 2416 the boot loader doesn't provide any, the default kernel command 2417 string provided in CMDLINE will be used. 2418 2419config CMDLINE_FORCE 2420 bool "Always use the default kernel command string" 2421 help 2422 Always use the default kernel command string, even if the boot 2423 loader passes other arguments to the kernel. 2424 This is useful if you cannot or don't want to change the 2425 command-line options your boot loader passes to the kernel. 2426 2427endchoice 2428 2429config EFI_STUB 2430 bool 2431 2432config EFI 2433 bool "UEFI runtime support" 2434 depends on OF && !CPU_BIG_ENDIAN 2435 depends on KERNEL_MODE_NEON 2436 select ARCH_SUPPORTS_ACPI 2437 select LIBFDT 2438 select UCS2_STRING 2439 select EFI_PARAMS_FROM_FDT 2440 select EFI_RUNTIME_WRAPPERS 2441 select EFI_STUB 2442 select EFI_GENERIC_STUB 2443 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2444 default y 2445 help 2446 This option provides support for runtime services provided 2447 by UEFI firmware (such as non-volatile variables, realtime 2448 clock, and platform reset). A UEFI stub is also provided to 2449 allow the kernel to be booted as an EFI application. This 2450 is only useful on systems that have UEFI firmware. 2451 2452config COMPRESSED_INSTALL 2453 bool "Install compressed image by default" 2454 help 2455 This makes the regular "make install" install the compressed 2456 image we built, not the legacy uncompressed one. 2457 2458 You can check that a compressed image works for you by doing 2459 "make zinstall" first, and verifying that everything is fine 2460 in your environment before making "make install" do this for 2461 you. 2462 2463config DMI 2464 bool "Enable support for SMBIOS (DMI) tables" 2465 depends on EFI 2466 default y 2467 help 2468 This enables SMBIOS/DMI feature for systems. 2469 2470 This option is only useful on systems that have UEFI firmware. 2471 However, even with this option, the resultant kernel should 2472 continue to boot on existing non-UEFI platforms. 2473 2474endmenu # "Boot options" 2475 2476menu "Power management options" 2477 2478source "kernel/power/Kconfig" 2479 2480config ARCH_HIBERNATION_POSSIBLE 2481 def_bool y 2482 depends on CPU_PM 2483 2484config ARCH_HIBERNATION_HEADER 2485 def_bool y 2486 depends on HIBERNATION 2487 2488config ARCH_SUSPEND_POSSIBLE 2489 def_bool y 2490 2491endmenu # "Power management options" 2492 2493menu "CPU Power Management" 2494 2495source "drivers/cpuidle/Kconfig" 2496 2497source "drivers/cpufreq/Kconfig" 2498 2499endmenu # "CPU Power Management" 2500 2501source "drivers/acpi/Kconfig" 2502 2503source "arch/arm64/kvm/Kconfig" 2504 2505