1# SPDX-License-Identifier: GPL-2.0-only 2config ARM64 3 def_bool y 4 select ACPI_CCA_REQUIRED if ACPI 5 select ACPI_GENERIC_GSI if ACPI 6 select ACPI_GTDT if ACPI 7 select ACPI_IORT if ACPI 8 select ACPI_REDUCED_HARDWARE_ONLY if ACPI 9 select ACPI_MCFG if (ACPI && PCI) 10 select ACPI_SPCR_TABLE if ACPI 11 select ACPI_PPTT if ACPI 12 select ARCH_HAS_DEBUG_WX 13 select ARCH_BINFMT_ELF_EXTRA_PHDRS 14 select ARCH_BINFMT_ELF_STATE 15 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE 16 select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION 17 select ARCH_ENABLE_MEMORY_HOTPLUG 18 select ARCH_ENABLE_MEMORY_HOTREMOVE 19 select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 20 select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE 21 select ARCH_HAS_CACHE_LINE_SIZE 22 select ARCH_HAS_CURRENT_STACK_POINTER 23 select ARCH_HAS_DEBUG_VIRTUAL 24 select ARCH_HAS_DEBUG_VM_PGTABLE 25 select ARCH_HAS_DMA_PREP_COHERENT 26 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI 27 select ARCH_HAS_FAST_MULTIPLIER 28 select ARCH_HAS_FORTIFY_SOURCE 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_HAS_GIGANTIC_PAGE 31 select ARCH_HAS_KCOV 32 select ARCH_HAS_KEEPINITRD 33 select ARCH_HAS_MEMBARRIER_SYNC_CORE 34 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 35 select ARCH_HAS_PTE_DEVMAP 36 select ARCH_HAS_PTE_SPECIAL 37 select ARCH_HAS_SETUP_DMA_OPS 38 select ARCH_HAS_SET_DIRECT_MAP 39 select ARCH_HAS_SET_MEMORY 40 select ARCH_STACKWALK 41 select ARCH_HAS_STRICT_KERNEL_RWX 42 select ARCH_HAS_STRICT_MODULE_RWX 43 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 44 select ARCH_HAS_SYNC_DMA_FOR_CPU 45 select ARCH_HAS_SYSCALL_WRAPPER 46 select ARCH_HAS_TEARDOWN_DMA_OPS if IOMMU_SUPPORT 47 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 48 select ARCH_HAS_ZONE_DMA_SET if EXPERT 49 select ARCH_HAVE_ELF_PROT 50 select ARCH_HAVE_NMI_SAFE_CMPXCHG 51 select ARCH_INLINE_READ_LOCK if !PREEMPTION 52 select ARCH_INLINE_READ_LOCK_BH if !PREEMPTION 53 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPTION 54 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPTION 55 select ARCH_INLINE_READ_UNLOCK if !PREEMPTION 56 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPTION 57 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPTION 58 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPTION 59 select ARCH_INLINE_WRITE_LOCK if !PREEMPTION 60 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPTION 61 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPTION 62 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPTION 63 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPTION 64 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPTION 65 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPTION 66 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPTION 67 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPTION 68 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPTION 69 select ARCH_INLINE_SPIN_LOCK if !PREEMPTION 70 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPTION 71 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPTION 72 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPTION 73 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPTION 74 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPTION 75 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPTION 76 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPTION 77 select ARCH_KEEP_MEMBLOCK 78 select ARCH_USE_CMPXCHG_LOCKREF 79 select ARCH_USE_GNU_PROPERTY 80 select ARCH_USE_MEMTEST 81 select ARCH_USE_QUEUED_RWLOCKS 82 select ARCH_USE_QUEUED_SPINLOCKS 83 select ARCH_USE_SYM_ANNOTATIONS 84 select ARCH_SUPPORTS_DEBUG_PAGEALLOC 85 select ARCH_SUPPORTS_HUGETLBFS 86 select ARCH_SUPPORTS_MEMORY_FAILURE 87 select ARCH_SUPPORTS_SHADOW_CALL_STACK if CC_HAVE_SHADOW_CALL_STACK 88 select ARCH_SUPPORTS_LTO_CLANG if CPU_LITTLE_ENDIAN 89 select ARCH_SUPPORTS_LTO_CLANG_THIN 90 select ARCH_SUPPORTS_CFI_CLANG 91 select ARCH_SUPPORTS_ATOMIC_RMW 92 select ARCH_SUPPORTS_INT128 if CC_HAS_INT128 93 select ARCH_SUPPORTS_NUMA_BALANCING 94 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION if COMPAT 95 select ARCH_WANT_DEFAULT_BPF_JIT 96 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT 97 select ARCH_WANT_FRAME_POINTERS 98 select ARCH_WANT_HUGE_PMD_SHARE if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36) 99 select ARCH_WANT_LD_ORPHAN_WARN 100 select ARCH_WANTS_NO_INSTR 101 select ARCH_HAS_UBSAN_SANITIZE_ALL 102 select ARM_AMBA 103 select ARM_ARCH_TIMER 104 select ARM_GIC 105 select AUDIT_ARCH_COMPAT_GENERIC 106 select ARM_GIC_V2M if PCI 107 select ARM_GIC_V3 108 select ARM_GIC_V3_ITS if PCI 109 select ARM_PSCI_FW 110 select BUILDTIME_TABLE_SORT 111 select CLONE_BACKWARDS 112 select COMMON_CLK 113 select CPU_PM if (SUSPEND || CPU_IDLE) 114 select CRC32 115 select DCACHE_WORD_ACCESS 116 select DMA_DIRECT_REMAP 117 select EDAC_SUPPORT 118 select FRAME_POINTER 119 select GENERIC_ALLOCATOR 120 select GENERIC_ARCH_TOPOLOGY 121 select GENERIC_CLOCKEVENTS_BROADCAST 122 select GENERIC_CPU_AUTOPROBE 123 select GENERIC_CPU_VULNERABILITIES 124 select GENERIC_EARLY_IOREMAP 125 select GENERIC_IDLE_POLL_SETUP 126 select GENERIC_IRQ_IPI 127 select GENERIC_IRQ_PROBE 128 select GENERIC_IRQ_SHOW 129 select GENERIC_IRQ_SHOW_LEVEL 130 select GENERIC_LIB_DEVMEM_IS_ALLOWED 131 select GENERIC_PCI_IOMAP 132 select GENERIC_PTDUMP 133 select GENERIC_SCHED_CLOCK 134 select GENERIC_SMP_IDLE_THREAD 135 select GENERIC_TIME_VSYSCALL 136 select GENERIC_GETTIMEOFDAY 137 select GENERIC_VDSO_TIME_NS 138 select HARDIRQS_SW_RESEND 139 select HAVE_MOVE_PMD 140 select HAVE_MOVE_PUD 141 select HAVE_PCI 142 select HAVE_ACPI_APEI if (ACPI && EFI) 143 select HAVE_ALIGNED_STRUCT_PAGE if SLUB 144 select HAVE_ARCH_AUDITSYSCALL 145 select HAVE_ARCH_BITREVERSE 146 select HAVE_ARCH_COMPILER_H 147 select HAVE_ARCH_HUGE_VMAP 148 select HAVE_ARCH_JUMP_LABEL 149 select HAVE_ARCH_JUMP_LABEL_RELATIVE 150 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48) 151 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 152 select HAVE_ARCH_KASAN_SW_TAGS if HAVE_ARCH_KASAN 153 select HAVE_ARCH_KASAN_HW_TAGS if (HAVE_ARCH_KASAN && ARM64_MTE) 154 # Some instrumentation may be unsound, hence EXPERT 155 select HAVE_ARCH_KCSAN if EXPERT 156 select HAVE_ARCH_KFENCE 157 select HAVE_ARCH_KGDB 158 select HAVE_ARCH_MMAP_RND_BITS 159 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT 160 select HAVE_ARCH_PREL32_RELOCATIONS 161 select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET 162 select HAVE_ARCH_SECCOMP_FILTER 163 select HAVE_ARCH_STACKLEAK 164 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 165 select HAVE_ARCH_TRACEHOOK 166 select HAVE_ARCH_TRANSPARENT_HUGEPAGE 167 select HAVE_ARCH_VMAP_STACK 168 select HAVE_ARM_SMCCC 169 select HAVE_ASM_MODVERSIONS 170 select HAVE_EBPF_JIT 171 select HAVE_C_RECORDMCOUNT 172 select HAVE_CMPXCHG_DOUBLE 173 select HAVE_CMPXCHG_LOCAL 174 select HAVE_CONTEXT_TRACKING 175 select HAVE_DEBUG_KMEMLEAK 176 select HAVE_DMA_CONTIGUOUS 177 select HAVE_DYNAMIC_FTRACE 178 select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY \ 179 if DYNAMIC_FTRACE_WITH_REGS 180 select HAVE_EFFICIENT_UNALIGNED_ACCESS 181 select HAVE_FAST_GUP 182 select HAVE_FTRACE_MCOUNT_RECORD 183 select HAVE_FUNCTION_TRACER 184 select HAVE_FUNCTION_ERROR_INJECTION 185 select HAVE_FUNCTION_GRAPH_TRACER 186 select HAVE_GCC_PLUGINS 187 select HAVE_HW_BREAKPOINT if PERF_EVENTS 188 select HAVE_IRQ_TIME_ACCOUNTING 189 select HAVE_KVM 190 select HAVE_NMI 191 select HAVE_PATA_PLATFORM 192 select HAVE_PERF_EVENTS 193 select HAVE_PERF_REGS 194 select HAVE_PERF_USER_STACK_DUMP 195 select HAVE_PREEMPT_DYNAMIC_KEY 196 select HAVE_REGS_AND_STACK_ACCESS_API 197 select HAVE_POSIX_CPU_TIMERS_TASK_WORK 198 select HAVE_FUNCTION_ARG_ACCESS_API 199 select MMU_GATHER_RCU_TABLE_FREE 200 select HAVE_RSEQ 201 select HAVE_STACKPROTECTOR 202 select HAVE_SYSCALL_TRACEPOINTS 203 select HAVE_KPROBES 204 select HAVE_KRETPROBES 205 select HAVE_GENERIC_VDSO 206 select IOMMU_DMA if IOMMU_SUPPORT 207 select IRQ_DOMAIN 208 select IRQ_FORCED_THREADING 209 select KASAN_VMALLOC if KASAN 210 select MODULES_USE_ELF_RELA 211 select NEED_DMA_MAP_STATE 212 select NEED_SG_DMA_LENGTH 213 select OF 214 select OF_EARLY_FLATTREE 215 select PCI_DOMAINS_GENERIC if PCI 216 select PCI_ECAM if (ACPI && PCI) 217 select PCI_SYSCALL if PCI 218 select POWER_RESET 219 select POWER_SUPPLY 220 select SPARSE_IRQ 221 select SWIOTLB 222 select SYSCTL_EXCEPTION_TRACE 223 select THREAD_INFO_IN_TASK 224 select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD 225 select TRACE_IRQFLAGS_SUPPORT 226 help 227 ARM 64-bit (AArch64) Linux support. 228 229config CLANG_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 230 def_bool CC_IS_CLANG 231 # https://github.com/ClangBuiltLinux/linux/issues/1507 232 depends on AS_IS_GNU || (AS_IS_LLVM && (LD_IS_LLD || LD_VERSION >= 23600)) 233 select HAVE_DYNAMIC_FTRACE_WITH_REGS 234 235config GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS 236 def_bool CC_IS_GCC 237 depends on $(cc-option,-fpatchable-function-entry=2) 238 select HAVE_DYNAMIC_FTRACE_WITH_REGS 239 240config 64BIT 241 def_bool y 242 243config MMU 244 def_bool y 245 246config ARM64_PAGE_SHIFT 247 int 248 default 16 if ARM64_64K_PAGES 249 default 14 if ARM64_16K_PAGES 250 default 12 251 252config ARM64_CONT_PTE_SHIFT 253 int 254 default 5 if ARM64_64K_PAGES 255 default 7 if ARM64_16K_PAGES 256 default 4 257 258config ARM64_CONT_PMD_SHIFT 259 int 260 default 5 if ARM64_64K_PAGES 261 default 5 if ARM64_16K_PAGES 262 default 4 263 264config ARCH_MMAP_RND_BITS_MIN 265 default 14 if ARM64_64K_PAGES 266 default 16 if ARM64_16K_PAGES 267 default 18 268 269# max bits determined by the following formula: 270# VA_BITS - PAGE_SHIFT - 3 271config ARCH_MMAP_RND_BITS_MAX 272 default 19 if ARM64_VA_BITS=36 273 default 24 if ARM64_VA_BITS=39 274 default 27 if ARM64_VA_BITS=42 275 default 30 if ARM64_VA_BITS=47 276 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES 277 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES 278 default 33 if ARM64_VA_BITS=48 279 default 14 if ARM64_64K_PAGES 280 default 16 if ARM64_16K_PAGES 281 default 18 282 283config ARCH_MMAP_RND_COMPAT_BITS_MIN 284 default 7 if ARM64_64K_PAGES 285 default 9 if ARM64_16K_PAGES 286 default 11 287 288config ARCH_MMAP_RND_COMPAT_BITS_MAX 289 default 16 290 291config NO_IOPORT_MAP 292 def_bool y if !PCI 293 294config STACKTRACE_SUPPORT 295 def_bool y 296 297config ILLEGAL_POINTER_VALUE 298 hex 299 default 0xdead000000000000 300 301config LOCKDEP_SUPPORT 302 def_bool y 303 304config GENERIC_BUG 305 def_bool y 306 depends on BUG 307 308config GENERIC_BUG_RELATIVE_POINTERS 309 def_bool y 310 depends on GENERIC_BUG 311 312config GENERIC_HWEIGHT 313 def_bool y 314 315config GENERIC_CSUM 316 def_bool y 317 318config GENERIC_CALIBRATE_DELAY 319 def_bool y 320 321config ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE 322 def_bool y 323 324config SMP 325 def_bool y 326 327config KERNEL_MODE_NEON 328 def_bool y 329 330config FIX_EARLYCON_MEM 331 def_bool y 332 333config PGTABLE_LEVELS 334 int 335 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 336 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 337 default 3 if ARM64_64K_PAGES && (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) 338 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 339 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 340 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 341 342config ARCH_SUPPORTS_UPROBES 343 def_bool y 344 345config ARCH_PROC_KCORE_TEXT 346 def_bool y 347 348config BROKEN_GAS_INST 349 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n) 350 351config KASAN_SHADOW_OFFSET 352 hex 353 depends on KASAN_GENERIC || KASAN_SW_TAGS 354 default 0xdfff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && !KASAN_SW_TAGS 355 default 0xdfffc00000000000 if ARM64_VA_BITS_47 && !KASAN_SW_TAGS 356 default 0xdffffe0000000000 if ARM64_VA_BITS_42 && !KASAN_SW_TAGS 357 default 0xdfffffc000000000 if ARM64_VA_BITS_39 && !KASAN_SW_TAGS 358 default 0xdffffff800000000 if ARM64_VA_BITS_36 && !KASAN_SW_TAGS 359 default 0xefff800000000000 if (ARM64_VA_BITS_48 || ARM64_VA_BITS_52) && KASAN_SW_TAGS 360 default 0xefffc00000000000 if ARM64_VA_BITS_47 && KASAN_SW_TAGS 361 default 0xeffffe0000000000 if ARM64_VA_BITS_42 && KASAN_SW_TAGS 362 default 0xefffffc000000000 if ARM64_VA_BITS_39 && KASAN_SW_TAGS 363 default 0xeffffff800000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS 364 default 0xffffffffffffffff 365 366source "arch/arm64/Kconfig.platforms" 367 368menu "Kernel Features" 369 370menu "ARM errata workarounds via the alternatives framework" 371 372config ARM64_WORKAROUND_CLEAN_CACHE 373 bool 374 375config ARM64_ERRATUM_826319 376 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted" 377 default y 378 select ARM64_WORKAROUND_CLEAN_CACHE 379 help 380 This option adds an alternative code sequence to work around ARM 381 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or 382 AXI master interface and an L2 cache. 383 384 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors 385 and is unable to accept a certain write via this interface, it will 386 not progress on read data presented on the read data channel and the 387 system can deadlock. 388 389 The workaround promotes data cache clean instructions to 390 data cache clean-and-invalidate. 391 Please note that this does not necessarily enable the workaround, 392 as it depends on the alternative framework, which will only patch 393 the kernel if an affected CPU is detected. 394 395 If unsure, say Y. 396 397config ARM64_ERRATUM_827319 398 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect" 399 default y 400 select ARM64_WORKAROUND_CLEAN_CACHE 401 help 402 This option adds an alternative code sequence to work around ARM 403 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI 404 master interface and an L2 cache. 405 406 Under certain conditions this erratum can cause a clean line eviction 407 to occur at the same time as another transaction to the same address 408 on the AMBA 5 CHI interface, which can cause data corruption if the 409 interconnect reorders the two transactions. 410 411 The workaround promotes data cache clean instructions to 412 data cache clean-and-invalidate. 413 Please note that this does not necessarily enable the workaround, 414 as it depends on the alternative framework, which will only patch 415 the kernel if an affected CPU is detected. 416 417 If unsure, say Y. 418 419config ARM64_ERRATUM_824069 420 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop" 421 default y 422 select ARM64_WORKAROUND_CLEAN_CACHE 423 help 424 This option adds an alternative code sequence to work around ARM 425 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected 426 to a coherent interconnect. 427 428 If a Cortex-A53 processor is executing a store or prefetch for 429 write instruction at the same time as a processor in another 430 cluster is executing a cache maintenance operation to the same 431 address, then this erratum might cause a clean cache line to be 432 incorrectly marked as dirty. 433 434 The workaround promotes data cache clean instructions to 435 data cache clean-and-invalidate. 436 Please note that this option does not necessarily enable the 437 workaround, as it depends on the alternative framework, which will 438 only patch the kernel if an affected CPU is detected. 439 440 If unsure, say Y. 441 442config ARM64_ERRATUM_819472 443 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption" 444 default y 445 select ARM64_WORKAROUND_CLEAN_CACHE 446 help 447 This option adds an alternative code sequence to work around ARM 448 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache 449 present when it is connected to a coherent interconnect. 450 451 If the processor is executing a load and store exclusive sequence at 452 the same time as a processor in another cluster is executing a cache 453 maintenance operation to the same address, then this erratum might 454 cause data corruption. 455 456 The workaround promotes data cache clean instructions to 457 data cache clean-and-invalidate. 458 Please note that this does not necessarily enable the workaround, 459 as it depends on the alternative framework, which will only patch 460 the kernel if an affected CPU is detected. 461 462 If unsure, say Y. 463 464config ARM64_ERRATUM_832075 465 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads" 466 default y 467 help 468 This option adds an alternative code sequence to work around ARM 469 erratum 832075 on Cortex-A57 parts up to r1p2. 470 471 Affected Cortex-A57 parts might deadlock when exclusive load/store 472 instructions to Write-Back memory are mixed with Device loads. 473 474 The workaround is to promote device loads to use Load-Acquire 475 semantics. 476 Please note that this does not necessarily enable the workaround, 477 as it depends on the alternative framework, which will only patch 478 the kernel if an affected CPU is detected. 479 480 If unsure, say Y. 481 482config ARM64_ERRATUM_834220 483 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault" 484 depends on KVM 485 default y 486 help 487 This option adds an alternative code sequence to work around ARM 488 erratum 834220 on Cortex-A57 parts up to r1p2. 489 490 Affected Cortex-A57 parts might report a Stage 2 translation 491 fault as the result of a Stage 1 fault for load crossing a 492 page boundary when there is a permission or device memory 493 alignment fault at Stage 1 and a translation fault at Stage 2. 494 495 The workaround is to verify that the Stage 1 translation 496 doesn't generate a fault before handling the Stage 2 fault. 497 Please note that this does not necessarily enable the workaround, 498 as it depends on the alternative framework, which will only patch 499 the kernel if an affected CPU is detected. 500 501 If unsure, say Y. 502 503config ARM64_ERRATUM_845719 504 bool "Cortex-A53: 845719: a load might read incorrect data" 505 depends on COMPAT 506 default y 507 help 508 This option adds an alternative code sequence to work around ARM 509 erratum 845719 on Cortex-A53 parts up to r0p4. 510 511 When running a compat (AArch32) userspace on an affected Cortex-A53 512 part, a load at EL0 from a virtual address that matches the bottom 32 513 bits of the virtual address used by a recent load at (AArch64) EL1 514 might return incorrect data. 515 516 The workaround is to write the contextidr_el1 register on exception 517 return to a 32-bit task. 518 Please note that this does not necessarily enable the workaround, 519 as it depends on the alternative framework, which will only patch 520 the kernel if an affected CPU is detected. 521 522 If unsure, say Y. 523 524config ARM64_ERRATUM_843419 525 bool "Cortex-A53: 843419: A load or store might access an incorrect address" 526 default y 527 select ARM64_MODULE_PLTS if MODULES 528 help 529 This option links the kernel with '--fix-cortex-a53-843419' and 530 enables PLT support to replace certain ADRP instructions, which can 531 cause subsequent memory accesses to use an incorrect address on 532 Cortex-A53 parts up to r0p4. 533 534 If unsure, say Y. 535 536config ARM64_LD_HAS_FIX_ERRATUM_843419 537 def_bool $(ld-option,--fix-cortex-a53-843419) 538 539config ARM64_ERRATUM_1024718 540 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" 541 default y 542 help 543 This option adds a workaround for ARM Cortex-A55 Erratum 1024718. 544 545 Affected Cortex-A55 cores (all revisions) could cause incorrect 546 update of the hardware dirty bit when the DBM/AP bits are updated 547 without a break-before-make. The workaround is to disable the usage 548 of hardware DBM locally on the affected cores. CPUs not affected by 549 this erratum will continue to use the feature. 550 551 If unsure, say Y. 552 553config ARM64_ERRATUM_1418040 554 bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result" 555 default y 556 depends on COMPAT 557 help 558 This option adds a workaround for ARM Cortex-A76/Neoverse-N1 559 errata 1188873 and 1418040. 560 561 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could 562 cause register corruption when accessing the timer registers 563 from AArch32 userspace. 564 565 If unsure, say Y. 566 567config ARM64_WORKAROUND_SPECULATIVE_AT 568 bool 569 570config ARM64_ERRATUM_1165522 571 bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 572 default y 573 select ARM64_WORKAROUND_SPECULATIVE_AT 574 help 575 This option adds a workaround for ARM Cortex-A76 erratum 1165522. 576 577 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with 578 corrupted TLBs by speculating an AT instruction during a guest 579 context switch. 580 581 If unsure, say Y. 582 583config ARM64_ERRATUM_1319367 584 bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 585 default y 586 select ARM64_WORKAROUND_SPECULATIVE_AT 587 help 588 This option adds work arounds for ARM Cortex-A57 erratum 1319537 589 and A72 erratum 1319367 590 591 Cortex-A57 and A72 cores could end-up with corrupted TLBs by 592 speculating an AT instruction during a guest context switch. 593 594 If unsure, say Y. 595 596config ARM64_ERRATUM_1530923 597 bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation" 598 default y 599 select ARM64_WORKAROUND_SPECULATIVE_AT 600 help 601 This option adds a workaround for ARM Cortex-A55 erratum 1530923. 602 603 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with 604 corrupted TLBs by speculating an AT instruction during a guest 605 context switch. 606 607 If unsure, say Y. 608 609config ARM64_WORKAROUND_REPEAT_TLBI 610 bool 611 612config ARM64_ERRATUM_1286807 613 bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation" 614 default y 615 select ARM64_WORKAROUND_REPEAT_TLBI 616 help 617 This option adds a workaround for ARM Cortex-A76 erratum 1286807. 618 619 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual 620 address for a cacheable mapping of a location is being 621 accessed by a core while another core is remapping the virtual 622 address to a new physical page using the recommended 623 break-before-make sequence, then under very rare circumstances 624 TLBI+DSB completes before a read using the translation being 625 invalidated has been observed by other observers. The 626 workaround repeats the TLBI+DSB operation. 627 628config ARM64_ERRATUM_1463225 629 bool "Cortex-A76: Software Step might prevent interrupt recognition" 630 default y 631 help 632 This option adds a workaround for Arm Cortex-A76 erratum 1463225. 633 634 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping 635 of a system call instruction (SVC) can prevent recognition of 636 subsequent interrupts when software stepping is disabled in the 637 exception handler of the system call and either kernel debugging 638 is enabled or VHE is in use. 639 640 Work around the erratum by triggering a dummy step exception 641 when handling a system call from a task that is being stepped 642 in a VHE configuration of the kernel. 643 644 If unsure, say Y. 645 646config ARM64_ERRATUM_1542419 647 bool "Neoverse-N1: workaround mis-ordering of instruction fetches" 648 default y 649 help 650 This option adds a workaround for ARM Neoverse-N1 erratum 651 1542419. 652 653 Affected Neoverse-N1 cores could execute a stale instruction when 654 modified by another CPU. The workaround depends on a firmware 655 counterpart. 656 657 Workaround the issue by hiding the DIC feature from EL0. This 658 forces user-space to perform cache maintenance. 659 660 If unsure, say Y. 661 662config ARM64_ERRATUM_1508412 663 bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive or PAR read" 664 default y 665 help 666 This option adds a workaround for Arm Cortex-A77 erratum 1508412. 667 668 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence 669 of a store-exclusive or read of PAR_EL1 and a load with device or 670 non-cacheable memory attributes. The workaround depends on a firmware 671 counterpart. 672 673 KVM guests must also have the workaround implemented or they can 674 deadlock the system. 675 676 Work around the issue by inserting DMB SY barriers around PAR_EL1 677 register reads and warning KVM users. The DMB barrier is sufficient 678 to prevent a speculative PAR_EL1 read. 679 680 If unsure, say Y. 681 682config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 683 bool 684 685config ARM64_ERRATUM_2051678 686 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit" 687 default y 688 help 689 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678. 690 Affected Cortex-A510 might not respect the ordering rules for 691 hardware update of the page table's dirty bit. The workaround 692 is to not enable the feature on affected CPUs. 693 694 If unsure, say Y. 695 696config ARM64_ERRATUM_2077057 697 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2" 698 default y 699 help 700 This option adds the workaround for ARM Cortex-A510 erratum 2077057. 701 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is 702 expected, but a Pointer Authentication trap is taken instead. The 703 erratum causes SPSR_EL1 to be copied to SPSR_EL2, which could allow 704 EL1 to cause a return to EL2 with a guest controlled ELR_EL2. 705 706 This can only happen when EL2 is stepping EL1. 707 708 When these conditions occur, the SPSR_EL2 value is unchanged from the 709 previous guest entry, and can be restored from the in-memory copy. 710 711 If unsure, say Y. 712 713config ARM64_ERRATUM_2119858 714 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode" 715 default y 716 depends on CORESIGHT_TRBE 717 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 718 help 719 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858. 720 721 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace 722 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 723 the event of a WRAP event. 724 725 Work around the issue by always making sure we move the TRBPTR_EL1 by 726 256 bytes before enabling the buffer and filling the first 256 bytes of 727 the buffer with ETM ignore packets upon disabling. 728 729 If unsure, say Y. 730 731config ARM64_ERRATUM_2139208 732 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" 733 default y 734 depends on CORESIGHT_TRBE 735 select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE 736 help 737 This option adds the workaround for ARM Neoverse-N2 erratum 2139208. 738 739 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace 740 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in 741 the event of a WRAP event. 742 743 Work around the issue by always making sure we move the TRBPTR_EL1 by 744 256 bytes before enabling the buffer and filling the first 256 bytes of 745 the buffer with ETM ignore packets upon disabling. 746 747 If unsure, say Y. 748 749config ARM64_WORKAROUND_TSB_FLUSH_FAILURE 750 bool 751 752config ARM64_ERRATUM_2054223 753 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" 754 default y 755 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 756 help 757 Enable workaround for ARM Cortex-A710 erratum 2054223 758 759 Affected cores may fail to flush the trace data on a TSB instruction, when 760 the PE is in trace prohibited state. This will cause losing a few bytes 761 of the trace cached. 762 763 Workaround is to issue two TSB consecutively on affected cores. 764 765 If unsure, say Y. 766 767config ARM64_ERRATUM_2067961 768 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" 769 default y 770 select ARM64_WORKAROUND_TSB_FLUSH_FAILURE 771 help 772 Enable workaround for ARM Neoverse-N2 erratum 2067961 773 774 Affected cores may fail to flush the trace data on a TSB instruction, when 775 the PE is in trace prohibited state. This will cause losing a few bytes 776 of the trace cached. 777 778 Workaround is to issue two TSB consecutively on affected cores. 779 780 If unsure, say Y. 781 782config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 783 bool 784 785config ARM64_ERRATUM_2253138 786 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" 787 depends on CORESIGHT_TRBE 788 default y 789 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 790 help 791 This option adds the workaround for ARM Neoverse-N2 erratum 2253138. 792 793 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved 794 for TRBE. Under some conditions, the TRBE might generate a write to the next 795 virtually addressed page following the last page of the TRBE address space 796 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 797 798 Work around this in the driver by always making sure that there is a 799 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 800 801 If unsure, say Y. 802 803config ARM64_ERRATUM_2224489 804 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range" 805 depends on CORESIGHT_TRBE 806 default y 807 select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE 808 help 809 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489. 810 811 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved 812 for TRBE. Under some conditions, the TRBE might generate a write to the next 813 virtually addressed page following the last page of the TRBE address space 814 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. 815 816 Work around this in the driver by always making sure that there is a 817 page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. 818 819 If unsure, say Y. 820 821config ARM64_ERRATUM_2064142 822 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" 823 depends on CORESIGHT_TRBE 824 default y 825 help 826 This option adds the workaround for ARM Cortex-A510 erratum 2064142. 827 828 Affected Cortex-A510 core might fail to write into system registers after the 829 TRBE has been disabled. Under some conditions after the TRBE has been disabled 830 writes into TRBE registers TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1, 831 and TRBTRG_EL1 will be ignored and will not be effected. 832 833 Work around this in the driver by executing TSB CSYNC and DSB after collection 834 is stopped and before performing a system register write to one of the affected 835 registers. 836 837 If unsure, say Y. 838 839config ARM64_ERRATUM_2038923 840 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" 841 depends on CORESIGHT_TRBE 842 default y 843 help 844 This option adds the workaround for ARM Cortex-A510 erratum 2038923. 845 846 Affected Cortex-A510 core might cause an inconsistent view on whether trace is 847 prohibited within the CPU. As a result, the trace buffer or trace buffer state 848 might be corrupted. This happens after TRBE buffer has been enabled by setting 849 TRBLIMITR_EL1.E, followed by just a single context synchronization event before 850 execution changes from a context, in which trace is prohibited to one where it 851 isn't, or vice versa. In these mentioned conditions, the view of whether trace 852 is prohibited is inconsistent between parts of the CPU, and the trace buffer or 853 the trace buffer state might be corrupted. 854 855 Work around this in the driver by preventing an inconsistent view of whether the 856 trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a 857 change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or 858 two ISB instructions if no ERET is to take place. 859 860 If unsure, say Y. 861 862config ARM64_ERRATUM_1902691 863 bool "Cortex-A510: 1902691: workaround TRBE trace corruption" 864 depends on CORESIGHT_TRBE 865 default y 866 help 867 This option adds the workaround for ARM Cortex-A510 erratum 1902691. 868 869 Affected Cortex-A510 core might cause trace data corruption, when being written 870 into the memory. Effectively TRBE is broken and hence cannot be used to capture 871 trace data. 872 873 Work around this problem in the driver by just preventing TRBE initialization on 874 affected cpus. The firmware must have disabled the access to TRBE for the kernel 875 on such implementations. This will cover the kernel for any firmware that doesn't 876 do this already. 877 878 If unsure, say Y. 879 880config CAVIUM_ERRATUM_22375 881 bool "Cavium erratum 22375, 24313" 882 default y 883 help 884 Enable workaround for errata 22375 and 24313. 885 886 This implements two gicv3-its errata workarounds for ThunderX. Both 887 with a small impact affecting only ITS table allocation. 888 889 erratum 22375: only alloc 8MB table size 890 erratum 24313: ignore memory access type 891 892 The fixes are in ITS initialization and basically ignore memory access 893 type and table size provided by the TYPER and BASER registers. 894 895 If unsure, say Y. 896 897config CAVIUM_ERRATUM_23144 898 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system" 899 depends on NUMA 900 default y 901 help 902 ITS SYNC command hang for cross node io and collections/cpu mapping. 903 904 If unsure, say Y. 905 906config CAVIUM_ERRATUM_23154 907 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation" 908 default y 909 help 910 The ThunderX GICv3 implementation requires a modified version for 911 reading the IAR status to ensure data synchronization 912 (access to icc_iar1_el1 is not sync'ed before and after). 913 914 It also suffers from erratum 38545 (also present on Marvell's 915 OcteonTX and OcteonTX2), resulting in deactivated interrupts being 916 spuriously presented to the CPU interface. 917 918 If unsure, say Y. 919 920config CAVIUM_ERRATUM_27456 921 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption" 922 default y 923 help 924 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI 925 instructions may cause the icache to become corrupted if it 926 contains data for a non-current ASID. The fix is to 927 invalidate the icache when changing the mm context. 928 929 If unsure, say Y. 930 931config CAVIUM_ERRATUM_30115 932 bool "Cavium erratum 30115: Guest may disable interrupts in host" 933 default y 934 help 935 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through 936 1.2, and T83 Pass 1.0, KVM guest execution may disable 937 interrupts in host. Trapping both GICv3 group-0 and group-1 938 accesses sidesteps the issue. 939 940 If unsure, say Y. 941 942config CAVIUM_TX2_ERRATUM_219 943 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails" 944 default y 945 help 946 On Cavium ThunderX2, a load, store or prefetch instruction between a 947 TTBR update and the corresponding context synchronizing operation can 948 cause a spurious Data Abort to be delivered to any hardware thread in 949 the CPU core. 950 951 Work around the issue by avoiding the problematic code sequence and 952 trapping KVM guest TTBRx_EL1 writes to EL2 when SMT is enabled. The 953 trap handler performs the corresponding register access, skips the 954 instruction and ensures context synchronization by virtue of the 955 exception return. 956 957 If unsure, say Y. 958 959config FUJITSU_ERRATUM_010001 960 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly" 961 default y 962 help 963 This option adds a workaround for Fujitsu-A64FX erratum E#010001. 964 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory 965 accesses may cause undefined fault (Data abort, DFSC=0b111111). 966 This fault occurs under a specific hardware condition when a 967 load/store instruction performs an address translation using: 968 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1. 969 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1. 970 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1. 971 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1. 972 973 The workaround is to ensure these bits are clear in TCR_ELx. 974 The workaround only affects the Fujitsu-A64FX. 975 976 If unsure, say Y. 977 978config HISILICON_ERRATUM_161600802 979 bool "Hip07 161600802: Erroneous redistributor VLPI base" 980 default y 981 help 982 The HiSilicon Hip07 SoC uses the wrong redistributor base 983 when issued ITS commands such as VMOVP and VMAPP, and requires 984 a 128kB offset to be applied to the target address in this commands. 985 986 If unsure, say Y. 987 988config QCOM_FALKOR_ERRATUM_1003 989 bool "Falkor E1003: Incorrect translation due to ASID change" 990 default y 991 help 992 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID 993 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID 994 in TTBR1_EL1, this situation only occurs in the entry trampoline and 995 then only for entries in the walk cache, since the leaf translation 996 is unchanged. Work around the erratum by invalidating the walk cache 997 entries for the trampoline before entering the kernel proper. 998 999config QCOM_FALKOR_ERRATUM_1009 1000 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" 1001 default y 1002 select ARM64_WORKAROUND_REPEAT_TLBI 1003 help 1004 On Falkor v1, the CPU may prematurely complete a DSB following a 1005 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation 1006 one more time to fix the issue. 1007 1008 If unsure, say Y. 1009 1010config QCOM_QDF2400_ERRATUM_0065 1011 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size" 1012 default y 1013 help 1014 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports 1015 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have 1016 been indicated as 16Bytes (0xf), not 8Bytes (0x7). 1017 1018 If unsure, say Y. 1019 1020config QCOM_FALKOR_ERRATUM_E1041 1021 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access" 1022 default y 1023 help 1024 Falkor CPU may speculatively fetch instructions from an improper 1025 memory location when MMU translation is changed from SCTLR_ELn[M]=1 1026 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem. 1027 1028 If unsure, say Y. 1029 1030config NVIDIA_CARMEL_CNP_ERRATUM 1031 bool "NVIDIA Carmel CNP: CNP on Carmel semantically different than ARM cores" 1032 default y 1033 help 1034 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not 1035 invalidate shared TLB entries installed by a different core, as it would 1036 on standard ARM cores. 1037 1038 If unsure, say Y. 1039 1040config SOCIONEXT_SYNQUACER_PREITS 1041 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" 1042 default y 1043 help 1044 Socionext Synquacer SoCs implement a separate h/w block to generate 1045 MSI doorbell writes with non-zero values for the device ID. 1046 1047 If unsure, say Y. 1048 1049endmenu 1050 1051 1052choice 1053 prompt "Page size" 1054 default ARM64_4K_PAGES 1055 help 1056 Page size (translation granule) configuration. 1057 1058config ARM64_4K_PAGES 1059 bool "4KB" 1060 help 1061 This feature enables 4KB pages support. 1062 1063config ARM64_16K_PAGES 1064 bool "16KB" 1065 help 1066 The system will use 16KB pages support. AArch32 emulation 1067 requires applications compiled with 16K (or a multiple of 16K) 1068 aligned segments. 1069 1070config ARM64_64K_PAGES 1071 bool "64KB" 1072 help 1073 This feature enables 64KB pages support (4KB by default) 1074 allowing only two levels of page tables and faster TLB 1075 look-up. AArch32 emulation requires applications compiled 1076 with 64K aligned segments. 1077 1078endchoice 1079 1080choice 1081 prompt "Virtual address space size" 1082 default ARM64_VA_BITS_39 if ARM64_4K_PAGES 1083 default ARM64_VA_BITS_47 if ARM64_16K_PAGES 1084 default ARM64_VA_BITS_42 if ARM64_64K_PAGES 1085 help 1086 Allows choosing one of multiple possible virtual address 1087 space sizes. The level of translation table is determined by 1088 a combination of page size and virtual address space size. 1089 1090config ARM64_VA_BITS_36 1091 bool "36-bit" if EXPERT 1092 depends on ARM64_16K_PAGES 1093 1094config ARM64_VA_BITS_39 1095 bool "39-bit" 1096 depends on ARM64_4K_PAGES 1097 1098config ARM64_VA_BITS_42 1099 bool "42-bit" 1100 depends on ARM64_64K_PAGES 1101 1102config ARM64_VA_BITS_47 1103 bool "47-bit" 1104 depends on ARM64_16K_PAGES 1105 1106config ARM64_VA_BITS_48 1107 bool "48-bit" 1108 1109config ARM64_VA_BITS_52 1110 bool "52-bit" 1111 depends on ARM64_64K_PAGES && (ARM64_PAN || !ARM64_SW_TTBR0_PAN) 1112 help 1113 Enable 52-bit virtual addressing for userspace when explicitly 1114 requested via a hint to mmap(). The kernel will also use 52-bit 1115 virtual addresses for its own mappings (provided HW support for 1116 this feature is available, otherwise it reverts to 48-bit). 1117 1118 NOTE: Enabling 52-bit virtual addressing in conjunction with 1119 ARMv8.3 Pointer Authentication will result in the PAC being 1120 reduced from 7 bits to 3 bits, which may have a significant 1121 impact on its susceptibility to brute-force attacks. 1122 1123 If unsure, select 48-bit virtual addressing instead. 1124 1125endchoice 1126 1127config ARM64_FORCE_52BIT 1128 bool "Force 52-bit virtual addresses for userspace" 1129 depends on ARM64_VA_BITS_52 && EXPERT 1130 help 1131 For systems with 52-bit userspace VAs enabled, the kernel will attempt 1132 to maintain compatibility with older software by providing 48-bit VAs 1133 unless a hint is supplied to mmap. 1134 1135 This configuration option disables the 48-bit compatibility logic, and 1136 forces all userspace addresses to be 52-bit on HW that supports it. One 1137 should only enable this configuration option for stress testing userspace 1138 memory management code. If unsure say N here. 1139 1140config ARM64_VA_BITS 1141 int 1142 default 36 if ARM64_VA_BITS_36 1143 default 39 if ARM64_VA_BITS_39 1144 default 42 if ARM64_VA_BITS_42 1145 default 47 if ARM64_VA_BITS_47 1146 default 48 if ARM64_VA_BITS_48 1147 default 52 if ARM64_VA_BITS_52 1148 1149choice 1150 prompt "Physical address space size" 1151 default ARM64_PA_BITS_48 1152 help 1153 Choose the maximum physical address range that the kernel will 1154 support. 1155 1156config ARM64_PA_BITS_48 1157 bool "48-bit" 1158 1159config ARM64_PA_BITS_52 1160 bool "52-bit (ARMv8.2)" 1161 depends on ARM64_64K_PAGES 1162 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1163 help 1164 Enable support for a 52-bit physical address space, introduced as 1165 part of the ARMv8.2-LPA extension. 1166 1167 With this enabled, the kernel will also continue to work on CPUs that 1168 do not support ARMv8.2-LPA, but with some added memory overhead (and 1169 minor performance overhead). 1170 1171endchoice 1172 1173config ARM64_PA_BITS 1174 int 1175 default 48 if ARM64_PA_BITS_48 1176 default 52 if ARM64_PA_BITS_52 1177 1178choice 1179 prompt "Endianness" 1180 default CPU_LITTLE_ENDIAN 1181 help 1182 Select the endianness of data accesses performed by the CPU. Userspace 1183 applications will need to be compiled and linked for the endianness 1184 that is selected here. 1185 1186config CPU_BIG_ENDIAN 1187 bool "Build big-endian kernel" 1188 depends on !LD_IS_LLD || LLD_VERSION >= 130000 1189 help 1190 Say Y if you plan on running a kernel with a big-endian userspace. 1191 1192config CPU_LITTLE_ENDIAN 1193 bool "Build little-endian kernel" 1194 help 1195 Say Y if you plan on running a kernel with a little-endian userspace. 1196 This is usually the case for distributions targeting arm64. 1197 1198endchoice 1199 1200config SCHED_MC 1201 bool "Multi-core scheduler support" 1202 help 1203 Multi-core scheduler support improves the CPU scheduler's decision 1204 making when dealing with multi-core CPU chips at a cost of slightly 1205 increased overhead in some places. If unsure say N here. 1206 1207config SCHED_CLUSTER 1208 bool "Cluster scheduler support" 1209 help 1210 Cluster scheduler support improves the CPU scheduler's decision 1211 making when dealing with machines that have clusters of CPUs. 1212 Cluster usually means a couple of CPUs which are placed closely 1213 by sharing mid-level caches, last-level cache tags or internal 1214 busses. 1215 1216config SCHED_SMT 1217 bool "SMT scheduler support" 1218 help 1219 Improves the CPU scheduler's decision making when dealing with 1220 MultiThreading at a cost of slightly increased overhead in some 1221 places. If unsure say N here. 1222 1223config NR_CPUS 1224 int "Maximum number of CPUs (2-4096)" 1225 range 2 4096 1226 default "256" 1227 1228config HOTPLUG_CPU 1229 bool "Support for hot-pluggable CPUs" 1230 select GENERIC_IRQ_MIGRATION 1231 help 1232 Say Y here to experiment with turning CPUs off and on. CPUs 1233 can be controlled through /sys/devices/system/cpu. 1234 1235# Common NUMA Features 1236config NUMA 1237 bool "NUMA Memory Allocation and Scheduler Support" 1238 select GENERIC_ARCH_NUMA 1239 select ACPI_NUMA if ACPI 1240 select OF_NUMA 1241 select HAVE_SETUP_PER_CPU_AREA 1242 select NEED_PER_CPU_EMBED_FIRST_CHUNK 1243 select NEED_PER_CPU_PAGE_FIRST_CHUNK 1244 select USE_PERCPU_NUMA_NODE_ID 1245 help 1246 Enable NUMA (Non-Uniform Memory Access) support. 1247 1248 The kernel will try to allocate memory used by a CPU on the 1249 local memory of the CPU and add some more 1250 NUMA awareness to the kernel. 1251 1252config NODES_SHIFT 1253 int "Maximum NUMA Nodes (as a power of 2)" 1254 range 1 10 1255 default "4" 1256 depends on NUMA 1257 help 1258 Specify the maximum number of NUMA Nodes available on the target 1259 system. Increases memory reserved to accommodate various tables. 1260 1261source "kernel/Kconfig.hz" 1262 1263config ARCH_SPARSEMEM_ENABLE 1264 def_bool y 1265 select SPARSEMEM_VMEMMAP_ENABLE 1266 select SPARSEMEM_VMEMMAP 1267 1268config HW_PERF_EVENTS 1269 def_bool y 1270 depends on ARM_PMU 1271 1272# Supported by clang >= 7.0 or GCC >= 12.0.0 1273config CC_HAVE_SHADOW_CALL_STACK 1274 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18) 1275 1276config PARAVIRT 1277 bool "Enable paravirtualization code" 1278 help 1279 This changes the kernel so it can modify itself when it is run 1280 under a hypervisor, potentially improving performance significantly 1281 over full virtualization. 1282 1283config PARAVIRT_TIME_ACCOUNTING 1284 bool "Paravirtual steal time accounting" 1285 select PARAVIRT 1286 help 1287 Select this option to enable fine granularity task steal time 1288 accounting. Time spent executing other tasks in parallel with 1289 the current vCPU is discounted from the vCPU power. To account for 1290 that, there can be a small performance impact. 1291 1292 If in doubt, say N here. 1293 1294config KEXEC 1295 depends on PM_SLEEP_SMP 1296 select KEXEC_CORE 1297 bool "kexec system call" 1298 help 1299 kexec is a system call that implements the ability to shutdown your 1300 current kernel, and to start another kernel. It is like a reboot 1301 but it is independent of the system firmware. And like a reboot 1302 you can start any kernel with it, not just Linux. 1303 1304config KEXEC_FILE 1305 bool "kexec file based system call" 1306 select KEXEC_CORE 1307 select HAVE_IMA_KEXEC if IMA 1308 help 1309 This is new version of kexec system call. This system call is 1310 file based and takes file descriptors as system call argument 1311 for kernel and initramfs as opposed to list of segments as 1312 accepted by previous system call. 1313 1314config KEXEC_SIG 1315 bool "Verify kernel signature during kexec_file_load() syscall" 1316 depends on KEXEC_FILE 1317 help 1318 Select this option to verify a signature with loaded kernel 1319 image. If configured, any attempt of loading a image without 1320 valid signature will fail. 1321 1322 In addition to that option, you need to enable signature 1323 verification for the corresponding kernel image type being 1324 loaded in order for this to work. 1325 1326config KEXEC_IMAGE_VERIFY_SIG 1327 bool "Enable Image signature verification support" 1328 default y 1329 depends on KEXEC_SIG 1330 depends on EFI && SIGNED_PE_FILE_VERIFICATION 1331 help 1332 Enable Image signature verification support. 1333 1334comment "Support for PE file signature verification disabled" 1335 depends on KEXEC_SIG 1336 depends on !EFI || !SIGNED_PE_FILE_VERIFICATION 1337 1338config CRASH_DUMP 1339 bool "Build kdump crash kernel" 1340 help 1341 Generate crash dump after being started by kexec. This should 1342 be normally only set in special crash dump kernels which are 1343 loaded in the main kernel with kexec-tools into a specially 1344 reserved region and then later executed after a crash by 1345 kdump/kexec. 1346 1347 For more details see Documentation/admin-guide/kdump/kdump.rst 1348 1349config TRANS_TABLE 1350 def_bool y 1351 depends on HIBERNATION || KEXEC_CORE 1352 1353config XEN_DOM0 1354 def_bool y 1355 depends on XEN 1356 1357config XEN 1358 bool "Xen guest support on ARM64" 1359 depends on ARM64 && OF 1360 select SWIOTLB_XEN 1361 select PARAVIRT 1362 help 1363 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64. 1364 1365config FORCE_MAX_ZONEORDER 1366 int 1367 default "14" if ARM64_64K_PAGES 1368 default "12" if ARM64_16K_PAGES 1369 default "11" 1370 help 1371 The kernel memory allocator divides physically contiguous memory 1372 blocks into "zones", where each zone is a power of two number of 1373 pages. This option selects the largest power of two that the kernel 1374 keeps in the memory allocator. If you need to allocate very large 1375 blocks of physically contiguous memory, then you may need to 1376 increase this value. 1377 1378 This config option is actually maximum order plus one. For example, 1379 a value of 11 means that the largest free memory block is 2^10 pages. 1380 1381 We make sure that we can allocate upto a HugePage size for each configuration. 1382 Hence we have : 1383 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2 1384 1385 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us 1386 4M allocations matching the default size used by generic code. 1387 1388config UNMAP_KERNEL_AT_EL0 1389 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT 1390 default y 1391 help 1392 Speculation attacks against some high-performance processors can 1393 be used to bypass MMU permission checks and leak kernel data to 1394 userspace. This can be defended against by unmapping the kernel 1395 when running in userspace, mapping it back in on exception entry 1396 via a trampoline page in the vector table. 1397 1398 If unsure, say Y. 1399 1400config MITIGATE_SPECTRE_BRANCH_HISTORY 1401 bool "Mitigate Spectre style attacks against branch history" if EXPERT 1402 default y 1403 help 1404 Speculation attacks against some high-performance processors can 1405 make use of branch history to influence future speculation. 1406 When taking an exception from user-space, a sequence of branches 1407 or a firmware call overwrites the branch history. 1408 1409config RODATA_FULL_DEFAULT_ENABLED 1410 bool "Apply r/o permissions of VM areas also to their linear aliases" 1411 default y 1412 help 1413 Apply read-only attributes of VM areas to the linear alias of 1414 the backing pages as well. This prevents code or read-only data 1415 from being modified (inadvertently or intentionally) via another 1416 mapping of the same memory page. This additional enhancement can 1417 be turned off at runtime by passing rodata=[off|on] (and turned on 1418 with rodata=full if this option is set to 'n') 1419 1420 This requires the linear region to be mapped down to pages, 1421 which may adversely affect performance in some cases. 1422 1423config ARM64_SW_TTBR0_PAN 1424 bool "Emulate Privileged Access Never using TTBR0_EL1 switching" 1425 help 1426 Enabling this option prevents the kernel from accessing 1427 user-space memory directly by pointing TTBR0_EL1 to a reserved 1428 zeroed area and reserved ASID. The user access routines 1429 restore the valid TTBR0_EL1 temporarily. 1430 1431config ARM64_TAGGED_ADDR_ABI 1432 bool "Enable the tagged user addresses syscall ABI" 1433 default y 1434 help 1435 When this option is enabled, user applications can opt in to a 1436 relaxed ABI via prctl() allowing tagged addresses to be passed 1437 to system calls as pointer arguments. For details, see 1438 Documentation/arm64/tagged-address-abi.rst. 1439 1440menuconfig COMPAT 1441 bool "Kernel support for 32-bit EL0" 1442 depends on ARM64_4K_PAGES || EXPERT 1443 select HAVE_UID16 1444 select OLD_SIGSUSPEND3 1445 select COMPAT_OLD_SIGACTION 1446 help 1447 This option enables support for a 32-bit EL0 running under a 64-bit 1448 kernel at EL1. AArch32-specific components such as system calls, 1449 the user helper functions, VFP support and the ptrace interface are 1450 handled appropriately by the kernel. 1451 1452 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware 1453 that you will only be able to execute AArch32 binaries that were compiled 1454 with page size aligned segments. 1455 1456 If you want to execute 32-bit userspace applications, say Y. 1457 1458if COMPAT 1459 1460config KUSER_HELPERS 1461 bool "Enable kuser helpers page for 32-bit applications" 1462 default y 1463 help 1464 Warning: disabling this option may break 32-bit user programs. 1465 1466 Provide kuser helpers to compat tasks. The kernel provides 1467 helper code to userspace in read only form at a fixed location 1468 to allow userspace to be independent of the CPU type fitted to 1469 the system. This permits binaries to be run on ARMv4 through 1470 to ARMv8 without modification. 1471 1472 See Documentation/arm/kernel_user_helpers.rst for details. 1473 1474 However, the fixed address nature of these helpers can be used 1475 by ROP (return orientated programming) authors when creating 1476 exploits. 1477 1478 If all of the binaries and libraries which run on your platform 1479 are built specifically for your platform, and make no use of 1480 these helpers, then you can turn this option off to hinder 1481 such exploits. However, in that case, if a binary or library 1482 relying on those helpers is run, it will not function correctly. 1483 1484 Say N here only if you are absolutely certain that you do not 1485 need these helpers; otherwise, the safe option is to say Y. 1486 1487config COMPAT_VDSO 1488 bool "Enable vDSO for 32-bit applications" 1489 depends on !CPU_BIG_ENDIAN 1490 depends on (CC_IS_CLANG && LD_IS_LLD) || "$(CROSS_COMPILE_COMPAT)" != "" 1491 select GENERIC_COMPAT_VDSO 1492 default y 1493 help 1494 Place in the process address space of 32-bit applications an 1495 ELF shared object providing fast implementations of gettimeofday 1496 and clock_gettime. 1497 1498 You must have a 32-bit build of glibc 2.22 or later for programs 1499 to seamlessly take advantage of this. 1500 1501config THUMB2_COMPAT_VDSO 1502 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT 1503 depends on COMPAT_VDSO 1504 default y 1505 help 1506 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y, 1507 otherwise with '-marm'. 1508 1509menuconfig ARMV8_DEPRECATED 1510 bool "Emulate deprecated/obsolete ARMv8 instructions" 1511 depends on SYSCTL 1512 help 1513 Legacy software support may require certain instructions 1514 that have been deprecated or obsoleted in the architecture. 1515 1516 Enable this config to enable selective emulation of these 1517 features. 1518 1519 If unsure, say Y 1520 1521if ARMV8_DEPRECATED 1522 1523config SWP_EMULATION 1524 bool "Emulate SWP/SWPB instructions" 1525 help 1526 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that 1527 they are always undefined. Say Y here to enable software 1528 emulation of these instructions for userspace using LDXR/STXR. 1529 This feature can be controlled at runtime with the abi.swp 1530 sysctl which is disabled by default. 1531 1532 In some older versions of glibc [<=2.8] SWP is used during futex 1533 trylock() operations with the assumption that the code will not 1534 be preempted. This invalid assumption may be more likely to fail 1535 with SWP emulation enabled, leading to deadlock of the user 1536 application. 1537 1538 NOTE: when accessing uncached shared regions, LDXR/STXR rely 1539 on an external transaction monitoring block called a global 1540 monitor to maintain update atomicity. If your system does not 1541 implement a global monitor, this option can cause programs that 1542 perform SWP operations to uncached memory to deadlock. 1543 1544 If unsure, say Y 1545 1546config CP15_BARRIER_EMULATION 1547 bool "Emulate CP15 Barrier instructions" 1548 help 1549 The CP15 barrier instructions - CP15ISB, CP15DSB, and 1550 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is 1551 strongly recommended to use the ISB, DSB, and DMB 1552 instructions instead. 1553 1554 Say Y here to enable software emulation of these 1555 instructions for AArch32 userspace code. When this option is 1556 enabled, CP15 barrier usage is traced which can help 1557 identify software that needs updating. This feature can be 1558 controlled at runtime with the abi.cp15_barrier sysctl. 1559 1560 If unsure, say Y 1561 1562config SETEND_EMULATION 1563 bool "Emulate SETEND instruction" 1564 help 1565 The SETEND instruction alters the data-endianness of the 1566 AArch32 EL0, and is deprecated in ARMv8. 1567 1568 Say Y here to enable software emulation of the instruction 1569 for AArch32 userspace code. This feature can be controlled 1570 at runtime with the abi.setend sysctl. 1571 1572 Note: All the cpus on the system must have mixed endian support at EL0 1573 for this feature to be enabled. If a new CPU - which doesn't support mixed 1574 endian - is hotplugged in after this feature has been enabled, there could 1575 be unexpected results in the applications. 1576 1577 If unsure, say Y 1578endif 1579 1580endif 1581 1582menu "ARMv8.1 architectural features" 1583 1584config ARM64_HW_AFDBM 1585 bool "Support for hardware updates of the Access and Dirty page flags" 1586 default y 1587 help 1588 The ARMv8.1 architecture extensions introduce support for 1589 hardware updates of the access and dirty information in page 1590 table entries. When enabled in TCR_EL1 (HA and HD bits) on 1591 capable processors, accesses to pages with PTE_AF cleared will 1592 set this bit instead of raising an access flag fault. 1593 Similarly, writes to read-only pages with the DBM bit set will 1594 clear the read-only bit (AP[2]) instead of raising a 1595 permission fault. 1596 1597 Kernels built with this configuration option enabled continue 1598 to work on pre-ARMv8.1 hardware and the performance impact is 1599 minimal. If unsure, say Y. 1600 1601config ARM64_PAN 1602 bool "Enable support for Privileged Access Never (PAN)" 1603 default y 1604 help 1605 Privileged Access Never (PAN; part of the ARMv8.1 Extensions) 1606 prevents the kernel or hypervisor from accessing user-space (EL0) 1607 memory directly. 1608 1609 Choosing this option will cause any unprotected (not using 1610 copy_to_user et al) memory access to fail with a permission fault. 1611 1612 The feature is detected at runtime, and will remain as a 'nop' 1613 instruction if the cpu does not implement the feature. 1614 1615config AS_HAS_LDAPR 1616 def_bool $(as-instr,.arch_extension rcpc) 1617 1618config AS_HAS_LSE_ATOMICS 1619 def_bool $(as-instr,.arch_extension lse) 1620 1621config ARM64_LSE_ATOMICS 1622 bool 1623 default ARM64_USE_LSE_ATOMICS 1624 depends on AS_HAS_LSE_ATOMICS 1625 1626config ARM64_USE_LSE_ATOMICS 1627 bool "Atomic instructions" 1628 depends on JUMP_LABEL 1629 default y 1630 help 1631 As part of the Large System Extensions, ARMv8.1 introduces new 1632 atomic instructions that are designed specifically to scale in 1633 very large systems. 1634 1635 Say Y here to make use of these instructions for the in-kernel 1636 atomic routines. This incurs a small overhead on CPUs that do 1637 not support these instructions and requires the kernel to be 1638 built with binutils >= 2.25 in order for the new instructions 1639 to be used. 1640 1641endmenu 1642 1643menu "ARMv8.2 architectural features" 1644 1645config AS_HAS_ARMV8_2 1646 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a) 1647 1648config AS_HAS_SHA3 1649 def_bool $(as-instr,.arch armv8.2-a+sha3) 1650 1651config ARM64_PMEM 1652 bool "Enable support for persistent memory" 1653 select ARCH_HAS_PMEM_API 1654 select ARCH_HAS_UACCESS_FLUSHCACHE 1655 help 1656 Say Y to enable support for the persistent memory API based on the 1657 ARMv8.2 DCPoP feature. 1658 1659 The feature is detected at runtime, and the kernel will use DC CVAC 1660 operations if DC CVAP is not supported (following the behaviour of 1661 DC CVAP itself if the system does not define a point of persistence). 1662 1663config ARM64_RAS_EXTN 1664 bool "Enable support for RAS CPU Extensions" 1665 default y 1666 help 1667 CPUs that support the Reliability, Availability and Serviceability 1668 (RAS) Extensions, part of ARMv8.2 are able to track faults and 1669 errors, classify them and report them to software. 1670 1671 On CPUs with these extensions system software can use additional 1672 barriers to determine if faults are pending and read the 1673 classification from a new set of registers. 1674 1675 Selecting this feature will allow the kernel to use these barriers 1676 and access the new registers if the system supports the extension. 1677 Platform RAS features may additionally depend on firmware support. 1678 1679config ARM64_CNP 1680 bool "Enable support for Common Not Private (CNP) translations" 1681 default y 1682 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN 1683 help 1684 Common Not Private (CNP) allows translation table entries to 1685 be shared between different PEs in the same inner shareable 1686 domain, so the hardware can use this fact to optimise the 1687 caching of such entries in the TLB. 1688 1689 Selecting this option allows the CNP feature to be detected 1690 at runtime, and does not affect PEs that do not implement 1691 this feature. 1692 1693endmenu 1694 1695menu "ARMv8.3 architectural features" 1696 1697config ARM64_PTR_AUTH 1698 bool "Enable support for pointer authentication" 1699 default y 1700 help 1701 Pointer authentication (part of the ARMv8.3 Extensions) provides 1702 instructions for signing and authenticating pointers against secret 1703 keys, which can be used to mitigate Return Oriented Programming (ROP) 1704 and other attacks. 1705 1706 This option enables these instructions at EL0 (i.e. for userspace). 1707 Choosing this option will cause the kernel to initialise secret keys 1708 for each process at exec() time, with these keys being 1709 context-switched along with the process. 1710 1711 The feature is detected at runtime. If the feature is not present in 1712 hardware it will not be advertised to userspace/KVM guest nor will it 1713 be enabled. 1714 1715 If the feature is present on the boot CPU but not on a late CPU, then 1716 the late CPU will be parked. Also, if the boot CPU does not have 1717 address auth and the late CPU has then the late CPU will still boot 1718 but with the feature disabled. On such a system, this option should 1719 not be selected. 1720 1721config ARM64_PTR_AUTH_KERNEL 1722 bool "Use pointer authentication for kernel" 1723 default y 1724 depends on ARM64_PTR_AUTH 1725 depends on (CC_HAS_SIGN_RETURN_ADDRESS || CC_HAS_BRANCH_PROT_PAC_RET) && AS_HAS_PAC 1726 # Modern compilers insert a .note.gnu.property section note for PAC 1727 # which is only understood by binutils starting with version 2.33.1. 1728 depends on LD_IS_LLD || LD_VERSION >= 23301 || (CC_IS_GCC && GCC_VERSION < 90100) 1729 depends on !CC_IS_CLANG || AS_HAS_CFI_NEGATE_RA_STATE 1730 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1731 help 1732 If the compiler supports the -mbranch-protection or 1733 -msign-return-address flag (e.g. GCC 7 or later), then this option 1734 will cause the kernel itself to be compiled with return address 1735 protection. In this case, and if the target hardware is known to 1736 support pointer authentication, then CONFIG_STACKPROTECTOR can be 1737 disabled with minimal loss of protection. 1738 1739 This feature works with FUNCTION_GRAPH_TRACER option only if 1740 DYNAMIC_FTRACE_WITH_REGS is enabled. 1741 1742config CC_HAS_BRANCH_PROT_PAC_RET 1743 # GCC 9 or later, clang 8 or later 1744 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf) 1745 1746config CC_HAS_SIGN_RETURN_ADDRESS 1747 # GCC 7, 8 1748 def_bool $(cc-option,-msign-return-address=all) 1749 1750config AS_HAS_PAC 1751 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a) 1752 1753config AS_HAS_CFI_NEGATE_RA_STATE 1754 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n) 1755 1756endmenu 1757 1758menu "ARMv8.4 architectural features" 1759 1760config ARM64_AMU_EXTN 1761 bool "Enable support for the Activity Monitors Unit CPU extension" 1762 default y 1763 help 1764 The activity monitors extension is an optional extension introduced 1765 by the ARMv8.4 CPU architecture. This enables support for version 1 1766 of the activity monitors architecture, AMUv1. 1767 1768 To enable the use of this extension on CPUs that implement it, say Y. 1769 1770 Note that for architectural reasons, firmware _must_ implement AMU 1771 support when running on CPUs that present the activity monitors 1772 extension. The required support is present in: 1773 * Version 1.5 and later of the ARM Trusted Firmware 1774 1775 For kernels that have this configuration enabled but boot with broken 1776 firmware, you may need to say N here until the firmware is fixed. 1777 Otherwise you may experience firmware panics or lockups when 1778 accessing the counter registers. Even if you are not observing these 1779 symptoms, the values returned by the register reads might not 1780 correctly reflect reality. Most commonly, the value read will be 0, 1781 indicating that the counter is not enabled. 1782 1783config AS_HAS_ARMV8_4 1784 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a) 1785 1786config ARM64_TLB_RANGE 1787 bool "Enable support for tlbi range feature" 1788 default y 1789 depends on AS_HAS_ARMV8_4 1790 help 1791 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a 1792 range of input addresses. 1793 1794 The feature introduces new assembly instructions, and they were 1795 support when binutils >= 2.30. 1796 1797endmenu 1798 1799menu "ARMv8.5 architectural features" 1800 1801config AS_HAS_ARMV8_5 1802 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a) 1803 1804config ARM64_BTI 1805 bool "Branch Target Identification support" 1806 default y 1807 help 1808 Branch Target Identification (part of the ARMv8.5 Extensions) 1809 provides a mechanism to limit the set of locations to which computed 1810 branch instructions such as BR or BLR can jump. 1811 1812 To make use of BTI on CPUs that support it, say Y. 1813 1814 BTI is intended to provide complementary protection to other control 1815 flow integrity protection mechanisms, such as the Pointer 1816 authentication mechanism provided as part of the ARMv8.3 Extensions. 1817 For this reason, it does not make sense to enable this option without 1818 also enabling support for pointer authentication. Thus, when 1819 enabling this option you should also select ARM64_PTR_AUTH=y. 1820 1821 Userspace binaries must also be specifically compiled to make use of 1822 this mechanism. If you say N here or the hardware does not support 1823 BTI, such binaries can still run, but you get no additional 1824 enforcement of branch destinations. 1825 1826config ARM64_BTI_KERNEL 1827 bool "Use Branch Target Identification for kernel" 1828 default y 1829 depends on ARM64_BTI 1830 depends on ARM64_PTR_AUTH_KERNEL 1831 depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI 1832 # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697 1833 depends on !CC_IS_GCC || GCC_VERSION >= 100100 1834 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9 1835 depends on !CC_IS_CLANG || CLANG_VERSION >= 120000 1836 depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS) 1837 help 1838 Build the kernel with Branch Target Identification annotations 1839 and enable enforcement of this for kernel code. When this option 1840 is enabled and the system supports BTI all kernel code including 1841 modular code must have BTI enabled. 1842 1843config CC_HAS_BRANCH_PROT_PAC_RET_BTI 1844 # GCC 9 or later, clang 8 or later 1845 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti) 1846 1847config ARM64_E0PD 1848 bool "Enable support for E0PD" 1849 default y 1850 help 1851 E0PD (part of the ARMv8.5 extensions) allows us to ensure 1852 that EL0 accesses made via TTBR1 always fault in constant time, 1853 providing similar benefits to KASLR as those provided by KPTI, but 1854 with lower overhead and without disrupting legitimate access to 1855 kernel memory such as SPE. 1856 1857 This option enables E0PD for TTBR1 where available. 1858 1859config ARCH_RANDOM 1860 bool "Enable support for random number generation" 1861 default y 1862 help 1863 Random number generation (part of the ARMv8.5 Extensions) 1864 provides a high bandwidth, cryptographically secure 1865 hardware random number generator. 1866 1867config ARM64_AS_HAS_MTE 1868 # Initial support for MTE went in binutils 2.32.0, checked with 1869 # ".arch armv8.5-a+memtag" below. However, this was incomplete 1870 # as a late addition to the final architecture spec (LDGM/STGM) 1871 # is only supported in the newer 2.32.x and 2.33 binutils 1872 # versions, hence the extra "stgm" instruction check below. 1873 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0]) 1874 1875config ARM64_MTE 1876 bool "Memory Tagging Extension support" 1877 default y 1878 depends on ARM64_AS_HAS_MTE && ARM64_TAGGED_ADDR_ABI 1879 depends on AS_HAS_ARMV8_5 1880 depends on AS_HAS_LSE_ATOMICS 1881 # Required for tag checking in the uaccess routines 1882 depends on ARM64_PAN 1883 select ARCH_USES_HIGH_VMA_FLAGS 1884 help 1885 Memory Tagging (part of the ARMv8.5 Extensions) provides 1886 architectural support for run-time, always-on detection of 1887 various classes of memory error to aid with software debugging 1888 to eliminate vulnerabilities arising from memory-unsafe 1889 languages. 1890 1891 This option enables the support for the Memory Tagging 1892 Extension at EL0 (i.e. for userspace). 1893 1894 Selecting this option allows the feature to be detected at 1895 runtime. Any secondary CPU not implementing this feature will 1896 not be allowed a late bring-up. 1897 1898 Userspace binaries that want to use this feature must 1899 explicitly opt in. The mechanism for the userspace is 1900 described in: 1901 1902 Documentation/arm64/memory-tagging-extension.rst. 1903 1904endmenu 1905 1906menu "ARMv8.7 architectural features" 1907 1908config ARM64_EPAN 1909 bool "Enable support for Enhanced Privileged Access Never (EPAN)" 1910 default y 1911 depends on ARM64_PAN 1912 help 1913 Enhanced Privileged Access Never (EPAN) allows Privileged 1914 Access Never to be used with Execute-only mappings. 1915 1916 The feature is detected at runtime, and will remain disabled 1917 if the cpu does not implement the feature. 1918endmenu 1919 1920config ARM64_SVE 1921 bool "ARM Scalable Vector Extension support" 1922 default y 1923 help 1924 The Scalable Vector Extension (SVE) is an extension to the AArch64 1925 execution state which complements and extends the SIMD functionality 1926 of the base architecture to support much larger vectors and to enable 1927 additional vectorisation opportunities. 1928 1929 To enable use of this extension on CPUs that implement it, say Y. 1930 1931 On CPUs that support the SVE2 extensions, this option will enable 1932 those too. 1933 1934 Note that for architectural reasons, firmware _must_ implement SVE 1935 support when running on SVE capable hardware. The required support 1936 is present in: 1937 1938 * version 1.5 and later of the ARM Trusted Firmware 1939 * the AArch64 boot wrapper since commit 5e1261e08abf 1940 ("bootwrapper: SVE: Enable SVE for EL2 and below"). 1941 1942 For other firmware implementations, consult the firmware documentation 1943 or vendor. 1944 1945 If you need the kernel to boot on SVE-capable hardware with broken 1946 firmware, you may need to say N here until you get your firmware 1947 fixed. Otherwise, you may experience firmware panics or lockups when 1948 booting the kernel. If unsure and you are not observing these 1949 symptoms, you should assume that it is safe to say Y. 1950 1951config ARM64_MODULE_PLTS 1952 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1953 depends on MODULES 1954 select HAVE_MOD_ARCH_SPECIFIC 1955 help 1956 Allocate PLTs when loading modules so that jumps and calls whose 1957 targets are too far away for their relative offsets to be encoded 1958 in the instructions themselves can be bounced via veneers in the 1959 module's PLT. This allows modules to be allocated in the generic 1960 vmalloc area after the dedicated module memory area has been 1961 exhausted. 1962 1963 When running with address space randomization (KASLR), the module 1964 region itself may be too far away for ordinary relative jumps and 1965 calls, and so in that case, module PLTs are required and cannot be 1966 disabled. 1967 1968 Specific errata workaround(s) might also force module PLTs to be 1969 enabled (ARM64_ERRATUM_843419). 1970 1971config ARM64_PSEUDO_NMI 1972 bool "Support for NMI-like interrupts" 1973 select ARM_GIC_V3 1974 help 1975 Adds support for mimicking Non-Maskable Interrupts through the use of 1976 GIC interrupt priority. This support requires version 3 or later of 1977 ARM GIC. 1978 1979 This high priority configuration for interrupts needs to be 1980 explicitly enabled by setting the kernel parameter 1981 "irqchip.gicv3_pseudo_nmi" to 1. 1982 1983 If unsure, say N 1984 1985if ARM64_PSEUDO_NMI 1986config ARM64_DEBUG_PRIORITY_MASKING 1987 bool "Debug interrupt priority masking" 1988 help 1989 This adds runtime checks to functions enabling/disabling 1990 interrupts when using priority masking. The additional checks verify 1991 the validity of ICC_PMR_EL1 when calling concerned functions. 1992 1993 If unsure, say N 1994endif 1995 1996config RELOCATABLE 1997 bool "Build a relocatable kernel image" if EXPERT 1998 select ARCH_HAS_RELR 1999 default y 2000 help 2001 This builds the kernel as a Position Independent Executable (PIE), 2002 which retains all relocation metadata required to relocate the 2003 kernel binary at runtime to a different virtual address than the 2004 address it was linked at. 2005 Since AArch64 uses the RELA relocation format, this requires a 2006 relocation pass at runtime even if the kernel is loaded at the 2007 same address it was linked at. 2008 2009config RANDOMIZE_BASE 2010 bool "Randomize the address of the kernel image" 2011 select ARM64_MODULE_PLTS if MODULES 2012 select RELOCATABLE 2013 help 2014 Randomizes the virtual address at which the kernel image is 2015 loaded, as a security feature that deters exploit attempts 2016 relying on knowledge of the location of kernel internals. 2017 2018 It is the bootloader's job to provide entropy, by passing a 2019 random u64 value in /chosen/kaslr-seed at kernel entry. 2020 2021 When booting via the UEFI stub, it will invoke the firmware's 2022 EFI_RNG_PROTOCOL implementation (if available) to supply entropy 2023 to the kernel proper. In addition, it will randomise the physical 2024 location of the kernel Image as well. 2025 2026 If unsure, say N. 2027 2028config RANDOMIZE_MODULE_REGION_FULL 2029 bool "Randomize the module region over a 2 GB range" 2030 depends on RANDOMIZE_BASE 2031 default y 2032 help 2033 Randomizes the location of the module region inside a 2 GB window 2034 covering the core kernel. This way, it is less likely for modules 2035 to leak information about the location of core kernel data structures 2036 but it does imply that function calls between modules and the core 2037 kernel will need to be resolved via veneers in the module PLT. 2038 2039 When this option is not set, the module region will be randomized over 2040 a limited range that contains the [_stext, _etext] interval of the 2041 core kernel, so branch relocations are almost always in range unless 2042 ARM64_MODULE_PLTS is enabled and the region is exhausted. In this 2043 particular case of region exhaustion, modules might be able to fall 2044 back to a larger 2GB area. 2045 2046config CC_HAVE_STACKPROTECTOR_SYSREG 2047 def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-protector-guard-offset=0) 2048 2049config STACKPROTECTOR_PER_TASK 2050 def_bool y 2051 depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_SYSREG 2052 2053endmenu 2054 2055menu "Boot options" 2056 2057config ARM64_ACPI_PARKING_PROTOCOL 2058 bool "Enable support for the ARM64 ACPI parking protocol" 2059 depends on ACPI 2060 help 2061 Enable support for the ARM64 ACPI parking protocol. If disabled 2062 the kernel will not allow booting through the ARM64 ACPI parking 2063 protocol even if the corresponding data is present in the ACPI 2064 MADT table. 2065 2066config CMDLINE 2067 string "Default kernel command string" 2068 default "" 2069 help 2070 Provide a set of default command-line options at build time by 2071 entering them here. As a minimum, you should specify the the 2072 root device (e.g. root=/dev/nfs). 2073 2074choice 2075 prompt "Kernel command line type" if CMDLINE != "" 2076 default CMDLINE_FROM_BOOTLOADER 2077 help 2078 Choose how the kernel will handle the provided default kernel 2079 command line string. 2080 2081config CMDLINE_FROM_BOOTLOADER 2082 bool "Use bootloader kernel arguments if available" 2083 help 2084 Uses the command-line options passed by the boot loader. If 2085 the boot loader doesn't provide any, the default kernel command 2086 string provided in CMDLINE will be used. 2087 2088config CMDLINE_FORCE 2089 bool "Always use the default kernel command string" 2090 help 2091 Always use the default kernel command string, even if the boot 2092 loader passes other arguments to the kernel. 2093 This is useful if you cannot or don't want to change the 2094 command-line options your boot loader passes to the kernel. 2095 2096endchoice 2097 2098config EFI_STUB 2099 bool 2100 2101config EFI 2102 bool "UEFI runtime support" 2103 depends on OF && !CPU_BIG_ENDIAN 2104 depends on KERNEL_MODE_NEON 2105 select ARCH_SUPPORTS_ACPI 2106 select LIBFDT 2107 select UCS2_STRING 2108 select EFI_PARAMS_FROM_FDT 2109 select EFI_RUNTIME_WRAPPERS 2110 select EFI_STUB 2111 select EFI_GENERIC_STUB 2112 imply IMA_SECURE_AND_OR_TRUSTED_BOOT 2113 default y 2114 help 2115 This option provides support for runtime services provided 2116 by UEFI firmware (such as non-volatile variables, realtime 2117 clock, and platform reset). A UEFI stub is also provided to 2118 allow the kernel to be booted as an EFI application. This 2119 is only useful on systems that have UEFI firmware. 2120 2121config DMI 2122 bool "Enable support for SMBIOS (DMI) tables" 2123 depends on EFI 2124 default y 2125 help 2126 This enables SMBIOS/DMI feature for systems. 2127 2128 This option is only useful on systems that have UEFI firmware. 2129 However, even with this option, the resultant kernel should 2130 continue to boot on existing non-UEFI platforms. 2131 2132endmenu 2133 2134config SYSVIPC_COMPAT 2135 def_bool y 2136 depends on COMPAT && SYSVIPC 2137 2138menu "Power management options" 2139 2140source "kernel/power/Kconfig" 2141 2142config ARCH_HIBERNATION_POSSIBLE 2143 def_bool y 2144 depends on CPU_PM 2145 2146config ARCH_HIBERNATION_HEADER 2147 def_bool y 2148 depends on HIBERNATION 2149 2150config ARCH_SUSPEND_POSSIBLE 2151 def_bool y 2152 2153endmenu 2154 2155menu "CPU Power Management" 2156 2157source "drivers/cpuidle/Kconfig" 2158 2159source "drivers/cpufreq/Kconfig" 2160 2161endmenu 2162 2163source "drivers/acpi/Kconfig" 2164 2165source "arch/arm64/kvm/Kconfig" 2166 2167if CRYPTO 2168source "arch/arm64/crypto/Kconfig" 2169endif 2170