1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/ { 7 cpus { 8 cpu@0 { 9 cpu0-supply = <&dcdc2_reg>; 10 }; 11 }; 12 13 memory@80000000 { 14 device_type = "memory"; 15 reg = <0x80000000 0x10000000>; /* 256 MB */ 16 }; 17 18 chosen { 19 stdout-path = &uart0; 20 }; 21 22 leds { 23 pinctrl-names = "default"; 24 pinctrl-0 = <&user_leds_s0>; 25 26 compatible = "gpio-leds"; 27 28 led2 { 29 label = "beaglebone:green:heartbeat"; 30 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 31 linux,default-trigger = "heartbeat"; 32 default-state = "off"; 33 }; 34 35 led3 { 36 label = "beaglebone:green:mmc0"; 37 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 38 linux,default-trigger = "mmc0"; 39 default-state = "off"; 40 }; 41 42 led4 { 43 label = "beaglebone:green:usr2"; 44 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 45 linux,default-trigger = "cpu0"; 46 default-state = "off"; 47 }; 48 49 led5 { 50 label = "beaglebone:green:usr3"; 51 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 52 linux,default-trigger = "mmc1"; 53 default-state = "off"; 54 }; 55 }; 56 57 vmmcsd_fixed: fixedregulator0 { 58 compatible = "regulator-fixed"; 59 regulator-name = "vmmcsd_fixed"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 }; 63}; 64 65&am33xx_pinmux { 66 pinctrl-names = "default"; 67 pinctrl-0 = <&clkout2_pin>; 68 69 user_leds_s0: user-leds-s0-pins { 70 pinctrl-single,pins = < 71 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 72 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a6.gpio1_22 */ 73 AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a7.gpio1_23 */ 74 AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_a8.gpio1_24 */ 75 >; 76 }; 77 78 i2c0_pins: i2c0-pins { 79 pinctrl-single,pins = < 80 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ 81 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ 82 >; 83 }; 84 85 i2c2_pins: i2c2-pins { 86 pinctrl-single,pins = < 87 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_ctsn.i2c2_sda */ 88 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart1_rtsn.i2c2_scl */ 89 >; 90 }; 91 92 uart0_pins: uart0-pins { 93 pinctrl-single,pins = < 94 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 95 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 96 >; 97 }; 98 99 clkout2_pin: clkout2-pins { 100 pinctrl-single,pins = < 101 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 102 >; 103 }; 104 105 cpsw_default: cpsw-default-pins { 106 pinctrl-single,pins = < 107 /* Slave 1 */ 108 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0) 109 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 110 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0) 111 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 112 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 113 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 114 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 115 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 116 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 117 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0) 118 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0) 119 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0) 120 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0) 121 >; 122 }; 123 124 cpsw_sleep: cpsw-sleep-pins { 125 pinctrl-single,pins = < 126 /* Slave 1 reset value */ 127 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) 128 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 129 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 130 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 131 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 132 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 133 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 134 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 135 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 136 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 137 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 138 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 139 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 140 >; 141 }; 142 143 davinci_mdio_default: davinci-mdio-default-pins { 144 pinctrl-single,pins = < 145 /* MDIO */ 146 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 147 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 148 /* Added to support GPIO controlled PHY reset */ 149 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7) 150 >; 151 }; 152 153 davinci_mdio_sleep: davinci-mdio-sleep-pins { 154 pinctrl-single,pins = < 155 /* MDIO reset value */ 156 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 157 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 158 /* Added to support GPIO controlled PHY reset */ 159 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7) 160 >; 161 }; 162 163 mmc1_pins: mmc1-pins { 164 pinctrl-single,pins = < 165 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spio0_cs1.gpio0_6 */ 166 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 167 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 168 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 169 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 170 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 171 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 172 >; 173 }; 174 175 emmc_pins: emmc-pins { 176 pinctrl-single,pins = < 177 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */ 178 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ 179 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ 180 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ 181 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ 182 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ 183 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ 184 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ 185 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ 186 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ 187 >; 188 }; 189}; 190 191&uart0 { 192 pinctrl-names = "default"; 193 pinctrl-0 = <&uart0_pins>; 194 195 status = "okay"; 196}; 197 198&usb0 { 199 dr_mode = "peripheral"; 200 interrupts-extended = <&intc 18 &tps 0>; 201 interrupt-names = "mc", "vbus"; 202}; 203 204&usb1 { 205 dr_mode = "host"; 206}; 207 208&i2c0 { 209 pinctrl-names = "default"; 210 pinctrl-0 = <&i2c0_pins>; 211 212 status = "okay"; 213 clock-frequency = <400000>; 214 215 tps: tps@24 { 216 reg = <0x24>; 217 }; 218 219 baseboard_eeprom: baseboard_eeprom@50 { 220 compatible = "atmel,24c256"; 221 reg = <0x50>; 222 vcc-supply = <&ldo4_reg>; 223 224 nvmem-layout { 225 compatible = "fixed-layout"; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 229 baseboard_data: baseboard_data@0 { 230 reg = <0 0x100>; 231 }; 232 }; 233 }; 234}; 235 236&i2c2 { 237 pinctrl-names = "default"; 238 pinctrl-0 = <&i2c2_pins>; 239 240 status = "okay"; 241 clock-frequency = <100000>; 242 243 cape_eeprom0: cape_eeprom0@54 { 244 compatible = "atmel,24c256"; 245 reg = <0x54>; 246 247 nvmem-layout { 248 compatible = "fixed-layout"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 252 cape0_data: cape_data@0 { 253 reg = <0 0x100>; 254 }; 255 }; 256 }; 257 258 cape_eeprom1: cape_eeprom1@55 { 259 compatible = "atmel,24c256"; 260 reg = <0x55>; 261 262 nvmem-layout { 263 compatible = "fixed-layout"; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 267 cape1_data: cape_data@0 { 268 reg = <0 0x100>; 269 }; 270 }; 271 }; 272 273 cape_eeprom2: cape_eeprom2@56 { 274 compatible = "atmel,24c256"; 275 reg = <0x56>; 276 277 nvmem-layout { 278 compatible = "fixed-layout"; 279 #address-cells = <1>; 280 #size-cells = <1>; 281 282 cape2_data: cape_data@0 { 283 reg = <0 0x100>; 284 }; 285 }; 286 }; 287 288 cape_eeprom3: cape_eeprom3@57 { 289 compatible = "atmel,24c256"; 290 reg = <0x57>; 291 292 nvmem-layout { 293 compatible = "fixed-layout"; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 297 cape3_data: cape_data@0 { 298 reg = <0 0x100>; 299 }; 300 }; 301 }; 302}; 303 304 305/include/ "../../tps65217.dtsi" 306 307&tps { 308 /* 309 * Configure pmic to enter OFF-state instead of SLEEP-state ("RTC-only 310 * mode") at poweroff. Most BeagleBone versions do not support RTC-only 311 * mode and risk hardware damage if this mode is entered. 312 * 313 * For details, see linux-omap mailing list May 2015 thread 314 * [PATCH] ARM: dts: am335x-bone* enable pmic-shutdown-controller 315 * In particular, messages: 316 * https://www.spinics.net/lists/linux-omap/msg118585.html 317 * https://www.spinics.net/lists/linux-omap/msg118615.html 318 * 319 * You can override this later with 320 * &tps { /delete-property/ ti,pmic-shutdown-controller; } 321 * if you want to use RTC-only mode and made sure you are not affected 322 * by the hardware problems. (Tip: double-check by performing a current 323 * measurement after shutdown: it should be less than 1 mA.) 324 */ 325 326 interrupts = <7>; /* NMI */ 327 interrupt-parent = <&intc>; 328 329 ti,pmic-shutdown-controller; 330 331 charger { 332 status = "okay"; 333 }; 334 335 pwrbutton { 336 status = "okay"; 337 }; 338 339 regulators { 340 dcdc1_reg: regulator@0 { 341 regulator-name = "vdds_dpr"; 342 regulator-always-on; 343 }; 344 345 dcdc2_reg: regulator@1 { 346 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 347 regulator-name = "vdd_mpu"; 348 regulator-min-microvolt = <925000>; 349 regulator-max-microvolt = <1351500>; 350 regulator-boot-on; 351 regulator-always-on; 352 }; 353 354 dcdc3_reg: regulator@2 { 355 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 356 regulator-name = "vdd_core"; 357 regulator-min-microvolt = <925000>; 358 regulator-max-microvolt = <1150000>; 359 regulator-boot-on; 360 regulator-always-on; 361 }; 362 363 ldo1_reg: regulator@3 { 364 regulator-name = "vio,vrtc,vdds"; 365 regulator-always-on; 366 }; 367 368 ldo2_reg: regulator@4 { 369 regulator-name = "vdd_3v3aux"; 370 regulator-always-on; 371 }; 372 373 ldo3_reg: regulator@5 { 374 regulator-name = "vdd_1v8"; 375 regulator-always-on; 376 }; 377 378 ldo4_reg: regulator@6 { 379 regulator-name = "vdd_3v3a"; 380 regulator-always-on; 381 }; 382 }; 383}; 384 385&cpsw_port1 { 386 phy-handle = <ðphy0>; 387 phy-mode = "mii"; 388 ti,dual-emac-pvid = <1>; 389}; 390 391&cpsw_port2 { 392 status = "disabled"; 393}; 394 395&mac_sw { 396 pinctrl-names = "default", "sleep"; 397 pinctrl-0 = <&cpsw_default>; 398 pinctrl-1 = <&cpsw_sleep>; 399 status = "okay"; 400}; 401 402&davinci_mdio_sw { 403 pinctrl-names = "default", "sleep"; 404 pinctrl-0 = <&davinci_mdio_default>; 405 pinctrl-1 = <&davinci_mdio_sleep>; 406 407 ethphy0: ethernet-phy@0 { 408 reg = <0>; 409 /* Support GPIO reset on revision C3 boards */ 410 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; 411 reset-assert-us = <300>; 412 reset-deassert-us = <13000>; 413 }; 414}; 415 416&mmc1 { 417 status = "okay"; 418 bus-width = <0x4>; 419 pinctrl-names = "default"; 420 pinctrl-0 = <&mmc1_pins>; 421 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 422}; 423 424&aes { 425 status = "okay"; 426}; 427 428&sham { 429 status = "okay"; 430}; 431 432&rtc { 433 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 434 clock-names = "ext-clk", "int-clk"; 435 system-power-controller; 436}; 437 438&pruss_tm { 439 status = "okay"; 440}; 441 442&wkup_m3_ipc { 443 firmware-name = "am335x-bone-scale-data.bin"; 444}; 445