xref: /linux/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi (revision 0fc8f6200d2313278fbf4539bbab74677c685531) 
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
4 * Author: Dom VOVARD <dom.vovard@linrt.com>
5 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
6 * Copyright (C) 2024 PHYTEC Messtechnik GmbH
7 * Author: Christophe Parant <c.parant@phytec.fr>
8 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/input/input.h>
12#include <dt-bindings/mfd/st,stpmic1.h>
13#include <dt-bindings/net/ti-dp83867.h>
14#include "stm32mp15-pinctrl.dtsi"
15#include "stm32mp15xxac-pinctrl.dtsi"
16
17/ {
18
19	aliases {
20		ethernet0 = &ethernet0;
21		rtc0 = &i2c4_rtc;
22		rtc1 = &rtc;
23	};
24
25	/*
26	 * Set the minimum memory size here and
27	 * let the bootloader set the real size.
28	 */
29	memory@c0000000 {
30		device_type = "memory";
31		reg = <0xc0000000 0x20000000>;
32	};
33
34	reserved-memory {
35		#address-cells = <1>;
36		#size-cells = <1>;
37		ranges;
38
39		mcuram2: mcuram2@10000000 {
40			compatible = "shared-dma-pool";
41			reg = <0x10000000 0x40000>;
42			no-map;
43		};
44
45		vdev0vring0: vdev0vring0@10040000 {
46			compatible = "shared-dma-pool";
47			reg = <0x10040000 0x1000>;
48			no-map;
49		};
50
51		vdev0vring1: vdev0vring1@10041000 {
52			compatible = "shared-dma-pool";
53			reg = <0x10041000 0x1000>;
54			no-map;
55		};
56
57		vdev0buffer: vdev0buffer@10042000 {
58			compatible = "shared-dma-pool";
59			reg = <0x10042000 0x4000>;
60			no-map;
61		};
62
63		mcuram: mcuram@30000000 {
64			compatible = "shared-dma-pool";
65			reg = <0x30000000 0x40000>;
66			no-map;
67		};
68
69		retram: retram@38000000 {
70			compatible = "shared-dma-pool";
71			reg = <0x38000000 0x10000>;
72			no-map;
73		};
74	};
75
76	regulator_vin: regulator {
77		compatible = "regulator-fixed";
78		regulator-name = "VIN";
79		regulator-min-microvolt = <5000000>;
80		regulator-max-microvolt = <5000000>;
81		regulator-always-on;
82	};
83};
84
85&ethernet0 {
86	pinctrl-0 = <&ethernet0_rgmii_pins_d>;
87	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_d>;
88	pinctrl-names = "default", "sleep";
89	phy-mode = "rgmii-id";
90	max-speed = <1000>;
91	phy-handle = <&phy0>;
92	st,eth-clk-sel;
93	status = "okay";
94
95	mdio {
96		#address-cells = <1>;
97		#size-cells = <0>;
98		compatible = "snps,dwmac-mdio";
99
100		phy0: ethernet-phy@1 {
101			compatible = "ethernet-phy-ieee802.3-c22";
102			reg = <1>;
103			interrupt-parent = <&gpiog>;
104			interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
105			enet-phy-lane-no-swap;
106			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
107			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
108			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
109			ti,min-output-impedance;
110			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
111		};
112	};
113};
114
115&fmc {
116	pinctrl-names = "default", "sleep";
117	pinctrl-0 = <&fmc_pins_a>;
118	pinctrl-1 = <&fmc_sleep_pins_a>;
119	status = "disabled";
120
121	nand-controller@4,0 {
122		nand0: nand@0 {
123			reg = <0>;
124			nand-on-flash-bbt;
125			nand-ecc-strength = <4>;
126			nand-ecc-step-size = <512>;
127		};
128	};
129};
130
131&i2c4 {
132	pinctrl-names = "default", "sleep";
133	pinctrl-0 = <&i2c4_pins_a>;
134	pinctrl-1 = <&i2c4_sleep_pins_a>;
135	i2c-scl-rising-time-ns = <185>;
136	i2c-scl-falling-time-ns = <20>;
137	status = "okay";
138
139	pmic@33 {
140		compatible = "st,stpmic1";
141		reg = <0x33>;
142		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
143		interrupt-controller;
144		#interrupt-cells = <2>;
145
146		regulators {
147			compatible = "st,stpmic1-regulators";
148			buck1-supply = <&regulator_vin>;
149			buck2-supply = <&regulator_vin>;
150			buck3-supply = <&regulator_vin>;
151			buck4-supply = <&regulator_vin>;
152			ldo1-supply = <&v3v3>;
153			ldo2-supply = <&v3v3>;
154			ldo3-supply = <&vdd_ddr>;
155			ldo4-supply = <&regulator_vin>;
156			ldo5-supply = <&v3v3>;
157			ldo6-supply = <&v3v3>;
158			boost-supply = <&regulator_vin>;
159			pwr_sw1-supply = <&bst_out>;
160			pwr_sw2-supply = <&bst_out>;
161
162			vddcore: buck1 {
163				regulator-name = "VDD_CORE";
164				regulator-min-microvolt = <1200000>;
165				regulator-max-microvolt = <1350000>;
166				regulator-always-on;
167				regulator-initial-mode = <0>;
168			};
169
170			vdd_ddr: buck2 {
171				regulator-name = "VDD_DDR";
172				regulator-min-microvolt = <1350000>;
173				regulator-max-microvolt = <1350000>;
174				regulator-always-on;
175				regulator-initial-mode = <0>;
176			};
177
178			vdd: buck3 {
179				regulator-name = "VDD";
180				regulator-min-microvolt = <3300000>;
181				regulator-max-microvolt = <3300000>;
182				regulator-always-on;
183				st,mask-reset;
184				regulator-initial-mode = <0>;
185			};
186
187			v3v3: buck4 {
188				regulator-name = "VDD_BUCK4";
189				regulator-min-microvolt = <3300000>;
190				regulator-max-microvolt = <3300000>;
191				regulator-always-on;
192				regulator-initial-mode = <0>;
193			};
194
195			v1v8_audio: ldo1 {
196				regulator-name = "VDD_LDO1";
197				regulator-min-microvolt = <1800000>;
198				regulator-max-microvolt = <1800000>;
199				regulator-always-on;
200				interrupts = <IT_CURLIM_LDO1 0>;
201
202			};
203
204			vdd_eth_2v5: ldo2 {
205				regulator-name = "VDD_ETH_2V5";
206				regulator-min-microvolt = <2500000>;
207				regulator-max-microvolt = <2500000>;
208				regulator-always-on;
209				interrupts = <IT_CURLIM_LDO2 0>;
210
211			};
212
213			vtt_ddr: ldo3 {
214				regulator-name = "VTT_DDR";
215				regulator-min-microvolt = <500000>;
216				regulator-max-microvolt = <750000>;
217				regulator-always-on;
218				regulator-over-current-protection;
219			};
220
221			vdd_usb: ldo4 {
222				regulator-name = "VDD_USB";
223				interrupts = <IT_CURLIM_LDO4 0>;
224			};
225
226			vdda: ldo5 {
227				regulator-name = "VDDA";
228				regulator-min-microvolt = <2900000>;
229				regulator-max-microvolt = <2900000>;
230				interrupts = <IT_CURLIM_LDO5 0>;
231				regulator-boot-on;
232			};
233
234			vdd_eth_1v0: ldo6 {
235				regulator-name = "VDD_ETH_1V0";
236				regulator-min-microvolt = <1000000>;
237				regulator-max-microvolt = <1000000>;
238				regulator-always-on;
239				interrupts = <IT_CURLIM_LDO6 0>;
240
241			};
242
243			vref_ddr: vref_ddr {
244				regulator-name = "VDD_REFDDR";
245				regulator-always-on;
246			};
247
248			bst_out: boost {
249				regulator-name = "BST_OUT";
250				interrupts = <IT_OCP_BOOST 0>;
251			};
252
253			vbus_otg: pwr_sw1 {
254				regulator-name = "VBUS_OTG";
255				interrupts = <IT_OCP_OTG 0>;
256				regulator-active-discharge = <1>;
257			};
258
259			vbus_sw: pwr_sw2 {
260				regulator-name = "VBUS_SW";
261				interrupts = <IT_OCP_SWOUT 0>;
262				regulator-active-discharge = <1>;
263			};
264		};
265
266		onkey {
267			compatible = "st,stpmic1-onkey";
268			interrupts = <IT_PONKEY_F 0>,
269				     <IT_PONKEY_R 0>;
270			interrupt-names = "onkey-falling",
271					  "onkey-rising";
272			power-off-time-sec = <10>;
273		};
274
275		watchdog {
276			compatible = "st,stpmic1-wdt";
277		};
278	};
279
280	i2c4_eeprom: eeprom@50 {
281		compatible = "atmel,24c32";
282		reg = <0x50>;
283		status = "disabled";
284	};
285
286	i2c4_rtc: rtc@52 {
287		compatible = "microcrystal,rv3028";
288		reg = <0x52>;
289		status = "disabled";
290	};
291};
292
293&ipcc {
294	status = "okay";
295};
296
297&iwdg2 {
298	timeout-sec = <32>;
299	status = "okay";
300};
301
302&m4_rproc {
303	memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>,
304			<&vdev0vring1>, <&vdev0buffer>;
305	mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>;
306	mbox-names = "vq0", "vq1", "shutdown", "detach";
307	interrupt-parent = <&exti>;
308	interrupts = <68 1>;
309	status = "okay";
310};
311
312&pwr_regulators {
313	vdd-supply = <&vdd>;
314	vdd_3v3_usbfs-supply = <&vdd_usb>;
315};
316
317&qspi {
318	pinctrl-names = "default", "sleep";
319	pinctrl-0 = <&qspi_clk_pins_a
320		     &qspi_bk1_pins_a
321		     &qspi_cs1_pins_a>;
322	pinctrl-1 = <&qspi_clk_sleep_pins_a
323		     &qspi_bk1_sleep_pins_a
324		     &qspi_cs1_sleep_pins_a>;
325	reg = <0x58003000 0x1000>,
326	      <0x70000000 0x1000000>;
327	status = "disabled";
328
329	flash0: flash@0 {
330		compatible = "jedec,spi-nor";
331		reg = <0>;
332		spi-rx-bus-width = <4>;
333		spi-max-frequency = <50000000>;
334		m25p,fast-read;
335	};
336};
337
338&rng1 {
339	status = "okay";
340};
341
342&rtc {
343	status = "okay";
344};
345
346&dts {
347	status = "okay";
348};
349
350&sdmmc2 {
351	pinctrl-names = "default", "opendrain", "sleep";
352	pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>;
353	pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>;
354	pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>;
355	non-removable;
356	no-sd;
357	no-sdio;
358	bus-width = <8>;
359	vmmc-supply = <&v3v3>;
360	vqmmc-supply = <&v3v3>;
361	mmc-ddr-3_3v;
362	st,neg-edge;
363	status = "disabled";
364};
365