1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2026 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <arm64/rockchip/rockchip-pinconf.dtsi> 8 9&pinctrl { 10 cam-clk0 { 11 /omit-if-no-ref/ 12 cam_clk0: cam-clk0 { 13 rockchip,pins = 14 /* cam_clk0_out */ 15 <1 RK_PB5 1 &pcfg_pull_none>; 16 }; 17 }; 18 19 cam-clk1 { 20 /omit-if-no-ref/ 21 cam_clk1: cam-clk1 { 22 rockchip,pins = 23 /* cam_clk1_out */ 24 <1 RK_PB6 1 &pcfg_pull_none>; 25 }; 26 }; 27 28 cam-spi { 29 /omit-if-no-ref/ 30 cam_spi_bus4: cam-spi-bus4 { 31 rockchip,pins = 32 /* cam_spi_d0 */ 33 <0 RK_PB5 4 &pcfg_pull_up_drv_level_2>, 34 /* cam_spi_d1 */ 35 <0 RK_PB2 4 &pcfg_pull_up_drv_level_2>, 36 /* cam_spi_d2 */ 37 <0 RK_PB1 4 &pcfg_pull_up_drv_level_2>, 38 /* cam_spi_d3 */ 39 <0 RK_PB0 4 &pcfg_pull_up_drv_level_2>; 40 }; 41 42 /omit-if-no-ref/ 43 cam_spi_clk: cam-spi-clk { 44 rockchip,pins = 45 /* cam_spi_clk */ 46 <0 RK_PB4 4 &pcfg_pull_none>; 47 }; 48 /omit-if-no-ref/ 49 cam_spi_cs0n: cam-spi-cs0n { 50 rockchip,pins = 51 /* cam_spi_cs0n */ 52 <0 RK_PB3 4 &pcfg_pull_none>; 53 }; 54 }; 55 56 clk { 57 /omit-if-no-ref/ 58 clk_32k: clk-32k { 59 rockchip,pins = 60 /* clk_32k */ 61 <0 RK_PA0 2 &pcfg_pull_none>; 62 }; 63 }; 64 65 clk-24m { 66 /omit-if-no-ref/ 67 clk_24m_out: clk-24m-out { 68 rockchip,pins = 69 /* clk_24m_out */ 70 <0 RK_PA0 3 &pcfg_pull_none>; 71 }; 72 }; 73 74 cpu { 75 /omit-if-no-ref/ 76 cpu: cpu { 77 rockchip,pins = 78 /* cpu_avs */ 79 <0 RK_PA1 2 &pcfg_pull_none>; 80 }; 81 }; 82 83 emmc { 84 /omit-if-no-ref/ 85 emmc_bus4: emmc-bus4 { 86 rockchip,pins = 87 /* emmc_d0 */ 88 <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 89 /* emmc_d1 */ 90 <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, 91 /* emmc_d2 */ 92 <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, 93 /* emmc_d3 */ 94 <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>; 95 }; 96 97 /omit-if-no-ref/ 98 emmc_clk: emmc-clk { 99 rockchip,pins = 100 /* emmc_clk */ 101 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 102 }; 103 104 /omit-if-no-ref/ 105 emmc_cmd: emmc-cmd { 106 rockchip,pins = 107 /* emmc_cmd */ 108 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; 109 }; 110 }; 111 112 fspi { 113 /omit-if-no-ref/ 114 fspi_bus4: fspi-bus4 { 115 rockchip,pins = 116 /* fspi_d0 */ 117 <1 RK_PA1 2 &pcfg_pull_none>, 118 /* fspi_d1 */ 119 <1 RK_PA2 2 &pcfg_pull_none>, 120 /* fspi_d2 */ 121 <1 RK_PA3 2 &pcfg_pull_none>, 122 /* fspi_d3 */ 123 <1 RK_PA0 2 &pcfg_pull_none>; 124 }; 125 126 /omit-if-no-ref/ 127 fspi_cs0: fspi-cs0 { 128 rockchip,pins = 129 /* fspi_cs0n */ 130 <1 RK_PA5 2 &pcfg_pull_up>; 131 }; 132 133 /omit-if-no-ref/ 134 fspi_clk: fspi-clk { 135 rockchip,pins = 136 /* fspi_clk */ 137 <1 RK_PA4 2 &pcfg_pull_none>; 138 }; 139 }; 140 141 i2c0 { 142 /omit-if-no-ref/ 143 i2c0m0_xfer: i2c0m0-xfer { 144 rockchip,pins = 145 /* i2c0_scl_m0 */ 146 <0 RK_PA5 3 &pcfg_pull_none_smt>, 147 /* i2c0_sda_m0 */ 148 <0 RK_PA6 3 &pcfg_pull_none_smt>; 149 }; 150 151 /omit-if-no-ref/ 152 i2c0m1_xfer: i2c0m1-xfer { 153 rockchip,pins = 154 /* i2c0_scl_m1 */ 155 <1 RK_PB4 5 &pcfg_pull_none_smt>, 156 /* i2c0_sda_m1 */ 157 <1 RK_PB3 5 &pcfg_pull_none_smt>; 158 }; 159 160 /omit-if-no-ref/ 161 i2c0m2_xfer: i2c0m2-xfer { 162 rockchip,pins = 163 /* i2c0_scl_m2 */ 164 <1 RK_PB5 2 &pcfg_pull_none_smt>, 165 /* i2c0_sda_m2 */ 166 <1 RK_PB6 2 &pcfg_pull_none_smt>; 167 }; 168 }; 169 170 i2c1 { 171 /omit-if-no-ref/ 172 i2c1m0_xfer: i2c1m0-xfer { 173 rockchip,pins = 174 /* i2c1_scl_m0 */ 175 <0 RK_PB0 1 &pcfg_pull_none_smt>, 176 /* i2c1_sda_m0 */ 177 <0 RK_PB1 1 &pcfg_pull_none_smt>; 178 }; 179 180 /omit-if-no-ref/ 181 i2c1m1_xfer: i2c1m1-xfer { 182 rockchip,pins = 183 /* i2c1_scl_m1 */ 184 <2 RK_PA4 4 &pcfg_pull_none_smt>, 185 /* i2c1_sda_m1 */ 186 <2 RK_PA5 4 &pcfg_pull_none_smt>; 187 }; 188 }; 189 190 i2c2 { 191 /omit-if-no-ref/ 192 i2c2m0_xfer: i2c2m0-xfer { 193 rockchip,pins = 194 /* i2c2_scl_m0 */ 195 <0 RK_PB2 1 &pcfg_pull_none_smt>, 196 /* i2c2_sda_m0 */ 197 <0 RK_PB3 1 &pcfg_pull_none_smt>; 198 }; 199 200 /omit-if-no-ref/ 201 i2c2m1_xfer: i2c2m1-xfer { 202 rockchip,pins = 203 /* i2c2_scl_m1 */ 204 <2 RK_PA6 4 &pcfg_pull_none_smt>, 205 /* i2c2_sda_m1 */ 206 <2 RK_PA7 4 &pcfg_pull_none_smt>; 207 }; 208 }; 209 210 i2c3 { 211 /omit-if-no-ref/ 212 i2c3m0_xfer: i2c3m0-xfer { 213 rockchip,pins = 214 /* i2c3_scl_m0 */ 215 <0 RK_PB4 1 &pcfg_pull_none_smt>, 216 /* i2c3_sda_m0 */ 217 <0 RK_PB5 1 &pcfg_pull_none_smt>; 218 }; 219 220 /omit-if-no-ref/ 221 i2c3m1_xfer: i2c3m1-xfer { 222 rockchip,pins = 223 /* i2c3_scl_m1 */ 224 <2 RK_PB3 4 &pcfg_pull_none_smt>, 225 /* i2c3_sda_m1 */ 226 <2 RK_PB2 4 &pcfg_pull_none_smt>; 227 }; 228 }; 229 230 i2c4 { 231 /omit-if-no-ref/ 232 i2c4m0_xfer: i2c4m0-xfer { 233 rockchip,pins = 234 /* i2c4_scl_m0 */ 235 <2 RK_PB0 4 &pcfg_pull_none_smt>, 236 /* i2c4_sda_m0 */ 237 <2 RK_PB1 4 &pcfg_pull_none_smt>; 238 }; 239 240 /omit-if-no-ref/ 241 i2c4m1_xfer: i2c4m1-xfer { 242 rockchip,pins = 243 /* i2c4_scl_m1 */ 244 <1 RK_PB7 2 &pcfg_pull_none_smt>, 245 /* i2c4_sda_m1 */ 246 <1 RK_PC0 2 &pcfg_pull_none_smt>; 247 }; 248 }; 249 250 jtag { 251 /omit-if-no-ref/ 252 jtagm0: jtagm0 { 253 rockchip,pins = 254 /* jtag_tck_m0 */ 255 <0 RK_PA5 5 &pcfg_pull_none>, 256 /* jtag_tms_m0 */ 257 <0 RK_PA6 5 &pcfg_pull_none>; 258 }; 259 260 /omit-if-no-ref/ 261 jtagm1: jtagm1 { 262 rockchip,pins = 263 /* jtag_tck_m1 */ 264 <0 RK_PB4 3 &pcfg_pull_none>, 265 /* jtag_tms_m1 */ 266 <0 RK_PB5 3 &pcfg_pull_none>; 267 }; 268 269 /omit-if-no-ref/ 270 jtagm2: jtagm2 { 271 rockchip,pins = 272 /* jtag_tck_m2 */ 273 <1 RK_PB4 3 &pcfg_pull_none>, 274 /* jtag_tms_m2 */ 275 <1 RK_PB3 3 &pcfg_pull_none>; 276 }; 277 }; 278 279 psram-spi { 280 /omit-if-no-ref/ 281 psram_spi_bus4: psram-spi-bus4 { 282 rockchip,pins = 283 /* psram_spi_d0 */ 284 <0 RK_PA2 4 &pcfg_pull_none>, 285 /* psram_spi_d1 */ 286 <0 RK_PA1 4 &pcfg_pull_none>, 287 /* psram_spi_d2 */ 288 <0 RK_PA5 4 &pcfg_pull_none>, 289 /* psram_spi_d3 */ 290 <0 RK_PA6 4 &pcfg_pull_none>; 291 }; 292 293 /omit-if-no-ref/ 294 psram_spi_clk: psram-spi-clk { 295 rockchip,pins = 296 /* psram_spi_clk */ 297 <0 RK_PA0 4 &pcfg_pull_none>; 298 }; 299 /omit-if-no-ref/ 300 psram_spi_cs0n: psram-spi-cs0n { 301 rockchip,pins = 302 /* psram_spi_cs0n */ 303 <0 RK_PA4 4 &pcfg_pull_none>; 304 }; 305 }; 306 307 pwm0 { 308 /omit-if-no-ref/ 309 pwm0m0_ch0: pwm0m0-ch0 { 310 rockchip,pins = 311 /* pwm0m0_ch0 */ 312 <0 RK_PA1 1 &pcfg_pull_none_drv_level_0>; 313 }; 314 /omit-if-no-ref/ 315 pwm0m0_ch1: pwm0m0-ch1 { 316 rockchip,pins = 317 /* pwm0m0_ch1 */ 318 <0 RK_PA5 2 &pcfg_pull_none_drv_level_0>; 319 }; 320 /omit-if-no-ref/ 321 pwm0m0_ch2: pwm0m0-ch2 { 322 rockchip,pins = 323 /* pwm0m0_ch2 */ 324 <0 RK_PA6 2 &pcfg_pull_none_drv_level_0>; 325 }; 326 /omit-if-no-ref/ 327 pwm0m0_ch3: pwm0m0-ch3 { 328 rockchip,pins = 329 /* pwm0m0_ch3 */ 330 <0 RK_PA2 1 &pcfg_pull_none_drv_level_0>; 331 }; 332 333 /omit-if-no-ref/ 334 pwm0m1_ch0: pwm0m1-ch0 { 335 rockchip,pins = 336 /* pwm0m1_ch0 */ 337 <2 RK_PA0 3 &pcfg_pull_none_drv_level_0>; 338 }; 339 /omit-if-no-ref/ 340 pwm0m1_ch1: pwm0m1-ch1 { 341 rockchip,pins = 342 /* pwm0m1_ch1 */ 343 <2 RK_PA1 3 &pcfg_pull_none_drv_level_0>; 344 }; 345 /omit-if-no-ref/ 346 pwm0m1_ch2: pwm0m1-ch2 { 347 rockchip,pins = 348 /* pwm0m1_ch2 */ 349 <2 RK_PA2 3 &pcfg_pull_none_drv_level_0>; 350 }; 351 /omit-if-no-ref/ 352 pwm0m1_ch3: pwm0m1-ch3 { 353 rockchip,pins = 354 /* pwm0m1_ch3 */ 355 <2 RK_PB0 3 &pcfg_pull_none_drv_level_0>; 356 }; 357 358 /omit-if-no-ref/ 359 pwm0m2_ch1: pwm0m2-ch1 { 360 rockchip,pins = 361 /* pwm0m2_ch1 */ 362 <1 RK_PB7 1 &pcfg_pull_none_drv_level_0>; 363 }; 364 /omit-if-no-ref/ 365 pwm0m2_ch2: pwm0m2-ch2 { 366 rockchip,pins = 367 /* pwm0m2_ch2 */ 368 <1 RK_PC0 1 &pcfg_pull_none_drv_level_0>; 369 }; 370 }; 371 372 pwm1 { 373 /omit-if-no-ref/ 374 pwm1m0_ch0: pwm1m0-ch0 { 375 rockchip,pins = 376 /* pwm1m0_ch0 */ 377 <0 RK_PB0 3 &pcfg_pull_none_drv_level_0>; 378 }; 379 /omit-if-no-ref/ 380 pwm1m0_ch1: pwm1m0-ch1 { 381 rockchip,pins = 382 /* pwm1m0_ch1 */ 383 <0 RK_PB1 3 &pcfg_pull_none_drv_level_0>; 384 }; 385 /omit-if-no-ref/ 386 pwm1m0_ch2: pwm1m0-ch2 { 387 rockchip,pins = 388 /* pwm1m0_ch2 */ 389 <0 RK_PB2 3 &pcfg_pull_none_drv_level_0>; 390 }; 391 /omit-if-no-ref/ 392 pwm1m0_ch3: pwm1m0-ch3 { 393 rockchip,pins = 394 /* pwm1m0_ch3 */ 395 <0 RK_PB3 3 &pcfg_pull_none_drv_level_0>; 396 }; 397 398 /omit-if-no-ref/ 399 pwm1m1_ch0: pwm1m1-ch0 { 400 rockchip,pins = 401 /* pwm1m1_ch0 */ 402 <2 RK_PA3 3 &pcfg_pull_none_drv_level_0>; 403 }; 404 /omit-if-no-ref/ 405 pwm1m1_ch1: pwm1m1-ch1 { 406 rockchip,pins = 407 /* pwm1m1_ch1 */ 408 <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; 409 }; 410 /omit-if-no-ref/ 411 pwm1m1_ch2: pwm1m1-ch2 { 412 rockchip,pins = 413 /* pwm1m1_ch2 */ 414 <2 RK_PA5 3 &pcfg_pull_none_drv_level_0>; 415 }; 416 /omit-if-no-ref/ 417 pwm1m1_ch3: pwm1m1-ch3 { 418 rockchip,pins = 419 /* pwm1m1_ch3 */ 420 <2 RK_PB1 3 &pcfg_pull_none_drv_level_0>; 421 }; 422 }; 423 424 pwm2 { 425 /omit-if-no-ref/ 426 pwm2m0_ch0: pwm2m0-ch0 { 427 rockchip,pins = 428 /* pwm2m0_ch0 */ 429 <1 RK_PB0 4 &pcfg_pull_none_drv_level_0>; 430 }; 431 /omit-if-no-ref/ 432 pwm2m0_ch1: pwm2m0-ch1 { 433 rockchip,pins = 434 /* pwm2m0_ch1 */ 435 <1 RK_PA7 4 &pcfg_pull_none_drv_level_0>; 436 }; 437 /omit-if-no-ref/ 438 pwm2m0_ch2: pwm2m0-ch2 { 439 rockchip,pins = 440 /* pwm2m0_ch2 */ 441 <1 RK_PB4 4 &pcfg_pull_none_drv_level_0>; 442 }; 443 /omit-if-no-ref/ 444 pwm2m0_ch3: pwm2m0-ch3 { 445 rockchip,pins = 446 /* pwm2m0_ch3 */ 447 <1 RK_PB3 4 &pcfg_pull_none_drv_level_0>; 448 }; 449 450 /omit-if-no-ref/ 451 pwm2m1_ch0: pwm2m1-ch0 { 452 rockchip,pins = 453 /* pwm2m1_ch0 */ 454 <2 RK_PA6 3 &pcfg_pull_none_drv_level_0>; 455 }; 456 /omit-if-no-ref/ 457 pwm2m1_ch1: pwm2m1-ch1 { 458 rockchip,pins = 459 /* pwm2m1_ch1 */ 460 <2 RK_PA7 3 &pcfg_pull_none_drv_level_0>; 461 }; 462 /omit-if-no-ref/ 463 pwm2m1_ch2: pwm2m1-ch2 { 464 rockchip,pins = 465 /* pwm2m1_ch2 */ 466 <2 RK_PB2 3 &pcfg_pull_none_drv_level_0>; 467 }; 468 /omit-if-no-ref/ 469 pwm2m1_ch3: pwm2m1-ch3 { 470 rockchip,pins = 471 /* pwm2m1_ch3 */ 472 <2 RK_PB3 3 &pcfg_pull_none_drv_level_0>; 473 }; 474 }; 475 476 pwr { 477 /omit-if-no-ref/ 478 pwr: pwr { 479 rockchip,pins = 480 /* pwr_ctrl0 */ 481 <0 RK_PA3 1 &pcfg_pull_none>, 482 /* pwr_ctrl1 */ 483 <0 RK_PA4 1 &pcfg_pull_none>; 484 }; 485 }; 486 487 rtc_32k { 488 /omit-if-no-ref/ 489 rtc_32k: rtc-32k { 490 rockchip,pins = 491 /* rtc_32k_out */ 492 <0 RK_PA0 1 &pcfg_pull_none>; 493 }; 494 }; 495 496 sai { 497 /omit-if-no-ref/ 498 sai: sai { 499 rockchip,pins = 500 /* sai_lrck */ 501 <2 RK_PB1 5 &pcfg_pull_none>, 502 /* sai_mclk */ 503 <2 RK_PB0 5 &pcfg_pull_none>, 504 /* sai_sclk */ 505 <2 RK_PA7 5 &pcfg_pull_none>, 506 /* sai_sdi */ 507 <2 RK_PA6 5 &pcfg_pull_none>, 508 /* sai_sdo */ 509 <2 RK_PB2 5 &pcfg_pull_none>; 510 }; 511 }; 512 513 sdmmc0 { 514 /omit-if-no-ref/ 515 sdmmc0_bus4: sdmmc0-bus4 { 516 rockchip,pins = 517 /* sdmmc0_d0 */ 518 <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>, 519 /* sdmmc0_d1 */ 520 <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>, 521 /* sdmmc0_d2 */ 522 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, 523 /* sdmmc0_d3 */ 524 <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; 525 }; 526 527 /omit-if-no-ref/ 528 sdmmc0_clk: sdmmc0-clk { 529 rockchip,pins = 530 /* sdmmc0_clk */ 531 <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; 532 }; 533 534 /omit-if-no-ref/ 535 sdmmc0_cmd: sdmmc0-cmd { 536 rockchip,pins = 537 /* sdmmc0_cmd */ 538 <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; 539 }; 540 541 /omit-if-no-ref/ 542 sdmmc0_det: sdmmc0-det { 543 rockchip,pins = 544 /* sdmmc0_det */ 545 <1 RK_PA6 1 &pcfg_pull_up>; 546 }; 547 }; 548 549 sdmmc1 { 550 /omit-if-no-ref/ 551 sdmmc1_bus4: sdmmc1-bus4 { 552 rockchip,pins = 553 /* sdmmc1_d0 */ 554 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 555 /* sdmmc1_d1 */ 556 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, 557 /* sdmmc1_d2 */ 558 <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, 559 /* sdmmc1_d3 */ 560 <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 561 }; 562 563 /omit-if-no-ref/ 564 sdmmc1_clk: sdmmc1-clk { 565 rockchip,pins = 566 /* sdmmc1_clk */ 567 <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; 568 }; 569 570 /omit-if-no-ref/ 571 sdmmc1_cmd: sdmmc1-cmd { 572 rockchip,pins = 573 /* sdmmc1_cmd */ 574 <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; 575 }; 576 }; 577 578 spi0 { 579 /omit-if-no-ref/ 580 spi0m0_clk: spi0m0-clk { 581 rockchip,pins = 582 /* spi0_clk_m0 */ 583 <2 RK_PB0 2 &pcfg_pull_none>, 584 /* spi0_miso_m0 */ 585 <2 RK_PB3 2 &pcfg_pull_none>, 586 /* spi0_mosi_m0 */ 587 <2 RK_PB1 2 &pcfg_pull_none>; 588 }; 589 590 /omit-if-no-ref/ 591 spi0m0_cs0: spi0m0-cs0 { 592 rockchip,pins = 593 /* spi0_cs0n_m0 */ 594 <2 RK_PB2 2 &pcfg_pull_none>; 595 }; 596 597 /omit-if-no-ref/ 598 spi0m0_cs1: spi0m0-cs1 { 599 rockchip,pins = 600 /* spi0_cs1n_m0 */ 601 <2 RK_PA7 2 &pcfg_pull_none>; 602 }; 603 604 /omit-if-no-ref/ 605 spi0m1_clk: spi0m1-clk { 606 rockchip,pins = 607 /* spi0_clk_m1 */ 608 <2 RK_PA2 5 &pcfg_pull_none>, 609 /* spi0_miso_m1 */ 610 <2 RK_PA4 5 &pcfg_pull_none>, 611 /* spi0_mosi_m1 */ 612 <2 RK_PA1 5 &pcfg_pull_none>; 613 }; 614 615 /omit-if-no-ref/ 616 spi0m1_cs0: spi0m1-cs0 { 617 rockchip,pins = 618 /* spi0_cs0n_m1 */ 619 <2 RK_PA3 5 &pcfg_pull_none>; 620 }; 621 622 /omit-if-no-ref/ 623 spi0m1_cs1: spi0m1-cs1 { 624 rockchip,pins = 625 /* spi0_cs1n_m1 */ 626 <2 RK_PA0 5 &pcfg_pull_none>; 627 }; 628 }; 629 630 uart0 { 631 /omit-if-no-ref/ 632 uart0m0_xfer: uart0m0-xfer { 633 rockchip,pins = 634 /* uart0_rx_m0 */ 635 <0 RK_PA6 1 &pcfg_pull_up>, 636 /* uart0_tx_m0 */ 637 <0 RK_PA5 1 &pcfg_pull_up>; 638 }; 639 640 /omit-if-no-ref/ 641 uart0m1_xfer: uart0m1-xfer { 642 rockchip,pins = 643 /* uart0_rx_m1 */ 644 <0 RK_PB5 2 &pcfg_pull_up>, 645 /* uart0_tx_m1 */ 646 <0 RK_PB4 2 &pcfg_pull_up>; 647 }; 648 649 /omit-if-no-ref/ 650 uart0m2_xfer: uart0m2-xfer { 651 rockchip,pins = 652 /* uart0_rx_m2 */ 653 <1 RK_PB3 2 &pcfg_pull_up>, 654 /* uart0_tx_m2 */ 655 <1 RK_PB4 2 &pcfg_pull_up>; 656 }; 657 }; 658 659 uart1 { 660 /omit-if-no-ref/ 661 uart1m0_xfer: uart1m0-xfer { 662 rockchip,pins = 663 /* uart1_rx_m0 */ 664 <0 RK_PB2 2 &pcfg_pull_up>, 665 /* uart1_tx_m0 */ 666 <0 RK_PB3 2 &pcfg_pull_up>; 667 }; 668 669 /omit-if-no-ref/ 670 uart1m0_ctsn: uart1m0-ctsn { 671 rockchip,pins = 672 /* uart1m0_ctsn */ 673 <0 RK_PB5 5 &pcfg_pull_none>; 674 }; 675 /omit-if-no-ref/ 676 uart1m0_rtsn: uart1m0-rtsn { 677 rockchip,pins = 678 /* uart1m0_rtsn */ 679 <0 RK_PB4 5 &pcfg_pull_none>; 680 }; 681 682 /omit-if-no-ref/ 683 uart1m1_xfer: uart1m1-xfer { 684 rockchip,pins = 685 /* uart1_rx_m1 */ 686 <1 RK_PA7 2 &pcfg_pull_up>, 687 /* uart1_tx_m1 */ 688 <1 RK_PB0 2 &pcfg_pull_up>; 689 }; 690 691 /omit-if-no-ref/ 692 uart1m1_ctsn: uart1m1-ctsn { 693 rockchip,pins = 694 /* uart1m1_ctsn */ 695 <1 RK_PB2 2 &pcfg_pull_none>; 696 }; 697 /omit-if-no-ref/ 698 uart1m1_rtsn: uart1m1-rtsn { 699 rockchip,pins = 700 /* uart1m1_rtsn */ 701 <1 RK_PB1 2 &pcfg_pull_none>; 702 }; 703 704 /omit-if-no-ref/ 705 uart1m2_xfer: uart1m2-xfer { 706 rockchip,pins = 707 /* uart1_rx_m2 */ 708 <2 RK_PA7 1 &pcfg_pull_up>, 709 /* uart1_tx_m2 */ 710 <2 RK_PA6 1 &pcfg_pull_up>; 711 }; 712 713 /omit-if-no-ref/ 714 uart1m2_ctsn: uart1m2-ctsn { 715 rockchip,pins = 716 /* uart1m2_ctsn */ 717 <2 RK_PA5 2 &pcfg_pull_none>; 718 }; 719 /omit-if-no-ref/ 720 uart1m2_rtsn: uart1m2-rtsn { 721 rockchip,pins = 722 /* uart1m2_rtsn */ 723 <2 RK_PA4 2 &pcfg_pull_none>; 724 }; 725 726 /omit-if-no-ref/ 727 uart1m3_xfer: uart1m3-xfer { 728 rockchip,pins = 729 /* uart1_rx_m3 */ 730 <2 RK_PA3 2 &pcfg_pull_up>, 731 /* uart1_tx_m3 */ 732 <2 RK_PA2 2 &pcfg_pull_up>; 733 }; 734 735 /omit-if-no-ref/ 736 uart1m3_ctsn: uart1m3-ctsn { 737 rockchip,pins = 738 /* uart1m3_ctsn */ 739 <2 RK_PA1 2 &pcfg_pull_none>; 740 }; 741 /omit-if-no-ref/ 742 uart1m3_rtsn: uart1m3-rtsn { 743 rockchip,pins = 744 /* uart1m3_rtsn */ 745 <2 RK_PA0 2 &pcfg_pull_none>; 746 }; 747 }; 748 749 uart2 { 750 /omit-if-no-ref/ 751 uart2m0_xfer: uart2m0-xfer { 752 rockchip,pins = 753 /* uart2_rx_m0 */ 754 <0 RK_PB1 2 &pcfg_pull_up>, 755 /* uart2_tx_m0 */ 756 <0 RK_PB0 2 &pcfg_pull_up>; 757 }; 758 759 /omit-if-no-ref/ 760 uart2m0_ctsn: uart2m0-ctsn { 761 rockchip,pins = 762 /* uart2m0_ctsn */ 763 <0 RK_PB3 5 &pcfg_pull_none>; 764 }; 765 /omit-if-no-ref/ 766 uart2m0_rtsn: uart2m0-rtsn { 767 rockchip,pins = 768 /* uart2m0_rtsn */ 769 <0 RK_PB2 5 &pcfg_pull_none>; 770 }; 771 772 /omit-if-no-ref/ 773 uart2m1_xfer: uart2m1-xfer { 774 rockchip,pins = 775 /* uart2_rx_m1 */ 776 <2 RK_PB1 1 &pcfg_pull_up>, 777 /* uart2_tx_m1 */ 778 <2 RK_PB0 1 &pcfg_pull_up>; 779 }; 780 781 /omit-if-no-ref/ 782 uart2m1_ctsn: uart2m1-ctsn { 783 rockchip,pins = 784 /* uart2m1_ctsn */ 785 <2 RK_PB3 1 &pcfg_pull_none>; 786 }; 787 /omit-if-no-ref/ 788 uart2m1_rtsn: uart2m1-rtsn { 789 rockchip,pins = 790 /* uart2m1_rtsn */ 791 <2 RK_PB2 1 &pcfg_pull_none>; 792 }; 793 794 /omit-if-no-ref/ 795 uart2m2_xfer: uart2m2-xfer { 796 rockchip,pins = 797 /* uart2_rx_m2 */ 798 <1 RK_PB6 3 &pcfg_pull_up>, 799 /* uart2_tx_m2 */ 800 <1 RK_PB5 3 &pcfg_pull_up>; 801 }; 802 803 /omit-if-no-ref/ 804 uart2m2_ctsn: uart2m2-ctsn { 805 rockchip,pins = 806 /* uart2m2_ctsn */ 807 <1 RK_PC0 3 &pcfg_pull_none>; 808 }; 809 /omit-if-no-ref/ 810 uart2m2_rtsn: uart2m2-rtsn { 811 rockchip,pins = 812 /* uart2m2_rtsn */ 813 <1 RK_PB7 3 &pcfg_pull_none>; 814 }; 815 }; 816}; 817