1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Ethernet ENET2 support for Variscite VAR-SOM-6UL module. 4 * 5 * Copyright 2019-2024 Variscite Ltd. 6 * Copyright 2026 Dimonoff 7 */ 8 9/ { 10 rmii_ref_clk: rmii-ref-clk { 11 compatible = "fixed-clock"; 12 #clock-cells = <0>; 13 clock-frequency = <25000000>; 14 clock-output-names = "rmii-ref"; 15 }; 16}; 17 18&fec2 { 19 pinctrl-names = "default"; 20 pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; 21 phy-mode = "rmii"; 22 phy-handle = <ðphy1>; 23 status = "okay"; 24 25 mdio_enet2: mdio { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 ethphy0: ethernet-phy@1 { 30 compatible = "ethernet-phy-ieee802.3-c22"; 31 reg = <1>; 32 clocks = <&rmii_ref_clk>; 33 clock-names = "rmii-ref"; 34 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 35 reset-assert-us = <100000>; 36 micrel,led-mode = <1>; 37 micrel,rmii-reference-clock-select-25-mhz; 38 }; 39 40 ethphy1: ethernet-phy@3 { 41 compatible = "ethernet-phy-ieee802.3-c22"; 42 reg = <3>; 43 clocks = <&rmii_ref_clk>; 44 clock-names = "rmii-ref"; 45 reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; 46 reset-assert-us = <100000>; 47 micrel,led-mode = <0>; 48 micrel,rmii-reference-clock-select-25-mhz; 49 }; 50 }; 51}; 52 53&iomuxc { 54 pinctrl_enet2: enet2grp { 55 fsl,pins = < 56 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 57 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 58 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 59 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 60 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 61 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 62 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 63 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 64 >; 65 }; 66 67 pinctrl_enet2_gpio: enet2-gpiogrp { 68 fsl,pins = < 69 MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ 70 >; 71 }; 72 73 pinctrl_enet2_mdio: enet2-mdiogrp { 74 fsl,pins = < 75 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 76 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 77 >; 78 }; 79}; 80