1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Support for the common parts shared by all the different CPU options on 4 * Variscite VAR-SOM-6UL Module 5 * 6 * Copyright 2019 Variscite Ltd. 7 * Copyright 2025 Bootlin 8 */ 9 10#include <dt-bindings/clock/imx6ul-clock.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Variscite VAR-SOM-6UL module"; 15 compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x20000000>; 20 }; 21 22 reg_3p3v: regulator-3p3v { 23 compatible = "regulator-fixed"; 24 regulator-name = "3P3V"; 25 regulator-min-microvolt = <3300000>; 26 regulator-max-microvolt = <3300000>; 27 regulator-always-on; 28 }; 29 30 reg_gpio_dvfs: reg-gpio-dvfs { 31 compatible = "regulator-gpio"; 32 regulator-min-microvolt = <1300000>; 33 regulator-max-microvolt = <1400000>; 34 regulator-name = "gpio_dvfs"; 35 regulator-type = "voltage"; 36 gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; 37 states = <1300000 0x1 38 1400000 0x0>; 39 }; 40}; 41 42&clks { 43 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; 44 assigned-clock-rates = <786432000>; 45}; 46 47&iomuxc { 48 pinctrl_i2c1: i2c1grp { 49 fsl,pins = < 50 MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 51 MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 52 >; 53 }; 54 55 pinctrl_tsc: tscgrp { 56 fsl,pins = < 57 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 58 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 59 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 60 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 61 >; 62 }; 63 64 pinctrl_uart2: uart2grp { 65 fsl,pins = < 66 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 67 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 68 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 69 MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 70 >; 71 }; 72 73 pinctrl_usdhc1: usdhc1grp { 74 fsl,pins = < 75 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 76 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 77 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 78 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 79 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 80 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 81 >; 82 }; 83 84 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 85 fsl,pins = < 86 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 87 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 88 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 89 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 90 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 91 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 92 >; 93 }; 94 95 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 96 fsl,pins = < 97 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 98 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 99 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 100 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 101 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 102 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 103 >; 104 }; 105 106 pinctrl_usdhc2: usdhc2grp { 107 fsl,pins = < 108 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 109 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 110 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 111 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 112 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 113 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 114 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 115 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 116 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 117 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 118 >; 119 }; 120 121 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 122 fsl,pins = < 123 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 124 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 125 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 126 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 127 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 128 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 129 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 130 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 131 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 132 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 133 >; 134 }; 135 136 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 137 fsl,pins = < 138 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 139 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 140 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 141 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 142 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 143 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 144 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 145 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 146 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 147 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 148 >; 149 }; 150}; 151 152&pxp { 153 status = "okay"; 154}; 155 156&snvs_poweroff { 157 status = "okay"; 158}; 159 160&tsc { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&pinctrl_tsc>; 163 xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; 164 measure-delay-time = <0xffff>; 165 pre-charge-time = <0xfff>; 166 status = "okay"; 167}; 168 169&uart2 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_uart2>; 172 uart-has-rtscts; 173 status = "okay"; 174}; 175 176&usdhc2 { 177 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 178 pinctrl-0 = <&pinctrl_usdhc2>; 179 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 180 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 181 bus-width = <8>; 182 no-1-8-v; 183 non-removable; 184 keep-power-in-suspend; 185 wakeup-source; 186 status = "okay"; 187}; 188