xref: /linux/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi (revision 621cde16e49b3ecf7d59a8106a20aaebfb4a59a9)
1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright 2013 Boundary Devices, Inc.
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Copyright 2011 Linaro Ltd.
6 */
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9
10/ {
11	chosen {
12		stdout-path = &uart2;
13	};
14
15	memory@10000000 {
16		device_type = "memory";
17		reg = <0x10000000 0x40000000>;
18	};
19
20	reg_2p5v: regulator-2p5v {
21		compatible = "regulator-fixed";
22		regulator-name = "2P5V";
23		regulator-min-microvolt = <2500000>;
24		regulator-max-microvolt = <2500000>;
25		regulator-always-on;
26	};
27
28	reg_3p3v: regulator-3p3v {
29		compatible = "regulator-fixed";
30		regulator-name = "3P3V";
31		regulator-min-microvolt = <3300000>;
32		regulator-max-microvolt = <3300000>;
33		regulator-always-on;
34	};
35
36	reg_usb_otg_vbus: regulator-usb-otg-vbus {
37		compatible = "regulator-fixed";
38		regulator-name = "usb_otg_vbus";
39		regulator-min-microvolt = <5000000>;
40		regulator-max-microvolt = <5000000>;
41		gpio = <&gpio3 22 0>;
42		enable-active-high;
43	};
44
45	reg_can_xcvr: regulator-can-xcvr {
46		compatible = "regulator-fixed";
47		regulator-name = "CAN XCVR";
48		regulator-min-microvolt = <3300000>;
49		regulator-max-microvolt = <3300000>;
50		pinctrl-names = "default";
51		pinctrl-0 = <&pinctrl_can_xcvr>;
52		gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
53	};
54
55	reg_wlan_vmmc: regulator-wlan-vmmc {
56		compatible = "regulator-fixed";
57		pinctrl-names = "default";
58		pinctrl-0 = <&pinctrl_wlan_vmmc>;
59		regulator-name = "reg_wlan_vmmc";
60		regulator-min-microvolt = <3300000>;
61		regulator-max-microvolt = <3300000>;
62		gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>;
63		startup-delay-us = <70000>;
64		enable-active-high;
65	};
66
67	reg_usb_h1_vbus: regulator-usb-h1-vbus {
68		compatible = "regulator-fixed";
69		pinctrl-names = "default";
70		pinctrl-0 = <&pinctrl_usbh1>;
71		regulator-name = "usb_h1_vbus";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74		gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
75		enable-active-high;
76	};
77
78	gpio-keys {
79		compatible = "gpio-keys";
80		pinctrl-names = "default";
81		pinctrl-0 = <&pinctrl_gpio_keys>;
82
83		power {
84			label = "Power Button";
85			gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
86			linux,code = <KEY_POWER>;
87			wakeup-source;
88		};
89
90		menu {
91			label = "Menu";
92			gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
93			linux,code = <KEY_MENU>;
94		};
95
96		home {
97			label = "Home";
98			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
99			linux,code = <KEY_HOME>;
100		};
101
102		back {
103			label = "Back";
104			gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
105			linux,code = <KEY_BACK>;
106		};
107
108		volume-up {
109			label = "Volume Up";
110			gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
111			linux,code = <KEY_VOLUMEUP>;
112		};
113
114		volume-down {
115			label = "Volume Down";
116			gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
117			linux,code = <KEY_VOLUMEDOWN>;
118		};
119	};
120
121	sound {
122		compatible = "fsl,imx6q-nitrogen6x-sgtl5000",
123			     "fsl,imx-audio-sgtl5000";
124		model = "imx6q-nitrogen6x-sgtl5000";
125		ssi-controller = <&ssi1>;
126		audio-codec = <&codec>;
127		audio-routing =
128			"MIC_IN", "Mic Jack",
129			"Mic Jack", "Mic Bias",
130			"Headphone Jack", "HP_OUT";
131		mux-int-port = <1>;
132		mux-ext-port = <3>;
133	};
134
135	backlight_lcd: backlight-lcd {
136		compatible = "pwm-backlight";
137		pwms = <&pwm1 0 5000000 0>;
138		brightness-levels = <0 4 8 16 32 64 128 255>;
139		default-brightness-level = <7>;
140		power-supply = <&reg_3p3v>;
141		status = "okay";
142	};
143
144	backlight_lvds: backlight-lvds {
145		compatible = "pwm-backlight";
146		pwms = <&pwm4 0 5000000 0>;
147		brightness-levels = <0 4 8 16 32 64 128 255>;
148		default-brightness-level = <7>;
149		power-supply = <&reg_3p3v>;
150		status = "okay";
151	};
152
153	lcd_display: disp0 {
154		compatible = "fsl,imx-parallel-display";
155		#address-cells = <1>;
156		#size-cells = <0>;
157		interface-pix-fmt = "bgr666";
158		pinctrl-names = "default";
159		pinctrl-0 = <&pinctrl_j15>;
160		status = "okay";
161
162		port@0 {
163			reg = <0>;
164
165			lcd_display_in: endpoint {
166				remote-endpoint = <&ipu1_di0_disp0>;
167			};
168		};
169
170		port@1 {
171			reg = <1>;
172
173			lcd_display_out: endpoint {
174				remote-endpoint = <&lcd_panel_in>;
175			};
176		};
177	};
178
179	panel-lcd {
180		compatible = "okaya,rs800480t-7x0gp";
181		backlight = <&backlight_lcd>;
182
183		port {
184			lcd_panel_in: endpoint {
185				remote-endpoint = <&lcd_display_out>;
186			};
187		};
188	};
189
190	panel-lvds0 {
191		compatible = "hannstar,hsd100pxn1";
192		backlight = <&backlight_lvds>;
193
194		port {
195			panel_in: endpoint {
196				remote-endpoint = <&lvds0_out>;
197			};
198		};
199	};
200};
201
202&audmux {
203	pinctrl-names = "default";
204	pinctrl-0 = <&pinctrl_audmux>;
205	status = "okay";
206};
207
208&can1 {
209	pinctrl-names = "default";
210	pinctrl-0 = <&pinctrl_can1>;
211	xceiver-supply = <&reg_can_xcvr>;
212	status = "okay";
213};
214
215&clks {
216	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
217			  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
218	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
219				 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
220};
221
222&ecspi1 {
223	cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
224	pinctrl-names = "default";
225	pinctrl-0 = <&pinctrl_ecspi1>;
226	status = "okay";
227
228	flash: flash@0 {
229		compatible = "sst,sst25vf016b", "jedec,spi-nor";
230		spi-max-frequency = <20000000>;
231		reg = <0>;
232		#address-cells = <1>;
233		#size-cells = <1>;
234
235		partition@0 {
236			label = "bootloader";
237			reg = <0x0 0xc0000>;
238		};
239
240		partition@c0000 {
241			label = "env";
242			reg = <0xc0000 0x2000>;
243		};
244
245		partition@c2000 {
246			label = "splash";
247			reg = <0xc2000 0x13e000>;
248		};
249	};
250};
251
252&fec {
253	pinctrl-names = "default";
254	pinctrl-0 = <&pinctrl_enet>;
255	phy-mode = "rgmii";
256	phy-handle = <&ethphy>;
257	phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
258	/delete-property/ interrupts;
259	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
260			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
261	fsl,err006687-workaround-present;
262	status = "okay";
263
264	mdio {
265		#address-cells = <1>;
266		#size-cells = <0>;
267
268		ethphy: ethernet-phy {
269			compatible = "ethernet-phy-ieee802.3-c22";
270			txen-skew-ps = <0>;
271			txc-skew-ps = <3000>;
272			rxdv-skew-ps = <0>;
273			rxc-skew-ps = <3000>;
274			rxd0-skew-ps = <0>;
275			rxd1-skew-ps = <0>;
276			rxd2-skew-ps = <0>;
277			rxd3-skew-ps = <0>;
278			txd0-skew-ps = <0>;
279			txd1-skew-ps = <0>;
280			txd2-skew-ps = <0>;
281			txd3-skew-ps = <0>;
282		};
283	};
284};
285
286&hdmi {
287	ddc-i2c-bus = <&i2c2>;
288	status = "okay";
289};
290
291&i2c1 {
292	clock-frequency = <100000>;
293	pinctrl-names = "default";
294	pinctrl-0 = <&pinctrl_i2c1>;
295	status = "okay";
296
297	codec: sgtl5000@a {
298		compatible = "fsl,sgtl5000";
299		reg = <0x0a>;
300		#sound-dai-cells = <0>;
301		clocks = <&clks IMX6QDL_CLK_CKO>;
302		VDDA-supply = <&reg_2p5v>;
303		VDDIO-supply = <&reg_3p3v>;
304	};
305
306	rtc: rtc@6f {
307		compatible = "isil,isl1208";
308		reg = <0x6f>;
309	};
310};
311
312&i2c2 {
313	clock-frequency = <100000>;
314	pinctrl-names = "default";
315	pinctrl-0 = <&pinctrl_i2c2>;
316	status = "okay";
317};
318
319&i2c3 {
320	clock-frequency = <100000>;
321	pinctrl-names = "default";
322	pinctrl-0 = <&pinctrl_i2c3>;
323	status = "okay";
324
325	touchscreen@4 {
326		compatible = "eeti,egalax_ts";
327		reg = <0x04>;
328		interrupt-parent = <&gpio1>;
329		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
330		wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
331	};
332
333	touchscreen@38 {
334		compatible = "edt,edt-ft5x06";
335		reg = <0x38>;
336		interrupt-parent = <&gpio1>;
337		interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
338		wakeup-source;
339	};
340};
341
342&iomuxc {
343	pinctrl-names = "default";
344	pinctrl-0 = <&pinctrl_hog>;
345
346	imx6q-nitrogen6x {
347		pinctrl_hog: hoggrp {
348			fsl,pins = <
349				/* SGTL5000 sys_mclk */
350				MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x030b0
351				MX6QDL_PAD_GPIO_9__GPIO1_IO09	0x1b0b0
352			>;
353		};
354
355		pinctrl_audmux: audmuxgrp {
356			fsl,pins = <
357				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
358				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
359				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
360				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
361			>;
362		};
363
364		pinctrl_can1: can1grp {
365			fsl,pins = <
366				MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
367				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
368			>;
369		};
370
371		pinctrl_can_xcvr: can-xcvrgrp {
372			fsl,pins = <
373				/* Flexcan XCVR enable */
374				MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0
375			>;
376		};
377
378		pinctrl_ecspi1: ecspi1grp {
379			fsl,pins = <
380				MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
381				MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
382				MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
383				MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x000b1	/* CS */
384			>;
385		};
386
387		pinctrl_enet: enetgrp {
388			fsl,pins = <
389				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
390				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
391				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
392				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
393				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
394				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
395				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
396				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
397				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
398				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
399				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
400				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
401				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
402				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
403				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
404				/* Phy reset */
405				MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x000b0
406				MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
407			>;
408		};
409
410		pinctrl_gpio_keys: gpio-keysgrp {
411			fsl,pins = <
412				/* Power Button */
413				MX6QDL_PAD_NANDF_D3__GPIO2_IO03		0x1b0b0
414				/* Menu Button */
415				MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1b0b0
416				/* Home Button */
417				MX6QDL_PAD_NANDF_D4__GPIO2_IO04		0x1b0b0
418				/* Back Button */
419				MX6QDL_PAD_NANDF_D2__GPIO2_IO02		0x1b0b0
420				/* Volume Up Button */
421				MX6QDL_PAD_GPIO_18__GPIO7_IO13		0x1b0b0
422				/* Volume Down Button */
423				MX6QDL_PAD_GPIO_19__GPIO4_IO05		0x1b0b0
424			>;
425		};
426
427		pinctrl_i2c1: i2c1grp {
428			fsl,pins = <
429				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
430				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
431			>;
432		};
433
434		pinctrl_i2c2: i2c2grp {
435			fsl,pins = <
436				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
437				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
438			>;
439		};
440
441		pinctrl_i2c3: i2c3grp {
442			fsl,pins = <
443				MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
444				MX6QDL_PAD_GPIO_16__I2C3_SDA		0x4001b8b1
445			>;
446		};
447
448		pinctrl_j15: j15grp {
449			fsl,pins = <
450				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
451				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
452				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
453				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
454				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
455				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
456				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
457				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
458				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
459				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
460				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
461				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
462				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
463				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
464				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
465				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
466				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
467				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
468				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
469				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
470				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
471				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
472				MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x10
473				MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x10
474				MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x10
475				MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x10
476				MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x10
477				MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x10
478			>;
479		};
480
481		pinctrl_pwm1: pwm1grp {
482			fsl,pins = <
483				MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
484			>;
485		};
486
487		pinctrl_pwm3: pwm3grp {
488			fsl,pins = <
489				MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
490			>;
491		};
492
493		pinctrl_pwm4: pwm4grp {
494			fsl,pins = <
495				MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
496			>;
497		};
498
499		pinctrl_uart1: uart1grp {
500			fsl,pins = <
501				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
502				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
503			>;
504		};
505
506		pinctrl_uart2: uart2grp {
507			fsl,pins = <
508				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
509				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
510			>;
511		};
512
513		pinctrl_usbh1: usbh1grp {
514			fsl,pins = <
515				MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x030b0
516			>;
517		};
518
519		pinctrl_usbotg: usbotggrp {
520			fsl,pins = <
521				MX6QDL_PAD_GPIO_1__USB_OTG_ID	0x17059
522				MX6QDL_PAD_KEY_COL4__USB_OTG_OC	0x1b0b0
523				/* power enable, high active */
524				MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x000b0
525			>;
526		};
527
528		pinctrl_usdhc2: usdhc2grp {
529			fsl,pins = <
530				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17071
531				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10071
532				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17071
533				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17071
534				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17071
535				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17071
536			>;
537		};
538
539		pinctrl_usdhc3: usdhc3grp {
540			fsl,pins = <
541				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
542				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
543				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
544				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
545				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
546				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
547				MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0	/* CD */
548			>;
549		};
550
551		pinctrl_usdhc4: usdhc4grp {
552			fsl,pins = <
553				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
554				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
555				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
556				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
557				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
558				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
559				MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0	/* CD */
560			>;
561		};
562
563		pinctrl_wlan_vmmc: wlan-vmmcgrp {
564			fsl,pins = <
565				MX6QDL_PAD_NANDF_CS0__GPIO6_IO11	0x100b0
566				MX6QDL_PAD_NANDF_CS2__GPIO6_IO15	0x000b0
567				MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x000b0
568				MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT	0x000b0
569			>;
570		};
571	};
572};
573
574&ipu1_di0_disp0 {
575	remote-endpoint = <&lcd_display_in>;
576};
577
578&ldb {
579	status = "okay";
580
581	lvds-channel@0 {
582		status = "okay";
583
584		port@4 {
585			reg = <4>;
586
587			lvds0_out: endpoint {
588				remote-endpoint = <&panel_in>;
589			};
590		};
591	};
592};
593
594&pcie {
595	status = "okay";
596};
597
598&pwm1 {
599	pinctrl-names = "default";
600	pinctrl-0 = <&pinctrl_pwm1>;
601	status = "okay";
602};
603
604&pwm3 {
605	pinctrl-names = "default";
606	pinctrl-0 = <&pinctrl_pwm3>;
607	status = "okay";
608};
609
610&pwm4 {
611	pinctrl-names = "default";
612	pinctrl-0 = <&pinctrl_pwm4>;
613	status = "okay";
614};
615
616&ssi1 {
617	status = "okay";
618};
619
620&uart1 {
621	pinctrl-names = "default";
622	pinctrl-0 = <&pinctrl_uart1>;
623	status = "okay";
624};
625
626&uart2 {
627	pinctrl-names = "default";
628	pinctrl-0 = <&pinctrl_uart2>;
629	status = "okay";
630};
631
632&usbh1 {
633	vbus-supply = <&reg_usb_h1_vbus>;
634	status = "okay";
635};
636
637&usbotg {
638	vbus-supply = <&reg_usb_otg_vbus>;
639	pinctrl-names = "default";
640	pinctrl-0 = <&pinctrl_usbotg>;
641	disable-over-current;
642	status = "okay";
643};
644
645&usdhc2 {
646	pinctrl-names = "default";
647	pinctrl-0 = <&pinctrl_usdhc2>;
648	bus-width = <4>;
649	non-removable;
650	vmmc-supply = <&reg_wlan_vmmc>;
651	cap-power-off-card;
652	keep-power-in-suspend;
653	status = "okay";
654
655	#address-cells = <1>;
656	#size-cells = <0>;
657	wlcore: wlcore@2 {
658		compatible = "ti,wl1271";
659		reg = <2>;
660		interrupt-parent = <&gpio6>;
661		interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
662		ref-clock-frequency = <38400000>;
663	};
664};
665
666&usdhc3 {
667	pinctrl-names = "default";
668	pinctrl-0 = <&pinctrl_usdhc3>;
669	cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
670	vmmc-supply = <&reg_3p3v>;
671	status = "okay";
672};
673
674&usdhc4 {
675	pinctrl-names = "default";
676	pinctrl-0 = <&pinctrl_usdhc4>;
677	cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
678	vmmc-supply = <&reg_3p3v>;
679	status = "okay";
680};
681