1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2014 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 nand = &gpmi; 17 usb0 = &usbh1; 18 usb1 = &usbotg; 19 }; 20 21 chosen { 22 bootargs = "console=ttymxc1,115200"; 23 }; 24 25 gpio-keys { 26 compatible = "gpio-keys"; 27 28 key-user-pb { 29 label = "user_pb"; 30 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 31 linux,code = <BTN_0>; 32 }; 33 34 key-user-pb1x { 35 label = "user_pb1x"; 36 linux,code = <BTN_1>; 37 interrupt-parent = <&gsc>; 38 interrupts = <0>; 39 }; 40 41 key-erased { 42 label = "key-erased"; 43 linux,code = <BTN_2>; 44 interrupt-parent = <&gsc>; 45 interrupts = <1>; 46 }; 47 48 key-eeprom-wp { 49 label = "eeprom_wp"; 50 linux,code = <BTN_3>; 51 interrupt-parent = <&gsc>; 52 interrupts = <2>; 53 }; 54 55 key-tamper { 56 label = "tamper"; 57 linux,code = <BTN_4>; 58 interrupt-parent = <&gsc>; 59 interrupts = <5>; 60 }; 61 62 key-switch-hold { 63 label = "switch_hold"; 64 linux,code = <BTN_5>; 65 interrupt-parent = <&gsc>; 66 interrupts = <7>; 67 }; 68 }; 69 70 leds { 71 compatible = "gpio-leds"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_gpio_leds>; 74 75 led0: led-user1 { 76 label = "user1"; 77 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 78 default-state = "on"; 79 linux,default-trigger = "heartbeat"; 80 }; 81 82 led1: led-user2 { 83 label = "user2"; 84 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 85 default-state = "off"; 86 }; 87 88 led2: led-user3 { 89 label = "user3"; 90 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 91 default-state = "off"; 92 }; 93 }; 94 95 memory@10000000 { 96 device_type = "memory"; 97 reg = <0x10000000 0x20000000>; 98 }; 99 100 reg_1p0v: regulator-1p0v { 101 compatible = "regulator-fixed"; 102 regulator-name = "1P0V"; 103 regulator-min-microvolt = <1000000>; 104 regulator-max-microvolt = <1000000>; 105 regulator-always-on; 106 }; 107 108 reg_3p3v: regulator-3p3v { 109 compatible = "regulator-fixed"; 110 regulator-name = "3P3V"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 regulator-always-on; 114 }; 115 116 reg_5p0v: regulator-5p0v { 117 compatible = "regulator-fixed"; 118 regulator-name = "5P0V"; 119 regulator-min-microvolt = <5000000>; 120 regulator-max-microvolt = <5000000>; 121 regulator-always-on; 122 }; 123}; 124 125&gpmi { 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_gpmi_nand>; 128 status = "okay"; 129}; 130 131&hdmi { 132 ddc-i2c-bus = <&i2c3>; 133 status = "okay"; 134}; 135 136&i2c1 { 137 clock-frequency = <100000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_i2c1>; 140 status = "okay"; 141 142 gsc: gsc@20 { 143 compatible = "gw,gsc"; 144 reg = <0x20>; 145 interrupt-parent = <&gpio1>; 146 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 147 interrupt-controller; 148 #interrupt-cells = <1>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 152 adc { 153 compatible = "gw,gsc-adc"; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 channel@0 { 158 gw,mode = <0>; 159 reg = <0x00>; 160 label = "temp"; 161 }; 162 163 channel@2 { 164 gw,mode = <1>; 165 reg = <0x02>; 166 label = "vdd_vin"; 167 }; 168 169 channel@5 { 170 gw,mode = <1>; 171 reg = <0x05>; 172 label = "vdd_3p3"; 173 }; 174 175 channel@8 { 176 gw,mode = <1>; 177 reg = <0x08>; 178 label = "vdd_bat"; 179 }; 180 181 channel@b { 182 gw,mode = <1>; 183 reg = <0x0b>; 184 label = "vdd_5p0"; 185 }; 186 187 channel@e { 188 gw,mode = <1>; 189 reg = <0xe>; 190 label = "vdd_arm"; 191 }; 192 193 channel@11 { 194 gw,mode = <1>; 195 reg = <0x11>; 196 label = "vdd_soc"; 197 }; 198 199 channel@14 { 200 gw,mode = <1>; 201 reg = <0x14>; 202 label = "vdd_3p0"; 203 }; 204 205 channel@17 { 206 gw,mode = <1>; 207 reg = <0x17>; 208 label = "vdd_1p5"; 209 }; 210 211 channel@1d { 212 gw,mode = <1>; 213 reg = <0x1d>; 214 label = "vdd_1p8"; 215 }; 216 217 channel@20 { 218 gw,mode = <1>; 219 reg = <0x20>; 220 label = "vdd_1p0"; 221 }; 222 223 channel@23 { 224 gw,mode = <1>; 225 reg = <0x23>; 226 label = "vdd_2p5"; 227 }; 228 }; 229 }; 230 231 gsc_gpio: gpio@23 { 232 compatible = "nxp,pca9555"; 233 reg = <0x23>; 234 gpio-controller; 235 #gpio-cells = <2>; 236 interrupt-parent = <&gsc>; 237 interrupts = <4>; 238 }; 239 240 eeprom1: eeprom@50 { 241 compatible = "atmel,24c02"; 242 reg = <0x50>; 243 pagesize = <16>; 244 }; 245 246 eeprom2: eeprom@51 { 247 compatible = "atmel,24c02"; 248 reg = <0x51>; 249 pagesize = <16>; 250 }; 251 252 eeprom3: eeprom@52 { 253 compatible = "atmel,24c02"; 254 reg = <0x52>; 255 pagesize = <16>; 256 }; 257 258 eeprom4: eeprom@53 { 259 compatible = "atmel,24c02"; 260 reg = <0x53>; 261 pagesize = <16>; 262 }; 263 264 rtc: rtc@68 { 265 compatible = "dallas,ds1672"; 266 reg = <0x68>; 267 }; 268}; 269 270&i2c2 { 271 clock-frequency = <100000>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_i2c2>; 274 status = "okay"; 275 276 ltc3676: pmic@3c { 277 compatible = "lltc,ltc3676"; 278 reg = <0x3c>; 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_pmic>; 281 interrupt-parent = <&gpio1>; 282 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 283 284 regulators { 285 /* VDD_SOC (1+R1/R2 = 1.635) */ 286 reg_vdd_soc: sw1 { 287 regulator-name = "vddsoc"; 288 regulator-min-microvolt = <674400>; 289 regulator-max-microvolt = <1308000>; 290 lltc,fb-voltage-divider = <127000 200000>; 291 regulator-ramp-delay = <7000>; 292 regulator-boot-on; 293 regulator-always-on; 294 }; 295 296 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */ 297 reg_1p8v: sw2 { 298 regulator-name = "vdd1p8"; 299 regulator-min-microvolt = <1033310>; 300 regulator-max-microvolt = <2004000>; 301 lltc,fb-voltage-divider = <301000 200000>; 302 regulator-ramp-delay = <7000>; 303 regulator-boot-on; 304 regulator-always-on; 305 }; 306 307 /* VDD_ARM (1+R1/R2 = 1.635) */ 308 reg_vdd_arm: sw3 { 309 regulator-name = "vddarm"; 310 regulator-min-microvolt = <674400>; 311 regulator-max-microvolt = <1308000>; 312 lltc,fb-voltage-divider = <127000 200000>; 313 regulator-ramp-delay = <7000>; 314 regulator-boot-on; 315 regulator-always-on; 316 }; 317 318 /* VDD_DDR (1+R1/R2 = 2.105) */ 319 reg_vdd_ddr: sw4 { 320 regulator-name = "vddddr"; 321 regulator-min-microvolt = <868310>; 322 regulator-max-microvolt = <1684000>; 323 lltc,fb-voltage-divider = <221000 200000>; 324 regulator-ramp-delay = <7000>; 325 regulator-boot-on; 326 regulator-always-on; 327 }; 328 329 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 330 reg_2p5v: ldo2 { 331 regulator-name = "vdd2p5"; 332 regulator-min-microvolt = <2490375>; 333 regulator-max-microvolt = <2490375>; 334 lltc,fb-voltage-divider = <487000 200000>; 335 regulator-boot-on; 336 regulator-always-on; 337 }; 338 339 /* VDD_HIGH (1+R1/R2 = 4.17) */ 340 reg_3p0v: ldo4 { 341 regulator-name = "vdd3p0"; 342 regulator-min-microvolt = <3023250>; 343 regulator-max-microvolt = <3023250>; 344 lltc,fb-voltage-divider = <634000 200000>; 345 regulator-boot-on; 346 regulator-always-on; 347 }; 348 }; 349 }; 350}; 351 352&i2c3 { 353 clock-frequency = <100000>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_i2c3>; 356 status = "okay"; 357}; 358 359&pcie { 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_pcie>; 362 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 363 status = "okay"; 364}; 365 366&pwm2 { 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 369 status = "disabled"; 370}; 371 372&pwm3 { 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 375 status = "disabled"; 376}; 377 378&uart2 { 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_uart2>; 381 status = "okay"; 382}; 383 384&uart3 { 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_uart3>; 387 status = "okay"; 388}; 389 390&uart5 { 391 pinctrl-names = "default"; 392 pinctrl-0 = <&pinctrl_uart5>; 393 status = "okay"; }; 394 395&usbh1 { 396 status = "okay"; 397}; 398 399&usbotg { 400 vbus-supply = <®_5p0v>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_usbotg>; 403 disable-over-current; 404 status = "okay"; 405}; 406 407&wdog1 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&pinctrl_wdog>; 410 fsl,ext-reset-output; 411}; 412 413&iomuxc { 414 pinctrl_gpio_leds: gpioledsgrp { 415 fsl,pins = < 416 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 417 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 418 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 419 >; 420 }; 421 422 pinctrl_gpmi_nand: gpminandgrp { 423 fsl,pins = < 424 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 425 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 426 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 427 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 428 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 429 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 430 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 431 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 432 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 433 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 434 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 435 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 436 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 437 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 438 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 439 >; 440 }; 441 442 pinctrl_i2c1: i2c1grp { 443 fsl,pins = < 444 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 445 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 446 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1 447 >; 448 }; 449 450 pinctrl_i2c2: i2c2grp { 451 fsl,pins = < 452 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 453 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 454 >; 455 }; 456 457 pinctrl_i2c3: i2c3grp { 458 fsl,pins = < 459 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 460 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 461 >; 462 }; 463 464 pinctrl_pcie: pciegrp { 465 fsl,pins = < 466 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 467 >; 468 }; 469 470 pinctrl_pmic: pmicgrp { 471 fsl,pins = < 472 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 473 >; 474 }; 475 476 pinctrl_pwm2: pwm2grp { 477 fsl,pins = < 478 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 479 >; 480 }; 481 482 pinctrl_pwm3: pwm3grp { 483 fsl,pins = < 484 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 485 >; 486 }; 487 488 pinctrl_uart2: uart2grp { 489 fsl,pins = < 490 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 491 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 492 >; 493 }; 494 495 pinctrl_uart3: uart3grp { 496 fsl,pins = < 497 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 498 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 499 >; 500 }; 501 502 pinctrl_uart5: uart5grp { 503 fsl,pins = < 504 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 505 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 506 >; 507 }; 508 509 pinctrl_usbotg: usbotggrp { 510 fsl,pins = < 511 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059 512 >; 513 }; 514 515 pinctrl_wdog: wdoggrp { 516 fsl,pins = < 517 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 518 >; 519 }; 520}; 521