xref: /linux/arch/arm/boot/dts/nxp/imx/imx6qdl-gw552x.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2014 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9
10/ {
11	/* these are used by bootloader for disabling nodes */
12	aliases {
13		led0 = &led0;
14		led1 = &led1;
15		led2 = &led2;
16		nand = &gpmi;
17		usb0 = &usbh1;
18		usb1 = &usbotg;
19	};
20
21	chosen {
22		bootargs = "console=ttymxc1,115200";
23	};
24
25	gpio-keys {
26		compatible = "gpio-keys";
27
28		user-pb {
29			label = "user_pb";
30			gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
31			linux,code = <BTN_0>;
32		};
33
34		user-pb1x {
35			label = "user_pb1x";
36			linux,code = <BTN_1>;
37			interrupt-parent = <&gsc>;
38			interrupts = <0>;
39		};
40
41		key-erased {
42			label = "key-erased";
43			linux,code = <BTN_2>;
44			interrupt-parent = <&gsc>;
45			interrupts = <1>;
46		};
47
48		eeprom-wp {
49			label = "eeprom_wp";
50			linux,code = <BTN_3>;
51			interrupt-parent = <&gsc>;
52			interrupts = <2>;
53		};
54
55		tamper {
56			label = "tamper";
57			linux,code = <BTN_4>;
58			interrupt-parent = <&gsc>;
59			interrupts = <5>;
60		};
61
62		switch-hold {
63			label = "switch_hold";
64			linux,code = <BTN_5>;
65			interrupt-parent = <&gsc>;
66			interrupts = <7>;
67		};
68	};
69
70	leds {
71		compatible = "gpio-leds";
72		pinctrl-names = "default";
73		pinctrl-0 = <&pinctrl_gpio_leds>;
74
75		led0: led-user1 {
76			label = "user1";
77			gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
78			default-state = "on";
79			linux,default-trigger = "heartbeat";
80		};
81
82		led1: led-user2 {
83			label = "user2";
84			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
85			default-state = "off";
86		};
87
88		led2: led-user3 {
89			label = "user3";
90			gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
91			default-state = "off";
92		};
93	};
94
95	memory@10000000 {
96		device_type = "memory";
97		reg = <0x10000000 0x20000000>;
98	};
99
100	reg_1p0v: regulator-1p0v {
101		compatible = "regulator-fixed";
102		regulator-name = "1P0V";
103		regulator-min-microvolt = <1000000>;
104		regulator-max-microvolt = <1000000>;
105		regulator-always-on;
106	};
107
108	reg_3p3v: regulator-3p3v {
109		compatible = "regulator-fixed";
110		regulator-name = "3P3V";
111		regulator-min-microvolt = <3300000>;
112		regulator-max-microvolt = <3300000>;
113		regulator-always-on;
114	};
115
116	reg_5p0v: regulator-5p0v {
117		compatible = "regulator-fixed";
118		regulator-name = "5P0V";
119		regulator-min-microvolt = <5000000>;
120		regulator-max-microvolt = <5000000>;
121		regulator-always-on;
122	};
123};
124
125&gpmi {
126	pinctrl-names = "default";
127	pinctrl-0 = <&pinctrl_gpmi_nand>;
128	status = "okay";
129};
130
131&hdmi {
132	ddc-i2c-bus = <&i2c3>;
133	status = "okay";
134};
135
136&i2c1 {
137	clock-frequency = <100000>;
138	pinctrl-names = "default";
139	pinctrl-0 = <&pinctrl_i2c1>;
140	status = "okay";
141
142	gsc: gsc@20 {
143		compatible = "gw,gsc";
144		reg = <0x20>;
145		interrupt-parent = <&gpio1>;
146		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
147		interrupt-controller;
148		#interrupt-cells = <1>;
149		#size-cells = <0>;
150
151		adc {
152			compatible = "gw,gsc-adc";
153			#address-cells = <1>;
154			#size-cells = <0>;
155
156			channel@0 {
157				gw,mode = <0>;
158				reg = <0x00>;
159				label = "temp";
160			};
161
162			channel@2 {
163				gw,mode = <1>;
164				reg = <0x02>;
165				label = "vdd_vin";
166			};
167
168			channel@5 {
169				gw,mode = <1>;
170				reg = <0x05>;
171				label = "vdd_3p3";
172			};
173
174			channel@8 {
175				gw,mode = <1>;
176				reg = <0x08>;
177				label = "vdd_bat";
178			};
179
180			channel@b {
181				gw,mode = <1>;
182				reg = <0x0b>;
183				label = "vdd_5p0";
184			};
185
186			channel@e {
187				gw,mode = <1>;
188				reg = <0xe>;
189				label = "vdd_arm";
190			};
191
192			channel@11 {
193				gw,mode = <1>;
194				reg = <0x11>;
195				label = "vdd_soc";
196			};
197
198			channel@14 {
199				gw,mode = <1>;
200				reg = <0x14>;
201				label = "vdd_3p0";
202			};
203
204			channel@17 {
205				gw,mode = <1>;
206				reg = <0x17>;
207				label = "vdd_1p5";
208			};
209
210			channel@1d {
211				gw,mode = <1>;
212				reg = <0x1d>;
213				label = "vdd_1p8";
214			};
215
216			channel@20 {
217				gw,mode = <1>;
218				reg = <0x20>;
219				label = "vdd_1p0";
220			};
221
222			channel@23 {
223				gw,mode = <1>;
224				reg = <0x23>;
225				label = "vdd_2p5";
226			};
227		};
228	};
229
230	gsc_gpio: gpio@23 {
231		compatible = "nxp,pca9555";
232		reg = <0x23>;
233		gpio-controller;
234		#gpio-cells = <2>;
235		interrupt-parent = <&gsc>;
236		interrupts = <4>;
237	};
238
239	eeprom1: eeprom@50 {
240		compatible = "atmel,24c02";
241		reg = <0x50>;
242		pagesize = <16>;
243	};
244
245	eeprom2: eeprom@51 {
246		compatible = "atmel,24c02";
247		reg = <0x51>;
248		pagesize = <16>;
249	};
250
251	eeprom3: eeprom@52 {
252		compatible = "atmel,24c02";
253		reg = <0x52>;
254		pagesize = <16>;
255	};
256
257	eeprom4: eeprom@53 {
258		compatible = "atmel,24c02";
259		reg = <0x53>;
260		pagesize = <16>;
261	};
262
263	rtc: ds1672@68 {
264		compatible = "dallas,ds1672";
265		reg = <0x68>;
266	};
267};
268
269&i2c2 {
270	clock-frequency = <100000>;
271	pinctrl-names = "default";
272	pinctrl-0 = <&pinctrl_i2c2>;
273	status = "okay";
274
275	ltc3676: pmic@3c {
276		compatible = "lltc,ltc3676";
277		reg = <0x3c>;
278		pinctrl-names = "default";
279		pinctrl-0 = <&pinctrl_pmic>;
280		interrupt-parent = <&gpio1>;
281		interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
282
283		regulators {
284			/* VDD_SOC (1+R1/R2 = 1.635) */
285			reg_vdd_soc: sw1 {
286				regulator-name = "vddsoc";
287				regulator-min-microvolt = <674400>;
288				regulator-max-microvolt = <1308000>;
289				lltc,fb-voltage-divider = <127000 200000>;
290				regulator-ramp-delay = <7000>;
291				regulator-boot-on;
292				regulator-always-on;
293			};
294
295			/* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
296			reg_1p8v: sw2 {
297				regulator-name = "vdd1p8";
298				regulator-min-microvolt = <1033310>;
299				regulator-max-microvolt = <2004000>;
300				lltc,fb-voltage-divider = <301000 200000>;
301				regulator-ramp-delay = <7000>;
302				regulator-boot-on;
303				regulator-always-on;
304			};
305
306			/* VDD_ARM (1+R1/R2 = 1.635) */
307			reg_vdd_arm: sw3 {
308				regulator-name = "vddarm";
309				regulator-min-microvolt = <674400>;
310				regulator-max-microvolt = <1308000>;
311				lltc,fb-voltage-divider = <127000 200000>;
312				regulator-ramp-delay = <7000>;
313				regulator-boot-on;
314				regulator-always-on;
315			};
316
317			/* VDD_DDR (1+R1/R2 = 2.105) */
318			reg_vdd_ddr: sw4 {
319				regulator-name = "vddddr";
320				regulator-min-microvolt = <868310>;
321				regulator-max-microvolt = <1684000>;
322				lltc,fb-voltage-divider = <221000 200000>;
323				regulator-ramp-delay = <7000>;
324				regulator-boot-on;
325				regulator-always-on;
326			};
327
328			/* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
329			reg_2p5v: ldo2 {
330				regulator-name = "vdd2p5";
331				regulator-min-microvolt = <2490375>;
332				regulator-max-microvolt = <2490375>;
333				lltc,fb-voltage-divider = <487000 200000>;
334				regulator-boot-on;
335				regulator-always-on;
336			};
337
338			/* VDD_HIGH (1+R1/R2 = 4.17) */
339			reg_3p0v: ldo4 {
340				regulator-name = "vdd3p0";
341				regulator-min-microvolt = <3023250>;
342				regulator-max-microvolt = <3023250>;
343				lltc,fb-voltage-divider = <634000 200000>;
344				regulator-boot-on;
345				regulator-always-on;
346			};
347		};
348	};
349};
350
351&i2c3 {
352	clock-frequency = <100000>;
353	pinctrl-names = "default";
354	pinctrl-0 = <&pinctrl_i2c3>;
355	status = "okay";
356};
357
358&pcie {
359	pinctrl-names = "default";
360	pinctrl-0 = <&pinctrl_pcie>;
361	reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
362	status = "okay";
363};
364
365&pwm2 {
366	pinctrl-names = "default";
367	pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
368	status = "disabled";
369};
370
371&pwm3 {
372	pinctrl-names = "default";
373	pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
374	status = "disabled";
375};
376
377&uart2 {
378	pinctrl-names = "default";
379	pinctrl-0 = <&pinctrl_uart2>;
380	status = "okay";
381};
382
383&uart3 {
384	pinctrl-names = "default";
385	pinctrl-0 = <&pinctrl_uart3>;
386	status = "okay";
387};
388
389&uart5 {
390	pinctrl-names = "default";
391	pinctrl-0 = <&pinctrl_uart5>;
392	status = "okay"; };
393
394&usbh1 {
395	status = "okay";
396};
397
398&usbotg {
399	vbus-supply = <&reg_5p0v>;
400	pinctrl-names = "default";
401	pinctrl-0 = <&pinctrl_usbotg>;
402	disable-over-current;
403	status = "okay";
404};
405
406&wdog1 {
407	pinctrl-names = "default";
408	pinctrl-0 = <&pinctrl_wdog>;
409	fsl,ext-reset-output;
410};
411
412&iomuxc {
413	pinctrl_gpio_leds: gpioledsgrp {
414		fsl,pins = <
415			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
416			MX6QDL_PAD_KEY_ROW0__GPIO4_IO07		0x1b0b0
417			MX6QDL_PAD_KEY_ROW4__GPIO4_IO15		0x1b0b0
418		>;
419	};
420
421	pinctrl_gpmi_nand: gpminandgrp {
422		fsl,pins = <
423			MX6QDL_PAD_NANDF_CLE__NAND_CLE		0xb0b1
424			MX6QDL_PAD_NANDF_ALE__NAND_ALE		0xb0b1
425			MX6QDL_PAD_NANDF_WP_B__NAND_WP_B	0xb0b1
426			MX6QDL_PAD_NANDF_RB0__NAND_READY_B	0xb000
427			MX6QDL_PAD_NANDF_CS0__NAND_CE0_B	0xb0b1
428			MX6QDL_PAD_SD4_CMD__NAND_RE_B		0xb0b1
429			MX6QDL_PAD_SD4_CLK__NAND_WE_B		0xb0b1
430			MX6QDL_PAD_NANDF_D0__NAND_DATA00	0xb0b1
431			MX6QDL_PAD_NANDF_D1__NAND_DATA01	0xb0b1
432			MX6QDL_PAD_NANDF_D2__NAND_DATA02	0xb0b1
433			MX6QDL_PAD_NANDF_D3__NAND_DATA03	0xb0b1
434			MX6QDL_PAD_NANDF_D4__NAND_DATA04	0xb0b1
435			MX6QDL_PAD_NANDF_D5__NAND_DATA05	0xb0b1
436			MX6QDL_PAD_NANDF_D6__NAND_DATA06	0xb0b1
437			MX6QDL_PAD_NANDF_D7__NAND_DATA07	0xb0b1
438		>;
439	};
440
441	pinctrl_i2c1: i2c1grp {
442		fsl,pins = <
443			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
444			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
445			MX6QDL_PAD_GPIO_4__GPIO1_IO04		0xb0b1
446		>;
447	};
448
449	pinctrl_i2c2: i2c2grp {
450		fsl,pins = <
451			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
452			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
453		>;
454	};
455
456	pinctrl_i2c3: i2c3grp {
457		fsl,pins = <
458			MX6QDL_PAD_GPIO_3__I2C3_SCL		0x4001b8b1
459			MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
460		>;
461	};
462
463	pinctrl_pcie: pciegrp {
464		fsl,pins = <
465			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0
466		>;
467	};
468
469	pinctrl_pmic: pmicgrp {
470		fsl,pins = <
471			MX6QDL_PAD_GPIO_8__GPIO1_IO08		0x0001b0b0 /* PMIC_IRQ# */
472		>;
473	};
474
475	pinctrl_pwm2: pwm2grp {
476		fsl,pins = <
477			MX6QDL_PAD_SD1_DAT2__PWM2_OUT		0x1b0b1
478		>;
479	};
480
481	pinctrl_pwm3: pwm3grp {
482		fsl,pins = <
483			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
484		>;
485	};
486
487	pinctrl_uart2: uart2grp {
488		fsl,pins = <
489			MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA	0x1b0b1
490			MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA	0x1b0b1
491		>;
492	};
493
494	pinctrl_uart3: uart3grp {
495		fsl,pins = <
496			MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
497			MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
498		>;
499	};
500
501	pinctrl_uart5: uart5grp {
502		fsl,pins = <
503			MX6QDL_PAD_KEY_COL1__UART5_TX_DATA	0x1b0b1
504			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
505		>;
506	};
507
508	pinctrl_usbotg: usbotggrp {
509		fsl,pins = <
510			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x13059
511		>;
512	};
513
514	pinctrl_wdog: wdoggrp {
515		fsl,pins = <
516			MX6QDL_PAD_DISP0_DAT8__WDOG1_B		0x1b0b0
517		>;
518	};
519};
520