1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10 11/ { 12 model = "Toradex Apalis iMX6Q/D Module"; 13 compatible = "toradex,apalis_imx6q", "fsl,imx6q"; 14 15 aliases { 16 mmc0 = &usdhc3; /* eMMC */ 17 mmc1 = &usdhc1; /* MMC1 slot */ 18 mmc2 = &usdhc2; /* SD1 slot */ 19 /delete-property/ mmc3; 20 }; 21 22 /* Will be filled by the bootloader */ 23 memory@10000000 { 24 device_type = "memory"; 25 reg = <0x10000000 0>; 26 }; 27 28 backlight: backlight { 29 compatible = "pwm-backlight"; 30 brightness-levels = <0 45 63 88 119 158 203 255>; 31 default-brightness-level = <4>; 32 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_bl_on>; 35 power-supply = <®_module_3v3>; 36 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; 37 status = "disabled"; 38 }; 39 40 clk_ov5640_osc: clk-ov5640-osc { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <24000000>; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_gpio_keys>; 50 51 key-wakeup { 52 debounce-interval = <10>; 53 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 54 label = "Wake-Up"; 55 linux,code = <KEY_WAKEUP>; 56 wakeup-source; 57 }; 58 }; 59 60 lcd_display: disp0 { 61 compatible = "fsl,imx-parallel-display"; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 interface-pix-fmt = "rgb24"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 67 status = "disabled"; 68 69 port@0 { 70 reg = <0>; 71 72 lcd_display_in: endpoint { 73 remote-endpoint = <&ipu1_di1_disp1>; 74 }; 75 }; 76 77 port@1 { 78 reg = <1>; 79 80 lcd_display_out: endpoint { 81 remote-endpoint = <&lcd_panel_in>; 82 }; 83 }; 84 }; 85 86 panel_dpi: panel-dpi { 87 compatible = "edt,et057090dhu"; 88 backlight = <&backlight>; 89 90 status = "disabled"; 91 92 port { 93 lcd_panel_in: endpoint { 94 remote-endpoint = <&lcd_display_out>; 95 }; 96 }; 97 }; 98 99 panel_lvds: panel-lvds { 100 compatible = "panel-lvds"; 101 backlight = <&backlight>; 102 status = "disabled"; 103 104 port { 105 lvds_panel_in: endpoint { 106 remote-endpoint = <&lvds0_out>; 107 }; 108 }; 109 }; 110 111 reg_module_3v3: regulator-module-3v3 { 112 compatible = "regulator-fixed"; 113 regulator-always-on; 114 regulator-max-microvolt = <3300000>; 115 regulator-min-microvolt = <3300000>; 116 regulator-name = "+V3.3"; 117 }; 118 119 reg_module_3v3_audio: regulator-module-3v3-audio { 120 compatible = "regulator-fixed"; 121 regulator-always-on; 122 regulator-max-microvolt = <3300000>; 123 regulator-min-microvolt = <3300000>; 124 regulator-name = "+V3.3_AUDIO"; 125 }; 126 127 reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { 128 compatible = "regulator-fixed"; 129 regulator-always-on; 130 regulator-max-microvolt = <1800000>; 131 regulator-min-microvolt = <1800000>; 132 regulator-name = "DOVDD/DVDD_1.8V"; 133 /* Note: The CSI module uses on-board 3.3V_SW supply */ 134 vin-supply = <®_module_3v3>; 135 }; 136 137 reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { 138 compatible = "regulator-fixed"; 139 regulator-always-on; 140 regulator-max-microvolt = <2800000>; 141 regulator-min-microvolt = <2800000>; 142 regulator-name = "AVDD/AFVDD_2.8V"; 143 /* Note: The CSI module uses on-board 3.3V_SW supply */ 144 vin-supply = <®_module_3v3>; 145 }; 146 147 reg_usb_otg_vbus: regulator-usb-otg-vbus { 148 compatible = "regulator-fixed"; 149 enable-active-high; 150 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 153 regulator-max-microvolt = <5000000>; 154 regulator-min-microvolt = <5000000>; 155 regulator-name = "usb_otg_vbus"; 156 status = "disabled"; 157 }; 158 159 /* on module USB hub */ 160 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 161 compatible = "regulator-fixed"; 162 enable-active-high; 163 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 166 regulator-max-microvolt = <5000000>; 167 regulator-min-microvolt = <5000000>; 168 regulator-name = "usb_host_vbus_hub"; 169 startup-delay-us = <2000>; 170 status = "okay"; 171 }; 172 173 reg_usb_host_vbus: regulator-usb-host-vbus { 174 compatible = "regulator-fixed"; 175 enable-active-high; 176 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 179 regulator-max-microvolt = <5000000>; 180 regulator-min-microvolt = <5000000>; 181 regulator-name = "usb_host_vbus"; 182 vin-supply = <®_usb_host_vbus_hub>; 183 status = "disabled"; 184 }; 185 186 sound { 187 compatible = "fsl,imx-audio-sgtl5000"; 188 audio-codec = <&codec>; 189 audio-routing = 190 "LINE_IN", "Line In Jack", 191 "MIC_IN", "Mic Jack", 192 "Mic Jack", "Mic Bias", 193 "Headphone Jack", "HP_OUT"; 194 model = "imx6q-apalis-sgtl5000"; 195 mux-ext-port = <4>; 196 mux-int-port = <1>; 197 ssi-controller = <&ssi1>; 198 }; 199 200 sound_spdif: sound-spdif { 201 compatible = "fsl,imx-audio-spdif"; 202 spdif-controller = <&spdif>; 203 spdif-in; 204 spdif-out; 205 model = "imx-spdif"; 206 status = "disabled"; 207 }; 208}; 209 210&audmux { 211 pinctrl-names = "default"; 212 pinctrl-0 = <&pinctrl_audmux>; 213 status = "okay"; 214}; 215 216&can1 { 217 pinctrl-names = "default", "sleep"; 218 pinctrl-0 = <&pinctrl_flexcan1_default>; 219 pinctrl-1 = <&pinctrl_flexcan1_sleep>; 220 status = "disabled"; 221}; 222 223&can2 { 224 pinctrl-names = "default", "sleep"; 225 pinctrl-0 = <&pinctrl_flexcan2_default>; 226 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 227 status = "disabled"; 228}; 229 230&clks { 231 fsl,pmic-stby-poweroff; 232}; 233 234/* Apalis SPI1 */ 235&ecspi1 { 236 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_ecspi1>; 239 status = "disabled"; 240}; 241 242/* Apalis SPI2 */ 243&ecspi2 { 244 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_ecspi2>; 247 status = "disabled"; 248}; 249 250&gpio1 { 251 gpio-line-names = "MXM3_84", 252 "MXM3_4", 253 "MXM3_15/GPIO7", 254 "MXM3_96", 255 "MXM3_37", 256 "", 257 "MXM3_17/GPIO8", 258 "MXM3_14", 259 "MXM3_12", 260 "MXM3_2", 261 "MXM3_184", 262 "MXM3_180", 263 "MXM3_178", 264 "MXM3_176", 265 "MXM3_188", 266 "MXM3_186", 267 "MXM3_160", 268 "MXM3_162", 269 "MXM3_150", 270 "MXM3_144", 271 "MXM3_154", 272 "MXM3_146", 273 "", 274 "", 275 "MXM3_72"; 276}; 277 278&gpio2 { 279 gpio-line-names = "MXM3_148", 280 "MXM3_152", 281 "MXM3_156", 282 "MXM3_158", 283 "MXM3_1/GPIO1", 284 "MXM3_3/GPIO2", 285 "MXM3_5/GPIO3", 286 "MXM3_7/GPIO4", 287 "MXM3_95", 288 "MXM3_6", 289 "MXM3_8", 290 "MXM3_123", 291 "MXM3_126", 292 "MXM3_128", 293 "MXM3_130", 294 "MXM3_132", 295 "MXM3_253", 296 "MXM3_251", 297 "MXM3_283", 298 "MXM3_281", 299 "MXM3_279", 300 "MXM3_277", 301 "MXM3_243", 302 "MXM3_235", 303 "MXM3_231", 304 "MXM3_229", 305 "MXM3_233", 306 "MXM3_198", 307 "MXM3_275", 308 "MXM3_273", 309 "MXM3_207", 310 "MXM3_122"; 311}; 312 313&gpio3 { 314 gpio-line-names = "MXM3_271", 315 "MXM3_269", 316 "MXM3_301", 317 "MXM3_299", 318 "MXM3_297", 319 "MXM3_295", 320 "MXM3_293", 321 "MXM3_291", 322 "MXM3_289", 323 "MXM3_287", 324 "MXM3_249", 325 "MXM3_247", 326 "MXM3_245", 327 "MXM3_286", 328 "MXM3_239", 329 "MXM3_35", 330 "MXM3_205", 331 "MXM3_203", 332 "MXM3_201", 333 "MXM3_116", 334 "MXM3_114", 335 "MXM3_262", 336 "MXM3_274", 337 "MXM3_124", 338 "MXM3_110", 339 "MXM3_120", 340 "MXM3_263", 341 "MXM3_265", 342 "", 343 "MXM3_135", 344 "MXM3_261", 345 "MXM3_259"; 346}; 347 348&gpio4 { 349 gpio-line-names = "", 350 "", 351 "", 352 "", 353 "", 354 "MXM3_194", 355 "MXM3_136", 356 "MXM3_134", 357 "MXM3_140", 358 "MXM3_138", 359 "", 360 "MXM3_220", 361 "", 362 "", 363 "MXM3_18", 364 "MXM3_16", 365 "", 366 "", 367 "MXM3_214", 368 "MXM3_216", 369 "MXM3_164"; 370}; 371 372&gpio5 { 373 gpio-line-names = "MXM3_159", 374 "", 375 "", 376 "", 377 "MXM3_257", 378 "", 379 "", 380 "", 381 "", 382 "", 383 "MXM3_200", 384 "MXM3_196", 385 "MXM3_204", 386 "MXM3_202", 387 "", 388 "", 389 "", 390 "", 391 "MXM3_191", 392 "MXM3_197", 393 "MXM3_77", 394 "MXM3_195", 395 "MXM3_221", 396 "MXM3_225", 397 "MXM3_223", 398 "MXM3_227", 399 "MXM3_209", 400 "MXM3_211", 401 "MXM3_118", 402 "MXM3_112", 403 "MXM3_187", 404 "MXM3_185"; 405}; 406 407&gpio6 { 408 gpio-line-names = "MXM3_183", 409 "MXM3_181", 410 "MXM3_179", 411 "MXM3_177", 412 "MXM3_175", 413 "MXM3_173", 414 "MXM3_255", 415 "MXM3_83", 416 "MXM3_91", 417 "MXM3_13/GPIO6", 418 "MXM3_11/GPIO5", 419 "MXM3_79", 420 "", 421 "", 422 "MXM3_190", 423 "MXM3_193", 424 "MXM3_89"; 425}; 426 427&gpio7 { 428 gpio-line-names = "", 429 "", 430 "", 431 "", 432 "", 433 "", 434 "", 435 "", 436 "", 437 "MXM3_99", 438 "MXM3_85", 439 "MXM3_217", 440 "MXM3_215"; 441}; 442 443&gpr { 444 ipu1_csi0_mux { 445 #address-cells = <1>; 446 #size-cells = <0>; 447 status = "disabled"; 448 449 port@1 { 450 reg = <1>; 451 ipu1_csi0_mux_from_parallel_sensor: endpoint { 452 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; 453 }; 454 }; 455 }; 456}; 457 458&fec { 459 pinctrl-names = "default"; 460 pinctrl-0 = <&pinctrl_enet>; 461 phy-mode = "rgmii-id"; 462 phy-handle = <ðphy>; 463 phy-reset-duration = <10>; 464 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 465 status = "okay"; 466 467 mdio { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 471 ethphy: ethernet-phy@7 { 472 interrupt-parent = <&gpio1>; 473 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 474 reg = <7>; 475 }; 476 }; 477}; 478 479&hdmi { 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; 482 status = "disabled"; 483}; 484 485/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ 486&i2c1 { 487 clock-frequency = <100000>; 488 pinctrl-names = "default", "gpio"; 489 pinctrl-0 = <&pinctrl_i2c1>; 490 pinctrl-1 = <&pinctrl_i2c1_gpio>; 491 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 492 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 493 status = "disabled"; 494 495 atmel_mxt_ts: touchscreen@4a { 496 compatible = "atmel,maxtouch"; 497 /* These GPIOs are muxed with the iomuxc node */ 498 interrupt-parent = <&gpio6>; 499 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ 500 reg = <0x4a>; 501 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ 502 status = "disabled"; 503 }; 504}; 505 506/* 507 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 508 * touch screen controller 509 */ 510&i2c2 { 511 clock-frequency = <100000>; 512 pinctrl-names = "default", "gpio"; 513 pinctrl-0 = <&pinctrl_i2c2>; 514 pinctrl-1 = <&pinctrl_i2c2_gpio>; 515 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 516 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 517 status = "okay"; 518 519 pmic: pmic@8 { 520 compatible = "fsl,pfuze100"; 521 fsl,pmic-stby-poweroff; 522 reg = <0x08>; 523 524 regulators { 525 sw1a_reg: sw1ab { 526 regulator-always-on; 527 regulator-boot-on; 528 regulator-max-microvolt = <1875000>; 529 regulator-min-microvolt = <300000>; 530 regulator-ramp-delay = <6250>; 531 }; 532 533 sw1c_reg: sw1c { 534 regulator-always-on; 535 regulator-boot-on; 536 regulator-max-microvolt = <1875000>; 537 regulator-min-microvolt = <300000>; 538 regulator-ramp-delay = <6250>; 539 }; 540 541 sw3a_reg: sw3a { 542 regulator-always-on; 543 regulator-boot-on; 544 regulator-max-microvolt = <1975000>; 545 regulator-min-microvolt = <400000>; 546 }; 547 548 swbst_reg: swbst { 549 regulator-always-on; 550 regulator-boot-on; 551 regulator-max-microvolt = <5150000>; 552 regulator-min-microvolt = <5000000>; 553 }; 554 555 snvs_reg: vsnvs { 556 regulator-always-on; 557 regulator-boot-on; 558 regulator-max-microvolt = <3000000>; 559 regulator-min-microvolt = <1000000>; 560 }; 561 562 vref_reg: vrefddr { 563 regulator-always-on; 564 regulator-boot-on; 565 }; 566 567 vgen1_reg: vgen1 { 568 regulator-always-on; 569 regulator-boot-on; 570 regulator-max-microvolt = <1550000>; 571 regulator-min-microvolt = <800000>; 572 }; 573 574 vgen2_reg: vgen2 { 575 regulator-always-on; 576 regulator-boot-on; 577 regulator-max-microvolt = <1550000>; 578 regulator-min-microvolt = <800000>; 579 }; 580 581 vgen3_reg: vgen3 { 582 regulator-always-on; 583 regulator-boot-on; 584 regulator-max-microvolt = <3300000>; 585 regulator-min-microvolt = <1800000>; 586 }; 587 588 vgen4_reg: vgen4 { 589 regulator-always-on; 590 regulator-boot-on; 591 regulator-max-microvolt = <1800000>; 592 regulator-min-microvolt = <1800000>; 593 }; 594 595 vgen5_reg: vgen5 { 596 regulator-always-on; 597 regulator-boot-on; 598 regulator-max-microvolt = <3300000>; 599 regulator-min-microvolt = <1800000>; 600 }; 601 602 vgen6_reg: vgen6 { 603 regulator-always-on; 604 regulator-boot-on; 605 regulator-max-microvolt = <3300000>; 606 regulator-min-microvolt = <1800000>; 607 }; 608 }; 609 }; 610 611 codec: sgtl5000@a { 612 compatible = "fsl,sgtl5000"; 613 #sound-dai-cells = <0>; 614 clocks = <&clks IMX6QDL_CLK_CKO>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pinctrl_sgtl5000>; 617 reg = <0x0a>; 618 VDDA-supply = <®_module_3v3_audio>; 619 VDDIO-supply = <®_module_3v3>; 620 VDDD-supply = <&vgen4_reg>; 621 }; 622 623 /* STMPE811 touch screen controller */ 624 stmpe811@41 { 625 compatible = "st,stmpe811"; 626 blocks = <0x5>; 627 id = <0>; 628 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 629 interrupt-controller; 630 interrupt-parent = <&gpio4>; 631 irq-trigger = <0x1>; 632 pinctrl-names = "default"; 633 pinctrl-0 = <&pinctrl_touch_int>; 634 reg = <0x41>; 635 /* 3.25 MHz ADC clock speed */ 636 st,adc-freq = <1>; 637 /* 12-bit ADC */ 638 st,mod-12b = <1>; 639 /* internal ADC reference */ 640 st,ref-sel = <0>; 641 /* ADC conversion time: 80 clocks */ 642 st,sample-time = <4>; 643 644 stmpe_ts: stmpe_touchscreen { 645 compatible = "st,stmpe-ts"; 646 /* 8 sample average control */ 647 st,ave-ctrl = <3>; 648 /* 7 length fractional part in z */ 649 st,fraction-z = <7>; 650 /* 651 * 50 mA typical 80 mA max touchscreen drivers 652 * current limit value 653 */ 654 st,i-drive = <1>; 655 /* 1 ms panel driver settling time */ 656 st,settling = <3>; 657 /* 5 ms touch detect interrupt delay */ 658 st,touch-det-delay = <5>; 659 status = "disabled"; 660 }; 661 662 stmpe_adc: stmpe_adc { 663 compatible = "st,stmpe-adc"; 664 #io-channel-cells = <1>; 665 /* forbid to use ADC channels 3-0 (touch) */ 666 st,norequest-mask = <0x0F>; 667 }; 668 }; 669}; 670 671/* 672 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier 673 * board) 674 */ 675&i2c3 { 676 clock-frequency = <100000>; 677 pinctrl-names = "default", "gpio"; 678 pinctrl-0 = <&pinctrl_i2c3>; 679 pinctrl-1 = <&pinctrl_i2c3_gpio>; 680 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 681 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 682 status = "disabled"; 683 684 adv_7280: adv7280@21 { 685 compatible = "adi,adv7280"; 686 adv,force-bt656-4; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&pinctrl_ipu1_csi0>; 689 reg = <0x21>; 690 status = "disabled"; 691 692 port { 693 adv7280_to_ipu1_csi0_mux: endpoint { 694 bus-width = <8>; 695 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 696 }; 697 }; 698 }; 699 700 ov5640_csi_cam: ov5640_mipi@3c { 701 compatible = "ovti,ov5640"; 702 AVDD-supply = <®_ov5640_2v8_a_vdd>; 703 DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; 704 DVDD-supply = <®_ov5640_1v8_d_o_vdd>; 705 clock-names = "xclk"; 706 clocks = <&clks IMX6QDL_CLK_CKO2>; 707 pinctrl-names = "default"; 708 pinctrl-0 = <&pinctrl_cam_mclk>; 709 /* These GPIOs are muxed with the iomuxc node */ 710 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 711 reg = <0x3c>; 712 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 713 status = "disabled"; 714 715 port { 716 ov5640_to_mipi_csi2: endpoint { 717 clock-lanes = <0>; 718 data-lanes = <1 2>; 719 remote-endpoint = <&mipi_csi_from_ov5640>; 720 }; 721 }; 722 }; 723}; 724 725&ipu1_di1_disp1 { 726 remote-endpoint = <&lcd_display_in>; 727}; 728 729&ldb { 730 lvds-channel@0 { 731 port@4 { 732 reg = <4>; 733 734 lvds0_out: endpoint { 735 remote-endpoint = <&lvds_panel_in>; 736 }; 737 }; 738 }; 739 740 lvds-channel@1 { 741 fsl,data-mapping = "spwg"; 742 fsl,data-width = <18>; 743 744 port@4 { 745 reg = <4>; 746 747 lvds1_out: endpoint { 748 }; 749 }; 750 }; 751}; 752 753&mipi_csi { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 status = "disabled"; 757 758 port@0 { 759 reg = <0>; 760 761 mipi_csi_from_ov5640: endpoint { 762 clock-lanes = <0>; 763 data-lanes = <1 2>; 764 remote-endpoint = <&ov5640_to_mipi_csi2>; 765 }; 766 }; 767}; 768 769&pwm1 { 770 pinctrl-names = "default"; 771 pinctrl-0 = <&pinctrl_pwm1>; 772 status = "disabled"; 773}; 774 775&pwm2 { 776 pinctrl-names = "default"; 777 pinctrl-0 = <&pinctrl_pwm2>; 778 status = "disabled"; 779}; 780 781&pwm3 { 782 pinctrl-names = "default"; 783 pinctrl-0 = <&pinctrl_pwm3>; 784 status = "disabled"; 785}; 786 787&pwm4 { 788 pinctrl-names = "default"; 789 pinctrl-0 = <&pinctrl_pwm4>; 790 status = "disabled"; 791}; 792 793&spdif { 794 pinctrl-names = "default"; 795 pinctrl-0 = <&pinctrl_spdif>; 796 status = "disabled"; 797}; 798 799&ssi1 { 800 status = "okay"; 801}; 802 803&uart1 { 804 fsl,dte-mode; 805 pinctrl-names = "default"; 806 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 807 uart-has-rtscts; 808 status = "disabled"; 809}; 810 811&uart2 { 812 fsl,dte-mode; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pinctrl_uart2_dte>; 815 uart-has-rtscts; 816 status = "disabled"; 817}; 818 819&uart4 { 820 fsl,dte-mode; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&pinctrl_uart4_dte>; 823 status = "disabled"; 824}; 825 826&uart5 { 827 fsl,dte-mode; 828 pinctrl-names = "default"; 829 pinctrl-0 = <&pinctrl_uart5_dte>; 830 status = "disabled"; 831}; 832 833&usbotg { 834 pinctrl-names = "default"; 835 pinctrl-0 = <&pinctrl_usbotg>; 836 status = "disabled"; 837}; 838 839/* MMC1 */ 840&usdhc1 { 841 bus-width = <8>; 842 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; 843 disable-wp; 844 no-1-8-v; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; 847 vqmmc-supply = <®_module_3v3>; 848 status = "disabled"; 849}; 850 851/* SD1 */ 852&usdhc2 { 853 bus-width = <4>; 854 disable-wp; 855 no-1-8-v; 856 pinctrl-names = "default"; 857 pinctrl-0 = <&pinctrl_usdhc2>; 858 vqmmc-supply = <®_module_3v3>; 859 status = "disabled"; 860}; 861 862/* eMMC */ 863&usdhc3 { 864 bus-width = <8>; 865 no-1-8-v; 866 non-removable; 867 pinctrl-names = "default"; 868 pinctrl-0 = <&pinctrl_usdhc3>; 869 vqmmc-supply = <®_module_3v3>; 870 status = "okay"; 871}; 872 873&weim { 874 status = "disabled"; 875}; 876 877&iomuxc { 878 /* Mux the Apalis GPIOs */ 879 pinctrl-names = "default"; 880 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 881 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 882 &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 883 &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 884 >; 885 886 pinctrl_apalis_gpio1: apalisgpio1grp { 887 fsl,pins = < 888 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 889 >; 890 }; 891 892 pinctrl_apalis_gpio2: apalisgpio2grp { 893 fsl,pins = < 894 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 895 >; 896 }; 897 898 pinctrl_apalis_gpio3: apalisgpio3grp { 899 fsl,pins = < 900 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 901 >; 902 }; 903 904 pinctrl_apalis_gpio4: apalisgpio4grp { 905 fsl,pins = < 906 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 907 >; 908 }; 909 910 pinctrl_apalis_gpio5: apalisgpio5grp { 911 fsl,pins = < 912 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 913 >; 914 }; 915 916 pinctrl_apalis_gpio6: apalisgpio6grp { 917 fsl,pins = < 918 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 919 >; 920 }; 921 922 pinctrl_apalis_gpio7: apalisgpio7grp { 923 fsl,pins = < 924 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 925 >; 926 }; 927 928 pinctrl_apalis_gpio8: apalisgpio8grp { 929 fsl,pins = < 930 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 931 >; 932 }; 933 934 pinctrl_audmux: audmuxgrp { 935 fsl,pins = < 936 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 937 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 938 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 939 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 940 >; 941 }; 942 943 pinctrl_cam_mclk: cammclkgrp { 944 fsl,pins = < 945 /* CAM sys_mclk */ 946 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 947 >; 948 }; 949 950 pinctrl_ecspi1: ecspi1grp { 951 fsl,pins = < 952 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 953 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 954 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 955 /* SPI1 cs */ 956 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 957 >; 958 }; 959 960 pinctrl_ecspi2: ecspi2grp { 961 fsl,pins = < 962 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 963 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 964 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 965 /* SPI2 cs */ 966 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 967 >; 968 }; 969 970 pinctrl_enet: enetgrp { 971 fsl,pins = < 972 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 973 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 974 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 975 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 976 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 977 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 978 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 979 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 980 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 981 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 982 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 983 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 984 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 985 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 986 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 987 /* Ethernet PHY reset */ 988 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 989 /* Ethernet PHY interrupt */ 990 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 991 >; 992 }; 993 994 pinctrl_flexcan1_default: flexcan1defgrp { 995 fsl,pins = < 996 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 997 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 998 >; 999 }; 1000 1001 pinctrl_flexcan1_sleep: flexcan1slpgrp { 1002 fsl,pins = < 1003 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 1004 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 1005 >; 1006 }; 1007 1008 pinctrl_flexcan2_default: flexcan2defgrp { 1009 fsl,pins = < 1010 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 1011 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 1012 >; 1013 }; 1014 pinctrl_flexcan2_sleep: flexcan2slpgrp { 1015 fsl,pins = < 1016 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 1017 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 1018 >; 1019 }; 1020 1021 pinctrl_gpio_bl_on: gpioblongrp { 1022 fsl,pins = < 1023 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 1024 >; 1025 }; 1026 1027 pinctrl_gpio_keys: gpio1io04grp { 1028 fsl,pins = < 1029 /* Power button */ 1030 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1031 >; 1032 }; 1033 1034 pinctrl_hdmi_cec: hdmicecgrp { 1035 fsl,pins = < 1036 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 1037 >; 1038 }; 1039 1040 pinctrl_hdmi_ddc: hdmiddcgrp { 1041 fsl,pins = < 1042 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 1043 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 1044 >; 1045 }; 1046 1047 pinctrl_i2c1: i2c1grp { 1048 fsl,pins = < 1049 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 1050 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 1051 >; 1052 }; 1053 1054 pinctrl_i2c1_gpio: i2c1gpiogrp { 1055 fsl,pins = < 1056 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 1057 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 1058 >; 1059 }; 1060 1061 pinctrl_i2c2: i2c2grp { 1062 fsl,pins = < 1063 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 1064 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 1065 >; 1066 }; 1067 1068 pinctrl_i2c2_gpio: i2c2gpiogrp { 1069 fsl,pins = < 1070 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 1071 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 1072 >; 1073 }; 1074 1075 pinctrl_i2c3: i2c3grp { 1076 fsl,pins = < 1077 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 1078 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 1079 >; 1080 }; 1081 1082 pinctrl_i2c3_gpio: i2c3gpiogrp { 1083 fsl,pins = < 1084 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 1085 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 1086 >; 1087 }; 1088 1089 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 1090 fsl,pins = < 1091 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 1092 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 1093 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 1094 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 1095 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 1096 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 1097 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 1098 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 1099 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 1100 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 1101 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 1102 >; 1103 }; 1104 1105 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 1106 fsl,pins = < 1107 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 1108 /* DE */ 1109 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 1110 /* HSync */ 1111 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 1112 /* VSync */ 1113 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 1114 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 1115 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 1116 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 1117 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 1118 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 1119 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 1120 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 1121 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 1122 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 1123 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 1124 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 1125 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 1126 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 1127 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 1128 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 1129 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 1130 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 1131 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 1132 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 1133 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 1134 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 1135 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 1136 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 1137 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 1138 >; 1139 }; 1140 1141 pinctrl_ipu2_vdac: ipu2vdacgrp { 1142 fsl,pins = < 1143 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 1144 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 1145 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 1146 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 1147 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 1148 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 1149 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 1150 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 1151 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 1152 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 1153 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 1154 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 1155 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 1156 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 1157 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 1158 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 1159 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 1160 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 1161 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 1162 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 1163 >; 1164 }; 1165 1166 pinctrl_mmc_cd: mmccdgrp { 1167 fsl,pins = < 1168 /* MMC1 CD */ 1169 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 1170 >; 1171 }; 1172 1173 pinctrl_pwm1: pwm1grp { 1174 fsl,pins = < 1175 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 1176 >; 1177 }; 1178 1179 pinctrl_pwm2: pwm2grp { 1180 fsl,pins = < 1181 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 1182 >; 1183 }; 1184 1185 pinctrl_pwm3: pwm3grp { 1186 fsl,pins = < 1187 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1188 >; 1189 }; 1190 1191 pinctrl_pwm4: pwm4grp { 1192 fsl,pins = < 1193 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 1194 >; 1195 }; 1196 1197 pinctrl_regulator_usbh_pwr: regusbhpwrgrp { 1198 fsl,pins = < 1199 /* USBH_EN */ 1200 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 1201 >; 1202 }; 1203 1204 pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { 1205 fsl,pins = < 1206 /* USBH_HUB_EN */ 1207 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 1208 >; 1209 }; 1210 1211 pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { 1212 fsl,pins = < 1213 /* USBO1 power en */ 1214 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 1215 >; 1216 }; 1217 1218 pinctrl_reset_moci: resetmocigrp { 1219 fsl,pins = < 1220 /* RESET_MOCI control */ 1221 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 1222 >; 1223 }; 1224 1225 pinctrl_sd_cd: sdcdgrp { 1226 fsl,pins = < 1227 /* SD1 CD */ 1228 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 1229 >; 1230 }; 1231 1232 pinctrl_sgtl5000: sgtl5000grp { 1233 fsl,pins = < 1234 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 1235 >; 1236 }; 1237 1238 pinctrl_spdif: spdifgrp { 1239 fsl,pins = < 1240 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 1241 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1242 >; 1243 }; 1244 1245 pinctrl_touch_int: touchintgrp { 1246 fsl,pins = < 1247 /* STMPE811 interrupt */ 1248 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1249 >; 1250 }; 1251 1252 /* Additional DTR, DSR, DCD */ 1253 pinctrl_uart1_ctrl: uart1ctrlgrp { 1254 fsl,pins = < 1255 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1256 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1257 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1258 >; 1259 }; 1260 1261 pinctrl_uart1_dce: uart1dcegrp { 1262 fsl,pins = < 1263 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1264 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1265 >; 1266 }; 1267 1268 /* DTE mode */ 1269 pinctrl_uart1_dte: uart1dtegrp { 1270 fsl,pins = < 1271 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1272 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1273 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1274 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1275 >; 1276 }; 1277 1278 pinctrl_uart2_dce: uart2dcegrp { 1279 fsl,pins = < 1280 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 1281 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 1282 >; 1283 }; 1284 1285 /* DTE mode */ 1286 pinctrl_uart2_dte: uart2dtegrp { 1287 fsl,pins = < 1288 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1289 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1290 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1291 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1292 >; 1293 }; 1294 1295 pinctrl_uart4_dce: uart4dcegrp { 1296 fsl,pins = < 1297 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 1298 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 1299 >; 1300 }; 1301 1302 /* DTE mode */ 1303 pinctrl_uart4_dte: uart4dtegrp { 1304 fsl,pins = < 1305 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 1306 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 1307 >; 1308 }; 1309 1310 pinctrl_uart5_dce: uart5dcegrp { 1311 fsl,pins = < 1312 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 1313 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 1314 >; 1315 }; 1316 1317 /* DTE mode */ 1318 pinctrl_uart5_dte: uart5dtegrp { 1319 fsl,pins = < 1320 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 1321 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 1322 >; 1323 }; 1324 1325 pinctrl_usbotg: usbotggrp { 1326 fsl,pins = < 1327 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 1328 >; 1329 }; 1330 1331 pinctrl_usdhc1_4bit: usdhc1-4bitgrp { 1332 fsl,pins = < 1333 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1334 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1335 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1336 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1337 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1338 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1339 >; 1340 }; 1341 1342 pinctrl_usdhc1_8bit: usdhc1-8bitgrp { 1343 fsl,pins = < 1344 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 1345 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 1346 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 1347 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 1348 >; 1349 }; 1350 1351 pinctrl_usdhc2: usdhc2grp { 1352 fsl,pins = < 1353 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 1354 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 1355 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 1356 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 1357 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 1358 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 1359 >; 1360 }; 1361 1362 pinctrl_usdhc3: usdhc3grp { 1363 fsl,pins = < 1364 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1365 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1366 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1367 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1368 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1369 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1370 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1371 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1372 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1373 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1374 /* eMMC reset */ 1375 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1376 >; 1377 }; 1378}; 1379