1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2014-2022 Toradex 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * Copyright 2011 Linaro Ltd. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pwm/pwm.h> 10 11/ { 12 model = "Toradex Apalis iMX6Q/D Module"; 13 compatible = "toradex,apalis_imx6q", "fsl,imx6q"; 14 15 aliases { 16 mmc0 = &usdhc3; /* eMMC */ 17 mmc1 = &usdhc1; /* MMC1 slot */ 18 mmc2 = &usdhc2; /* SD1 slot */ 19 /delete-property/ mmc3; 20 }; 21 22 /* Will be filled by the bootloader */ 23 memory@10000000 { 24 device_type = "memory"; 25 reg = <0x10000000 0>; 26 }; 27 28 backlight: backlight { 29 compatible = "pwm-backlight"; 30 brightness-levels = <0 45 63 88 119 158 203 255>; 31 default-brightness-level = <4>; 32 enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_bl_on>; 35 power-supply = <®_module_3v3>; 36 pwms = <&pwm4 0 5000000 PWM_POLARITY_INVERTED>; 37 status = "disabled"; 38 }; 39 40 clk_ov5640_osc: clk-ov5640-osc { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <24000000>; 44 }; 45 46 gpio-keys { 47 compatible = "gpio-keys"; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_gpio_keys>; 50 51 key-wakeup { 52 debounce-interval = <10>; 53 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 54 label = "Wake-Up"; 55 linux,code = <KEY_WAKEUP>; 56 wakeup-source; 57 }; 58 }; 59 60 lcd_display: disp0 { 61 compatible = "fsl,imx-parallel-display"; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 interface-pix-fmt = "rgb24"; 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_ipu1_lcdif>; 67 status = "disabled"; 68 69 port@0 { 70 reg = <0>; 71 72 lcd_display_in: endpoint { 73 remote-endpoint = <&ipu1_di1_disp1>; 74 }; 75 }; 76 77 port@1 { 78 reg = <1>; 79 80 lcd_display_out: endpoint { 81 remote-endpoint = <&lcd_panel_in>; 82 }; 83 }; 84 }; 85 86 panel_dpi: panel-dpi { 87 compatible = "edt,et057090dhu"; 88 backlight = <&backlight>; 89 90 status = "disabled"; 91 92 port { 93 lcd_panel_in: endpoint { 94 remote-endpoint = <&lcd_display_out>; 95 }; 96 }; 97 }; 98 99 panel_lvds: panel-lvds { 100 compatible = "panel-lvds"; 101 backlight = <&backlight>; 102 status = "disabled"; 103 104 port { 105 lvds_panel_in: endpoint { 106 remote-endpoint = <&lvds0_out>; 107 }; 108 }; 109 }; 110 111 reg_module_3v3: regulator-module-3v3 { 112 compatible = "regulator-fixed"; 113 regulator-always-on; 114 regulator-max-microvolt = <3300000>; 115 regulator-min-microvolt = <3300000>; 116 regulator-name = "+V3.3"; 117 }; 118 119 reg_module_3v3_audio: regulator-module-3v3-audio { 120 compatible = "regulator-fixed"; 121 regulator-always-on; 122 regulator-max-microvolt = <3300000>; 123 regulator-min-microvolt = <3300000>; 124 regulator-name = "+V3.3_AUDIO"; 125 }; 126 127 reg_ov5640_1v8_d_o_vdd: regulator-ov5640-1v8-d-o-vdd { 128 compatible = "regulator-fixed"; 129 regulator-always-on; 130 regulator-max-microvolt = <1800000>; 131 regulator-min-microvolt = <1800000>; 132 regulator-name = "DOVDD/DVDD_1.8V"; 133 /* Note: The CSI module uses on-board 3.3V_SW supply */ 134 vin-supply = <®_module_3v3>; 135 }; 136 137 reg_ov5640_2v8_a_vdd: regulator-ov5640-2v8-a-vdd { 138 compatible = "regulator-fixed"; 139 regulator-always-on; 140 regulator-max-microvolt = <2800000>; 141 regulator-min-microvolt = <2800000>; 142 regulator-name = "AVDD/AFVDD_2.8V"; 143 /* Note: The CSI module uses on-board 3.3V_SW supply */ 144 vin-supply = <®_module_3v3>; 145 }; 146 147 reg_usb_otg_vbus: regulator-usb-otg-vbus { 148 compatible = "regulator-fixed"; 149 enable-active-high; 150 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_regulator_usbotg_pwr>; 153 regulator-max-microvolt = <5000000>; 154 regulator-min-microvolt = <5000000>; 155 regulator-name = "usb_otg_vbus"; 156 status = "disabled"; 157 }; 158 159 /* on module USB hub */ 160 reg_usb_host_vbus_hub: regulator-usb-host-vbus-hub { 161 compatible = "regulator-fixed"; 162 enable-active-high; 163 gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_regulator_usbhub_pwr>; 166 regulator-max-microvolt = <5000000>; 167 regulator-min-microvolt = <5000000>; 168 regulator-name = "usb_host_vbus_hub"; 169 startup-delay-us = <2000>; 170 status = "okay"; 171 }; 172 173 reg_usb_host_vbus: regulator-usb-host-vbus { 174 compatible = "regulator-fixed"; 175 enable-active-high; 176 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; 179 regulator-max-microvolt = <5000000>; 180 regulator-min-microvolt = <5000000>; 181 regulator-name = "usb_host_vbus"; 182 vin-supply = <®_usb_host_vbus_hub>; 183 status = "disabled"; 184 }; 185 186 sound { 187 compatible = "fsl,imx-audio-sgtl5000"; 188 audio-codec = <&codec>; 189 audio-routing = 190 "LINE_IN", "Line In Jack", 191 "MIC_IN", "Mic Jack", 192 "Mic Jack", "Mic Bias", 193 "Headphone Jack", "HP_OUT"; 194 model = "imx6q-apalis-sgtl5000"; 195 mux-ext-port = <4>; 196 mux-int-port = <1>; 197 ssi-controller = <&ssi1>; 198 }; 199 200 spdif_out: spdif-out { 201 compatible = "linux,spdif-dit"; 202 #sound-dai-cells = <0>; 203 }; 204 205 spdif_in: spdif-in { 206 compatible = "linux,spdif-dir"; 207 #sound-dai-cells = <0>; 208 }; 209 210 sound_spdif: sound-spdif { 211 compatible = "fsl,imx-audio-spdif"; 212 audio-cpu = <&spdif>; 213 audio-codec = <&spdif_out>, <&spdif_in>; 214 model = "imx-spdif"; 215 status = "disabled"; 216 }; 217}; 218 219&audmux { 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_audmux>; 222 status = "okay"; 223}; 224 225&can1 { 226 pinctrl-names = "default", "sleep"; 227 pinctrl-0 = <&pinctrl_flexcan1_default>; 228 pinctrl-1 = <&pinctrl_flexcan1_sleep>; 229 status = "disabled"; 230}; 231 232&can2 { 233 pinctrl-names = "default", "sleep"; 234 pinctrl-0 = <&pinctrl_flexcan2_default>; 235 pinctrl-1 = <&pinctrl_flexcan2_sleep>; 236 status = "disabled"; 237}; 238 239&clks { 240 fsl,pmic-stby-poweroff; 241}; 242 243/* Apalis SPI1 */ 244&ecspi1 { 245 cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_ecspi1>; 248 status = "disabled"; 249}; 250 251/* Apalis SPI2 */ 252&ecspi2 { 253 cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_ecspi2>; 256 status = "disabled"; 257}; 258 259&gpio1 { 260 gpio-line-names = "MXM3_84", 261 "MXM3_4", 262 "MXM3_15/GPIO7", 263 "MXM3_96", 264 "MXM3_37", 265 "", 266 "MXM3_17/GPIO8", 267 "MXM3_14", 268 "MXM3_12", 269 "MXM3_2", 270 "MXM3_184", 271 "MXM3_180", 272 "MXM3_178", 273 "MXM3_176", 274 "MXM3_188", 275 "MXM3_186", 276 "MXM3_160", 277 "MXM3_162", 278 "MXM3_150", 279 "MXM3_144", 280 "MXM3_154", 281 "MXM3_146", 282 "", 283 "", 284 "MXM3_72"; 285}; 286 287&gpio2 { 288 gpio-line-names = "MXM3_148", 289 "MXM3_152", 290 "MXM3_156", 291 "MXM3_158", 292 "MXM3_1/GPIO1", 293 "MXM3_3/GPIO2", 294 "MXM3_5/GPIO3", 295 "MXM3_7/GPIO4", 296 "MXM3_95", 297 "MXM3_6", 298 "MXM3_8", 299 "MXM3_123", 300 "MXM3_126", 301 "MXM3_128", 302 "MXM3_130", 303 "MXM3_132", 304 "MXM3_253", 305 "MXM3_251", 306 "MXM3_283", 307 "MXM3_281", 308 "MXM3_279", 309 "MXM3_277", 310 "MXM3_243", 311 "MXM3_235", 312 "MXM3_231", 313 "MXM3_229", 314 "MXM3_233", 315 "MXM3_198", 316 "MXM3_275", 317 "MXM3_273", 318 "MXM3_207", 319 "MXM3_122"; 320}; 321 322&gpio3 { 323 gpio-line-names = "MXM3_271", 324 "MXM3_269", 325 "MXM3_301", 326 "MXM3_299", 327 "MXM3_297", 328 "MXM3_295", 329 "MXM3_293", 330 "MXM3_291", 331 "MXM3_289", 332 "MXM3_287", 333 "MXM3_249", 334 "MXM3_247", 335 "MXM3_245", 336 "MXM3_286", 337 "MXM3_239", 338 "MXM3_35", 339 "MXM3_205", 340 "MXM3_203", 341 "MXM3_201", 342 "MXM3_116", 343 "MXM3_114", 344 "MXM3_262", 345 "MXM3_274", 346 "MXM3_124", 347 "MXM3_110", 348 "MXM3_120", 349 "MXM3_263", 350 "MXM3_265", 351 "", 352 "MXM3_135", 353 "MXM3_261", 354 "MXM3_259"; 355}; 356 357&gpio4 { 358 gpio-line-names = "", 359 "", 360 "", 361 "", 362 "", 363 "MXM3_194", 364 "MXM3_136", 365 "MXM3_134", 366 "MXM3_140", 367 "MXM3_138", 368 "", 369 "MXM3_220", 370 "", 371 "", 372 "MXM3_18", 373 "MXM3_16", 374 "", 375 "", 376 "MXM3_214", 377 "MXM3_216", 378 "MXM3_164"; 379}; 380 381&gpio5 { 382 gpio-line-names = "MXM3_159", 383 "", 384 "", 385 "", 386 "MXM3_257", 387 "", 388 "", 389 "", 390 "", 391 "", 392 "MXM3_200", 393 "MXM3_196", 394 "MXM3_204", 395 "MXM3_202", 396 "", 397 "", 398 "", 399 "", 400 "MXM3_191", 401 "MXM3_197", 402 "MXM3_77", 403 "MXM3_195", 404 "MXM3_221", 405 "MXM3_225", 406 "MXM3_223", 407 "MXM3_227", 408 "MXM3_209", 409 "MXM3_211", 410 "MXM3_118", 411 "MXM3_112", 412 "MXM3_187", 413 "MXM3_185"; 414}; 415 416&gpio6 { 417 gpio-line-names = "MXM3_183", 418 "MXM3_181", 419 "MXM3_179", 420 "MXM3_177", 421 "MXM3_175", 422 "MXM3_173", 423 "MXM3_255", 424 "MXM3_83", 425 "MXM3_91", 426 "MXM3_13/GPIO6", 427 "MXM3_11/GPIO5", 428 "MXM3_79", 429 "", 430 "", 431 "MXM3_190", 432 "MXM3_193", 433 "MXM3_89"; 434}; 435 436&gpio7 { 437 gpio-line-names = "", 438 "", 439 "", 440 "", 441 "", 442 "", 443 "", 444 "", 445 "", 446 "MXM3_99", 447 "MXM3_85", 448 "MXM3_217", 449 "MXM3_215"; 450}; 451 452&gpr { 453 ipu1_csi0_mux { 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "disabled"; 457 458 port@1 { 459 reg = <1>; 460 ipu1_csi0_mux_from_parallel_sensor: endpoint { 461 remote-endpoint = <&adv7280_to_ipu1_csi0_mux>; 462 }; 463 }; 464 }; 465}; 466 467&fec { 468 pinctrl-names = "default"; 469 pinctrl-0 = <&pinctrl_enet>; 470 phy-mode = "rgmii-id"; 471 phy-handle = <ðphy>; 472 phy-reset-duration = <10>; 473 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 474 status = "okay"; 475 476 mdio { 477 #address-cells = <1>; 478 #size-cells = <0>; 479 480 ethphy: ethernet-phy@7 { 481 interrupt-parent = <&gpio1>; 482 interrupts = <30 IRQ_TYPE_LEVEL_LOW>; 483 reg = <7>; 484 }; 485 }; 486}; 487 488&hdmi { 489 pinctrl-names = "default"; 490 pinctrl-0 = <&pinctrl_hdmi_ddc &pinctrl_hdmi_cec>; 491 status = "disabled"; 492}; 493 494/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ 495&i2c1 { 496 clock-frequency = <100000>; 497 pinctrl-names = "default", "gpio"; 498 pinctrl-0 = <&pinctrl_i2c1>; 499 pinctrl-1 = <&pinctrl_i2c1_gpio>; 500 scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 501 sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 502 status = "disabled"; 503 504 atmel_mxt_ts: touchscreen@4a { 505 compatible = "atmel,maxtouch"; 506 /* These GPIOs are muxed with the iomuxc node */ 507 interrupt-parent = <&gpio6>; 508 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* MXM3_11 */ 509 reg = <0x4a>; 510 reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>; /* MXM3_13 */ 511 status = "disabled"; 512 }; 513}; 514 515/* 516 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 517 * touch screen controller 518 */ 519&i2c2 { 520 clock-frequency = <100000>; 521 pinctrl-names = "default", "gpio"; 522 pinctrl-0 = <&pinctrl_i2c2>; 523 pinctrl-1 = <&pinctrl_i2c2_gpio>; 524 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 525 sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 526 status = "okay"; 527 528 pmic: pmic@8 { 529 compatible = "fsl,pfuze100"; 530 fsl,pmic-stby-poweroff; 531 reg = <0x08>; 532 533 regulators { 534 sw1a_reg: sw1ab { 535 regulator-always-on; 536 regulator-boot-on; 537 regulator-max-microvolt = <1875000>; 538 regulator-min-microvolt = <300000>; 539 regulator-ramp-delay = <6250>; 540 }; 541 542 sw1c_reg: sw1c { 543 regulator-always-on; 544 regulator-boot-on; 545 regulator-max-microvolt = <1875000>; 546 regulator-min-microvolt = <300000>; 547 regulator-ramp-delay = <6250>; 548 }; 549 550 sw3a_reg: sw3a { 551 regulator-always-on; 552 regulator-boot-on; 553 regulator-max-microvolt = <1975000>; 554 regulator-min-microvolt = <400000>; 555 }; 556 557 swbst_reg: swbst { 558 regulator-always-on; 559 regulator-boot-on; 560 regulator-max-microvolt = <5150000>; 561 regulator-min-microvolt = <5000000>; 562 }; 563 564 snvs_reg: vsnvs { 565 regulator-always-on; 566 regulator-boot-on; 567 regulator-max-microvolt = <3000000>; 568 regulator-min-microvolt = <1000000>; 569 }; 570 571 vref_reg: vrefddr { 572 regulator-always-on; 573 regulator-boot-on; 574 }; 575 576 vgen1_reg: vgen1 { 577 regulator-always-on; 578 regulator-boot-on; 579 regulator-max-microvolt = <1550000>; 580 regulator-min-microvolt = <800000>; 581 }; 582 583 vgen2_reg: vgen2 { 584 regulator-always-on; 585 regulator-boot-on; 586 regulator-max-microvolt = <1550000>; 587 regulator-min-microvolt = <800000>; 588 }; 589 590 vgen3_reg: vgen3 { 591 regulator-always-on; 592 regulator-boot-on; 593 regulator-max-microvolt = <3300000>; 594 regulator-min-microvolt = <1800000>; 595 }; 596 597 vgen4_reg: vgen4 { 598 regulator-always-on; 599 regulator-boot-on; 600 regulator-max-microvolt = <1800000>; 601 regulator-min-microvolt = <1800000>; 602 }; 603 604 vgen5_reg: vgen5 { 605 regulator-always-on; 606 regulator-boot-on; 607 regulator-max-microvolt = <3300000>; 608 regulator-min-microvolt = <1800000>; 609 }; 610 611 vgen6_reg: vgen6 { 612 regulator-always-on; 613 regulator-boot-on; 614 regulator-max-microvolt = <3300000>; 615 regulator-min-microvolt = <1800000>; 616 }; 617 }; 618 }; 619 620 codec: sgtl5000@a { 621 compatible = "fsl,sgtl5000"; 622 #sound-dai-cells = <0>; 623 clocks = <&clks IMX6QDL_CLK_CKO>; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_sgtl5000>; 626 reg = <0x0a>; 627 VDDA-supply = <®_module_3v3_audio>; 628 VDDIO-supply = <®_module_3v3>; 629 VDDD-supply = <&vgen4_reg>; 630 }; 631 632 /* STMPE811 touch screen controller */ 633 stmpe811@41 { 634 compatible = "st,stmpe811"; 635 blocks = <0x5>; 636 id = <0>; 637 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 638 interrupt-parent = <&gpio4>; 639 irq-trigger = <0x1>; 640 pinctrl-names = "default"; 641 pinctrl-0 = <&pinctrl_touch_int>; 642 reg = <0x41>; 643 /* 3.25 MHz ADC clock speed */ 644 st,adc-freq = <1>; 645 /* 12-bit ADC */ 646 st,mod-12b = <1>; 647 /* internal ADC reference */ 648 st,ref-sel = <0>; 649 /* ADC conversion time: 80 clocks */ 650 st,sample-time = <4>; 651 652 stmpe_ts: stmpe_touchscreen { 653 compatible = "st,stmpe-ts"; 654 /* 8 sample average control */ 655 st,ave-ctrl = <3>; 656 /* 7 length fractional part in z */ 657 st,fraction-z = <7>; 658 /* 659 * 50 mA typical 80 mA max touchscreen drivers 660 * current limit value 661 */ 662 st,i-drive = <1>; 663 /* 1 ms panel driver settling time */ 664 st,settling = <3>; 665 /* 5 ms touch detect interrupt delay */ 666 st,touch-det-delay = <5>; 667 status = "disabled"; 668 }; 669 670 stmpe_adc: stmpe_adc { 671 compatible = "st,stmpe-adc"; 672 #io-channel-cells = <1>; 673 /* forbid to use ADC channels 3-0 (touch) */ 674 st,norequest-mask = <0x0F>; 675 }; 676 }; 677}; 678 679/* 680 * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier 681 * board) 682 */ 683&i2c3 { 684 clock-frequency = <100000>; 685 pinctrl-names = "default", "gpio"; 686 pinctrl-0 = <&pinctrl_i2c3>; 687 pinctrl-1 = <&pinctrl_i2c3_gpio>; 688 scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 689 sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 690 status = "disabled"; 691 692 adv_7280: adv7280@21 { 693 compatible = "adi,adv7280"; 694 adv,force-bt656-4; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&pinctrl_ipu1_csi0>; 697 reg = <0x21>; 698 status = "disabled"; 699 700 port { 701 adv7280_to_ipu1_csi0_mux: endpoint { 702 bus-width = <8>; 703 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 704 }; 705 }; 706 }; 707 708 ov5640_csi_cam: ov5640_mipi@3c { 709 compatible = "ovti,ov5640"; 710 AVDD-supply = <®_ov5640_2v8_a_vdd>; 711 DOVDD-supply = <®_ov5640_1v8_d_o_vdd>; 712 DVDD-supply = <®_ov5640_1v8_d_o_vdd>; 713 clock-names = "xclk"; 714 clocks = <&clks IMX6QDL_CLK_CKO2>; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&pinctrl_cam_mclk>; 717 /* These GPIOs are muxed with the iomuxc node */ 718 powerdown-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 719 reg = <0x3c>; 720 reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 721 status = "disabled"; 722 723 port { 724 ov5640_to_mipi_csi2: endpoint { 725 clock-lanes = <0>; 726 data-lanes = <1 2>; 727 remote-endpoint = <&mipi_csi_from_ov5640>; 728 }; 729 }; 730 }; 731}; 732 733&ipu1_di1_disp1 { 734 remote-endpoint = <&lcd_display_in>; 735}; 736 737&ldb { 738 lvds-channel@0 { 739 port@4 { 740 reg = <4>; 741 742 lvds0_out: endpoint { 743 remote-endpoint = <&lvds_panel_in>; 744 }; 745 }; 746 }; 747 748 lvds-channel@1 { 749 fsl,data-mapping = "spwg"; 750 fsl,data-width = <18>; 751 752 port@4 { 753 reg = <4>; 754 755 lvds1_out: endpoint { 756 }; 757 }; 758 }; 759}; 760 761&mipi_csi { 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 766 port@0 { 767 reg = <0>; 768 769 mipi_csi_from_ov5640: endpoint { 770 clock-lanes = <0>; 771 data-lanes = <1 2>; 772 remote-endpoint = <&ov5640_to_mipi_csi2>; 773 }; 774 }; 775}; 776 777&pwm1 { 778 pinctrl-names = "default"; 779 pinctrl-0 = <&pinctrl_pwm1>; 780 status = "disabled"; 781}; 782 783&pwm2 { 784 pinctrl-names = "default"; 785 pinctrl-0 = <&pinctrl_pwm2>; 786 status = "disabled"; 787}; 788 789&pwm3 { 790 pinctrl-names = "default"; 791 pinctrl-0 = <&pinctrl_pwm3>; 792 status = "disabled"; 793}; 794 795&pwm4 { 796 pinctrl-names = "default"; 797 pinctrl-0 = <&pinctrl_pwm4>; 798 status = "disabled"; 799}; 800 801&spdif { 802 pinctrl-names = "default"; 803 pinctrl-0 = <&pinctrl_spdif>; 804 status = "disabled"; 805}; 806 807&ssi1 { 808 status = "okay"; 809}; 810 811&uart1 { 812 fsl,dte-mode; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>; 815 uart-has-rtscts; 816 status = "disabled"; 817}; 818 819&uart2 { 820 fsl,dte-mode; 821 pinctrl-names = "default"; 822 pinctrl-0 = <&pinctrl_uart2_dte>; 823 uart-has-rtscts; 824 status = "disabled"; 825}; 826 827&uart4 { 828 fsl,dte-mode; 829 pinctrl-names = "default"; 830 pinctrl-0 = <&pinctrl_uart4_dte>; 831 status = "disabled"; 832}; 833 834&uart5 { 835 fsl,dte-mode; 836 pinctrl-names = "default"; 837 pinctrl-0 = <&pinctrl_uart5_dte>; 838 status = "disabled"; 839}; 840 841&usbotg { 842 pinctrl-names = "default"; 843 pinctrl-0 = <&pinctrl_usbotg>; 844 status = "disabled"; 845}; 846 847/* MMC1 */ 848&usdhc1 { 849 bus-width = <8>; 850 cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>; 851 disable-wp; 852 no-1-8-v; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>; 855 vqmmc-supply = <®_module_3v3>; 856 status = "disabled"; 857}; 858 859/* SD1 */ 860&usdhc2 { 861 bus-width = <4>; 862 disable-wp; 863 no-1-8-v; 864 pinctrl-names = "default"; 865 pinctrl-0 = <&pinctrl_usdhc2>; 866 vqmmc-supply = <®_module_3v3>; 867 status = "disabled"; 868}; 869 870/* eMMC */ 871&usdhc3 { 872 bus-width = <8>; 873 no-1-8-v; 874 non-removable; 875 pinctrl-names = "default"; 876 pinctrl-0 = <&pinctrl_usdhc3>; 877 vqmmc-supply = <®_module_3v3>; 878 status = "okay"; 879}; 880 881&weim { 882 status = "disabled"; 883}; 884 885&iomuxc { 886 /* Mux the Apalis GPIOs */ 887 pinctrl-names = "default"; 888 pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 889 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 890 &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 891 &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 892 >; 893 894 pinctrl_apalis_gpio1: apalisgpio1grp { 895 fsl,pins = < 896 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 897 >; 898 }; 899 900 pinctrl_apalis_gpio2: apalisgpio2grp { 901 fsl,pins = < 902 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0 903 >; 904 }; 905 906 pinctrl_apalis_gpio3: apalisgpio3grp { 907 fsl,pins = < 908 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0 909 >; 910 }; 911 912 pinctrl_apalis_gpio4: apalisgpio4grp { 913 fsl,pins = < 914 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0 915 >; 916 }; 917 918 pinctrl_apalis_gpio5: apalisgpio5grp { 919 fsl,pins = < 920 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0 921 >; 922 }; 923 924 pinctrl_apalis_gpio6: apalisgpio6grp { 925 fsl,pins = < 926 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0 927 >; 928 }; 929 930 pinctrl_apalis_gpio7: apalisgpio7grp { 931 fsl,pins = < 932 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0 933 >; 934 }; 935 936 pinctrl_apalis_gpio8: apalisgpio8grp { 937 fsl,pins = < 938 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0 939 >; 940 }; 941 942 pinctrl_audmux: audmuxgrp { 943 fsl,pins = < 944 MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 945 MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 946 MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 947 MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 948 >; 949 }; 950 951 pinctrl_cam_mclk: cammclkgrp { 952 fsl,pins = < 953 /* CAM sys_mclk */ 954 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 955 >; 956 }; 957 958 pinctrl_ecspi1: ecspi1grp { 959 fsl,pins = < 960 MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x100b1 961 MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x100b1 962 MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x100b1 963 /* SPI1 cs */ 964 MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000b1 965 >; 966 }; 967 968 pinctrl_ecspi2: ecspi2grp { 969 fsl,pins = < 970 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 971 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 972 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 973 /* SPI2 cs */ 974 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 975 >; 976 }; 977 978 pinctrl_enet: enetgrp { 979 fsl,pins = < 980 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 981 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 982 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 983 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 984 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 985 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 986 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 987 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 988 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 989 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 990 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 991 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 992 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 993 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 994 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 995 /* Ethernet PHY reset */ 996 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 997 /* Ethernet PHY interrupt */ 998 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x000b1 999 >; 1000 }; 1001 1002 pinctrl_flexcan1_default: flexcan1defgrp { 1003 fsl,pins = < 1004 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 1005 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 1006 >; 1007 }; 1008 1009 pinctrl_flexcan1_sleep: flexcan1slpgrp { 1010 fsl,pins = < 1011 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 1012 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 1013 >; 1014 }; 1015 1016 pinctrl_flexcan2_default: flexcan2defgrp { 1017 fsl,pins = < 1018 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 1019 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 1020 >; 1021 }; 1022 pinctrl_flexcan2_sleep: flexcan2slpgrp { 1023 fsl,pins = < 1024 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 1025 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 1026 >; 1027 }; 1028 1029 pinctrl_gpio_bl_on: gpioblongrp { 1030 fsl,pins = < 1031 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b0 1032 >; 1033 }; 1034 1035 pinctrl_gpio_keys: gpio1io04grp { 1036 fsl,pins = < 1037 /* Power button */ 1038 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 1039 >; 1040 }; 1041 1042 pinctrl_hdmi_cec: hdmicecgrp { 1043 fsl,pins = < 1044 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 1045 >; 1046 }; 1047 1048 pinctrl_hdmi_ddc: hdmiddcgrp { 1049 fsl,pins = < 1050 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 1051 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 1052 >; 1053 }; 1054 1055 pinctrl_i2c1: i2c1grp { 1056 fsl,pins = < 1057 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 1058 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 1059 >; 1060 }; 1061 1062 pinctrl_i2c1_gpio: i2c1gpiogrp { 1063 fsl,pins = < 1064 MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 1065 MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 1066 >; 1067 }; 1068 1069 pinctrl_i2c2: i2c2grp { 1070 fsl,pins = < 1071 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 1072 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 1073 >; 1074 }; 1075 1076 pinctrl_i2c2_gpio: i2c2gpiogrp { 1077 fsl,pins = < 1078 MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 1079 MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 1080 >; 1081 }; 1082 1083 pinctrl_i2c3: i2c3grp { 1084 fsl,pins = < 1085 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 1086 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 1087 >; 1088 }; 1089 1090 pinctrl_i2c3_gpio: i2c3gpiogrp { 1091 fsl,pins = < 1092 MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x4001b8b1 1093 MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x4001b8b1 1094 >; 1095 }; 1096 1097 pinctrl_ipu1_csi0: ipu1csi0grp { /* parallel camera */ 1098 fsl,pins = < 1099 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0xb0b1 1100 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0xb0b1 1101 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0xb0b1 1102 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0xb0b1 1103 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0xb0b1 1104 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0xb0b1 1105 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0xb0b1 1106 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0xb0b1 1107 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 1108 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0xb0b1 1109 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0xb0b1 1110 >; 1111 }; 1112 1113 pinctrl_ipu1_lcdif: ipu1lcdifgrp { 1114 fsl,pins = < 1115 MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x61 1116 /* DE */ 1117 MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x61 1118 /* HSync */ 1119 MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x61 1120 /* VSync */ 1121 MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x61 1122 MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x61 1123 MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x61 1124 MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x61 1125 MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x61 1126 MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x61 1127 MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x61 1128 MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x61 1129 MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x61 1130 MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x61 1131 MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x61 1132 MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x61 1133 MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x61 1134 MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x61 1135 MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x61 1136 MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x61 1137 MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x61 1138 MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x61 1139 MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x61 1140 MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x61 1141 MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x61 1142 MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x61 1143 MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x61 1144 MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x61 1145 MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x61 1146 >; 1147 }; 1148 1149 pinctrl_ipu2_vdac: ipu2vdacgrp { 1150 fsl,pins = < 1151 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0xd1 1152 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0xd1 1153 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0xd1 1154 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0xd1 1155 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0xf9 1156 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0xf9 1157 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0xf9 1158 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0xf9 1159 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0xf9 1160 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0xf9 1161 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0xf9 1162 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0xf9 1163 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0xf9 1164 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0xf9 1165 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0xf9 1166 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0xf9 1167 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0xf9 1168 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0xf9 1169 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0xf9 1170 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0xf9 1171 >; 1172 }; 1173 1174 pinctrl_mmc_cd: mmccdgrp { 1175 fsl,pins = < 1176 /* MMC1 CD */ 1177 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0 1178 >; 1179 }; 1180 1181 pinctrl_pwm1: pwm1grp { 1182 fsl,pins = < 1183 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 1184 >; 1185 }; 1186 1187 pinctrl_pwm2: pwm2grp { 1188 fsl,pins = < 1189 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 1190 >; 1191 }; 1192 1193 pinctrl_pwm3: pwm3grp { 1194 fsl,pins = < 1195 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 1196 >; 1197 }; 1198 1199 pinctrl_pwm4: pwm4grp { 1200 fsl,pins = < 1201 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 1202 >; 1203 }; 1204 1205 pinctrl_regulator_usbh_pwr: regusbhpwrgrp { 1206 fsl,pins = < 1207 /* USBH_EN */ 1208 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058 1209 >; 1210 }; 1211 1212 pinctrl_regulator_usbhub_pwr: regusbhubpwrgrp { 1213 fsl,pins = < 1214 /* USBH_HUB_EN */ 1215 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058 1216 >; 1217 }; 1218 1219 pinctrl_regulator_usbotg_pwr: regusbotgpwrgrp { 1220 fsl,pins = < 1221 /* USBO1 power en */ 1222 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058 1223 >; 1224 }; 1225 1226 pinctrl_reset_moci: resetmocigrp { 1227 fsl,pins = < 1228 /* RESET_MOCI control */ 1229 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058 1230 >; 1231 }; 1232 1233 pinctrl_sd_cd: sdcdgrp { 1234 fsl,pins = < 1235 /* SD1 CD */ 1236 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0 1237 >; 1238 }; 1239 1240 pinctrl_sgtl5000: sgtl5000grp { 1241 fsl,pins = < 1242 MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 1243 >; 1244 }; 1245 1246 pinctrl_spdif: spdifgrp { 1247 fsl,pins = < 1248 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 1249 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 1250 >; 1251 }; 1252 1253 pinctrl_touch_int: touchintgrp { 1254 fsl,pins = < 1255 /* STMPE811 interrupt */ 1256 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 1257 >; 1258 }; 1259 1260 /* Additional DTR, DSR, DCD */ 1261 pinctrl_uart1_ctrl: uart1ctrlgrp { 1262 fsl,pins = < 1263 MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0 1264 MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0 1265 MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0 1266 >; 1267 }; 1268 1269 pinctrl_uart1_dce: uart1dcegrp { 1270 fsl,pins = < 1271 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 1272 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 1273 >; 1274 }; 1275 1276 /* DTE mode */ 1277 pinctrl_uart1_dte: uart1dtegrp { 1278 fsl,pins = < 1279 MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1 1280 MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1 1281 MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1 1282 MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1 1283 >; 1284 }; 1285 1286 pinctrl_uart2_dce: uart2dcegrp { 1287 fsl,pins = < 1288 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 1289 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 1290 >; 1291 }; 1292 1293 /* DTE mode */ 1294 pinctrl_uart2_dte: uart2dtegrp { 1295 fsl,pins = < 1296 MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1 1297 MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1 1298 MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1 1299 MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1 1300 >; 1301 }; 1302 1303 pinctrl_uart4_dce: uart4dcegrp { 1304 fsl,pins = < 1305 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 1306 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 1307 >; 1308 }; 1309 1310 /* DTE mode */ 1311 pinctrl_uart4_dte: uart4dtegrp { 1312 fsl,pins = < 1313 MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1b0b1 1314 MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1b0b1 1315 >; 1316 }; 1317 1318 pinctrl_uart5_dce: uart5dcegrp { 1319 fsl,pins = < 1320 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 1321 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 1322 >; 1323 }; 1324 1325 /* DTE mode */ 1326 pinctrl_uart5_dte: uart5dtegrp { 1327 fsl,pins = < 1328 MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 1329 MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 1330 >; 1331 }; 1332 1333 pinctrl_usbotg: usbotggrp { 1334 fsl,pins = < 1335 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 1336 >; 1337 }; 1338 1339 pinctrl_usdhc1_4bit: usdhc1-4bitgrp { 1340 fsl,pins = < 1341 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 1342 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 1343 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 1344 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 1345 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 1346 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 1347 >; 1348 }; 1349 1350 pinctrl_usdhc1_8bit: usdhc1-8bitgrp { 1351 fsl,pins = < 1352 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071 1353 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071 1354 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071 1355 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17071 1356 >; 1357 }; 1358 1359 pinctrl_usdhc2: usdhc2grp { 1360 fsl,pins = < 1361 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17071 1362 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 1363 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17071 1364 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17071 1365 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17071 1366 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17071 1367 >; 1368 }; 1369 1370 pinctrl_usdhc3: usdhc3grp { 1371 fsl,pins = < 1372 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 1373 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 1374 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 1375 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 1376 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 1377 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 1378 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 1379 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 1380 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 1381 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 1382 /* eMMC reset */ 1383 MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 1384 >; 1385 }; 1386}; 1387