1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC 4 * 5 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Ryan Wanner <Ryan.Wanner@microchip.com> 8 * 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/mfd/at91-usart.h> 17 18/ { 19 model = "Microchip SAMA7D65 family SoC"; 20 compatible = "microchip,sama7d65"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 d-cache-size = <0x8000>; // L1, 32 KB 36 i-cache-size = <0x8000>; // L1, 32 KB 37 next-level-cache = <&L2>; 38 39 L2: l2-cache { 40 compatible = "cache"; 41 cache-level = <2>; 42 cache-size = <0x40000>; // L2, 256 KB 43 cache-unified; 44 }; 45 }; 46 }; 47 48 clocks { 49 main_xtal: clock-mainxtal { 50 compatible = "fixed-clock"; 51 clock-output-names = "main_xtal"; 52 #clock-cells = <0>; 53 }; 54 55 slow_xtal: clock-slowxtal { 56 compatible = "fixed-clock"; 57 clock-output-names = "slow_xtal"; 58 #clock-cells = <0>; 59 }; 60 }; 61 62 ns_sram: sram@100000 { 63 compatible = "mmio-sram"; 64 reg = <0x100000 0x20000>; 65 ranges; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 }; 69 70 soc { 71 compatible = "simple-bus"; 72 ranges; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 76 securam: sram@e0000800 { 77 compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; 78 reg = <0xe0000800 0x4000>; 79 ranges = <0 0xe0000800 0x4000>; 80 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 no-memory-wc; 84 }; 85 86 secumod: security-module@e0004000 { 87 compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; 88 reg = <0xe0004000 0x4000>; 89 gpio-controller; 90 #gpio-cells = <2>; 91 }; 92 93 sfrbu: sfr@e0008000 { 94 compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 95 reg = <0xe0008000 0x20>; 96 }; 97 98 pioa: pinctrl@e0014000 { 99 compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; 100 reg = <0xe0014000 0x800>; 101 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 107 interrupt-controller; 108 #interrupt-cells = <2>; 109 gpio-controller; 110 #gpio-cells = <2>; 111 }; 112 113 pmc: clock-controller@e0018000 { 114 compatible = "microchip,sama7d65-pmc", "syscon"; 115 reg = <0xe0018000 0x200>; 116 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 117 #clock-cells = <2>; 118 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 119 clock-names = "td_slck", "md_slck", "main_xtal"; 120 }; 121 122 ps_wdt: watchdog@e001d000 { 123 compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; 124 reg = <0xe001d000 0x30>; 125 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&clk32k 0>; 127 }; 128 129 reset_controller: reset-controller@e001d100 { 130 compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; 131 reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; 132 #reset-cells = <1>; 133 clocks = <&clk32k 0>; 134 }; 135 136 shdwc: poweroff@e001d200 { 137 compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; 138 reg = <0xe001d200 0x20>; 139 clocks = <&clk32k 0>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 atmel,wakeup-rtc-timer; 143 atmel,wakeup-rtt-timer; 144 status = "disabled"; 145 }; 146 147 rtt: rtc@e001d300 { 148 compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; 149 reg = <0xe001d300 0x30>; 150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&clk32k 0>; 152 }; 153 154 clk32k: clock-controller@e001d500 { 155 compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; 156 reg = <0xe001d500 0x4>; 157 clocks = <&slow_xtal>; 158 #clock-cells = <1>; 159 }; 160 161 gpbr: syscon@e001d700 { 162 compatible = "microchip,sama7d65-gpbr", "syscon"; 163 reg = <0xe001d700 0x48>; 164 }; 165 166 rtc: rtc@e001d800 { 167 compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; 168 reg = <0xe001d800 0x30>; 169 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&clk32k 1>; 171 }; 172 173 chipid@e0020000 { 174 compatible = "microchip,sama7d65-chipid"; 175 reg = <0xe0020000 0x8>; 176 }; 177 178 can0: can@e0828000 { 179 compatible = "bosch,m_can"; 180 reg = <0xe0828000 0x200>, <0x100000 0x7800>; 181 reg-names = "m_can", "message_ram"; 182 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "int0", "int1"; 185 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 186 clock-names = "hclk", "cclk"; 187 assigned-clocks = <&pmc PMC_TYPE_GCK 58>; 188 assigned-clock-rates = <40000000>; 189 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 190 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 191 status = "disabled"; 192 }; 193 194 can1: can@e082c000 { 195 compatible = "bosch,m_can"; 196 reg = <0xe082c000 0x200>, <0x100000 0xbc00>; 197 reg-names = "m_can", "message_ram"; 198 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-names = "int0", "int1"; 201 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 202 clock-names = "hclk", "cclk"; 203 assigned-clocks = <&pmc PMC_TYPE_GCK 59>; 204 assigned-clock-rates = <40000000>; 205 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 206 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 207 status = "disabled"; 208 }; 209 210 can2: can@e0830000 { 211 compatible = "bosch,m_can"; 212 reg = <0xe0830000 0x200>, <0x100000 0x10000>; 213 reg-names = "m_can", "message_ram"; 214 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "int0", "int1"; 217 clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; 218 clock-names = "hclk", "cclk"; 219 assigned-clocks = <&pmc PMC_TYPE_GCK 60>; 220 assigned-clock-rates = <40000000>; 221 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 222 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 223 status = "disabled"; 224 }; 225 226 can3: can@e0834000 { 227 compatible = "bosch,m_can"; 228 reg = <0xe0834000 0x200>, <0x110000 0x4400>; 229 reg-names = "m_can", "message_ram"; 230 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-names = "int0", "int1"; 233 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 234 clock-names = "hclk", "cclk"; 235 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 236 assigned-clock-rates = <40000000>; 237 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 238 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 239 status = "disabled"; 240 }; 241 242 can4: can@e0838000 { 243 compatible = "bosch,m_can"; 244 reg = <0xe0838000 0x200>, <0x110000 0x8800>; 245 reg-names = "m_can", "message_ram"; 246 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-names = "int0", "int1"; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 250 clock-names = "hclk", "cclk"; 251 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 252 assigned-clock-rates = <40000000>; 253 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 254 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 255 status = "disabled"; 256 }; 257 258 dma2: dma-controller@e1200000 { 259 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 260 reg = <0xe1200000 0x1000>; 261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 262 #dma-cells = <1>; 263 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 264 clock-names = "dma_clk"; 265 dma-requests = <0>; 266 status = "disabled"; 267 }; 268 269 sdmmc1: mmc@e1208000 { 270 compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; 271 reg = <0xe1208000 0x400>; 272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; 274 clock-names = "hclock", "multclk"; 275 assigned-clocks = <&pmc PMC_TYPE_GCK 76>; 276 assigned-clock-rates = <200000000>; 277 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; 278 status = "disabled"; 279 }; 280 281 aes: crypto@e1600000 { 282 compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; 283 reg = <0xe1600000 0x100>; 284 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 286 clock-names = "aes_clk"; 287 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 288 <&dma0 AT91_XDMAC_DT_PERID(2)>; 289 dma-names = "tx", "rx"; 290 }; 291 292 sha: crypto@e1604000 { 293 compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha"; 294 reg = <0xe1604000 0x100>; 295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>; 297 clock-names = "sha_clk"; 298 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 299 dma-names = "tx"; 300 }; 301 302 tdes: crypto@e1608000 { 303 compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes"; 304 reg = <0xe1608000 0x100>; 305 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>; 307 clock-names = "tdes_clk"; 308 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 309 <&dma0 AT91_XDMAC_DT_PERID(53)>; 310 dma-names = "tx", "rx"; 311 }; 312 313 trng: rng@e160c000 { 314 compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng"; 315 reg = <0xe160c000 0x100>; 316 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&pmc PMC_TYPE_PERIPHERAL 92>; 318 }; 319 320 dma0: dma-controller@e1610000 { 321 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 322 reg = <0xe1610000 0x1000>; 323 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 324 #dma-cells = <1>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 326 clock-names = "dma_clk"; 327 status = "disabled"; 328 }; 329 330 dma1: dma-controller@e1614000 { 331 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 332 reg = <0xe1614000 0x1000>; 333 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 334 #dma-cells = <1>; 335 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 336 clock-names = "dma_clk"; 337 status = "disabled"; 338 }; 339 340 gmac0: ethernet@e1618000 { 341 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 342 reg = <0xe1618000 0x2000>; 343 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 350 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 351 assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 352 assigned-clock-rates = <125000000>, <200000000>; 353 status = "disabled"; 354 }; 355 356 gmac1: ethernet@e161c000 { 357 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 358 reg = <0xe161c000 0x2000>; 359 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 366 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 367 assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 368 assigned-clock-rates = <125000000>, <200000000>; 369 status = "disabled"; 370 }; 371 372 pit64b0: timer@e1800000 { 373 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 374 reg = <0xe1800000 0x100>; 375 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 377 clock-names = "pclk", "gclk"; 378 }; 379 380 pit64b1: timer@e1804000 { 381 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 382 reg = <0xe1804000 0x100>; 383 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; 385 clock-names = "pclk", "gclk"; 386 }; 387 388 pwm: pwm@e1818000 { 389 compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm"; 390 reg = <0xe1818000 0x500>; 391 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&pmc PMC_TYPE_PERIPHERAL 72>; 393 #pwm-cells = <3>; 394 status = "disabled"; 395 }; 396 397 flx0: flexcom@e1820000 { 398 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 399 reg = <0xe1820000 0x200>; 400 ranges = <0x0 0xe1820000 0x800>; 401 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 status = "disabled"; 405 406 uart0: serial@200 { 407 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 408 reg = <0x200 0x200>; 409 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 411 clock-names = "usart"; 412 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 413 <&dma1 AT91_XDMAC_DT_PERID(5)>; 414 dma-names = "tx", "rx"; 415 atmel,use-dma-rx; 416 atmel,use-dma-tx; 417 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 418 status = "disabled"; 419 }; 420 421 i2c0: i2c@600 { 422 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 423 reg = <0x600 0x200>; 424 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 atmel,fifo-size = <32>; 429 dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>, 430 <&dma0 AT91_XDMAC_DT_PERID(5)>; 431 dma-names = "tx", "rx"; 432 status = "disabled"; 433 }; 434 }; 435 436 flx1: flexcom@e1824000 { 437 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 438 reg = <0xe1824000 0x200>; 439 ranges = <0x0 0xe1824000 0x800>; 440 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 status = "disabled"; 444 445 spi1: spi@400 { 446 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 447 reg = <0x400 0x200>; 448 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 450 clock-names = "spi_clk"; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 454 <&dma0 AT91_XDMAC_DT_PERID(7)>; 455 dma-names = "tx", "rx"; 456 atmel,fifo-size = <32>; 457 status = "disabled"; 458 }; 459 460 i2c1: i2c@600 { 461 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 462 reg = <0x600 0x200>; 463 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 468 <&dma0 AT91_XDMAC_DT_PERID(7)>; 469 dma-names = "tx", "rx"; 470 atmel,fifo-size = <32>; 471 status = "disabled"; 472 }; 473 }; 474 475 flx2: flexcom@e1828000 { 476 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 477 reg = <0xe1828000 0x200>; 478 ranges = <0x0 0xe1828000 0x800>; 479 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 480 #address-cells = <1>; 481 #size-cells = <1>; 482 status = "disabled"; 483 484 uart2: serial@200 { 485 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 486 reg = <0x200 0x200>; 487 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 489 clock-names = "usart"; 490 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 491 <&dma1 AT91_XDMAC_DT_PERID(9)>; 492 dma-names = "tx", "rx"; 493 atmel,use-dma-rx; 494 atmel,use-dma-tx; 495 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 496 status = "disabled"; 497 }; 498 }; 499 500 flx3: flexcom@e182c000 { 501 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 502 reg = <0xe182c000 0x200>; 503 ranges = <0x0 0xe182c000 0x800>; 504 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 505 #address-cells = <1>; 506 #size-cells = <1>; 507 status = "disabled"; 508 509 i2c3: i2c@600 { 510 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 511 reg = <0x600 0x200>; 512 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 513 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 514 #address-cells = <1>; 515 #size-cells = <1>; 516 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 517 <&dma0 AT91_XDMAC_DT_PERID(11)>; 518 dma-names = "tx", "rx"; 519 atmel,fifo-size = <32>; 520 status = "disabled"; 521 }; 522 523 }; 524 525 flx4: flexcom@e2018000 { 526 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 527 reg = <0xe2018000 0x200>; 528 ranges = <0x0 0xe2018000 0x800>; 529 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 status = "disabled"; 533 534 uart4: serial@200 { 535 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 536 reg = <0x200 0x200>; 537 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 539 clock-names = "usart"; 540 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 541 <&dma1 AT91_XDMAC_DT_PERID(13)>; 542 dma-names = "tx", "rx"; 543 atmel,use-dma-rx; 544 atmel,use-dma-tx; 545 atmel,fifo-size = <16>; 546 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 547 status = "disabled"; 548 }; 549 550 spi4: spi@400 { 551 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 552 reg = <0x400 0x200>; 553 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 555 clock-names = "spi_clk"; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>, 559 <&dma0 AT91_XDMAC_DT_PERID(13)>; 560 dma-names = "tx", "rx"; 561 atmel,fifo-size = <32>; 562 status = "disabled"; 563 }; 564 }; 565 566 flx5: flexcom@e201c000 { 567 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 568 reg = <0xe201c000 0x200>; 569 ranges = <0x0 0xe201c000 0x800>; 570 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 status = "disabled"; 574 575 i2c5: i2c@600 { 576 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 577 reg = <0x600 0x200>; 578 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 583 <&dma0 AT91_XDMAC_DT_PERID(15)>; 584 dma-names = "tx", "rx"; 585 atmel,fifo-size = <32>; 586 status = "disabled"; 587 }; 588 }; 589 590 flx6: flexcom@e2020000 { 591 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 592 reg = <0xe2020000 0x200>; 593 ranges = <0x0 0xe2020000 0x800>; 594 #address-cells = <1>; 595 #size-cells = <1>; 596 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 597 status = "disabled"; 598 599 uart6: serial@200 { 600 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 601 reg = <0x200 0x200>; 602 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 604 clock-names = "usart"; 605 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 606 atmel,fifo-size = <16>; 607 status = "disabled"; 608 }; 609 }; 610 611 flx7: flexcom@e2024000 { 612 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 613 reg = <0xe2024000 0x200>; 614 ranges = <0x0 0xe2024000 0x800>; 615 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 status = "disabled"; 619 620 uart7: serial@200 { 621 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 622 reg = <0x200 0x200>; 623 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 625 clock-names = "usart"; 626 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 627 <&dma1 AT91_XDMAC_DT_PERID(19)>; 628 dma-names = "tx", "rx"; 629 atmel,use-dma-rx; 630 atmel,use-dma-tx; 631 atmel,fifo-size = <16>; 632 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 633 status = "disabled"; 634 }; 635 }; 636 637 flx8: flexcom@e281c000 { 638 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 639 reg = <0xe281c000 0x200>; 640 ranges = <0x0 0xe281c000 0x800>; 641 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 642 #address-cells = <1>; 643 #size-cells = <1>; 644 status = "disabled"; 645 646 i2c8: i2c@600 { 647 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 648 reg = <0x600 0x200>; 649 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 654 <&dma0 AT91_XDMAC_DT_PERID(21)>; 655 dma-names = "tx", "rx"; 656 atmel,fifo-size = <32>; 657 status = "disabled"; 658 }; 659 }; 660 661 flx9: flexcom@e2820000 { 662 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 663 reg = <0xe2820000 0x200>; 664 ranges = <0x0 0xe281c000 0x800>; 665 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 status = "disabled"; 669 670 i2c9: i2c@600 { 671 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 672 reg = <0x600 0x200>; 673 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 675 #address-cells = <1>; 676 #size-cells = <0>; 677 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 678 <&dma0 AT91_XDMAC_DT_PERID(23)>; 679 dma-names = "tx", "rx"; 680 atmel,fifo-size = <32>; 681 status = "disabled"; 682 }; 683 }; 684 685 flx10: flexcom@e2824000 { 686 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 687 reg = <0xe2824000 0x200>; 688 ranges = <0x0 0xe2824000 0x800>; 689 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 status = "disabled"; 693 694 i2c10: i2c@600 { 695 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 696 reg = <0x600 0x200>; 697 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 atmel,fifo-size = <32>; 702 status = "disabled"; 703 }; 704 }; 705 706 uddrc: uddrc@e3800000 { 707 compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; 708 reg = <0xe3800000 0x4000>; 709 }; 710 711 ddr3phy: ddr3phy@e3804000 { 712 compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; 713 reg = <0xe3804000 0x1000>; 714 }; 715 716 gic: interrupt-controller@e8c11000 { 717 compatible = "arm,cortex-a7-gic"; 718 reg = <0xe8c11000 0x1000>, 719 <0xe8c12000 0x2000>; 720 #interrupt-cells = <3>; 721 #address-cells = <0>; 722 interrupt-controller; 723 }; 724 }; 725}; 726