1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC 4 * 5 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Ryan Wanner <Ryan.Wanner@microchip.com> 8 * 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/mfd/at91-usart.h> 17 18/ { 19 model = "Microchip SAMA7D65 family SoC"; 20 compatible = "microchip,sama7d65"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 }; 36 }; 37 38 clocks { 39 main_xtal: clock-mainxtal { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 }; 43 44 slow_xtal: clock-slowxtal { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 soc { 51 compatible = "simple-bus"; 52 ranges; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 sfrbu: sfr@e0008000 { 57 compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 58 reg = <0xe0008000 0x20>; 59 }; 60 61 pioa: pinctrl@e0014000 { 62 compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; 63 reg = <0xe0014000 0x800>; 64 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 70 interrupt-controller; 71 #interrupt-cells = <2>; 72 gpio-controller; 73 #gpio-cells = <2>; 74 }; 75 76 pmc: clock-controller@e0018000 { 77 compatible = "microchip,sama7d65-pmc", "syscon"; 78 reg = <0xe0018000 0x200>; 79 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 80 #clock-cells = <2>; 81 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 82 clock-names = "td_slck", "md_slck", "main_xtal"; 83 }; 84 85 ps_wdt: watchdog@e001d000 { 86 compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; 87 reg = <0xe001d000 0x30>; 88 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 89 clocks = <&clk32k 0>; 90 }; 91 92 reset_controller: reset-controller@e001d100 { 93 compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; 94 reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; 95 #reset-cells = <1>; 96 clocks = <&clk32k 0>; 97 }; 98 99 shdwc: poweroff@e001d200 { 100 compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; 101 reg = <0xe001d200 0x20>; 102 clocks = <&clk32k 0>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 atmel,wakeup-rtc-timer; 106 atmel,wakeup-rtt-timer; 107 status = "disabled"; 108 }; 109 110 clk32k: clock-controller@e001d500 { 111 compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; 112 reg = <0xe001d500 0x4>; 113 clocks = <&slow_xtal>; 114 #clock-cells = <1>; 115 }; 116 117 rtc: rtc@e001d800 { 118 compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; 119 reg = <0xe001d800 0x30>; 120 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&clk32k 1>; 122 }; 123 124 chipid@e0020000 { 125 compatible = "microchip,sama7d65-chipid"; 126 reg = <0xe0020000 0x8>; 127 }; 128 129 dma2: dma-controller@e1200000 { 130 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 131 reg = <0xe1200000 0x1000>; 132 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 133 #dma-cells = <1>; 134 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 135 clock-names = "dma_clk"; 136 dma-requests = <0>; 137 status = "disabled"; 138 }; 139 140 sdmmc1: mmc@e1208000 { 141 compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; 142 reg = <0xe1208000 0x400>; 143 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 144 clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; 145 clock-names = "hclock", "multclk"; 146 assigned-clocks = <&pmc PMC_TYPE_GCK 76>; 147 assigned-clock-rates = <200000000>; 148 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; 149 status = "disabled"; 150 }; 151 152 dma0: dma-controller@e1610000 { 153 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 154 reg = <0xe1610000 0x1000>; 155 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 156 #dma-cells = <1>; 157 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 158 clock-names = "dma_clk"; 159 status = "disabled"; 160 }; 161 162 dma1: dma-controller@e1614000 { 163 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 164 reg = <0xe1614000 0x1000>; 165 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 168 clock-names = "dma_clk"; 169 status = "disabled"; 170 }; 171 172 pit64b0: timer@e1800000 { 173 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 174 reg = <0xe1800000 0x100>; 175 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 176 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 177 clock-names = "pclk", "gclk"; 178 }; 179 180 pit64b1: timer@e1804000 { 181 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 182 reg = <0xe1804000 0x100>; 183 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; 185 clock-names = "pclk", "gclk"; 186 }; 187 188 flx6: flexcom@e2020000 { 189 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 190 reg = <0xe2020000 0x200>; 191 ranges = <0x0 0xe2020000 0x800>; 192 #address-cells = <1>; 193 #size-cells = <1>; 194 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 195 status = "disabled"; 196 197 uart6: serial@200 { 198 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 199 reg = <0x200 0x200>; 200 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 202 clock-names = "usart"; 203 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 204 atmel,fifo-size = <16>; 205 status = "disabled"; 206 }; 207 }; 208 209 flx10: flexcom@e2824000 { 210 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 211 reg = <0xe2824000 0x200>; 212 ranges = <0x0 0xe2824000 0x800>; 213 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 status = "disabled"; 217 218 i2c10: i2c@600 { 219 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 220 reg = <0x600 0x200>; 221 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 atmel,fifo-size = <32>; 226 status = "disabled"; 227 }; 228 }; 229 230 gic: interrupt-controller@e8c11000 { 231 compatible = "arm,cortex-a7-gic"; 232 reg = <0xe8c11000 0x1000>, 233 <0xe8c12000 0x2000>; 234 #interrupt-cells = <3>; 235 #address-cells = <0>; 236 interrupt-controller; 237 }; 238 }; 239}; 240