1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC 4 * 5 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Ryan Wanner <Ryan.Wanner@microchip.com> 8 * 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/mfd/at91-usart.h> 17 18/ { 19 model = "Microchip SAMA7D65 family SoC"; 20 compatible = "microchip,sama7d65"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 d-cache-size = <0x8000>; // L1, 32 KB 36 i-cache-size = <0x8000>; // L1, 32 KB 37 next-level-cache = <&L2>; 38 39 L2: l2-cache { 40 compatible = "cache"; 41 cache-level = <2>; 42 cache-size = <0x40000>; // L2, 256 KB 43 cache-unified; 44 }; 45 }; 46 }; 47 48 clocks { 49 main_xtal: clock-mainxtal { 50 compatible = "fixed-clock"; 51 clock-output-names = "main_xtal"; 52 #clock-cells = <0>; 53 }; 54 55 slow_xtal: clock-slowxtal { 56 compatible = "fixed-clock"; 57 clock-output-names = "slow_xtal"; 58 #clock-cells = <0>; 59 }; 60 }; 61 62 ns_sram: sram@100000 { 63 compatible = "mmio-sram"; 64 reg = <0x100000 0x20000>; 65 ranges; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a7-pmu"; 72 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 73 }; 74 75 soc { 76 compatible = "simple-bus"; 77 ranges; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 81 securam: sram@e0000800 { 82 compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; 83 reg = <0xe0000800 0x4000>; 84 ranges = <0 0xe0000800 0x4000>; 85 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 86 #address-cells = <1>; 87 #size-cells = <1>; 88 no-memory-wc; 89 }; 90 91 secumod: security-module@e0004000 { 92 compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; 93 reg = <0xe0004000 0x4000>; 94 gpio-controller; 95 #gpio-cells = <2>; 96 }; 97 98 sfrbu: sfr@e0008000 { 99 compatible = "microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 100 reg = <0xe0008000 0x20>; 101 }; 102 103 pioa: pinctrl@e0014000 { 104 compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; 105 reg = <0xe0014000 0x800>; 106 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 108 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 109 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 110 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 gpio-controller; 115 #gpio-cells = <2>; 116 }; 117 118 pmc: clock-controller@e0018000 { 119 compatible = "microchip,sama7d65-pmc", "syscon"; 120 reg = <0xe0018000 0x200>; 121 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 122 #clock-cells = <2>; 123 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 124 clock-names = "td_slck", "md_slck", "main_xtal"; 125 }; 126 127 ps_wdt: watchdog@e001d000 { 128 compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; 129 reg = <0xe001d000 0x30>; 130 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&clk32k 0>; 132 }; 133 134 reset_controller: reset-controller@e001d100 { 135 compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; 136 reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; 137 #reset-cells = <1>; 138 clocks = <&clk32k 0>; 139 }; 140 141 shdwc: poweroff@e001d200 { 142 compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; 143 reg = <0xe001d200 0x20>; 144 clocks = <&clk32k 0>; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 atmel,wakeup-rtc-timer; 148 atmel,wakeup-rtt-timer; 149 status = "disabled"; 150 }; 151 152 rtt: rtc@e001d300 { 153 compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; 154 reg = <0xe001d300 0x30>; 155 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&clk32k 0>; 157 }; 158 159 clk32k: clock-controller@e001d500 { 160 compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; 161 reg = <0xe001d500 0x4>; 162 clocks = <&slow_xtal>; 163 #clock-cells = <1>; 164 }; 165 166 gpbr: syscon@e001d700 { 167 compatible = "microchip,sama7d65-gpbr", "syscon"; 168 reg = <0xe001d700 0x48>; 169 }; 170 171 rtc: rtc@e001d800 { 172 compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; 173 reg = <0xe001d800 0x30>; 174 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&clk32k 1>; 176 }; 177 178 chipid@e0020000 { 179 compatible = "microchip,sama7d65-chipid"; 180 reg = <0xe0020000 0x8>; 181 }; 182 183 can0: can@e0828000 { 184 compatible = "bosch,m_can"; 185 reg = <0xe0828000 0x200>, <0x100000 0x7800>; 186 reg-names = "m_can", "message_ram"; 187 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-names = "int0", "int1"; 190 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 191 clock-names = "hclk", "cclk"; 192 assigned-clocks = <&pmc PMC_TYPE_GCK 58>; 193 assigned-clock-rates = <40000000>; 194 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 195 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 196 status = "disabled"; 197 }; 198 199 can1: can@e082c000 { 200 compatible = "bosch,m_can"; 201 reg = <0xe082c000 0x200>, <0x100000 0xbc00>; 202 reg-names = "m_can", "message_ram"; 203 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 205 interrupt-names = "int0", "int1"; 206 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 207 clock-names = "hclk", "cclk"; 208 assigned-clocks = <&pmc PMC_TYPE_GCK 59>; 209 assigned-clock-rates = <40000000>; 210 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 211 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 212 status = "disabled"; 213 }; 214 215 can2: can@e0830000 { 216 compatible = "bosch,m_can"; 217 reg = <0xe0830000 0x200>, <0x100000 0x10000>; 218 reg-names = "m_can", "message_ram"; 219 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-names = "int0", "int1"; 222 clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; 223 clock-names = "hclk", "cclk"; 224 assigned-clocks = <&pmc PMC_TYPE_GCK 60>; 225 assigned-clock-rates = <40000000>; 226 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 227 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 228 status = "disabled"; 229 }; 230 231 can3: can@e0834000 { 232 compatible = "bosch,m_can"; 233 reg = <0xe0834000 0x200>, <0x110000 0x4400>; 234 reg-names = "m_can", "message_ram"; 235 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "int0", "int1"; 238 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 239 clock-names = "hclk", "cclk"; 240 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 241 assigned-clock-rates = <40000000>; 242 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 243 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 244 status = "disabled"; 245 }; 246 247 can4: can@e0838000 { 248 compatible = "bosch,m_can"; 249 reg = <0xe0838000 0x200>, <0x110000 0x8800>; 250 reg-names = "m_can", "message_ram"; 251 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 253 interrupt-names = "int0", "int1"; 254 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 255 clock-names = "hclk", "cclk"; 256 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 257 assigned-clock-rates = <40000000>; 258 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 259 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 260 status = "disabled"; 261 }; 262 263 dma2: dma-controller@e1200000 { 264 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 265 reg = <0xe1200000 0x1000>; 266 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 267 #dma-cells = <1>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 269 clock-names = "dma_clk"; 270 dma-requests = <0>; 271 status = "disabled"; 272 }; 273 274 sdmmc1: mmc@e1208000 { 275 compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; 276 reg = <0xe1208000 0x400>; 277 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; 279 clock-names = "hclock", "multclk"; 280 assigned-clocks = <&pmc PMC_TYPE_GCK 76>; 281 assigned-clock-rates = <200000000>; 282 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; 283 status = "disabled"; 284 }; 285 286 xlcdc: lcd-controller@e1400000 { 287 compatible = "microchip,sama7d65-xlcdc"; 288 reg = <0xe1400000 0x2000>; 289 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>, <&clk32k 1>; 291 clock-names = "periph_clk", "sys_clk", "slow_clk"; 292 status = "disabled"; 293 294 display-controller { 295 compatible = "atmel,hlcdc-display-controller"; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 port@0 { 300 reg = <0>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 }; 304 }; 305 306 pwm { 307 compatible = "atmel,hlcdc-pwm"; 308 #pwm-cells = <3>; 309 }; 310 }; 311 312 lvdsc: lvds-controller@e1408000 { 313 compatible = "microchip,sama7d65-lvds", "microchip,sam9x75-lvds"; 314 reg = <0xe1408000 0x100>; 315 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&pmc PMC_TYPE_PERIPHERAL 104>; 317 clock-names = "pclk"; 318 status = "disabled"; 319 }; 320 321 aes: crypto@e1600000 { 322 compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; 323 reg = <0xe1600000 0x100>; 324 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 326 clock-names = "aes_clk"; 327 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 328 <&dma0 AT91_XDMAC_DT_PERID(2)>; 329 dma-names = "tx", "rx"; 330 }; 331 332 sha: crypto@e1604000 { 333 compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha"; 334 reg = <0xe1604000 0x100>; 335 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>; 337 clock-names = "sha_clk"; 338 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 339 dma-names = "tx"; 340 }; 341 342 tdes: crypto@e1608000 { 343 compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes"; 344 reg = <0xe1608000 0x100>; 345 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>; 347 clock-names = "tdes_clk"; 348 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 349 <&dma0 AT91_XDMAC_DT_PERID(53)>; 350 dma-names = "tx", "rx"; 351 }; 352 353 trng: rng@e160c000 { 354 compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng"; 355 reg = <0xe160c000 0x100>; 356 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&pmc PMC_TYPE_PERIPHERAL 92>; 358 }; 359 360 dma0: dma-controller@e1610000 { 361 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 362 reg = <0xe1610000 0x1000>; 363 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 364 #dma-cells = <1>; 365 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 366 clock-names = "dma_clk"; 367 status = "disabled"; 368 }; 369 370 dma1: dma-controller@e1614000 { 371 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 372 reg = <0xe1614000 0x1000>; 373 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 374 #dma-cells = <1>; 375 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 376 clock-names = "dma_clk"; 377 status = "disabled"; 378 }; 379 380 gmac0: ethernet@e1618000 { 381 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 382 reg = <0xe1618000 0x2000>; 383 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 390 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 391 assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 392 assigned-clock-rates = <125000000>, <200000000>; 393 status = "disabled"; 394 }; 395 396 gmac1: ethernet@e161c000 { 397 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 398 reg = <0xe161c000 0x2000>; 399 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 406 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 407 assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 408 assigned-clock-rates = <125000000>, <200000000>; 409 status = "disabled"; 410 }; 411 412 pit64b0: timer@e1800000 { 413 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 414 reg = <0xe1800000 0x100>; 415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 417 clock-names = "pclk", "gclk"; 418 }; 419 420 pit64b1: timer@e1804000 { 421 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 422 reg = <0xe1804000 0x100>; 423 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; 425 clock-names = "pclk", "gclk"; 426 }; 427 428 pwm: pwm@e1818000 { 429 compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm"; 430 reg = <0xe1818000 0x500>; 431 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&pmc PMC_TYPE_PERIPHERAL 72>; 433 #pwm-cells = <3>; 434 status = "disabled"; 435 }; 436 437 flx0: flexcom@e1820000 { 438 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 439 reg = <0xe1820000 0x200>; 440 ranges = <0x0 0xe1820000 0x800>; 441 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 status = "disabled"; 445 446 uart0: serial@200 { 447 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 448 reg = <0x200 0x200>; 449 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 451 clock-names = "usart"; 452 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 453 <&dma1 AT91_XDMAC_DT_PERID(5)>; 454 dma-names = "tx", "rx"; 455 atmel,use-dma-rx; 456 atmel,use-dma-tx; 457 atmel,fifo-size = <32>; 458 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 459 status = "disabled"; 460 }; 461 462 spi0: spi@400 { 463 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 464 reg = <0x400 0x200>; 465 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 467 clock-names = "spi_clk"; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 471 <&dma1 AT91_XDMAC_DT_PERID(5)>; 472 dma-names = "tx", "rx"; 473 atmel,fifo-size = <32>; 474 status = "disabled"; 475 }; 476 477 i2c0: i2c@600 { 478 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 479 reg = <0x600 0x200>; 480 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 atmel,fifo-size = <32>; 485 dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>, 486 <&dma0 AT91_XDMAC_DT_PERID(5)>; 487 dma-names = "tx", "rx"; 488 status = "disabled"; 489 }; 490 }; 491 492 flx1: flexcom@e1824000 { 493 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 494 reg = <0xe1824000 0x200>; 495 ranges = <0x0 0xe1824000 0x800>; 496 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 497 #address-cells = <1>; 498 #size-cells = <1>; 499 status = "disabled"; 500 501 uart1: serial@200 { 502 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 503 reg = <0x200 0x200>; 504 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 506 clock-names = "usart"; 507 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 508 <&dma0 AT91_XDMAC_DT_PERID(7)>; 509 dma-names = "tx", "rx"; 510 atmel,use-dma-rx; 511 atmel,use-dma-tx; 512 atmel,fifo-size = <32>; 513 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 514 status = "disabled"; 515 }; 516 517 spi1: spi@400 { 518 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 519 reg = <0x400 0x200>; 520 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 522 clock-names = "spi_clk"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 526 <&dma0 AT91_XDMAC_DT_PERID(7)>; 527 dma-names = "tx", "rx"; 528 atmel,fifo-size = <32>; 529 status = "disabled"; 530 }; 531 532 i2c1: i2c@600 { 533 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 534 reg = <0x600 0x200>; 535 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 540 <&dma0 AT91_XDMAC_DT_PERID(7)>; 541 dma-names = "tx", "rx"; 542 atmel,fifo-size = <32>; 543 status = "disabled"; 544 }; 545 }; 546 547 flx2: flexcom@e1828000 { 548 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 549 reg = <0xe1828000 0x200>; 550 ranges = <0x0 0xe1828000 0x800>; 551 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 status = "disabled"; 555 556 uart2: serial@200 { 557 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 558 reg = <0x200 0x200>; 559 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 561 clock-names = "usart"; 562 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 563 <&dma1 AT91_XDMAC_DT_PERID(9)>; 564 dma-names = "tx", "rx"; 565 atmel,use-dma-rx; 566 atmel,use-dma-tx; 567 atmel,fifo-size = <32>; 568 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 569 status = "disabled"; 570 }; 571 572 spi2: spi@400 { 573 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 574 reg = <0x400 0x200>; 575 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 577 clock-names = "spi_clk"; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 581 <&dma1 AT91_XDMAC_DT_PERID(9)>; 582 dma-names = "tx", "rx"; 583 atmel,fifo-size = <32>; 584 status = "disabled"; 585 }; 586 587 i2c2: i2c@600 { 588 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 589 reg = <0x600 0x200>; 590 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 595 <&dma1 AT91_XDMAC_DT_PERID(9)>; 596 dma-names = "tx", "rx"; 597 atmel,fifo-size = <32>; 598 status = "disabled"; 599 }; 600 }; 601 602 flx3: flexcom@e182c000 { 603 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 604 reg = <0xe182c000 0x200>; 605 ranges = <0x0 0xe182c000 0x800>; 606 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 607 #address-cells = <1>; 608 #size-cells = <1>; 609 status = "disabled"; 610 611 uart3: serial@200 { 612 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 613 reg = <0x200 0x200>; 614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 616 clock-names = "usart"; 617 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 618 <&dma0 AT91_XDMAC_DT_PERID(11)>; 619 dma-names = "tx", "rx"; 620 atmel,use-dma-rx; 621 atmel,use-dma-tx; 622 atmel,fifo-size = <32>; 623 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 624 status = "disabled"; 625 }; 626 627 spi3: spi@400 { 628 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 629 reg = <0x400 0x200>; 630 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 632 clock-names = "spi_clk"; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 636 <&dma0 AT91_XDMAC_DT_PERID(11)>; 637 dma-names = "tx", "rx"; 638 atmel,fifo-size = <32>; 639 status = "disabled"; 640 }; 641 642 i2c3: i2c@600 { 643 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 644 reg = <0x600 0x200>; 645 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 650 <&dma0 AT91_XDMAC_DT_PERID(11)>; 651 dma-names = "tx", "rx"; 652 atmel,fifo-size = <32>; 653 status = "disabled"; 654 }; 655 656 }; 657 658 flx4: flexcom@e2018000 { 659 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 660 reg = <0xe2018000 0x200>; 661 ranges = <0x0 0xe2018000 0x800>; 662 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 663 #address-cells = <1>; 664 #size-cells = <1>; 665 status = "disabled"; 666 667 uart4: serial@200 { 668 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 669 reg = <0x200 0x200>; 670 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 672 clock-names = "usart"; 673 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 674 <&dma1 AT91_XDMAC_DT_PERID(13)>; 675 dma-names = "tx", "rx"; 676 atmel,use-dma-rx; 677 atmel,use-dma-tx; 678 atmel,fifo-size = <32>; 679 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 680 status = "disabled"; 681 }; 682 683 spi4: spi@400 { 684 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 685 reg = <0x400 0x200>; 686 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 688 clock-names = "spi_clk"; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>, 692 <&dma0 AT91_XDMAC_DT_PERID(13)>; 693 dma-names = "tx", "rx"; 694 atmel,fifo-size = <32>; 695 status = "disabled"; 696 }; 697 698 i2c4: i2c@600 { 699 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 700 reg = <0x600 0x200>; 701 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 703 #address-cells = <1>; 704 #size-cells = <0>; 705 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 706 <&dma1 AT91_XDMAC_DT_PERID(13)>; 707 dma-names = "tx", "rx"; 708 atmel,fifo-size = <32>; 709 status = "disabled"; 710 }; 711 }; 712 713 flx5: flexcom@e201c000 { 714 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 715 reg = <0xe201c000 0x200>; 716 ranges = <0x0 0xe201c000 0x800>; 717 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 718 #address-cells = <1>; 719 #size-cells = <1>; 720 status = "disabled"; 721 722 uart5: serial@200 { 723 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 724 reg = <0x200 0x200>; 725 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 727 clock-names = "usart"; 728 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 729 <&dma0 AT91_XDMAC_DT_PERID(15)>; 730 dma-names = "tx", "rx"; 731 atmel,use-dma-rx; 732 atmel,use-dma-tx; 733 atmel,fifo-size = <32>; 734 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 735 status = "disabled"; 736 }; 737 738 spi5: spi@400 { 739 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 740 reg = <0x400 0x200>; 741 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 743 clock-names = "spi_clk"; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 747 <&dma0 AT91_XDMAC_DT_PERID(15)>; 748 dma-names = "tx", "rx"; 749 atmel,fifo-size = <32>; 750 status = "disabled"; 751 }; 752 753 i2c5: i2c@600 { 754 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 755 reg = <0x600 0x200>; 756 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 761 <&dma0 AT91_XDMAC_DT_PERID(15)>; 762 dma-names = "tx", "rx"; 763 atmel,fifo-size = <32>; 764 status = "disabled"; 765 }; 766 }; 767 768 flx6: flexcom@e2020000 { 769 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 770 reg = <0xe2020000 0x200>; 771 ranges = <0x0 0xe2020000 0x800>; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 775 status = "disabled"; 776 777 uart6: serial@200 { 778 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 779 reg = <0x200 0x200>; 780 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 782 clock-names = "usart"; 783 dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, 784 <&dma1 AT91_XDMAC_DT_PERID(17)>; 785 dma-names = "tx", "rx"; 786 atmel,use-dma-rx; 787 atmel,use-dma-tx; 788 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 789 atmel,fifo-size = <32>; 790 status = "disabled"; 791 }; 792 793 spi6: spi@400 { 794 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 795 reg = <0x400 0x200>; 796 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 798 clock-names = "spi_clk"; 799 #address-cells = <1>; 800 #size-cells = <0>; 801 dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, 802 <&dma1 AT91_XDMAC_DT_PERID(17)>; 803 dma-names = "tx", "rx"; 804 atmel,fifo-size = <32>; 805 status = "disabled"; 806 }; 807 808 i2c6: i2c@600 { 809 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 810 reg = <0x600 0x200>; 811 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, 816 <&dma1 AT91_XDMAC_DT_PERID(17)>; 817 dma-names = "tx", "rx"; 818 atmel,fifo-size = <32>; 819 status = "disabled"; 820 }; 821 }; 822 823 flx7: flexcom@e2024000 { 824 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 825 reg = <0xe2024000 0x200>; 826 ranges = <0x0 0xe2024000 0x800>; 827 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 828 #address-cells = <1>; 829 #size-cells = <1>; 830 status = "disabled"; 831 832 uart7: serial@200 { 833 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 834 reg = <0x200 0x200>; 835 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 837 clock-names = "usart"; 838 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 839 <&dma1 AT91_XDMAC_DT_PERID(19)>; 840 dma-names = "tx", "rx"; 841 atmel,use-dma-rx; 842 atmel,use-dma-tx; 843 atmel,fifo-size = <32>; 844 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 845 status = "disabled"; 846 }; 847 848 spi7: spi@400 { 849 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 850 reg = <0x400 0x200>; 851 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 852 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 853 clock-names = "spi_clk"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 857 <&dma1 AT91_XDMAC_DT_PERID(19)>; 858 dma-names = "tx", "rx"; 859 atmel,fifo-size = <32>; 860 status = "disabled"; 861 }; 862 863 i2c7: i2c@600 { 864 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 865 reg = <0x600 0x200>; 866 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 871 <&dma1 AT91_XDMAC_DT_PERID(19)>; 872 dma-names = "tx", "rx"; 873 atmel,fifo-size = <32>; 874 status = "disabled"; 875 }; 876 }; 877 878 flx8: flexcom@e281c000 { 879 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 880 reg = <0xe281c000 0x200>; 881 ranges = <0x0 0xe281c000 0x800>; 882 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 883 #address-cells = <1>; 884 #size-cells = <1>; 885 status = "disabled"; 886 887 uart8: serial@200 { 888 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 889 reg = <0x200 0x200>; 890 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 892 clock-names = "usart"; 893 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 894 <&dma0 AT91_XDMAC_DT_PERID(21)>; 895 dma-names = "tx", "rx"; 896 atmel,use-dma-rx; 897 atmel,use-dma-tx; 898 atmel,fifo-size = <32>; 899 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 900 status = "disabled"; 901 }; 902 903 spi8: spi@400 { 904 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 905 reg = <0x400 0x200>; 906 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 907 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 908 clock-names = "spi_clk"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 912 <&dma0 AT91_XDMAC_DT_PERID(21)>; 913 dma-names = "tx", "rx"; 914 atmel,fifo-size = <32>; 915 status = "disabled"; 916 }; 917 918 i2c8: i2c@600 { 919 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 920 reg = <0x600 0x200>; 921 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 926 <&dma0 AT91_XDMAC_DT_PERID(21)>; 927 dma-names = "tx", "rx"; 928 atmel,fifo-size = <32>; 929 status = "disabled"; 930 }; 931 }; 932 933 flx9: flexcom@e2820000 { 934 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 935 reg = <0xe2820000 0x200>; 936 ranges = <0x0 0xe2820000 0x800>; 937 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 938 #address-cells = <1>; 939 #size-cells = <1>; 940 status = "disabled"; 941 942 uart9: serial@200 { 943 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 944 reg = <0x200 0x200>; 945 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 947 clock-names = "usart"; 948 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 949 <&dma0 AT91_XDMAC_DT_PERID(23)>; 950 dma-names = "tx", "rx"; 951 atmel,use-dma-rx; 952 atmel,use-dma-tx; 953 atmel,fifo-size = <32>; 954 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 955 status = "disabled"; 956 }; 957 958 spi9: spi@400 { 959 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 960 reg = <0x400 0x200>; 961 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 963 clock-names = "spi_clk"; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 967 <&dma0 AT91_XDMAC_DT_PERID(23)>; 968 dma-names = "tx", "rx"; 969 atmel,fifo-size = <32>; 970 status = "disabled"; 971 }; 972 973 i2c9: i2c@600 { 974 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 975 reg = <0x600 0x200>; 976 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 978 #address-cells = <1>; 979 #size-cells = <0>; 980 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 981 <&dma0 AT91_XDMAC_DT_PERID(23)>; 982 dma-names = "tx", "rx"; 983 atmel,fifo-size = <32>; 984 status = "disabled"; 985 }; 986 }; 987 988 flx10: flexcom@e2824000 { 989 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 990 reg = <0xe2824000 0x200>; 991 ranges = <0x0 0xe2824000 0x800>; 992 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 993 #address-cells = <1>; 994 #size-cells = <1>; 995 status = "disabled"; 996 997 uart10: serial@200 { 998 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 999 reg = <0x200 0x200>; 1000 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1002 clock-names = "usart"; 1003 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 1004 <&dma0 AT91_XDMAC_DT_PERID(25)>; 1005 dma-names = "tx", "rx"; 1006 atmel,use-dma-rx; 1007 atmel,use-dma-tx; 1008 atmel,fifo-size = <32>; 1009 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1010 status = "disabled"; 1011 }; 1012 1013 spi10: spi@400 { 1014 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 1015 reg = <0x400 0x200>; 1016 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1018 clock-names = "spi_clk"; 1019 #address-cells = <1>; 1020 #size-cells = <0>; 1021 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 1022 <&dma0 AT91_XDMAC_DT_PERID(25)>; 1023 dma-names = "tx", "rx"; 1024 atmel,fifo-size = <32>; 1025 status = "disabled"; 1026 }; 1027 1028 i2c10: i2c@600 { 1029 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 1030 reg = <0x600 0x200>; 1031 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 atmel,fifo-size = <32>; 1036 status = "disabled"; 1037 }; 1038 }; 1039 1040 uddrc: uddrc@e3800000 { 1041 compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; 1042 reg = <0xe3800000 0x4000>; 1043 }; 1044 1045 ddr3phy: ddr3phy@e3804000 { 1046 compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; 1047 reg = <0xe3804000 0x1000>; 1048 }; 1049 1050 gic: interrupt-controller@e8c11000 { 1051 compatible = "arm,cortex-a7-gic"; 1052 reg = <0xe8c11000 0x1000>, 1053 <0xe8c12000 0x2000>; 1054 #interrupt-cells = <3>; 1055 #address-cells = <0>; 1056 interrupt-controller; 1057 }; 1058 }; 1059}; 1060