1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC 4 * 5 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Ryan Wanner <Ryan.Wanner@microchip.com> 8 * 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/mfd/at91-usart.h> 17 18/ { 19 model = "Microchip SAMA7D65 family SoC"; 20 compatible = "microchip,sama7d65"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 }; 36 }; 37 38 clocks { 39 main_xtal: clock-mainxtal { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 }; 43 44 slow_xtal: clock-slowxtal { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 ns_sram: sram@100000 { 51 compatible = "mmio-sram"; 52 reg = <0x100000 0x20000>; 53 ranges; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 }; 57 58 soc { 59 compatible = "simple-bus"; 60 ranges; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 64 securam: sram@e0000800 { 65 compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; 66 reg = <0xe0000800 0x4000>; 67 ranges = <0 0xe0000800 0x4000>; 68 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 no-memory-wc; 72 }; 73 74 secumod: security-module@e0004000 { 75 compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; 76 reg = <0xe0004000 0x4000>; 77 gpio-controller; 78 #gpio-cells = <2>; 79 }; 80 81 sfrbu: sfr@e0008000 { 82 compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 83 reg = <0xe0008000 0x20>; 84 }; 85 86 pioa: pinctrl@e0014000 { 87 compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; 88 reg = <0xe0014000 0x800>; 89 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 90 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 91 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 92 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 93 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 95 interrupt-controller; 96 #interrupt-cells = <2>; 97 gpio-controller; 98 #gpio-cells = <2>; 99 }; 100 101 pmc: clock-controller@e0018000 { 102 compatible = "microchip,sama7d65-pmc", "syscon"; 103 reg = <0xe0018000 0x200>; 104 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 105 #clock-cells = <2>; 106 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 107 clock-names = "td_slck", "md_slck", "main_xtal"; 108 }; 109 110 ps_wdt: watchdog@e001d000 { 111 compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; 112 reg = <0xe001d000 0x30>; 113 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&clk32k 0>; 115 }; 116 117 reset_controller: reset-controller@e001d100 { 118 compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; 119 reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; 120 #reset-cells = <1>; 121 clocks = <&clk32k 0>; 122 }; 123 124 shdwc: poweroff@e001d200 { 125 compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; 126 reg = <0xe001d200 0x20>; 127 clocks = <&clk32k 0>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 atmel,wakeup-rtc-timer; 131 atmel,wakeup-rtt-timer; 132 status = "disabled"; 133 }; 134 135 rtt: rtc@e001d300 { 136 compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; 137 reg = <0xe001d300 0x30>; 138 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&clk32k 0>; 140 }; 141 142 clk32k: clock-controller@e001d500 { 143 compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; 144 reg = <0xe001d500 0x4>; 145 clocks = <&slow_xtal>; 146 #clock-cells = <1>; 147 }; 148 149 gpbr: syscon@e001d700 { 150 compatible = "microchip,sama7d65-gpbr", "syscon"; 151 reg = <0xe001d700 0x48>; 152 }; 153 154 rtc: rtc@e001d800 { 155 compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; 156 reg = <0xe001d800 0x30>; 157 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 158 clocks = <&clk32k 1>; 159 }; 160 161 chipid@e0020000 { 162 compatible = "microchip,sama7d65-chipid"; 163 reg = <0xe0020000 0x8>; 164 }; 165 166 dma2: dma-controller@e1200000 { 167 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 168 reg = <0xe1200000 0x1000>; 169 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 170 #dma-cells = <1>; 171 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 172 clock-names = "dma_clk"; 173 dma-requests = <0>; 174 status = "disabled"; 175 }; 176 177 sdmmc1: mmc@e1208000 { 178 compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; 179 reg = <0xe1208000 0x400>; 180 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; 182 clock-names = "hclock", "multclk"; 183 assigned-clocks = <&pmc PMC_TYPE_GCK 76>; 184 assigned-clock-rates = <200000000>; 185 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; 186 status = "disabled"; 187 }; 188 189 dma0: dma-controller@e1610000 { 190 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 191 reg = <0xe1610000 0x1000>; 192 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 193 #dma-cells = <1>; 194 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 195 clock-names = "dma_clk"; 196 status = "disabled"; 197 }; 198 199 dma1: dma-controller@e1614000 { 200 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 201 reg = <0xe1614000 0x1000>; 202 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 203 #dma-cells = <1>; 204 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 205 clock-names = "dma_clk"; 206 status = "disabled"; 207 }; 208 209 gmac0: ethernet@e1618000 { 210 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 211 reg = <0xe1618000 0x2000>; 212 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 219 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 220 assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 221 assigned-clock-rates = <125000000>, <200000000>; 222 status = "disabled"; 223 }; 224 225 gmac1: ethernet@e161c000 { 226 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 227 reg = <0xe161c000 0x2000>; 228 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 235 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 236 assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 237 assigned-clock-rates = <125000000>, <200000000>; 238 status = "disabled"; 239 }; 240 241 pit64b0: timer@e1800000 { 242 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 243 reg = <0xe1800000 0x100>; 244 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 246 clock-names = "pclk", "gclk"; 247 }; 248 249 pit64b1: timer@e1804000 { 250 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 251 reg = <0xe1804000 0x100>; 252 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; 254 clock-names = "pclk", "gclk"; 255 }; 256 257 flx0: flexcom@e1820000 { 258 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 259 reg = <0xe1820000 0x200>; 260 ranges = <0x0 0xe1820000 0x800>; 261 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 status = "disabled"; 265 266 uart0: serial@200 { 267 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 268 reg = <0x200 0x200>; 269 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 271 clock-names = "usart"; 272 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 273 <&dma1 AT91_XDMAC_DT_PERID(5)>; 274 dma-names = "tx", "rx"; 275 atmel,use-dma-rx; 276 atmel,use-dma-tx; 277 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 278 status = "disabled"; 279 }; 280 281 i2c0: i2c@600 { 282 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 283 reg = <0x600 0x200>; 284 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 286 #address-cells = <1>; 287 #size-cells = <0>; 288 atmel,fifo-size = <32>; 289 dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>, 290 <&dma0 AT91_XDMAC_DT_PERID(5)>; 291 dma-names = "tx", "rx"; 292 status = "disabled"; 293 }; 294 }; 295 296 flx1: flexcom@e1824000 { 297 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 298 reg = <0xe1824000 0x200>; 299 ranges = <0x0 0xe1824000 0x800>; 300 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 301 #address-cells = <1>; 302 #size-cells = <1>; 303 status = "disabled"; 304 305 spi1: spi@400 { 306 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 307 reg = <0x400 0x200>; 308 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 310 clock-names = "spi_clk"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 314 <&dma0 AT91_XDMAC_DT_PERID(7)>; 315 dma-names = "tx", "rx"; 316 atmel,fifo-size = <32>; 317 status = "disabled"; 318 }; 319 320 i2c1: i2c@600 { 321 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 322 reg = <0x600 0x200>; 323 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 328 <&dma0 AT91_XDMAC_DT_PERID(7)>; 329 dma-names = "tx", "rx"; 330 atmel,fifo-size = <32>; 331 status = "disabled"; 332 }; 333 }; 334 335 flx2: flexcom@e1828000 { 336 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 337 reg = <0xe1828000 0x200>; 338 ranges = <0x0 0xe1828000 0x800>; 339 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 340 #address-cells = <1>; 341 #size-cells = <1>; 342 status = "disabled"; 343 344 uart2: serial@200 { 345 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 346 reg = <0x200 0x200>; 347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 348 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 349 clock-names = "usart"; 350 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 351 <&dma1 AT91_XDMAC_DT_PERID(9)>; 352 dma-names = "tx", "rx"; 353 atmel,use-dma-rx; 354 atmel,use-dma-tx; 355 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 356 status = "disabled"; 357 }; 358 }; 359 360 flx3: flexcom@e182c000 { 361 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 362 reg = <0xe182c000 0x200>; 363 ranges = <0x0 0xe182c000 0x800>; 364 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 status = "disabled"; 368 369 i2c3: i2c@600 { 370 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 371 reg = <0x600 0x200>; 372 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 377 <&dma0 AT91_XDMAC_DT_PERID(11)>; 378 dma-names = "tx", "rx"; 379 atmel,fifo-size = <32>; 380 status = "disabled"; 381 }; 382 383 }; 384 385 flx4: flexcom@e2018000 { 386 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 387 reg = <0xe2018000 0x200>; 388 ranges = <0x0 0xe2018000 0x800>; 389 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 390 #address-cells = <1>; 391 #size-cells = <1>; 392 status = "disabled"; 393 394 uart4: serial@200 { 395 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 396 reg = <0x200 0x200>; 397 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 399 clock-names = "usart"; 400 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 401 <&dma1 AT91_XDMAC_DT_PERID(13)>; 402 dma-names = "tx", "rx"; 403 atmel,use-dma-rx; 404 atmel,use-dma-tx; 405 atmel,fifo-size = <16>; 406 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 407 status = "disabled"; 408 }; 409 410 spi4: spi@400 { 411 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 412 reg = <0x400 0x200>; 413 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 415 clock-names = "spi_clk"; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>, 419 <&dma0 AT91_XDMAC_DT_PERID(13)>; 420 dma-names = "tx", "rx"; 421 atmel,fifo-size = <32>; 422 status = "disabled"; 423 }; 424 }; 425 426 flx5: flexcom@e201c000 { 427 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 428 reg = <0xe201c000 0x200>; 429 ranges = <0x0 0xe201c000 0x800>; 430 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 431 #address-cells = <1>; 432 #size-cells = <1>; 433 status = "disabled"; 434 435 i2c5: i2c@600 { 436 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 437 reg = <0x600 0x200>; 438 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 443 <&dma0 AT91_XDMAC_DT_PERID(15)>; 444 dma-names = "tx", "rx"; 445 atmel,fifo-size = <32>; 446 status = "disabled"; 447 }; 448 }; 449 450 flx6: flexcom@e2020000 { 451 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 452 reg = <0xe2020000 0x200>; 453 ranges = <0x0 0xe2020000 0x800>; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 457 status = "disabled"; 458 459 uart6: serial@200 { 460 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 461 reg = <0x200 0x200>; 462 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 463 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 464 clock-names = "usart"; 465 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 466 atmel,fifo-size = <16>; 467 status = "disabled"; 468 }; 469 }; 470 471 flx7: flexcom@e2024000 { 472 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 473 reg = <0xe2024000 0x200>; 474 ranges = <0x0 0xe2024000 0x800>; 475 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 status = "disabled"; 479 480 uart7: serial@200 { 481 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 482 reg = <0x200 0x200>; 483 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 485 clock-names = "usart"; 486 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 487 <&dma1 AT91_XDMAC_DT_PERID(19)>; 488 dma-names = "tx", "rx"; 489 atmel,use-dma-rx; 490 atmel,use-dma-tx; 491 atmel,fifo-size = <16>; 492 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 493 status = "disabled"; 494 }; 495 }; 496 497 flx8: flexcom@e281c000 { 498 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 499 reg = <0xe281c000 0x200>; 500 ranges = <0x0 0xe281c000 0x800>; 501 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 502 #address-cells = <1>; 503 #size-cells = <1>; 504 status = "disabled"; 505 506 i2c8: i2c@600 { 507 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 508 reg = <0x600 0x200>; 509 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 514 <&dma0 AT91_XDMAC_DT_PERID(21)>; 515 dma-names = "tx", "rx"; 516 atmel,fifo-size = <32>; 517 status = "disabled"; 518 }; 519 }; 520 521 flx9: flexcom@e2820000 { 522 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 523 reg = <0xe2820000 0x200>; 524 ranges = <0x0 0xe281c000 0x800>; 525 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 526 #address-cells = <1>; 527 #size-cells = <1>; 528 status = "disabled"; 529 530 i2c9: i2c@600 { 531 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 532 reg = <0x600 0x200>; 533 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 538 <&dma0 AT91_XDMAC_DT_PERID(23)>; 539 dma-names = "tx", "rx"; 540 atmel,fifo-size = <32>; 541 status = "disabled"; 542 }; 543 }; 544 545 flx10: flexcom@e2824000 { 546 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 547 reg = <0xe2824000 0x200>; 548 ranges = <0x0 0xe2824000 0x800>; 549 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 status = "disabled"; 553 554 i2c10: i2c@600 { 555 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 556 reg = <0x600 0x200>; 557 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 atmel,fifo-size = <32>; 562 status = "disabled"; 563 }; 564 }; 565 566 uddrc: uddrc@e3800000 { 567 compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; 568 reg = <0xe3800000 0x4000>; 569 }; 570 571 ddr3phy: ddr3phy@e3804000 { 572 compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; 573 reg = <0xe3804000 0x1000>; 574 }; 575 576 gic: interrupt-controller@e8c11000 { 577 compatible = "arm,cortex-a7-gic"; 578 reg = <0xe8c11000 0x1000>, 579 <0xe8c12000 0x2000>; 580 #interrupt-cells = <3>; 581 #address-cells = <0>; 582 interrupt-controller; 583 }; 584 }; 585}; 586