1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC 4 * 5 * Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Ryan Wanner <Ryan.Wanner@microchip.com> 8 * 9 */ 10 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/dma/at91.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/interrupt-controller/irq.h> 16#include <dt-bindings/mfd/at91-usart.h> 17 18/ { 19 model = "Microchip SAMA7D65 family SoC"; 20 compatible = "microchip,sama7d65"; 21 #address-cells = <1>; 22 #size-cells = <1>; 23 interrupt-parent = <&gic>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 device_type = "cpu"; 33 clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; 34 clock-names = "cpu"; 35 d-cache-size = <0x8000>; // L1, 32 KB 36 i-cache-size = <0x8000>; // L1, 32 KB 37 next-level-cache = <&L2>; 38 39 L2: l2-cache { 40 compatible = "cache"; 41 cache-level = <2>; 42 cache-size = <0x40000>; // L2, 256 KB 43 cache-unified; 44 }; 45 }; 46 }; 47 48 clocks { 49 main_xtal: clock-mainxtal { 50 compatible = "fixed-clock"; 51 clock-output-names = "main_xtal"; 52 #clock-cells = <0>; 53 }; 54 55 slow_xtal: clock-slowxtal { 56 compatible = "fixed-clock"; 57 clock-output-names = "slow_xtal"; 58 #clock-cells = <0>; 59 }; 60 }; 61 62 ns_sram: sram@100000 { 63 compatible = "mmio-sram"; 64 reg = <0x100000 0x20000>; 65 ranges; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 }; 69 70 soc { 71 compatible = "simple-bus"; 72 ranges; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 76 securam: sram@e0000800 { 77 compatible = "microchip,sama7d65-securam", "atmel,sama5d2-securam", "mmio-sram"; 78 reg = <0xe0000800 0x4000>; 79 ranges = <0 0xe0000800 0x4000>; 80 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 no-memory-wc; 84 }; 85 86 secumod: security-module@e0004000 { 87 compatible = "microchip,sama7d65-secumod", "atmel,sama5d2-secumod", "syscon"; 88 reg = <0xe0004000 0x4000>; 89 gpio-controller; 90 #gpio-cells = <2>; 91 }; 92 93 sfrbu: sfr@e0008000 { 94 compatible = "microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; 95 reg = <0xe0008000 0x20>; 96 }; 97 98 pioa: pinctrl@e0014000 { 99 compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; 100 reg = <0xe0014000 0x800>; 101 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 107 interrupt-controller; 108 #interrupt-cells = <2>; 109 gpio-controller; 110 #gpio-cells = <2>; 111 }; 112 113 pmc: clock-controller@e0018000 { 114 compatible = "microchip,sama7d65-pmc", "syscon"; 115 reg = <0xe0018000 0x200>; 116 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 117 #clock-cells = <2>; 118 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 119 clock-names = "td_slck", "md_slck", "main_xtal"; 120 }; 121 122 ps_wdt: watchdog@e001d000 { 123 compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; 124 reg = <0xe001d000 0x30>; 125 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&clk32k 0>; 127 }; 128 129 reset_controller: reset-controller@e001d100 { 130 compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; 131 reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; 132 #reset-cells = <1>; 133 clocks = <&clk32k 0>; 134 }; 135 136 shdwc: poweroff@e001d200 { 137 compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; 138 reg = <0xe001d200 0x20>; 139 clocks = <&clk32k 0>; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 atmel,wakeup-rtc-timer; 143 atmel,wakeup-rtt-timer; 144 status = "disabled"; 145 }; 146 147 rtt: rtc@e001d300 { 148 compatible = "microchip,sama7d65-rtt", "atmel,at91sam9260-rtt"; 149 reg = <0xe001d300 0x30>; 150 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&clk32k 0>; 152 }; 153 154 clk32k: clock-controller@e001d500 { 155 compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; 156 reg = <0xe001d500 0x4>; 157 clocks = <&slow_xtal>; 158 #clock-cells = <1>; 159 }; 160 161 gpbr: syscon@e001d700 { 162 compatible = "microchip,sama7d65-gpbr", "syscon"; 163 reg = <0xe001d700 0x48>; 164 }; 165 166 rtc: rtc@e001d800 { 167 compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; 168 reg = <0xe001d800 0x30>; 169 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&clk32k 1>; 171 }; 172 173 chipid@e0020000 { 174 compatible = "microchip,sama7d65-chipid"; 175 reg = <0xe0020000 0x8>; 176 }; 177 178 can0: can@e0828000 { 179 compatible = "bosch,m_can"; 180 reg = <0xe0828000 0x200>, <0x100000 0x7800>; 181 reg-names = "m_can", "message_ram"; 182 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-names = "int0", "int1"; 185 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 186 clock-names = "hclk", "cclk"; 187 assigned-clocks = <&pmc PMC_TYPE_GCK 58>; 188 assigned-clock-rates = <40000000>; 189 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 190 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 191 status = "disabled"; 192 }; 193 194 can1: can@e082c000 { 195 compatible = "bosch,m_can"; 196 reg = <0xe082c000 0x200>, <0x100000 0xbc00>; 197 reg-names = "m_can", "message_ram"; 198 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 200 interrupt-names = "int0", "int1"; 201 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 202 clock-names = "hclk", "cclk"; 203 assigned-clocks = <&pmc PMC_TYPE_GCK 59>; 204 assigned-clock-rates = <40000000>; 205 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 206 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 207 status = "disabled"; 208 }; 209 210 can2: can@e0830000 { 211 compatible = "bosch,m_can"; 212 reg = <0xe0830000 0x200>, <0x100000 0x10000>; 213 reg-names = "m_can", "message_ram"; 214 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 216 interrupt-names = "int0", "int1"; 217 clocks = <&pmc PMC_TYPE_PERIPHERAL 60>, <&pmc PMC_TYPE_GCK 60>; 218 clock-names = "hclk", "cclk"; 219 assigned-clocks = <&pmc PMC_TYPE_GCK 60>; 220 assigned-clock-rates = <40000000>; 221 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 222 bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>; 223 status = "disabled"; 224 }; 225 226 can3: can@e0834000 { 227 compatible = "bosch,m_can"; 228 reg = <0xe0834000 0x200>, <0x110000 0x4400>; 229 reg-names = "m_can", "message_ram"; 230 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-names = "int0", "int1"; 233 clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; 234 clock-names = "hclk", "cclk"; 235 assigned-clocks = <&pmc PMC_TYPE_GCK 61>; 236 assigned-clock-rates = <40000000>; 237 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 238 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 239 status = "disabled"; 240 }; 241 242 can4: can@e0838000 { 243 compatible = "bosch,m_can"; 244 reg = <0xe0838000 0x200>, <0x110000 0x8800>; 245 reg-names = "m_can", "message_ram"; 246 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-names = "int0", "int1"; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; 250 clock-names = "hclk", "cclk"; 251 assigned-clocks = <&pmc PMC_TYPE_GCK 62>; 252 assigned-clock-rates = <40000000>; 253 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 254 bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>; 255 status = "disabled"; 256 }; 257 258 dma2: dma-controller@e1200000 { 259 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 260 reg = <0xe1200000 0x1000>; 261 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 262 #dma-cells = <1>; 263 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 264 clock-names = "dma_clk"; 265 dma-requests = <0>; 266 status = "disabled"; 267 }; 268 269 sdmmc1: mmc@e1208000 { 270 compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; 271 reg = <0xe1208000 0x400>; 272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; 274 clock-names = "hclock", "multclk"; 275 assigned-clocks = <&pmc PMC_TYPE_GCK 76>; 276 assigned-clock-rates = <200000000>; 277 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; 278 status = "disabled"; 279 }; 280 281 aes: crypto@e1600000 { 282 compatible = "microchip,sama7d65-aes", "atmel,at91sam9g46-aes"; 283 reg = <0xe1600000 0x100>; 284 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 286 clock-names = "aes_clk"; 287 dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>, 288 <&dma0 AT91_XDMAC_DT_PERID(2)>; 289 dma-names = "tx", "rx"; 290 }; 291 292 sha: crypto@e1604000 { 293 compatible = "microchip,sama7d65-sha", "atmel,at91sam9g46-sha"; 294 reg = <0xe1604000 0x100>; 295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 78>; 297 clock-names = "sha_clk"; 298 dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>; 299 dma-names = "tx"; 300 }; 301 302 tdes: crypto@e1608000 { 303 compatible = "microchip,sama7d65-tdes", "atmel,at91sam9g46-tdes"; 304 reg = <0xe1608000 0x100>; 305 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&pmc PMC_TYPE_PERIPHERAL 91>; 307 clock-names = "tdes_clk"; 308 dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>, 309 <&dma0 AT91_XDMAC_DT_PERID(53)>; 310 dma-names = "tx", "rx"; 311 }; 312 313 trng: rng@e160c000 { 314 compatible = "microchip,sama7d65-trng", "microchip,sam9x60-trng"; 315 reg = <0xe160c000 0x100>; 316 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&pmc PMC_TYPE_PERIPHERAL 92>; 318 }; 319 320 dma0: dma-controller@e1610000 { 321 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 322 reg = <0xe1610000 0x1000>; 323 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 324 #dma-cells = <1>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 326 clock-names = "dma_clk"; 327 status = "disabled"; 328 }; 329 330 dma1: dma-controller@e1614000 { 331 compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; 332 reg = <0xe1614000 0x1000>; 333 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 334 #dma-cells = <1>; 335 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 336 clock-names = "dma_clk"; 337 status = "disabled"; 338 }; 339 340 gmac0: ethernet@e1618000 { 341 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 342 reg = <0xe1618000 0x2000>; 343 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 350 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 351 assigned-clocks = <&pmc PMC_TYPE_GCK 46>, <&pmc PMC_TYPE_GCK 49>; 352 assigned-clock-rates = <125000000>, <200000000>; 353 status = "disabled"; 354 }; 355 356 gmac1: ethernet@e161c000 { 357 compatible = "microchip,sama7d65-gem", "microchip,sama7g5-gem"; 358 reg = <0xe161c000 0x2000>; 359 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_PERIPHERAL 47>,<&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 366 clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; 367 assigned-clocks = <&pmc PMC_TYPE_GCK 47>, <&pmc PMC_TYPE_GCK 50>; 368 assigned-clock-rates = <125000000>, <200000000>; 369 status = "disabled"; 370 }; 371 372 pit64b0: timer@e1800000 { 373 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 374 reg = <0xe1800000 0x100>; 375 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; 377 clock-names = "pclk", "gclk"; 378 }; 379 380 pit64b1: timer@e1804000 { 381 compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; 382 reg = <0xe1804000 0x100>; 383 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 384 clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; 385 clock-names = "pclk", "gclk"; 386 }; 387 388 pwm: pwm@e1818000 { 389 compatible = "microchip,sama7d65-pwm", "atmel,sama5d2-pwm"; 390 reg = <0xe1818000 0x500>; 391 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 392 clocks = <&pmc PMC_TYPE_PERIPHERAL 72>; 393 #pwm-cells = <3>; 394 status = "disabled"; 395 }; 396 397 flx0: flexcom@e1820000 { 398 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 399 reg = <0xe1820000 0x200>; 400 ranges = <0x0 0xe1820000 0x800>; 401 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 402 #address-cells = <1>; 403 #size-cells = <1>; 404 status = "disabled"; 405 406 uart0: serial@200 { 407 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 408 reg = <0x200 0x200>; 409 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 411 clock-names = "usart"; 412 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 413 <&dma1 AT91_XDMAC_DT_PERID(5)>; 414 dma-names = "tx", "rx"; 415 atmel,use-dma-rx; 416 atmel,use-dma-tx; 417 atmel,fifo-size = <32>; 418 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 419 status = "disabled"; 420 }; 421 422 spi0: spi@400 { 423 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 424 reg = <0x400 0x200>; 425 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 426 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 427 clock-names = "spi_clk"; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>, 431 <&dma1 AT91_XDMAC_DT_PERID(5)>; 432 dma-names = "tx", "rx"; 433 atmel,fifo-size = <32>; 434 status = "disabled"; 435 }; 436 437 i2c0: i2c@600 { 438 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 439 reg = <0x600 0x200>; 440 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 441 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 atmel,fifo-size = <32>; 445 dmas = <&dma0 AT91_XDMAC_DT_PERID(6)>, 446 <&dma0 AT91_XDMAC_DT_PERID(5)>; 447 dma-names = "tx", "rx"; 448 status = "disabled"; 449 }; 450 }; 451 452 flx1: flexcom@e1824000 { 453 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 454 reg = <0xe1824000 0x200>; 455 ranges = <0x0 0xe1824000 0x800>; 456 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 status = "disabled"; 460 461 uart1: serial@200 { 462 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 463 reg = <0x200 0x200>; 464 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 466 clock-names = "usart"; 467 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 468 <&dma0 AT91_XDMAC_DT_PERID(7)>; 469 dma-names = "tx", "rx"; 470 atmel,use-dma-rx; 471 atmel,use-dma-tx; 472 atmel,fifo-size = <32>; 473 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 474 status = "disabled"; 475 }; 476 477 spi1: spi@400 { 478 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 479 reg = <0x400 0x200>; 480 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 482 clock-names = "spi_clk"; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 486 <&dma0 AT91_XDMAC_DT_PERID(7)>; 487 dma-names = "tx", "rx"; 488 atmel,fifo-size = <32>; 489 status = "disabled"; 490 }; 491 492 i2c1: i2c@600 { 493 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 494 reg = <0x600 0x200>; 495 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 dmas = <&dma0 AT91_XDMAC_DT_PERID(8)>, 500 <&dma0 AT91_XDMAC_DT_PERID(7)>; 501 dma-names = "tx", "rx"; 502 atmel,fifo-size = <32>; 503 status = "disabled"; 504 }; 505 }; 506 507 flx2: flexcom@e1828000 { 508 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 509 reg = <0xe1828000 0x200>; 510 ranges = <0x0 0xe1828000 0x800>; 511 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 512 #address-cells = <1>; 513 #size-cells = <1>; 514 status = "disabled"; 515 516 uart2: serial@200 { 517 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 518 reg = <0x200 0x200>; 519 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 521 clock-names = "usart"; 522 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 523 <&dma1 AT91_XDMAC_DT_PERID(9)>; 524 dma-names = "tx", "rx"; 525 atmel,use-dma-rx; 526 atmel,use-dma-tx; 527 atmel,fifo-size = <32>; 528 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 529 status = "disabled"; 530 }; 531 532 spi2: spi@400 { 533 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 534 reg = <0x400 0x200>; 535 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 537 clock-names = "spi_clk"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 541 <&dma1 AT91_XDMAC_DT_PERID(9)>; 542 dma-names = "tx", "rx"; 543 atmel,fifo-size = <32>; 544 status = "disabled"; 545 }; 546 547 i2c2: i2c@600 { 548 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 549 reg = <0x600 0x200>; 550 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 dmas = <&dma1 AT91_XDMAC_DT_PERID(10)>, 555 <&dma1 AT91_XDMAC_DT_PERID(9)>; 556 dma-names = "tx", "rx"; 557 atmel,fifo-size = <32>; 558 status = "disabled"; 559 }; 560 }; 561 562 flx3: flexcom@e182c000 { 563 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 564 reg = <0xe182c000 0x200>; 565 ranges = <0x0 0xe182c000 0x800>; 566 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 567 #address-cells = <1>; 568 #size-cells = <1>; 569 status = "disabled"; 570 571 uart3: serial@200 { 572 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 573 reg = <0x200 0x200>; 574 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 576 clock-names = "usart"; 577 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 578 <&dma0 AT91_XDMAC_DT_PERID(11)>; 579 dma-names = "tx", "rx"; 580 atmel,use-dma-rx; 581 atmel,use-dma-tx; 582 atmel,fifo-size = <32>; 583 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 584 status = "disabled"; 585 }; 586 587 spi3: spi@400 { 588 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 589 reg = <0x400 0x200>; 590 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 592 clock-names = "spi_clk"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 596 <&dma0 AT91_XDMAC_DT_PERID(11)>; 597 dma-names = "tx", "rx"; 598 atmel,fifo-size = <32>; 599 status = "disabled"; 600 }; 601 602 i2c3: i2c@600 { 603 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 604 reg = <0x600 0x200>; 605 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 dmas = <&dma0 AT91_XDMAC_DT_PERID(12)>, 610 <&dma0 AT91_XDMAC_DT_PERID(11)>; 611 dma-names = "tx", "rx"; 612 atmel,fifo-size = <32>; 613 status = "disabled"; 614 }; 615 616 }; 617 618 flx4: flexcom@e2018000 { 619 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 620 reg = <0xe2018000 0x200>; 621 ranges = <0x0 0xe2018000 0x800>; 622 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 623 #address-cells = <1>; 624 #size-cells = <1>; 625 status = "disabled"; 626 627 uart4: serial@200 { 628 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 629 reg = <0x200 0x200>; 630 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 632 clock-names = "usart"; 633 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 634 <&dma1 AT91_XDMAC_DT_PERID(13)>; 635 dma-names = "tx", "rx"; 636 atmel,use-dma-rx; 637 atmel,use-dma-tx; 638 atmel,fifo-size = <32>; 639 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 640 status = "disabled"; 641 }; 642 643 spi4: spi@400 { 644 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 645 reg = <0x400 0x200>; 646 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 648 clock-names = "spi_clk"; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>, 652 <&dma0 AT91_XDMAC_DT_PERID(13)>; 653 dma-names = "tx", "rx"; 654 atmel,fifo-size = <32>; 655 status = "disabled"; 656 }; 657 658 i2c4: i2c@600 { 659 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 660 reg = <0x600 0x200>; 661 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 662 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>, 666 <&dma1 AT91_XDMAC_DT_PERID(13)>; 667 dma-names = "tx", "rx"; 668 atmel,fifo-size = <32>; 669 status = "disabled"; 670 }; 671 }; 672 673 flx5: flexcom@e201c000 { 674 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 675 reg = <0xe201c000 0x200>; 676 ranges = <0x0 0xe201c000 0x800>; 677 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 678 #address-cells = <1>; 679 #size-cells = <1>; 680 status = "disabled"; 681 682 uart5: serial@200 { 683 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 684 reg = <0x200 0x200>; 685 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 687 clock-names = "usart"; 688 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 689 <&dma0 AT91_XDMAC_DT_PERID(15)>; 690 dma-names = "tx", "rx"; 691 atmel,use-dma-rx; 692 atmel,use-dma-tx; 693 atmel,fifo-size = <32>; 694 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 695 status = "disabled"; 696 }; 697 698 spi5: spi@400 { 699 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 700 reg = <0x400 0x200>; 701 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 703 clock-names = "spi_clk"; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 707 <&dma0 AT91_XDMAC_DT_PERID(15)>; 708 dma-names = "tx", "rx"; 709 atmel,fifo-size = <32>; 710 status = "disabled"; 711 }; 712 713 i2c5: i2c@600 { 714 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 715 reg = <0x600 0x200>; 716 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 dmas = <&dma0 AT91_XDMAC_DT_PERID(16)>, 721 <&dma0 AT91_XDMAC_DT_PERID(15)>; 722 dma-names = "tx", "rx"; 723 atmel,fifo-size = <32>; 724 status = "disabled"; 725 }; 726 }; 727 728 flx6: flexcom@e2020000 { 729 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 730 reg = <0xe2020000 0x200>; 731 ranges = <0x0 0xe2020000 0x800>; 732 #address-cells = <1>; 733 #size-cells = <1>; 734 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 735 status = "disabled"; 736 737 uart6: serial@200 { 738 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 739 reg = <0x200 0x200>; 740 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 742 clock-names = "usart"; 743 dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, 744 <&dma1 AT91_XDMAC_DT_PERID(17)>; 745 dma-names = "tx", "rx"; 746 atmel,use-dma-rx; 747 atmel,use-dma-tx; 748 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 749 atmel,fifo-size = <32>; 750 status = "disabled"; 751 }; 752 753 spi6: spi@400 { 754 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 755 reg = <0x400 0x200>; 756 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 758 clock-names = "spi_clk"; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, 762 <&dma1 AT91_XDMAC_DT_PERID(17)>; 763 dma-names = "tx", "rx"; 764 atmel,fifo-size = <32>; 765 status = "disabled"; 766 }; 767 768 i2c6: i2c@600 { 769 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 770 reg = <0x600 0x200>; 771 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 dmas = <&dma1 AT91_XDMAC_DT_PERID(18)>, 776 <&dma1 AT91_XDMAC_DT_PERID(17)>; 777 dma-names = "tx", "rx"; 778 atmel,fifo-size = <32>; 779 status = "disabled"; 780 }; 781 }; 782 783 flx7: flexcom@e2024000 { 784 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 785 reg = <0xe2024000 0x200>; 786 ranges = <0x0 0xe2024000 0x800>; 787 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 788 #address-cells = <1>; 789 #size-cells = <1>; 790 status = "disabled"; 791 792 uart7: serial@200 { 793 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 794 reg = <0x200 0x200>; 795 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 797 clock-names = "usart"; 798 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 799 <&dma1 AT91_XDMAC_DT_PERID(19)>; 800 dma-names = "tx", "rx"; 801 atmel,use-dma-rx; 802 atmel,use-dma-tx; 803 atmel,fifo-size = <32>; 804 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 805 status = "disabled"; 806 }; 807 808 spi7: spi@400 { 809 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 810 reg = <0x400 0x200>; 811 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 813 clock-names = "spi_clk"; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 817 <&dma1 AT91_XDMAC_DT_PERID(19)>; 818 dma-names = "tx", "rx"; 819 atmel,fifo-size = <32>; 820 status = "disabled"; 821 }; 822 823 i2c7: i2c@600 { 824 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 825 reg = <0x600 0x200>; 826 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>, 831 <&dma1 AT91_XDMAC_DT_PERID(19)>; 832 dma-names = "tx", "rx"; 833 atmel,fifo-size = <32>; 834 status = "disabled"; 835 }; 836 }; 837 838 flx8: flexcom@e281c000 { 839 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 840 reg = <0xe281c000 0x200>; 841 ranges = <0x0 0xe281c000 0x800>; 842 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 843 #address-cells = <1>; 844 #size-cells = <1>; 845 status = "disabled"; 846 847 uart8: serial@200 { 848 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 849 reg = <0x200 0x200>; 850 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 852 clock-names = "usart"; 853 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 854 <&dma0 AT91_XDMAC_DT_PERID(21)>; 855 dma-names = "tx", "rx"; 856 atmel,use-dma-rx; 857 atmel,use-dma-tx; 858 atmel,fifo-size = <32>; 859 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 860 status = "disabled"; 861 }; 862 863 spi8: spi@400 { 864 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 865 reg = <0x400 0x200>; 866 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 867 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 868 clock-names = "spi_clk"; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 872 <&dma0 AT91_XDMAC_DT_PERID(21)>; 873 dma-names = "tx", "rx"; 874 atmel,fifo-size = <32>; 875 status = "disabled"; 876 }; 877 878 i2c8: i2c@600 { 879 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 880 reg = <0x600 0x200>; 881 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 dmas = <&dma0 AT91_XDMAC_DT_PERID(22)>, 886 <&dma0 AT91_XDMAC_DT_PERID(21)>; 887 dma-names = "tx", "rx"; 888 atmel,fifo-size = <32>; 889 status = "disabled"; 890 }; 891 }; 892 893 flx9: flexcom@e2820000 { 894 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 895 reg = <0xe2820000 0x200>; 896 ranges = <0x0 0xe2820000 0x800>; 897 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 898 #address-cells = <1>; 899 #size-cells = <1>; 900 status = "disabled"; 901 902 uart9: serial@200 { 903 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 904 reg = <0x200 0x200>; 905 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 907 clock-names = "usart"; 908 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 909 <&dma0 AT91_XDMAC_DT_PERID(23)>; 910 dma-names = "tx", "rx"; 911 atmel,use-dma-rx; 912 atmel,use-dma-tx; 913 atmel,fifo-size = <32>; 914 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 915 status = "disabled"; 916 }; 917 918 spi9: spi@400 { 919 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 920 reg = <0x400 0x200>; 921 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 923 clock-names = "spi_clk"; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 927 <&dma0 AT91_XDMAC_DT_PERID(23)>; 928 dma-names = "tx", "rx"; 929 atmel,fifo-size = <32>; 930 status = "disabled"; 931 }; 932 933 i2c9: i2c@600 { 934 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 935 reg = <0x600 0x200>; 936 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 937 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 938 #address-cells = <1>; 939 #size-cells = <0>; 940 dmas = <&dma0 AT91_XDMAC_DT_PERID(24)>, 941 <&dma0 AT91_XDMAC_DT_PERID(23)>; 942 dma-names = "tx", "rx"; 943 atmel,fifo-size = <32>; 944 status = "disabled"; 945 }; 946 }; 947 948 flx10: flexcom@e2824000 { 949 compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; 950 reg = <0xe2824000 0x200>; 951 ranges = <0x0 0xe2824000 0x800>; 952 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 953 #address-cells = <1>; 954 #size-cells = <1>; 955 status = "disabled"; 956 957 uart10: serial@200 { 958 compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; 959 reg = <0x200 0x200>; 960 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 962 clock-names = "usart"; 963 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 964 <&dma0 AT91_XDMAC_DT_PERID(25)>; 965 dma-names = "tx", "rx"; 966 atmel,use-dma-rx; 967 atmel,use-dma-tx; 968 atmel,fifo-size = <32>; 969 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 970 status = "disabled"; 971 }; 972 973 spi10: spi@400 { 974 compatible = "microchip,sama7d65-spi", "atmel,at91rm9200-spi"; 975 reg = <0x400 0x200>; 976 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 977 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 978 clock-names = "spi_clk"; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 dmas = <&dma0 AT91_XDMAC_DT_PERID(26)>, 982 <&dma0 AT91_XDMAC_DT_PERID(25)>; 983 dma-names = "tx", "rx"; 984 atmel,fifo-size = <32>; 985 status = "disabled"; 986 }; 987 988 i2c10: i2c@600 { 989 compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; 990 reg = <0x600 0x200>; 991 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 atmel,fifo-size = <32>; 996 status = "disabled"; 997 }; 998 }; 999 1000 uddrc: uddrc@e3800000 { 1001 compatible = "microchip,sama7d65-uddrc", "microchip,sama7g5-uddrc"; 1002 reg = <0xe3800000 0x4000>; 1003 }; 1004 1005 ddr3phy: ddr3phy@e3804000 { 1006 compatible = "microchip,sama7d65-ddr3phy", "microchip,sama7g5-ddr3phy"; 1007 reg = <0xe3804000 0x1000>; 1008 }; 1009 1010 gic: interrupt-controller@e8c11000 { 1011 compatible = "arm,cortex-a7-gic"; 1012 reg = <0xe8c11000 0x1000>, 1013 <0xe8c12000 0x2000>; 1014 #interrupt-cells = <3>; 1015 #address-cells = <0>; 1016 interrupt-controller; 1017 }; 1018 }; 1019}; 1020