1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2017, Intel Corporation 4 * 5 * based on socfpga_cyclone5_de0_nano_soc.dts 6 */ 7/dts-v1/; 8 9#include "socfpga_cyclone5.dtsi" 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Terasic DE10-Nano"; 15 compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga"; 16 17 chosen { 18 stdout-path = "serial0:115200n8"; 19 }; 20 21 memory@0 { 22 /* 1 GiB */ 23 device_type = "memory"; 24 reg = <0x0 0x40000000>; 25 }; 26 27 soc { 28 fpga: bus@ff200000 { 29 compatible = "simple-bus"; 30 reg = <0xff200000 0x00200000>; 31 ranges = <0x00000000 0xff200000 0x00200000>; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 35 /* 36 * Here the devices will appear if an FPGA image is 37 * loaded. Their description is expected to be added 38 * using a device tree overlay that matches the image. 39 */ 40 }; 41 }; 42}; 43 44&gmac1 { 45 /* Uses a KSZ9031RNX phy */ 46 phy-mode = "rgmii-id"; 47 rxd0-skew-ps = <420>; 48 rxd1-skew-ps = <420>; 49 rxd2-skew-ps = <420>; 50 rxd3-skew-ps = <420>; 51 txen-skew-ps = <0>; 52 rxdv-skew-ps = <420>; 53 status = "okay"; 54}; 55 56&gpio0 { 57 status = "okay"; 58}; 59 60&gpio1 { 61 status = "okay"; 62}; 63 64&gpio2 { 65 status = "okay"; 66}; 67 68&i2c0 { 69 clock-frequency = <100000>; 70 status = "okay"; 71 72 accelerometer@53 { 73 compatible = "adi,adxl345"; 74 reg = <0x53>; 75 /* HPS_GSENSOR_INT is routed to UART0_RX/CAN0_RX/SPIM0_SS1/HPS_GPIO61 */ 76 interrupt-parent = <&portc>; 77 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 78 interrupt-names = "INT1"; 79 }; 80}; 81 82&mmc0 { 83 /* micro SD card socket J11 */ 84 status = "okay"; 85}; 86 87&uart0 { 88 /* 89 * Accessible via USB (FT232R) on Mini-USB plug J4 90 * RX = TRACE_D0/SPIS0_CLK/UART0_RX/HPS_GPIO49 91 * TX = TRACE_D1/SPIS0_MOSI/UART0_TX/HPS_GPIO50 92 * no handshaking lines 93 */ 94 clock-frequency = <100000000>; 95}; 96