1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 9 select ARCH_HAS_CURRENT_STACK_POINTER 10 select ARCH_HAS_DEBUG_VIRTUAL if MMU 11 select ARCH_HAS_DMA_ALLOC if MMU 12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 13 select ARCH_HAS_ELF_RANDOMIZE 14 select ARCH_HAS_FORTIFY_SOURCE 15 select ARCH_HAS_KEEPINITRD 16 select ARCH_HAS_KCOV 17 select ARCH_HAS_MEMBARRIER_SYNC_CORE 18 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 19 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 20 select ARCH_HAS_SETUP_DMA_OPS 21 select ARCH_HAS_SET_MEMORY 22 select ARCH_STACKWALK 23 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 24 select ARCH_HAS_STRICT_MODULE_RWX if MMU 25 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 26 select ARCH_HAS_SYNC_DMA_FOR_CPU 27 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 28 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 29 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 30 select ARCH_HAS_GCOV_PROFILE_ALL 31 select ARCH_KEEP_MEMBLOCK 32 select ARCH_HAS_UBSAN 33 select ARCH_MIGHT_HAVE_PC_PARPORT 34 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 35 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 36 select ARCH_SUPPORTS_ATOMIC_RMW 37 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 38 select ARCH_SUPPORTS_PER_VMA_LOCK 39 select ARCH_USE_BUILTIN_BSWAP 40 select ARCH_USE_CMPXCHG_LOCKREF 41 select ARCH_USE_MEMTEST 42 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 43 select ARCH_WANT_GENERAL_HUGETLB 44 select ARCH_WANT_IPC_PARSE_VERSION 45 select ARCH_WANT_LD_ORPHAN_WARN 46 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 47 select BUILDTIME_TABLE_SORT if MMU 48 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 49 select CLONE_BACKWARDS 50 select CPU_PM if SUSPEND || CPU_IDLE 51 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 52 select DMA_DECLARE_COHERENT 53 select DMA_GLOBAL_POOL if !MMU 54 select DMA_OPS 55 select DMA_NONCOHERENT_MMAP if MMU 56 select EDAC_SUPPORT 57 select EDAC_ATOMIC_SCRUB 58 select GENERIC_ALLOCATOR 59 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 60 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 61 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 62 select GENERIC_IRQ_IPI if SMP 63 select GENERIC_CPU_AUTOPROBE 64 select GENERIC_EARLY_IOREMAP 65 select GENERIC_IDLE_POLL_SETUP 66 select GENERIC_IRQ_MULTI_HANDLER 67 select GENERIC_IRQ_PROBE 68 select GENERIC_IRQ_SHOW 69 select GENERIC_IRQ_SHOW_LEVEL 70 select GENERIC_LIB_DEVMEM_IS_ALLOWED 71 select GENERIC_PCI_IOMAP 72 select GENERIC_SCHED_CLOCK 73 select GENERIC_SMP_IDLE_THREAD 74 select HARDIRQS_SW_RESEND 75 select HAS_IOPORT 76 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 77 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 78 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 79 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 80 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 81 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 82 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 83 select HAVE_ARCH_MMAP_RND_BITS if MMU 84 select HAVE_ARCH_PFN_VALID 85 select HAVE_ARCH_SECCOMP 86 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 87 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 88 select HAVE_ARCH_TRACEHOOK 89 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 90 select HAVE_ARM_SMCCC if CPU_V7 91 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 92 select HAVE_CONTEXT_TRACKING_USER 93 select HAVE_C_RECORDMCOUNT 94 select HAVE_BUILDTIME_MCOUNT_SORT 95 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 96 select HAVE_DMA_CONTIGUOUS if MMU 97 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 98 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 99 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 100 select HAVE_EXIT_THREAD 101 select HAVE_FAST_GUP if ARM_LPAE 102 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 103 select HAVE_FUNCTION_ERROR_INJECTION 104 select HAVE_FUNCTION_GRAPH_TRACER 105 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 106 select HAVE_GCC_PLUGINS 107 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 108 select HAVE_IRQ_TIME_ACCOUNTING 109 select HAVE_KERNEL_GZIP 110 select HAVE_KERNEL_LZ4 111 select HAVE_KERNEL_LZMA 112 select HAVE_KERNEL_LZO 113 select HAVE_KERNEL_XZ 114 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 115 select HAVE_KRETPROBES if HAVE_KPROBES 116 select HAVE_MOD_ARCH_SPECIFIC 117 select HAVE_NMI 118 select HAVE_OPTPROBES if !THUMB2_KERNEL 119 select HAVE_PAGE_SIZE_4KB 120 select HAVE_PCI if MMU 121 select HAVE_PERF_EVENTS 122 select HAVE_PERF_REGS 123 select HAVE_PERF_USER_STACK_DUMP 124 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 125 select HAVE_REGS_AND_STACK_ACCESS_API 126 select HAVE_RSEQ 127 select HAVE_STACKPROTECTOR 128 select HAVE_SYSCALL_TRACEPOINTS 129 select HAVE_UID16 130 select HAVE_VIRT_CPU_ACCOUNTING_GEN 131 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 132 select IRQ_FORCED_THREADING 133 select LOCK_MM_AND_FIND_VMA 134 select MODULES_USE_ELF_REL 135 select NEED_DMA_MAP_STATE 136 select OF_EARLY_FLATTREE if OF 137 select OLD_SIGACTION 138 select OLD_SIGSUSPEND3 139 select PCI_DOMAINS_GENERIC if PCI 140 select PCI_SYSCALL if PCI 141 select PERF_USE_VMALLOC 142 select RTC_LIB 143 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 144 select SYS_SUPPORTS_APM_EMULATION 145 select THREAD_INFO_IN_TASK 146 select TIMER_OF if OF 147 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 148 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 149 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 150 # Above selects are sorted alphabetically; please add new ones 151 # according to that. Thanks. 152 help 153 The ARM series is a line of low-power-consumption RISC chip designs 154 licensed by ARM Ltd and targeted at embedded applications and 155 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 156 manufactured, but legacy ARM-based PC hardware remains popular in 157 Europe. There is an ARM Linux project with a web page at 158 <http://www.arm.linux.org.uk/>. 159 160config ARM_HAS_GROUP_RELOCS 161 def_bool y 162 depends on !LD_IS_LLD || LLD_VERSION >= 140000 163 depends on !COMPILE_TEST 164 help 165 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 166 relocations, which have been around for a long time, but were not 167 supported in LLD until version 14. The combined range is -/+ 256 MiB, 168 which is usually sufficient, but not for allyesconfig, so we disable 169 this feature when doing compile testing. 170 171config ARM_DMA_USE_IOMMU 172 bool 173 select NEED_SG_DMA_LENGTH 174 175if ARM_DMA_USE_IOMMU 176 177config ARM_DMA_IOMMU_ALIGNMENT 178 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 179 range 4 9 180 default 8 181 help 182 DMA mapping framework by default aligns all buffers to the smallest 183 PAGE_SIZE order which is greater than or equal to the requested buffer 184 size. This works well for buffers up to a few hundreds kilobytes, but 185 for larger buffers it just a waste of address space. Drivers which has 186 relatively small addressing window (like 64Mib) might run out of 187 virtual space with just a few allocations. 188 189 With this parameter you can specify the maximum PAGE_SIZE order for 190 DMA IOMMU buffers. Larger buffers will be aligned only to this 191 specified order. The order is expressed as a power of two multiplied 192 by the PAGE_SIZE. 193 194endif 195 196config SYS_SUPPORTS_APM_EMULATION 197 bool 198 199config HAVE_TCM 200 bool 201 select GENERIC_ALLOCATOR 202 203config HAVE_PROC_CPU 204 bool 205 206config NO_IOPORT_MAP 207 bool 208 209config SBUS 210 bool 211 212config STACKTRACE_SUPPORT 213 bool 214 default y 215 216config LOCKDEP_SUPPORT 217 bool 218 default y 219 220config ARCH_HAS_ILOG2_U32 221 bool 222 223config ARCH_HAS_ILOG2_U64 224 bool 225 226config ARCH_HAS_BANDGAP 227 bool 228 229config FIX_EARLYCON_MEM 230 def_bool y if MMU 231 232config GENERIC_HWEIGHT 233 bool 234 default y 235 236config GENERIC_CALIBRATE_DELAY 237 bool 238 default y 239 240config ARCH_MAY_HAVE_PC_FDC 241 bool 242 243config ARCH_SUPPORTS_UPROBES 244 def_bool y 245 246config GENERIC_ISA_DMA 247 bool 248 249config FIQ 250 bool 251 252config ARCH_MTD_XIP 253 bool 254 255config ARM_PATCH_PHYS_VIRT 256 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 257 default y 258 depends on MMU 259 help 260 Patch phys-to-virt and virt-to-phys translation functions at 261 boot and module load time according to the position of the 262 kernel in system memory. 263 264 This can only be used with non-XIP MMU kernels where the base 265 of physical memory is at a 2 MiB boundary. 266 267 Only disable this option if you know that you do not require 268 this feature (eg, building a kernel for a single machine) and 269 you need to shrink the kernel to the minimal size. 270 271config NEED_MACH_IO_H 272 bool 273 help 274 Select this when mach/io.h is required to provide special 275 definitions for this platform. The need for mach/io.h should 276 be avoided when possible. 277 278config NEED_MACH_MEMORY_H 279 bool 280 help 281 Select this when mach/memory.h is required to provide special 282 definitions for this platform. The need for mach/memory.h should 283 be avoided when possible. 284 285config PHYS_OFFSET 286 hex "Physical address of main memory" if MMU 287 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 288 default DRAM_BASE if !MMU 289 default 0x00000000 if ARCH_FOOTBRIDGE 290 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 291 default 0xa0000000 if ARCH_PXA 292 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 293 default 0 294 help 295 Please provide the physical address corresponding to the 296 location of main memory in your system. 297 298config GENERIC_BUG 299 def_bool y 300 depends on BUG 301 302config PGTABLE_LEVELS 303 int 304 default 3 if ARM_LPAE 305 default 2 306 307menu "System Type" 308 309config MMU 310 bool "MMU-based Paged Memory Management Support" 311 default y 312 help 313 Select if you want MMU-based virtualised addressing space 314 support by paged memory management. If unsure, say 'Y'. 315 316config ARM_SINGLE_ARMV7M 317 def_bool !MMU 318 select ARM_NVIC 319 select CPU_V7M 320 select NO_IOPORT_MAP 321 322config ARCH_MMAP_RND_BITS_MIN 323 default 8 324 325config ARCH_MMAP_RND_BITS_MAX 326 default 14 if PAGE_OFFSET=0x40000000 327 default 15 if PAGE_OFFSET=0x80000000 328 default 16 329 330config ARCH_MULTIPLATFORM 331 bool "Require kernel to be portable to multiple machines" if EXPERT 332 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 333 default y 334 help 335 In general, all Arm machines can be supported in a single 336 kernel image, covering either Armv4/v5 or Armv6/v7. 337 338 However, some configuration options require hardcoding machine 339 specific physical addresses or enable errata workarounds that may 340 break other machines. 341 342 Selecting N here allows using those options, including 343 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 344 345source "arch/arm/Kconfig.platforms" 346 347# 348# This is sorted alphabetically by mach-* pathname. However, plat-* 349# Kconfigs may be included either alphabetically (according to the 350# plat- suffix) or along side the corresponding mach-* source. 351# 352source "arch/arm/mach-actions/Kconfig" 353 354source "arch/arm/mach-alpine/Kconfig" 355 356source "arch/arm/mach-artpec/Kconfig" 357 358source "arch/arm/mach-aspeed/Kconfig" 359 360source "arch/arm/mach-at91/Kconfig" 361 362source "arch/arm/mach-axxia/Kconfig" 363 364source "arch/arm/mach-bcm/Kconfig" 365 366source "arch/arm/mach-berlin/Kconfig" 367 368source "arch/arm/mach-clps711x/Kconfig" 369 370source "arch/arm/mach-davinci/Kconfig" 371 372source "arch/arm/mach-digicolor/Kconfig" 373 374source "arch/arm/mach-dove/Kconfig" 375 376source "arch/arm/mach-ep93xx/Kconfig" 377 378source "arch/arm/mach-exynos/Kconfig" 379 380source "arch/arm/mach-footbridge/Kconfig" 381 382source "arch/arm/mach-gemini/Kconfig" 383 384source "arch/arm/mach-highbank/Kconfig" 385 386source "arch/arm/mach-hisi/Kconfig" 387 388source "arch/arm/mach-hpe/Kconfig" 389 390source "arch/arm/mach-imx/Kconfig" 391 392source "arch/arm/mach-ixp4xx/Kconfig" 393 394source "arch/arm/mach-keystone/Kconfig" 395 396source "arch/arm/mach-lpc32xx/Kconfig" 397 398source "arch/arm/mach-mediatek/Kconfig" 399 400source "arch/arm/mach-meson/Kconfig" 401 402source "arch/arm/mach-milbeaut/Kconfig" 403 404source "arch/arm/mach-mmp/Kconfig" 405 406source "arch/arm/mach-mstar/Kconfig" 407 408source "arch/arm/mach-mv78xx0/Kconfig" 409 410source "arch/arm/mach-mvebu/Kconfig" 411 412source "arch/arm/mach-mxs/Kconfig" 413 414source "arch/arm/mach-nomadik/Kconfig" 415 416source "arch/arm/mach-npcm/Kconfig" 417 418source "arch/arm/mach-omap1/Kconfig" 419 420source "arch/arm/mach-omap2/Kconfig" 421 422source "arch/arm/mach-orion5x/Kconfig" 423 424source "arch/arm/mach-pxa/Kconfig" 425 426source "arch/arm/mach-qcom/Kconfig" 427 428source "arch/arm/mach-realtek/Kconfig" 429 430source "arch/arm/mach-rpc/Kconfig" 431 432source "arch/arm/mach-rockchip/Kconfig" 433 434source "arch/arm/mach-s3c/Kconfig" 435 436source "arch/arm/mach-s5pv210/Kconfig" 437 438source "arch/arm/mach-sa1100/Kconfig" 439 440source "arch/arm/mach-shmobile/Kconfig" 441 442source "arch/arm/mach-socfpga/Kconfig" 443 444source "arch/arm/mach-spear/Kconfig" 445 446source "arch/arm/mach-sti/Kconfig" 447 448source "arch/arm/mach-stm32/Kconfig" 449 450source "arch/arm/mach-sunxi/Kconfig" 451 452source "arch/arm/mach-tegra/Kconfig" 453 454source "arch/arm/mach-ux500/Kconfig" 455 456source "arch/arm/mach-versatile/Kconfig" 457 458source "arch/arm/mach-vt8500/Kconfig" 459 460source "arch/arm/mach-zynq/Kconfig" 461 462# ARMv7-M architecture 463config ARCH_LPC18XX 464 bool "NXP LPC18xx/LPC43xx" 465 depends on ARM_SINGLE_ARMV7M 466 select ARCH_HAS_RESET_CONTROLLER 467 select ARM_AMBA 468 select CLKSRC_LPC32XX 469 select PINCTRL 470 help 471 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 472 high performance microcontrollers. 473 474config ARCH_MPS2 475 bool "ARM MPS2 platform" 476 depends on ARM_SINGLE_ARMV7M 477 select ARM_AMBA 478 select CLKSRC_MPS2 479 help 480 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 481 with a range of available cores like Cortex-M3/M4/M7. 482 483 Please, note that depends which Application Note is used memory map 484 for the platform may vary, so adjustment of RAM base might be needed. 485 486# Definitions to make life easier 487config ARCH_ACORN 488 bool 489 490config PLAT_ORION 491 bool 492 select CLKSRC_MMIO 493 select GENERIC_IRQ_CHIP 494 select IRQ_DOMAIN 495 496config PLAT_ORION_LEGACY 497 bool 498 select PLAT_ORION 499 500config PLAT_VERSATILE 501 bool 502 503source "arch/arm/mm/Kconfig" 504 505config IWMMXT 506 bool "Enable iWMMXt support" 507 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 508 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 509 help 510 Enable support for iWMMXt context switching at run time if 511 running on a CPU that supports it. 512 513if !MMU 514source "arch/arm/Kconfig-nommu" 515endif 516 517config PJ4B_ERRATA_4742 518 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 519 depends on CPU_PJ4B && MACH_ARMADA_370 520 default y 521 help 522 When coming out of either a Wait for Interrupt (WFI) or a Wait for 523 Event (WFE) IDLE states, a specific timing sensitivity exists between 524 the retiring WFI/WFE instructions and the newly issued subsequent 525 instructions. This sensitivity can result in a CPU hang scenario. 526 Workaround: 527 The software must insert either a Data Synchronization Barrier (DSB) 528 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 529 instruction 530 531config ARM_ERRATA_326103 532 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 533 depends on CPU_V6 534 help 535 Executing a SWP instruction to read-only memory does not set bit 11 536 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 537 treat the access as a read, preventing a COW from occurring and 538 causing the faulting task to livelock. 539 540config ARM_ERRATA_411920 541 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 542 depends on CPU_V6 || CPU_V6K 543 help 544 Invalidation of the Instruction Cache operation can 545 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 546 It does not affect the MPCore. This option enables the ARM Ltd. 547 recommended workaround. 548 549config ARM_ERRATA_430973 550 bool "ARM errata: Stale prediction on replaced interworking branch" 551 depends on CPU_V7 552 help 553 This option enables the workaround for the 430973 Cortex-A8 554 r1p* erratum. If a code sequence containing an ARM/Thumb 555 interworking branch is replaced with another code sequence at the 556 same virtual address, whether due to self-modifying code or virtual 557 to physical address re-mapping, Cortex-A8 does not recover from the 558 stale interworking branch prediction. This results in Cortex-A8 559 executing the new code sequence in the incorrect ARM or Thumb state. 560 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 561 and also flushes the branch target cache at every context switch. 562 Note that setting specific bits in the ACTLR register may not be 563 available in non-secure mode. 564 565config ARM_ERRATA_458693 566 bool "ARM errata: Processor deadlock when a false hazard is created" 567 depends on CPU_V7 568 depends on !ARCH_MULTIPLATFORM 569 help 570 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 571 erratum. For very specific sequences of memory operations, it is 572 possible for a hazard condition intended for a cache line to instead 573 be incorrectly associated with a different cache line. This false 574 hazard might then cause a processor deadlock. The workaround enables 575 the L1 caching of the NEON accesses and disables the PLD instruction 576 in the ACTLR register. Note that setting specific bits in the ACTLR 577 register may not be available in non-secure mode and thus is not 578 available on a multiplatform kernel. This should be applied by the 579 bootloader instead. 580 581config ARM_ERRATA_460075 582 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 583 depends on CPU_V7 584 depends on !ARCH_MULTIPLATFORM 585 help 586 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 587 erratum. Any asynchronous access to the L2 cache may encounter a 588 situation in which recent store transactions to the L2 cache are lost 589 and overwritten with stale memory contents from external memory. The 590 workaround disables the write-allocate mode for the L2 cache via the 591 ACTLR register. Note that setting specific bits in the ACTLR register 592 may not be available in non-secure mode and thus is not available on 593 a multiplatform kernel. This should be applied by the bootloader 594 instead. 595 596config ARM_ERRATA_742230 597 bool "ARM errata: DMB operation may be faulty" 598 depends on CPU_V7 && SMP 599 depends on !ARCH_MULTIPLATFORM 600 help 601 This option enables the workaround for the 742230 Cortex-A9 602 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 603 between two write operations may not ensure the correct visibility 604 ordering of the two writes. This workaround sets a specific bit in 605 the diagnostic register of the Cortex-A9 which causes the DMB 606 instruction to behave as a DSB, ensuring the correct behaviour of 607 the two writes. Note that setting specific bits in the diagnostics 608 register may not be available in non-secure mode and thus is not 609 available on a multiplatform kernel. This should be applied by the 610 bootloader instead. 611 612config ARM_ERRATA_742231 613 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 614 depends on CPU_V7 && SMP 615 depends on !ARCH_MULTIPLATFORM 616 help 617 This option enables the workaround for the 742231 Cortex-A9 618 (r2p0..r2p2) erratum. Under certain conditions, specific to the 619 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 620 accessing some data located in the same cache line, may get corrupted 621 data due to bad handling of the address hazard when the line gets 622 replaced from one of the CPUs at the same time as another CPU is 623 accessing it. This workaround sets specific bits in the diagnostic 624 register of the Cortex-A9 which reduces the linefill issuing 625 capabilities of the processor. Note that setting specific bits in the 626 diagnostics register may not be available in non-secure mode and thus 627 is not available on a multiplatform kernel. This should be applied by 628 the bootloader instead. 629 630config ARM_ERRATA_643719 631 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 632 depends on CPU_V7 && SMP 633 default y 634 help 635 This option enables the workaround for the 643719 Cortex-A9 (prior to 636 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 637 register returns zero when it should return one. The workaround 638 corrects this value, ensuring cache maintenance operations which use 639 it behave as intended and avoiding data corruption. 640 641config ARM_ERRATA_720789 642 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 643 depends on CPU_V7 644 help 645 This option enables the workaround for the 720789 Cortex-A9 (prior to 646 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 647 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 648 As a consequence of this erratum, some TLB entries which should be 649 invalidated are not, resulting in an incoherency in the system page 650 tables. The workaround changes the TLB flushing routines to invalidate 651 entries regardless of the ASID. 652 653config ARM_ERRATA_743622 654 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 655 depends on CPU_V7 656 depends on !ARCH_MULTIPLATFORM 657 help 658 This option enables the workaround for the 743622 Cortex-A9 659 (r2p*) erratum. Under very rare conditions, a faulty 660 optimisation in the Cortex-A9 Store Buffer may lead to data 661 corruption. This workaround sets a specific bit in the diagnostic 662 register of the Cortex-A9 which disables the Store Buffer 663 optimisation, preventing the defect from occurring. This has no 664 visible impact on the overall performance or power consumption of the 665 processor. Note that setting specific bits in the diagnostics register 666 may not be available in non-secure mode and thus is not available on a 667 multiplatform kernel. This should be applied by the bootloader instead. 668 669config ARM_ERRATA_751472 670 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 671 depends on CPU_V7 672 depends on !ARCH_MULTIPLATFORM 673 help 674 This option enables the workaround for the 751472 Cortex-A9 (prior 675 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 676 completion of a following broadcasted operation if the second 677 operation is received by a CPU before the ICIALLUIS has completed, 678 potentially leading to corrupted entries in the cache or TLB. 679 Note that setting specific bits in the diagnostics register may 680 not be available in non-secure mode and thus is not available on 681 a multiplatform kernel. This should be applied by the bootloader 682 instead. 683 684config ARM_ERRATA_754322 685 bool "ARM errata: possible faulty MMU translations following an ASID switch" 686 depends on CPU_V7 687 help 688 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 689 r3p*) erratum. A speculative memory access may cause a page table walk 690 which starts prior to an ASID switch but completes afterwards. This 691 can populate the micro-TLB with a stale entry which may be hit with 692 the new ASID. This workaround places two dsb instructions in the mm 693 switching code so that no page table walks can cross the ASID switch. 694 695config ARM_ERRATA_754327 696 bool "ARM errata: no automatic Store Buffer drain" 697 depends on CPU_V7 && SMP 698 help 699 This option enables the workaround for the 754327 Cortex-A9 (prior to 700 r2p0) erratum. The Store Buffer does not have any automatic draining 701 mechanism and therefore a livelock may occur if an external agent 702 continuously polls a memory location waiting to observe an update. 703 This workaround defines cpu_relax() as smp_mb(), preventing correctly 704 written polling loops from denying visibility of updates to memory. 705 706config ARM_ERRATA_364296 707 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 708 depends on CPU_V6 709 help 710 This options enables the workaround for the 364296 ARM1136 711 r0p2 erratum (possible cache data corruption with 712 hit-under-miss enabled). It sets the undocumented bit 31 in 713 the auxiliary control register and the FI bit in the control 714 register, thus disabling hit-under-miss without putting the 715 processor into full low interrupt latency mode. ARM11MPCore 716 is not affected. 717 718config ARM_ERRATA_764369 719 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 720 depends on CPU_V7 && SMP 721 help 722 This option enables the workaround for erratum 764369 723 affecting Cortex-A9 MPCore with two or more processors (all 724 current revisions). Under certain timing circumstances, a data 725 cache line maintenance operation by MVA targeting an Inner 726 Shareable memory region may fail to proceed up to either the 727 Point of Coherency or to the Point of Unification of the 728 system. This workaround adds a DSB instruction before the 729 relevant cache maintenance functions and sets a specific bit 730 in the diagnostic control register of the SCU. 731 732config ARM_ERRATA_764319 733 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 734 depends on CPU_V7 735 help 736 This option enables the workaround for the 764319 Cortex A-9 erratum. 737 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 738 unexpected Undefined Instruction exception when the DBGSWENABLE 739 external pin is set to 0, even when the CP14 accesses are performed 740 from a privileged mode. This work around catches the exception in a 741 way the kernel does not stop execution. 742 743config ARM_ERRATA_775420 744 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 745 depends on CPU_V7 746 help 747 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 748 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 749 operation aborts with MMU exception, it might cause the processor 750 to deadlock. This workaround puts DSB before executing ISB if 751 an abort may occur on cache maintenance. 752 753config ARM_ERRATA_798181 754 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 755 depends on CPU_V7 && SMP 756 help 757 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 758 adequately shooting down all use of the old entries. This 759 option enables the Linux kernel workaround for this erratum 760 which sends an IPI to the CPUs that are running the same ASID 761 as the one being invalidated. 762 763config ARM_ERRATA_773022 764 bool "ARM errata: incorrect instructions may be executed from loop buffer" 765 depends on CPU_V7 766 help 767 This option enables the workaround for the 773022 Cortex-A15 768 (up to r0p4) erratum. In certain rare sequences of code, the 769 loop buffer may deliver incorrect instructions. This 770 workaround disables the loop buffer to avoid the erratum. 771 772config ARM_ERRATA_818325_852422 773 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 774 depends on CPU_V7 775 help 776 This option enables the workaround for: 777 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 778 instruction might deadlock. Fixed in r0p1. 779 - Cortex-A12 852422: Execution of a sequence of instructions might 780 lead to either a data corruption or a CPU deadlock. Not fixed in 781 any Cortex-A12 cores yet. 782 This workaround for all both errata involves setting bit[12] of the 783 Feature Register. This bit disables an optimisation applied to a 784 sequence of 2 instructions that use opposing condition codes. 785 786config ARM_ERRATA_821420 787 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 788 depends on CPU_V7 789 help 790 This option enables the workaround for the 821420 Cortex-A12 791 (all revs) erratum. In very rare timing conditions, a sequence 792 of VMOV to Core registers instructions, for which the second 793 one is in the shadow of a branch or abort, can lead to a 794 deadlock when the VMOV instructions are issued out-of-order. 795 796config ARM_ERRATA_825619 797 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 798 depends on CPU_V7 799 help 800 This option enables the workaround for the 825619 Cortex-A12 801 (all revs) erratum. Within rare timing constraints, executing a 802 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 803 and Device/Strongly-Ordered loads and stores might cause deadlock 804 805config ARM_ERRATA_857271 806 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 807 depends on CPU_V7 808 help 809 This option enables the workaround for the 857271 Cortex-A12 810 (all revs) erratum. Under very rare timing conditions, the CPU might 811 hang. The workaround is expected to have a < 1% performance impact. 812 813config ARM_ERRATA_852421 814 bool "ARM errata: A17: DMB ST might fail to create order between stores" 815 depends on CPU_V7 816 help 817 This option enables the workaround for the 852421 Cortex-A17 818 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 819 execution of a DMB ST instruction might fail to properly order 820 stores from GroupA and stores from GroupB. 821 822config ARM_ERRATA_852423 823 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 824 depends on CPU_V7 825 help 826 This option enables the workaround for: 827 - Cortex-A17 852423: Execution of a sequence of instructions might 828 lead to either a data corruption or a CPU deadlock. Not fixed in 829 any Cortex-A17 cores yet. 830 This is identical to Cortex-A12 erratum 852422. It is a separate 831 config option from the A12 erratum due to the way errata are checked 832 for and handled. 833 834config ARM_ERRATA_857272 835 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 836 depends on CPU_V7 837 help 838 This option enables the workaround for the 857272 Cortex-A17 erratum. 839 This erratum is not known to be fixed in any A17 revision. 840 This is identical to Cortex-A12 erratum 857271. It is a separate 841 config option from the A12 erratum due to the way errata are checked 842 for and handled. 843 844endmenu 845 846source "arch/arm/common/Kconfig" 847 848menu "Bus support" 849 850config ISA 851 bool 852 help 853 Find out whether you have ISA slots on your motherboard. ISA is the 854 name of a bus system, i.e. the way the CPU talks to the other stuff 855 inside your box. Other bus systems are PCI, EISA, MicroChannel 856 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 857 newer boards don't support it. If you have ISA, say Y, otherwise N. 858 859# Select ISA DMA interface 860config ISA_DMA_API 861 bool 862 863config ARM_ERRATA_814220 864 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 865 depends on CPU_V7 866 help 867 The v7 ARM states that all cache and branch predictor maintenance 868 operations that do not specify an address execute, relative to 869 each other, in program order. 870 However, because of this erratum, an L2 set/way cache maintenance 871 operation can overtake an L1 set/way cache maintenance operation. 872 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 873 r0p4, r0p5. 874 875endmenu 876 877menu "Kernel Features" 878 879config HAVE_SMP 880 bool 881 help 882 This option should be selected by machines which have an SMP- 883 capable CPU. 884 885 The only effect of this option is to make the SMP-related 886 options available to the user for configuration. 887 888config SMP 889 bool "Symmetric Multi-Processing" 890 depends on CPU_V6K || CPU_V7 891 depends on HAVE_SMP 892 depends on MMU || ARM_MPU 893 select IRQ_WORK 894 help 895 This enables support for systems with more than one CPU. If you have 896 a system with only one CPU, say N. If you have a system with more 897 than one CPU, say Y. 898 899 If you say N here, the kernel will run on uni- and multiprocessor 900 machines, but will use only one CPU of a multiprocessor machine. If 901 you say Y here, the kernel will run on many, but not all, 902 uniprocessor machines. On a uniprocessor machine, the kernel 903 will run faster if you say N here. 904 905 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 906 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 907 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 908 909 If you don't know what to do here, say N. 910 911config SMP_ON_UP 912 bool "Allow booting SMP kernel on uniprocessor systems" 913 depends on SMP && MMU 914 default y 915 help 916 SMP kernels contain instructions which fail on non-SMP processors. 917 Enabling this option allows the kernel to modify itself to make 918 these instructions safe. Disabling it allows about 1K of space 919 savings. 920 921 If you don't know what to do here, say Y. 922 923 924config CURRENT_POINTER_IN_TPIDRURO 925 def_bool y 926 depends on CPU_32v6K && !CPU_V6 927 928config IRQSTACKS 929 def_bool y 930 select HAVE_IRQ_EXIT_ON_IRQ_STACK 931 select HAVE_SOFTIRQ_ON_OWN_STACK 932 933config ARM_CPU_TOPOLOGY 934 bool "Support cpu topology definition" 935 depends on SMP && CPU_V7 936 default y 937 help 938 Support ARM cpu topology definition. The MPIDR register defines 939 affinity between processors which is then used to describe the cpu 940 topology of an ARM System. 941 942config SCHED_MC 943 bool "Multi-core scheduler support" 944 depends on ARM_CPU_TOPOLOGY 945 help 946 Multi-core scheduler support improves the CPU scheduler's decision 947 making when dealing with multi-core CPU chips at a cost of slightly 948 increased overhead in some places. If unsure say N here. 949 950config SCHED_SMT 951 bool "SMT scheduler support" 952 depends on ARM_CPU_TOPOLOGY 953 help 954 Improves the CPU scheduler's decision making when dealing with 955 MultiThreading at a cost of slightly increased overhead in some 956 places. If unsure say N here. 957 958config HAVE_ARM_SCU 959 bool 960 help 961 This option enables support for the ARM snoop control unit 962 963config HAVE_ARM_ARCH_TIMER 964 bool "Architected timer support" 965 depends on CPU_V7 966 select ARM_ARCH_TIMER 967 help 968 This option enables support for the ARM architected timer 969 970config HAVE_ARM_TWD 971 bool 972 help 973 This options enables support for the ARM timer and watchdog unit 974 975config MCPM 976 bool "Multi-Cluster Power Management" 977 depends on CPU_V7 && SMP 978 help 979 This option provides the common power management infrastructure 980 for (multi-)cluster based systems, such as big.LITTLE based 981 systems. 982 983config MCPM_QUAD_CLUSTER 984 bool 985 depends on MCPM 986 help 987 To avoid wasting resources unnecessarily, MCPM only supports up 988 to 2 clusters by default. 989 Platforms with 3 or 4 clusters that use MCPM must select this 990 option to allow the additional clusters to be managed. 991 992config BIG_LITTLE 993 bool "big.LITTLE support (Experimental)" 994 depends on CPU_V7 && SMP 995 select MCPM 996 help 997 This option enables support selections for the big.LITTLE 998 system architecture. 999 1000config BL_SWITCHER 1001 bool "big.LITTLE switcher support" 1002 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1003 select CPU_PM 1004 help 1005 The big.LITTLE "switcher" provides the core functionality to 1006 transparently handle transition between a cluster of A15's 1007 and a cluster of A7's in a big.LITTLE system. 1008 1009config BL_SWITCHER_DUMMY_IF 1010 tristate "Simple big.LITTLE switcher user interface" 1011 depends on BL_SWITCHER && DEBUG_KERNEL 1012 help 1013 This is a simple and dummy char dev interface to control 1014 the big.LITTLE switcher core code. It is meant for 1015 debugging purposes only. 1016 1017choice 1018 prompt "Memory split" 1019 depends on MMU 1020 default VMSPLIT_3G 1021 help 1022 Select the desired split between kernel and user memory. 1023 1024 If you are not absolutely sure what you are doing, leave this 1025 option alone! 1026 1027 config VMSPLIT_3G 1028 bool "3G/1G user/kernel split" 1029 config VMSPLIT_3G_OPT 1030 depends on !ARM_LPAE 1031 bool "3G/1G user/kernel split (for full 1G low memory)" 1032 config VMSPLIT_2G 1033 bool "2G/2G user/kernel split" 1034 config VMSPLIT_1G 1035 bool "1G/3G user/kernel split" 1036endchoice 1037 1038config PAGE_OFFSET 1039 hex 1040 default PHYS_OFFSET if !MMU 1041 default 0x40000000 if VMSPLIT_1G 1042 default 0x80000000 if VMSPLIT_2G 1043 default 0xB0000000 if VMSPLIT_3G_OPT 1044 default 0xC0000000 1045 1046config KASAN_SHADOW_OFFSET 1047 hex 1048 depends on KASAN 1049 default 0x1f000000 if PAGE_OFFSET=0x40000000 1050 default 0x5f000000 if PAGE_OFFSET=0x80000000 1051 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1052 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1053 default 0xffffffff 1054 1055config NR_CPUS 1056 int "Maximum number of CPUs (2-32)" 1057 range 2 16 if DEBUG_KMAP_LOCAL 1058 range 2 32 if !DEBUG_KMAP_LOCAL 1059 depends on SMP 1060 default "4" 1061 help 1062 The maximum number of CPUs that the kernel can support. 1063 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1064 debugging is enabled, which uses half of the per-CPU fixmap 1065 slots as guard regions. 1066 1067config HOTPLUG_CPU 1068 bool "Support for hot-pluggable CPUs" 1069 depends on SMP 1070 select GENERIC_IRQ_MIGRATION 1071 help 1072 Say Y here to experiment with turning CPUs off and on. CPUs 1073 can be controlled through /sys/devices/system/cpu. 1074 1075config ARM_PSCI 1076 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1077 depends on HAVE_ARM_SMCCC 1078 select ARM_PSCI_FW 1079 help 1080 Say Y here if you want Linux to communicate with system firmware 1081 implementing the PSCI specification for CPU-centric power 1082 management operations described in ARM document number ARM DEN 1083 0022A ("Power State Coordination Interface System Software on 1084 ARM processors"). 1085 1086config HZ_FIXED 1087 int 1088 default 128 if SOC_AT91RM9200 1089 default 0 1090 1091choice 1092 depends on HZ_FIXED = 0 1093 prompt "Timer frequency" 1094 1095config HZ_100 1096 bool "100 Hz" 1097 1098config HZ_200 1099 bool "200 Hz" 1100 1101config HZ_250 1102 bool "250 Hz" 1103 1104config HZ_300 1105 bool "300 Hz" 1106 1107config HZ_500 1108 bool "500 Hz" 1109 1110config HZ_1000 1111 bool "1000 Hz" 1112 1113endchoice 1114 1115config HZ 1116 int 1117 default HZ_FIXED if HZ_FIXED != 0 1118 default 100 if HZ_100 1119 default 200 if HZ_200 1120 default 250 if HZ_250 1121 default 300 if HZ_300 1122 default 500 if HZ_500 1123 default 1000 1124 1125config SCHED_HRTICK 1126 def_bool HIGH_RES_TIMERS 1127 1128config THUMB2_KERNEL 1129 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1130 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1131 default y if CPU_THUMBONLY 1132 select ARM_UNWIND 1133 help 1134 By enabling this option, the kernel will be compiled in 1135 Thumb-2 mode. 1136 1137 If unsure, say N. 1138 1139config ARM_PATCH_IDIV 1140 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1141 depends on CPU_32v7 1142 default y 1143 help 1144 The ARM compiler inserts calls to __aeabi_idiv() and 1145 __aeabi_uidiv() when it needs to perform division on signed 1146 and unsigned integers. Some v7 CPUs have support for the sdiv 1147 and udiv instructions that can be used to implement those 1148 functions. 1149 1150 Enabling this option allows the kernel to modify itself to 1151 replace the first two instructions of these library functions 1152 with the sdiv or udiv plus "bx lr" instructions when the CPU 1153 it is running on supports them. Typically this will be faster 1154 and less power intensive than running the original library 1155 code to do integer division. 1156 1157config AEABI 1158 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1159 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1160 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1161 help 1162 This option allows for the kernel to be compiled using the latest 1163 ARM ABI (aka EABI). This is only useful if you are using a user 1164 space environment that is also compiled with EABI. 1165 1166 Since there are major incompatibilities between the legacy ABI and 1167 EABI, especially with regard to structure member alignment, this 1168 option also changes the kernel syscall calling convention to 1169 disambiguate both ABIs and allow for backward compatibility support 1170 (selected with CONFIG_OABI_COMPAT). 1171 1172 To use this you need GCC version 4.0.0 or later. 1173 1174config OABI_COMPAT 1175 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1176 depends on AEABI && !THUMB2_KERNEL 1177 help 1178 This option preserves the old syscall interface along with the 1179 new (ARM EABI) one. It also provides a compatibility layer to 1180 intercept syscalls that have structure arguments which layout 1181 in memory differs between the legacy ABI and the new ARM EABI 1182 (only for non "thumb" binaries). This option adds a tiny 1183 overhead to all syscalls and produces a slightly larger kernel. 1184 1185 The seccomp filter system will not be available when this is 1186 selected, since there is no way yet to sensibly distinguish 1187 between calling conventions during filtering. 1188 1189 If you know you'll be using only pure EABI user space then you 1190 can say N here. If this option is not selected and you attempt 1191 to execute a legacy ABI binary then the result will be 1192 UNPREDICTABLE (in fact it can be predicted that it won't work 1193 at all). If in doubt say N. 1194 1195config ARCH_SELECT_MEMORY_MODEL 1196 def_bool y 1197 1198config ARCH_FLATMEM_ENABLE 1199 def_bool !(ARCH_RPC || ARCH_SA1100) 1200 1201config ARCH_SPARSEMEM_ENABLE 1202 def_bool !ARCH_FOOTBRIDGE 1203 select SPARSEMEM_STATIC if SPARSEMEM 1204 1205config HIGHMEM 1206 bool "High Memory Support" 1207 depends on MMU 1208 select KMAP_LOCAL 1209 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1210 help 1211 The address space of ARM processors is only 4 Gigabytes large 1212 and it has to accommodate user address space, kernel address 1213 space as well as some memory mapped IO. That means that, if you 1214 have a large amount of physical memory and/or IO, not all of the 1215 memory can be "permanently mapped" by the kernel. The physical 1216 memory that is not permanently mapped is called "high memory". 1217 1218 Depending on the selected kernel/user memory split, minimum 1219 vmalloc space and actual amount of RAM, you may not need this 1220 option which should result in a slightly faster kernel. 1221 1222 If unsure, say n. 1223 1224config HIGHPTE 1225 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1226 depends on HIGHMEM 1227 default y 1228 help 1229 The VM uses one page of physical memory for each page table. 1230 For systems with a lot of processes, this can use a lot of 1231 precious low memory, eventually leading to low memory being 1232 consumed by page tables. Setting this option will allow 1233 user-space 2nd level page tables to reside in high memory. 1234 1235config CPU_SW_DOMAIN_PAN 1236 bool "Enable use of CPU domains to implement privileged no-access" 1237 depends on MMU && !ARM_LPAE 1238 default y 1239 help 1240 Increase kernel security by ensuring that normal kernel accesses 1241 are unable to access userspace addresses. This can help prevent 1242 use-after-free bugs becoming an exploitable privilege escalation 1243 by ensuring that magic values (such as LIST_POISON) will always 1244 fault when dereferenced. 1245 1246 CPUs with low-vector mappings use a best-efforts implementation. 1247 Their lower 1MB needs to remain accessible for the vectors, but 1248 the remainder of userspace will become appropriately inaccessible. 1249 1250config HW_PERF_EVENTS 1251 def_bool y 1252 depends on ARM_PMU 1253 1254config ARM_MODULE_PLTS 1255 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1256 depends on MODULES 1257 select KASAN_VMALLOC if KASAN 1258 default y 1259 help 1260 Allocate PLTs when loading modules so that jumps and calls whose 1261 targets are too far away for their relative offsets to be encoded 1262 in the instructions themselves can be bounced via veneers in the 1263 module's PLT. This allows modules to be allocated in the generic 1264 vmalloc area after the dedicated module memory area has been 1265 exhausted. The modules will use slightly more memory, but after 1266 rounding up to page size, the actual memory footprint is usually 1267 the same. 1268 1269 Disabling this is usually safe for small single-platform 1270 configurations. If unsure, say y. 1271 1272config ARCH_FORCE_MAX_ORDER 1273 int "Order of maximal physically contiguous allocations" 1274 default "11" if SOC_AM33XX 1275 default "8" if SA1111 1276 default "10" 1277 help 1278 The kernel page allocator limits the size of maximal physically 1279 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1280 defines the maximal power of two of number of pages that can be 1281 allocated as a single contiguous block. This option allows 1282 overriding the default setting when ability to allocate very 1283 large blocks of physically contiguous memory is required. 1284 1285 Don't change if unsure. 1286 1287config ALIGNMENT_TRAP 1288 def_bool CPU_CP15_MMU 1289 select HAVE_PROC_CPU if PROC_FS 1290 help 1291 ARM processors cannot fetch/store information which is not 1292 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1293 address divisible by 4. On 32-bit ARM processors, these non-aligned 1294 fetch/store instructions will be emulated in software if you say 1295 here, which has a severe performance impact. This is necessary for 1296 correct operation of some network protocols. With an IP-only 1297 configuration it is safe to say N, otherwise say Y. 1298 1299config UACCESS_WITH_MEMCPY 1300 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1301 depends on MMU 1302 default y if CPU_FEROCEON 1303 help 1304 Implement faster copy_to_user and clear_user methods for CPU 1305 cores where a 8-word STM instruction give significantly higher 1306 memory write throughput than a sequence of individual 32bit stores. 1307 1308 A possible side effect is a slight increase in scheduling latency 1309 between threads sharing the same address space if they invoke 1310 such copy operations with large buffers. 1311 1312 However, if the CPU data cache is using a write-allocate mode, 1313 this option is unlikely to provide any performance gain. 1314 1315config PARAVIRT 1316 bool "Enable paravirtualization code" 1317 help 1318 This changes the kernel so it can modify itself when it is run 1319 under a hypervisor, potentially improving performance significantly 1320 over full virtualization. 1321 1322config PARAVIRT_TIME_ACCOUNTING 1323 bool "Paravirtual steal time accounting" 1324 select PARAVIRT 1325 help 1326 Select this option to enable fine granularity task steal time 1327 accounting. Time spent executing other tasks in parallel with 1328 the current vCPU is discounted from the vCPU power. To account for 1329 that, there can be a small performance impact. 1330 1331 If in doubt, say N here. 1332 1333config XEN_DOM0 1334 def_bool y 1335 depends on XEN 1336 1337config XEN 1338 bool "Xen guest support on ARM" 1339 depends on ARM && AEABI && OF 1340 depends on CPU_V7 && !CPU_V6 1341 depends on !GENERIC_ATOMIC64 1342 depends on MMU 1343 select ARCH_DMA_ADDR_T_64BIT 1344 select ARM_PSCI 1345 select SWIOTLB 1346 select SWIOTLB_XEN 1347 select PARAVIRT 1348 help 1349 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1350 1351config CC_HAVE_STACKPROTECTOR_TLS 1352 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1353 1354config STACKPROTECTOR_PER_TASK 1355 bool "Use a unique stack canary value for each task" 1356 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1357 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1358 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1359 default y 1360 help 1361 Due to the fact that GCC uses an ordinary symbol reference from 1362 which to load the value of the stack canary, this value can only 1363 change at reboot time on SMP systems, and all tasks running in the 1364 kernel's address space are forced to use the same canary value for 1365 the entire duration that the system is up. 1366 1367 Enable this option to switch to a different method that uses a 1368 different canary value for each task. 1369 1370endmenu 1371 1372menu "Boot options" 1373 1374config USE_OF 1375 bool "Flattened Device Tree support" 1376 select IRQ_DOMAIN 1377 select OF 1378 help 1379 Include support for flattened device tree machine descriptions. 1380 1381config ARCH_WANT_FLAT_DTB_INSTALL 1382 def_bool y 1383 1384config ATAGS 1385 bool "Support for the traditional ATAGS boot data passing" 1386 default y 1387 help 1388 This is the traditional way of passing data to the kernel at boot 1389 time. If you are solely relying on the flattened device tree (or 1390 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1391 to remove ATAGS support from your kernel binary. 1392 1393config DEPRECATED_PARAM_STRUCT 1394 bool "Provide old way to pass kernel parameters" 1395 depends on ATAGS 1396 help 1397 This was deprecated in 2001 and announced to live on for 5 years. 1398 Some old boot loaders still use this way. 1399 1400# Compressed boot loader in ROM. Yes, we really want to ask about 1401# TEXT and BSS so we preserve their values in the config files. 1402config ZBOOT_ROM_TEXT 1403 hex "Compressed ROM boot loader base address" 1404 default 0x0 1405 help 1406 The physical address at which the ROM-able zImage is to be 1407 placed in the target. Platforms which normally make use of 1408 ROM-able zImage formats normally set this to a suitable 1409 value in their defconfig file. 1410 1411 If ZBOOT_ROM is not enabled, this has no effect. 1412 1413config ZBOOT_ROM_BSS 1414 hex "Compressed ROM boot loader BSS address" 1415 default 0x0 1416 help 1417 The base address of an area of read/write memory in the target 1418 for the ROM-able zImage which must be available while the 1419 decompressor is running. It must be large enough to hold the 1420 entire decompressed kernel plus an additional 128 KiB. 1421 Platforms which normally make use of ROM-able zImage formats 1422 normally set this to a suitable value in their defconfig file. 1423 1424 If ZBOOT_ROM is not enabled, this has no effect. 1425 1426config ZBOOT_ROM 1427 bool "Compressed boot loader in ROM/flash" 1428 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1429 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1430 help 1431 Say Y here if you intend to execute your compressed kernel image 1432 (zImage) directly from ROM or flash. If unsure, say N. 1433 1434config ARM_APPENDED_DTB 1435 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1436 depends on OF 1437 help 1438 With this option, the boot code will look for a device tree binary 1439 (DTB) appended to zImage 1440 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1441 1442 This is meant as a backward compatibility convenience for those 1443 systems with a bootloader that can't be upgraded to accommodate 1444 the documented boot protocol using a device tree. 1445 1446 Beware that there is very little in terms of protection against 1447 this option being confused by leftover garbage in memory that might 1448 look like a DTB header after a reboot if no actual DTB is appended 1449 to zImage. Do not leave this option active in a production kernel 1450 if you don't intend to always append a DTB. Proper passing of the 1451 location into r2 of a bootloader provided DTB is always preferable 1452 to this option. 1453 1454config ARM_ATAG_DTB_COMPAT 1455 bool "Supplement the appended DTB with traditional ATAG information" 1456 depends on ARM_APPENDED_DTB 1457 help 1458 Some old bootloaders can't be updated to a DTB capable one, yet 1459 they provide ATAGs with memory configuration, the ramdisk address, 1460 the kernel cmdline string, etc. Such information is dynamically 1461 provided by the bootloader and can't always be stored in a static 1462 DTB. To allow a device tree enabled kernel to be used with such 1463 bootloaders, this option allows zImage to extract the information 1464 from the ATAG list and store it at run time into the appended DTB. 1465 1466choice 1467 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1468 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1469 1470config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1471 bool "Use bootloader kernel arguments if available" 1472 help 1473 Uses the command-line options passed by the boot loader instead of 1474 the device tree bootargs property. If the boot loader doesn't provide 1475 any, the device tree bootargs property will be used. 1476 1477config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1478 bool "Extend with bootloader kernel arguments" 1479 help 1480 The command-line arguments provided by the boot loader will be 1481 appended to the the device tree bootargs property. 1482 1483endchoice 1484 1485config CMDLINE 1486 string "Default kernel command string" 1487 default "" 1488 help 1489 On some architectures (e.g. CATS), there is currently no way 1490 for the boot loader to pass arguments to the kernel. For these 1491 architectures, you should supply some command-line options at build 1492 time by entering them here. As a minimum, you should specify the 1493 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1494 1495choice 1496 prompt "Kernel command line type" if CMDLINE != "" 1497 default CMDLINE_FROM_BOOTLOADER 1498 1499config CMDLINE_FROM_BOOTLOADER 1500 bool "Use bootloader kernel arguments if available" 1501 help 1502 Uses the command-line options passed by the boot loader. If 1503 the boot loader doesn't provide any, the default kernel command 1504 string provided in CMDLINE will be used. 1505 1506config CMDLINE_EXTEND 1507 bool "Extend bootloader kernel arguments" 1508 help 1509 The command-line arguments provided by the boot loader will be 1510 appended to the default kernel command string. 1511 1512config CMDLINE_FORCE 1513 bool "Always use the default kernel command string" 1514 help 1515 Always use the default kernel command string, even if the boot 1516 loader passes other arguments to the kernel. 1517 This is useful if you cannot or don't want to change the 1518 command-line options your boot loader passes to the kernel. 1519endchoice 1520 1521config XIP_KERNEL 1522 bool "Kernel Execute-In-Place from ROM" 1523 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1524 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1525 help 1526 Execute-In-Place allows the kernel to run from non-volatile storage 1527 directly addressable by the CPU, such as NOR flash. This saves RAM 1528 space since the text section of the kernel is not loaded from flash 1529 to RAM. Read-write sections, such as the data section and stack, 1530 are still copied to RAM. The XIP kernel is not compressed since 1531 it has to run directly from flash, so it will take more space to 1532 store it. The flash address used to link the kernel object files, 1533 and for storing it, is configuration dependent. Therefore, if you 1534 say Y here, you must know the proper physical address where to 1535 store the kernel image depending on your own flash memory usage. 1536 1537 Also note that the make target becomes "make xipImage" rather than 1538 "make zImage" or "make Image". The final kernel binary to put in 1539 ROM memory will be arch/arm/boot/xipImage. 1540 1541 If unsure, say N. 1542 1543config XIP_PHYS_ADDR 1544 hex "XIP Kernel Physical Location" 1545 depends on XIP_KERNEL 1546 default "0x00080000" 1547 help 1548 This is the physical address in your flash memory the kernel will 1549 be linked for and stored to. This address is dependent on your 1550 own flash usage. 1551 1552config XIP_DEFLATED_DATA 1553 bool "Store kernel .data section compressed in ROM" 1554 depends on XIP_KERNEL 1555 select ZLIB_INFLATE 1556 help 1557 Before the kernel is actually executed, its .data section has to be 1558 copied to RAM from ROM. This option allows for storing that data 1559 in compressed form and decompressed to RAM rather than merely being 1560 copied, saving some precious ROM space. A possible drawback is a 1561 slightly longer boot delay. 1562 1563config ARCH_SUPPORTS_KEXEC 1564 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1565 1566config ATAGS_PROC 1567 bool "Export atags in procfs" 1568 depends on ATAGS && KEXEC 1569 default y 1570 help 1571 Should the atags used to boot the kernel be exported in an "atags" 1572 file in procfs. Useful with kexec. 1573 1574config ARCH_SUPPORTS_CRASH_DUMP 1575 def_bool y 1576 1577config AUTO_ZRELADDR 1578 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1579 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1580 help 1581 ZRELADDR is the physical address where the decompressed kernel 1582 image will be placed. If AUTO_ZRELADDR is selected, the address 1583 will be determined at run-time, either by masking the current IP 1584 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1585 This assumes the zImage being placed in the first 128MB from 1586 start of memory. 1587 1588config EFI_STUB 1589 bool 1590 1591config EFI 1592 bool "UEFI runtime support" 1593 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1594 select UCS2_STRING 1595 select EFI_PARAMS_FROM_FDT 1596 select EFI_STUB 1597 select EFI_GENERIC_STUB 1598 select EFI_RUNTIME_WRAPPERS 1599 help 1600 This option provides support for runtime services provided 1601 by UEFI firmware (such as non-volatile variables, realtime 1602 clock, and platform reset). A UEFI stub is also provided to 1603 allow the kernel to be booted as an EFI application. This 1604 is only useful for kernels that may run on systems that have 1605 UEFI firmware. 1606 1607config DMI 1608 bool "Enable support for SMBIOS (DMI) tables" 1609 depends on EFI 1610 default y 1611 help 1612 This enables SMBIOS/DMI feature for systems. 1613 1614 This option is only useful on systems that have UEFI firmware. 1615 However, even with this option, the resultant kernel should 1616 continue to boot on existing non-UEFI platforms. 1617 1618 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1619 i.e., the the practice of identifying the platform via DMI to 1620 decide whether certain workarounds for buggy hardware and/or 1621 firmware need to be enabled. This would require the DMI subsystem 1622 to be enabled much earlier than we do on ARM, which is non-trivial. 1623 1624endmenu 1625 1626menu "CPU Power Management" 1627 1628source "drivers/cpufreq/Kconfig" 1629 1630source "drivers/cpuidle/Kconfig" 1631 1632endmenu 1633 1634menu "Floating point emulation" 1635 1636comment "At least one emulation must be selected" 1637 1638config FPE_NWFPE 1639 bool "NWFPE math emulation" 1640 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1641 help 1642 Say Y to include the NWFPE floating point emulator in the kernel. 1643 This is necessary to run most binaries. Linux does not currently 1644 support floating point hardware so you need to say Y here even if 1645 your machine has an FPA or floating point co-processor podule. 1646 1647 You may say N here if you are going to load the Acorn FPEmulator 1648 early in the bootup. 1649 1650config FPE_NWFPE_XP 1651 bool "Support extended precision" 1652 depends on FPE_NWFPE 1653 help 1654 Say Y to include 80-bit support in the kernel floating-point 1655 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1656 Note that gcc does not generate 80-bit operations by default, 1657 so in most cases this option only enlarges the size of the 1658 floating point emulator without any good reason. 1659 1660 You almost surely want to say N here. 1661 1662config FPE_FASTFPE 1663 bool "FastFPE math emulation (EXPERIMENTAL)" 1664 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1665 help 1666 Say Y here to include the FAST floating point emulator in the kernel. 1667 This is an experimental much faster emulator which now also has full 1668 precision for the mantissa. It does not support any exceptions. 1669 It is very simple, and approximately 3-6 times faster than NWFPE. 1670 1671 It should be sufficient for most programs. It may be not suitable 1672 for scientific calculations, but you have to check this for yourself. 1673 If you do not feel you need a faster FP emulation you should better 1674 choose NWFPE. 1675 1676config VFP 1677 bool "VFP-format floating point maths" 1678 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1679 help 1680 Say Y to include VFP support code in the kernel. This is needed 1681 if your hardware includes a VFP unit. 1682 1683 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1684 release notes and additional status information. 1685 1686 Say N if your target does not have VFP hardware. 1687 1688config VFPv3 1689 bool 1690 depends on VFP 1691 default y if CPU_V7 1692 1693config NEON 1694 bool "Advanced SIMD (NEON) Extension support" 1695 depends on VFPv3 && CPU_V7 1696 help 1697 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1698 Extension. 1699 1700config KERNEL_MODE_NEON 1701 bool "Support for NEON in kernel mode" 1702 depends on NEON && AEABI 1703 help 1704 Say Y to include support for NEON in kernel mode. 1705 1706endmenu 1707 1708menu "Power management options" 1709 1710source "kernel/power/Kconfig" 1711 1712config ARCH_SUSPEND_POSSIBLE 1713 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1714 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1715 def_bool y 1716 1717config ARM_CPU_SUSPEND 1718 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1719 depends on ARCH_SUSPEND_POSSIBLE 1720 1721config ARCH_HIBERNATION_POSSIBLE 1722 bool 1723 depends on MMU 1724 default y if ARCH_SUSPEND_POSSIBLE 1725 1726endmenu 1727 1728source "arch/arm/Kconfig.assembler" 1729