1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CURRENT_STACK_POINTER 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 11 select ARCH_HAS_ELF_RANDOMIZE 12 select ARCH_HAS_FORTIFY_SOURCE 13 select ARCH_HAS_KEEPINITRD 14 select ARCH_HAS_KCOV 15 select ARCH_HAS_MEMBARRIER_SYNC_CORE 16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_STACKWALK 21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 22 select ARCH_HAS_STRICT_MODULE_RWX if MMU 23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 24 select ARCH_HAS_SYNC_DMA_FOR_CPU 25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 27 select ARCH_HAVE_CUSTOM_GPIO_H 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 74 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 75 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 76 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 77 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 78 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 79 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 80 select HAVE_ARCH_MMAP_RND_BITS if MMU 81 select HAVE_ARCH_PFN_VALID 82 select HAVE_ARCH_SECCOMP 83 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 85 select HAVE_ARCH_TRACEHOOK 86 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 87 select HAVE_ARM_SMCCC if CPU_V7 88 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 89 select HAVE_CONTEXT_TRACKING_USER 90 select HAVE_C_RECORDMCOUNT 91 select HAVE_BUILDTIME_MCOUNT_SORT 92 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 93 select HAVE_DMA_CONTIGUOUS if MMU 94 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 95 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 96 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 97 select HAVE_EXIT_THREAD 98 select HAVE_FAST_GUP if ARM_LPAE 99 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 100 select HAVE_FUNCTION_ERROR_INJECTION 101 select HAVE_FUNCTION_GRAPH_TRACER 102 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 103 select HAVE_GCC_PLUGINS 104 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 105 select HAVE_IRQ_TIME_ACCOUNTING 106 select HAVE_KERNEL_GZIP 107 select HAVE_KERNEL_LZ4 108 select HAVE_KERNEL_LZMA 109 select HAVE_KERNEL_LZO 110 select HAVE_KERNEL_XZ 111 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 112 select HAVE_KRETPROBES if HAVE_KPROBES 113 select HAVE_MOD_ARCH_SPECIFIC 114 select HAVE_NMI 115 select HAVE_OPTPROBES if !THUMB2_KERNEL 116 select HAVE_PCI if MMU 117 select HAVE_PERF_EVENTS 118 select HAVE_PERF_REGS 119 select HAVE_PERF_USER_STACK_DUMP 120 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 121 select HAVE_REGS_AND_STACK_ACCESS_API 122 select HAVE_RSEQ 123 select HAVE_STACKPROTECTOR 124 select HAVE_SYSCALL_TRACEPOINTS 125 select HAVE_UID16 126 select HAVE_VIRT_CPU_ACCOUNTING_GEN 127 select IRQ_FORCED_THREADING 128 select MODULES_USE_ELF_REL 129 select NEED_DMA_MAP_STATE 130 select OF_EARLY_FLATTREE if OF 131 select OLD_SIGACTION 132 select OLD_SIGSUSPEND3 133 select PCI_DOMAINS_GENERIC if PCI 134 select PCI_SYSCALL if PCI 135 select PERF_USE_VMALLOC 136 select RTC_LIB 137 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 138 select SYS_SUPPORTS_APM_EMULATION 139 select THREAD_INFO_IN_TASK 140 select TIMER_OF if OF 141 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 142 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 143 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 144 # Above selects are sorted alphabetically; please add new ones 145 # according to that. Thanks. 146 help 147 The ARM series is a line of low-power-consumption RISC chip designs 148 licensed by ARM Ltd and targeted at embedded applications and 149 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 150 manufactured, but legacy ARM-based PC hardware remains popular in 151 Europe. There is an ARM Linux project with a web page at 152 <http://www.arm.linux.org.uk/>. 153 154config ARM_HAS_GROUP_RELOCS 155 def_bool y 156 depends on !LD_IS_LLD || LLD_VERSION >= 140000 157 depends on !COMPILE_TEST 158 help 159 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 160 relocations, which have been around for a long time, but were not 161 supported in LLD until version 14. The combined range is -/+ 256 MiB, 162 which is usually sufficient, but not for allyesconfig, so we disable 163 this feature when doing compile testing. 164 165config ARM_DMA_USE_IOMMU 166 bool 167 select NEED_SG_DMA_LENGTH 168 169if ARM_DMA_USE_IOMMU 170 171config ARM_DMA_IOMMU_ALIGNMENT 172 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 173 range 4 9 174 default 8 175 help 176 DMA mapping framework by default aligns all buffers to the smallest 177 PAGE_SIZE order which is greater than or equal to the requested buffer 178 size. This works well for buffers up to a few hundreds kilobytes, but 179 for larger buffers it just a waste of address space. Drivers which has 180 relatively small addressing window (like 64Mib) might run out of 181 virtual space with just a few allocations. 182 183 With this parameter you can specify the maximum PAGE_SIZE order for 184 DMA IOMMU buffers. Larger buffers will be aligned only to this 185 specified order. The order is expressed as a power of two multiplied 186 by the PAGE_SIZE. 187 188endif 189 190config SYS_SUPPORTS_APM_EMULATION 191 bool 192 193config HAVE_TCM 194 bool 195 select GENERIC_ALLOCATOR 196 197config HAVE_PROC_CPU 198 bool 199 200config NO_IOPORT_MAP 201 bool 202 203config SBUS 204 bool 205 206config STACKTRACE_SUPPORT 207 bool 208 default y 209 210config LOCKDEP_SUPPORT 211 bool 212 default y 213 214config ARCH_HAS_ILOG2_U32 215 bool 216 217config ARCH_HAS_ILOG2_U64 218 bool 219 220config ARCH_HAS_BANDGAP 221 bool 222 223config FIX_EARLYCON_MEM 224 def_bool y if MMU 225 226config GENERIC_HWEIGHT 227 bool 228 default y 229 230config GENERIC_CALIBRATE_DELAY 231 bool 232 default y 233 234config ARCH_MAY_HAVE_PC_FDC 235 bool 236 237config ARCH_SUPPORTS_UPROBES 238 def_bool y 239 240config GENERIC_ISA_DMA 241 bool 242 243config FIQ 244 bool 245 246config ARCH_MTD_XIP 247 bool 248 249config ARM_PATCH_PHYS_VIRT 250 bool "Patch physical to virtual translations at runtime" if EMBEDDED 251 default y 252 depends on MMU 253 help 254 Patch phys-to-virt and virt-to-phys translation functions at 255 boot and module load time according to the position of the 256 kernel in system memory. 257 258 This can only be used with non-XIP MMU kernels where the base 259 of physical memory is at a 2 MiB boundary. 260 261 Only disable this option if you know that you do not require 262 this feature (eg, building a kernel for a single machine) and 263 you need to shrink the kernel to the minimal size. 264 265config NEED_MACH_IO_H 266 bool 267 help 268 Select this when mach/io.h is required to provide special 269 definitions for this platform. The need for mach/io.h should 270 be avoided when possible. 271 272config NEED_MACH_MEMORY_H 273 bool 274 help 275 Select this when mach/memory.h is required to provide special 276 definitions for this platform. The need for mach/memory.h should 277 be avoided when possible. 278 279config PHYS_OFFSET 280 hex "Physical address of main memory" if MMU 281 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 282 default DRAM_BASE if !MMU 283 default 0x00000000 if ARCH_FOOTBRIDGE 284 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 285 default 0x30000000 if ARCH_S3C24XX 286 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA 287 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 288 default 0 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARM_SINGLE_ARMV7M 312 def_bool !MMU 313 select ARM_NVIC 314 select CPU_V7M 315 select NO_IOPORT_MAP 316 317config ARCH_MMAP_RND_BITS_MIN 318 default 8 319 320config ARCH_MMAP_RND_BITS_MAX 321 default 14 if PAGE_OFFSET=0x40000000 322 default 15 if PAGE_OFFSET=0x80000000 323 default 16 324 325config ARCH_MULTIPLATFORM 326 bool "Require kernel to be portable to multiple machines" if EXPERT 327 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 328 default y 329 help 330 In general, all Arm machines can be supported in a single 331 kernel image, covering either Armv4/v5 or Armv6/v7. 332 333 However, some configuration options require hardcoding machine 334 specific physical addresses or enable errata workarounds that may 335 break other machines. 336 337 Selecting N here allows using those options, including 338 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 339 340menu "Platform selection" 341 depends on MMU 342 343comment "CPU Core family selection" 344 345config ARCH_MULTI_V4 346 bool "ARMv4 based platforms (FA526, StrongARM)" 347 depends on !ARCH_MULTI_V6_V7 348 select ARCH_MULTI_V4_V5 349 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 350 351config ARCH_MULTI_V4T 352 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 353 depends on !ARCH_MULTI_V6_V7 354 select ARCH_MULTI_V4_V5 355 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 356 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 357 CPU_ARM925T || CPU_ARM940T) 358 359config ARCH_MULTI_V5 360 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 361 depends on !ARCH_MULTI_V6_V7 362 select ARCH_MULTI_V4_V5 363 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 364 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 365 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 366 367config ARCH_MULTI_V4_V5 368 bool 369 370config ARCH_MULTI_V6 371 bool "ARMv6 based platforms (ARM11)" 372 select ARCH_MULTI_V6_V7 373 select CPU_V6K 374 375config ARCH_MULTI_V7 376 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 377 default y 378 select ARCH_MULTI_V6_V7 379 select CPU_V7 380 select HAVE_SMP 381 382config ARCH_MULTI_V6_V7 383 bool 384 select MIGHT_HAVE_CACHE_L2X0 385 386config ARCH_MULTI_CPU_AUTO 387 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 388 select ARCH_MULTI_V5 389 390endmenu 391 392config ARCH_VIRT 393 bool "Dummy Virtual Machine" 394 depends on ARCH_MULTI_V7 395 select ARM_AMBA 396 select ARM_GIC 397 select ARM_GIC_V2M if PCI 398 select ARM_GIC_V3 399 select ARM_GIC_V3_ITS if PCI 400 select ARM_PSCI 401 select HAVE_ARM_ARCH_TIMER 402 403config ARCH_AIROHA 404 bool "Airoha SoC Support" 405 depends on ARCH_MULTI_V7 406 select ARM_AMBA 407 select ARM_GIC 408 select ARM_GIC_V3 409 select ARM_PSCI 410 select HAVE_ARM_ARCH_TIMER 411 help 412 Support for Airoha EN7523 SoCs 413 414# 415# This is sorted alphabetically by mach-* pathname. However, plat-* 416# Kconfigs may be included either alphabetically (according to the 417# plat- suffix) or along side the corresponding mach-* source. 418# 419source "arch/arm/mach-actions/Kconfig" 420 421source "arch/arm/mach-alpine/Kconfig" 422 423source "arch/arm/mach-artpec/Kconfig" 424 425source "arch/arm/mach-asm9260/Kconfig" 426 427source "arch/arm/mach-aspeed/Kconfig" 428 429source "arch/arm/mach-at91/Kconfig" 430 431source "arch/arm/mach-axxia/Kconfig" 432 433source "arch/arm/mach-bcm/Kconfig" 434 435source "arch/arm/mach-berlin/Kconfig" 436 437source "arch/arm/mach-clps711x/Kconfig" 438 439source "arch/arm/mach-cns3xxx/Kconfig" 440 441source "arch/arm/mach-davinci/Kconfig" 442 443source "arch/arm/mach-digicolor/Kconfig" 444 445source "arch/arm/mach-dove/Kconfig" 446 447source "arch/arm/mach-ep93xx/Kconfig" 448 449source "arch/arm/mach-exynos/Kconfig" 450 451source "arch/arm/mach-footbridge/Kconfig" 452 453source "arch/arm/mach-gemini/Kconfig" 454 455source "arch/arm/mach-highbank/Kconfig" 456 457source "arch/arm/mach-hisi/Kconfig" 458 459source "arch/arm/mach-hpe/Kconfig" 460 461source "arch/arm/mach-imx/Kconfig" 462 463source "arch/arm/mach-iop32x/Kconfig" 464 465source "arch/arm/mach-ixp4xx/Kconfig" 466 467source "arch/arm/mach-keystone/Kconfig" 468 469source "arch/arm/mach-lpc32xx/Kconfig" 470 471source "arch/arm/mach-mediatek/Kconfig" 472 473source "arch/arm/mach-meson/Kconfig" 474 475source "arch/arm/mach-milbeaut/Kconfig" 476 477source "arch/arm/mach-mmp/Kconfig" 478 479source "arch/arm/mach-moxart/Kconfig" 480 481source "arch/arm/mach-mstar/Kconfig" 482 483source "arch/arm/mach-mv78xx0/Kconfig" 484 485source "arch/arm/mach-mvebu/Kconfig" 486 487source "arch/arm/mach-mxs/Kconfig" 488 489source "arch/arm/mach-nomadik/Kconfig" 490 491source "arch/arm/mach-npcm/Kconfig" 492 493source "arch/arm/mach-nspire/Kconfig" 494 495source "arch/arm/mach-omap1/Kconfig" 496 497source "arch/arm/mach-omap2/Kconfig" 498 499source "arch/arm/mach-orion5x/Kconfig" 500 501source "arch/arm/mach-oxnas/Kconfig" 502 503source "arch/arm/mach-pxa/Kconfig" 504 505source "arch/arm/mach-qcom/Kconfig" 506 507source "arch/arm/mach-rda/Kconfig" 508 509source "arch/arm/mach-realtek/Kconfig" 510 511source "arch/arm/mach-rpc/Kconfig" 512 513source "arch/arm/mach-rockchip/Kconfig" 514 515source "arch/arm/mach-s3c/Kconfig" 516 517source "arch/arm/mach-s5pv210/Kconfig" 518 519source "arch/arm/mach-sa1100/Kconfig" 520 521source "arch/arm/mach-shmobile/Kconfig" 522 523source "arch/arm/mach-socfpga/Kconfig" 524 525source "arch/arm/mach-spear/Kconfig" 526 527source "arch/arm/mach-sti/Kconfig" 528 529source "arch/arm/mach-stm32/Kconfig" 530 531source "arch/arm/mach-sunplus/Kconfig" 532 533source "arch/arm/mach-sunxi/Kconfig" 534 535source "arch/arm/mach-tegra/Kconfig" 536 537source "arch/arm/mach-uniphier/Kconfig" 538 539source "arch/arm/mach-ux500/Kconfig" 540 541source "arch/arm/mach-versatile/Kconfig" 542 543source "arch/arm/mach-vt8500/Kconfig" 544 545source "arch/arm/mach-zynq/Kconfig" 546 547# ARMv7-M architecture 548config ARCH_LPC18XX 549 bool "NXP LPC18xx/LPC43xx" 550 depends on ARM_SINGLE_ARMV7M 551 select ARCH_HAS_RESET_CONTROLLER 552 select ARM_AMBA 553 select CLKSRC_LPC32XX 554 select PINCTRL 555 help 556 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 557 high performance microcontrollers. 558 559config ARCH_MPS2 560 bool "ARM MPS2 platform" 561 depends on ARM_SINGLE_ARMV7M 562 select ARM_AMBA 563 select CLKSRC_MPS2 564 help 565 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 566 with a range of available cores like Cortex-M3/M4/M7. 567 568 Please, note that depends which Application Note is used memory map 569 for the platform may vary, so adjustment of RAM base might be needed. 570 571# Definitions to make life easier 572config ARCH_ACORN 573 bool 574 575config PLAT_ORION 576 bool 577 select CLKSRC_MMIO 578 select GENERIC_IRQ_CHIP 579 select IRQ_DOMAIN 580 581config PLAT_ORION_LEGACY 582 bool 583 select PLAT_ORION 584 585config PLAT_VERSATILE 586 bool 587 588source "arch/arm/mm/Kconfig" 589 590config IWMMXT 591 bool "Enable iWMMXt support" 592 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 593 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 594 help 595 Enable support for iWMMXt context switching at run time if 596 running on a CPU that supports it. 597 598if !MMU 599source "arch/arm/Kconfig-nommu" 600endif 601 602config PJ4B_ERRATA_4742 603 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 604 depends on CPU_PJ4B && MACH_ARMADA_370 605 default y 606 help 607 When coming out of either a Wait for Interrupt (WFI) or a Wait for 608 Event (WFE) IDLE states, a specific timing sensitivity exists between 609 the retiring WFI/WFE instructions and the newly issued subsequent 610 instructions. This sensitivity can result in a CPU hang scenario. 611 Workaround: 612 The software must insert either a Data Synchronization Barrier (DSB) 613 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 614 instruction 615 616config ARM_ERRATA_326103 617 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 618 depends on CPU_V6 619 help 620 Executing a SWP instruction to read-only memory does not set bit 11 621 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 622 treat the access as a read, preventing a COW from occurring and 623 causing the faulting task to livelock. 624 625config ARM_ERRATA_411920 626 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 627 depends on CPU_V6 || CPU_V6K 628 help 629 Invalidation of the Instruction Cache operation can 630 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 631 It does not affect the MPCore. This option enables the ARM Ltd. 632 recommended workaround. 633 634config ARM_ERRATA_430973 635 bool "ARM errata: Stale prediction on replaced interworking branch" 636 depends on CPU_V7 637 help 638 This option enables the workaround for the 430973 Cortex-A8 639 r1p* erratum. If a code sequence containing an ARM/Thumb 640 interworking branch is replaced with another code sequence at the 641 same virtual address, whether due to self-modifying code or virtual 642 to physical address re-mapping, Cortex-A8 does not recover from the 643 stale interworking branch prediction. This results in Cortex-A8 644 executing the new code sequence in the incorrect ARM or Thumb state. 645 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 646 and also flushes the branch target cache at every context switch. 647 Note that setting specific bits in the ACTLR register may not be 648 available in non-secure mode. 649 650config ARM_ERRATA_458693 651 bool "ARM errata: Processor deadlock when a false hazard is created" 652 depends on CPU_V7 653 depends on !ARCH_MULTIPLATFORM 654 help 655 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 656 erratum. For very specific sequences of memory operations, it is 657 possible for a hazard condition intended for a cache line to instead 658 be incorrectly associated with a different cache line. This false 659 hazard might then cause a processor deadlock. The workaround enables 660 the L1 caching of the NEON accesses and disables the PLD instruction 661 in the ACTLR register. Note that setting specific bits in the ACTLR 662 register may not be available in non-secure mode. 663 664config ARM_ERRATA_460075 665 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 666 depends on CPU_V7 667 depends on !ARCH_MULTIPLATFORM 668 help 669 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 670 erratum. Any asynchronous access to the L2 cache may encounter a 671 situation in which recent store transactions to the L2 cache are lost 672 and overwritten with stale memory contents from external memory. The 673 workaround disables the write-allocate mode for the L2 cache via the 674 ACTLR register. Note that setting specific bits in the ACTLR register 675 may not be available in non-secure mode. 676 677config ARM_ERRATA_742230 678 bool "ARM errata: DMB operation may be faulty" 679 depends on CPU_V7 && SMP 680 depends on !ARCH_MULTIPLATFORM 681 help 682 This option enables the workaround for the 742230 Cortex-A9 683 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 684 between two write operations may not ensure the correct visibility 685 ordering of the two writes. This workaround sets a specific bit in 686 the diagnostic register of the Cortex-A9 which causes the DMB 687 instruction to behave as a DSB, ensuring the correct behaviour of 688 the two writes. 689 690config ARM_ERRATA_742231 691 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 692 depends on CPU_V7 && SMP 693 depends on !ARCH_MULTIPLATFORM 694 help 695 This option enables the workaround for the 742231 Cortex-A9 696 (r2p0..r2p2) erratum. Under certain conditions, specific to the 697 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 698 accessing some data located in the same cache line, may get corrupted 699 data due to bad handling of the address hazard when the line gets 700 replaced from one of the CPUs at the same time as another CPU is 701 accessing it. This workaround sets specific bits in the diagnostic 702 register of the Cortex-A9 which reduces the linefill issuing 703 capabilities of the processor. 704 705config ARM_ERRATA_643719 706 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 707 depends on CPU_V7 && SMP 708 default y 709 help 710 This option enables the workaround for the 643719 Cortex-A9 (prior to 711 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 712 register returns zero when it should return one. The workaround 713 corrects this value, ensuring cache maintenance operations which use 714 it behave as intended and avoiding data corruption. 715 716config ARM_ERRATA_720789 717 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 718 depends on CPU_V7 719 help 720 This option enables the workaround for the 720789 Cortex-A9 (prior to 721 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 722 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 723 As a consequence of this erratum, some TLB entries which should be 724 invalidated are not, resulting in an incoherency in the system page 725 tables. The workaround changes the TLB flushing routines to invalidate 726 entries regardless of the ASID. 727 728config ARM_ERRATA_743622 729 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 730 depends on CPU_V7 731 depends on !ARCH_MULTIPLATFORM 732 help 733 This option enables the workaround for the 743622 Cortex-A9 734 (r2p*) erratum. Under very rare conditions, a faulty 735 optimisation in the Cortex-A9 Store Buffer may lead to data 736 corruption. This workaround sets a specific bit in the diagnostic 737 register of the Cortex-A9 which disables the Store Buffer 738 optimisation, preventing the defect from occurring. This has no 739 visible impact on the overall performance or power consumption of the 740 processor. 741 742config ARM_ERRATA_751472 743 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 744 depends on CPU_V7 745 depends on !ARCH_MULTIPLATFORM 746 help 747 This option enables the workaround for the 751472 Cortex-A9 (prior 748 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 749 completion of a following broadcasted operation if the second 750 operation is received by a CPU before the ICIALLUIS has completed, 751 potentially leading to corrupted entries in the cache or TLB. 752 753config ARM_ERRATA_754322 754 bool "ARM errata: possible faulty MMU translations following an ASID switch" 755 depends on CPU_V7 756 help 757 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 758 r3p*) erratum. A speculative memory access may cause a page table walk 759 which starts prior to an ASID switch but completes afterwards. This 760 can populate the micro-TLB with a stale entry which may be hit with 761 the new ASID. This workaround places two dsb instructions in the mm 762 switching code so that no page table walks can cross the ASID switch. 763 764config ARM_ERRATA_754327 765 bool "ARM errata: no automatic Store Buffer drain" 766 depends on CPU_V7 && SMP 767 help 768 This option enables the workaround for the 754327 Cortex-A9 (prior to 769 r2p0) erratum. The Store Buffer does not have any automatic draining 770 mechanism and therefore a livelock may occur if an external agent 771 continuously polls a memory location waiting to observe an update. 772 This workaround defines cpu_relax() as smp_mb(), preventing correctly 773 written polling loops from denying visibility of updates to memory. 774 775config ARM_ERRATA_364296 776 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 777 depends on CPU_V6 778 help 779 This options enables the workaround for the 364296 ARM1136 780 r0p2 erratum (possible cache data corruption with 781 hit-under-miss enabled). It sets the undocumented bit 31 in 782 the auxiliary control register and the FI bit in the control 783 register, thus disabling hit-under-miss without putting the 784 processor into full low interrupt latency mode. ARM11MPCore 785 is not affected. 786 787config ARM_ERRATA_764369 788 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 789 depends on CPU_V7 && SMP 790 help 791 This option enables the workaround for erratum 764369 792 affecting Cortex-A9 MPCore with two or more processors (all 793 current revisions). Under certain timing circumstances, a data 794 cache line maintenance operation by MVA targeting an Inner 795 Shareable memory region may fail to proceed up to either the 796 Point of Coherency or to the Point of Unification of the 797 system. This workaround adds a DSB instruction before the 798 relevant cache maintenance functions and sets a specific bit 799 in the diagnostic control register of the SCU. 800 801config ARM_ERRATA_764319 802 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 803 depends on CPU_V7 804 help 805 This option enables the workaround for the 764319 Cortex A-9 erratum. 806 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 807 unexpected Undefined Instruction exception when the DBGSWENABLE 808 external pin is set to 0, even when the CP14 accesses are performed 809 from a privileged mode. This work around catches the exception in a 810 way the kernel does not stop execution. 811 812config ARM_ERRATA_775420 813 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 814 depends on CPU_V7 815 help 816 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 817 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 818 operation aborts with MMU exception, it might cause the processor 819 to deadlock. This workaround puts DSB before executing ISB if 820 an abort may occur on cache maintenance. 821 822config ARM_ERRATA_798181 823 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 824 depends on CPU_V7 && SMP 825 help 826 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 827 adequately shooting down all use of the old entries. This 828 option enables the Linux kernel workaround for this erratum 829 which sends an IPI to the CPUs that are running the same ASID 830 as the one being invalidated. 831 832config ARM_ERRATA_773022 833 bool "ARM errata: incorrect instructions may be executed from loop buffer" 834 depends on CPU_V7 835 help 836 This option enables the workaround for the 773022 Cortex-A15 837 (up to r0p4) erratum. In certain rare sequences of code, the 838 loop buffer may deliver incorrect instructions. This 839 workaround disables the loop buffer to avoid the erratum. 840 841config ARM_ERRATA_818325_852422 842 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 843 depends on CPU_V7 844 help 845 This option enables the workaround for: 846 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 847 instruction might deadlock. Fixed in r0p1. 848 - Cortex-A12 852422: Execution of a sequence of instructions might 849 lead to either a data corruption or a CPU deadlock. Not fixed in 850 any Cortex-A12 cores yet. 851 This workaround for all both errata involves setting bit[12] of the 852 Feature Register. This bit disables an optimisation applied to a 853 sequence of 2 instructions that use opposing condition codes. 854 855config ARM_ERRATA_821420 856 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 857 depends on CPU_V7 858 help 859 This option enables the workaround for the 821420 Cortex-A12 860 (all revs) erratum. In very rare timing conditions, a sequence 861 of VMOV to Core registers instructions, for which the second 862 one is in the shadow of a branch or abort, can lead to a 863 deadlock when the VMOV instructions are issued out-of-order. 864 865config ARM_ERRATA_825619 866 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 867 depends on CPU_V7 868 help 869 This option enables the workaround for the 825619 Cortex-A12 870 (all revs) erratum. Within rare timing constraints, executing a 871 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 872 and Device/Strongly-Ordered loads and stores might cause deadlock 873 874config ARM_ERRATA_857271 875 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 876 depends on CPU_V7 877 help 878 This option enables the workaround for the 857271 Cortex-A12 879 (all revs) erratum. Under very rare timing conditions, the CPU might 880 hang. The workaround is expected to have a < 1% performance impact. 881 882config ARM_ERRATA_852421 883 bool "ARM errata: A17: DMB ST might fail to create order between stores" 884 depends on CPU_V7 885 help 886 This option enables the workaround for the 852421 Cortex-A17 887 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 888 execution of a DMB ST instruction might fail to properly order 889 stores from GroupA and stores from GroupB. 890 891config ARM_ERRATA_852423 892 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 893 depends on CPU_V7 894 help 895 This option enables the workaround for: 896 - Cortex-A17 852423: Execution of a sequence of instructions might 897 lead to either a data corruption or a CPU deadlock. Not fixed in 898 any Cortex-A17 cores yet. 899 This is identical to Cortex-A12 erratum 852422. It is a separate 900 config option from the A12 erratum due to the way errata are checked 901 for and handled. 902 903config ARM_ERRATA_857272 904 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 905 depends on CPU_V7 906 help 907 This option enables the workaround for the 857272 Cortex-A17 erratum. 908 This erratum is not known to be fixed in any A17 revision. 909 This is identical to Cortex-A12 erratum 857271. It is a separate 910 config option from the A12 erratum due to the way errata are checked 911 for and handled. 912 913endmenu 914 915source "arch/arm/common/Kconfig" 916 917menu "Bus support" 918 919config ISA 920 bool 921 help 922 Find out whether you have ISA slots on your motherboard. ISA is the 923 name of a bus system, i.e. the way the CPU talks to the other stuff 924 inside your box. Other bus systems are PCI, EISA, MicroChannel 925 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 926 newer boards don't support it. If you have ISA, say Y, otherwise N. 927 928# Select ISA DMA interface 929config ISA_DMA_API 930 bool 931 932config PCI_NANOENGINE 933 bool "BSE nanoEngine PCI support" 934 depends on SA1100_NANOENGINE 935 help 936 Enable PCI on the BSE nanoEngine board. 937 938config ARM_ERRATA_814220 939 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 940 depends on CPU_V7 941 help 942 The v7 ARM states that all cache and branch predictor maintenance 943 operations that do not specify an address execute, relative to 944 each other, in program order. 945 However, because of this erratum, an L2 set/way cache maintenance 946 operation can overtake an L1 set/way cache maintenance operation. 947 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 948 r0p4, r0p5. 949 950endmenu 951 952menu "Kernel Features" 953 954config HAVE_SMP 955 bool 956 help 957 This option should be selected by machines which have an SMP- 958 capable CPU. 959 960 The only effect of this option is to make the SMP-related 961 options available to the user for configuration. 962 963config SMP 964 bool "Symmetric Multi-Processing" 965 depends on CPU_V6K || CPU_V7 966 depends on HAVE_SMP 967 depends on MMU || ARM_MPU 968 select IRQ_WORK 969 help 970 This enables support for systems with more than one CPU. If you have 971 a system with only one CPU, say N. If you have a system with more 972 than one CPU, say Y. 973 974 If you say N here, the kernel will run on uni- and multiprocessor 975 machines, but will use only one CPU of a multiprocessor machine. If 976 you say Y here, the kernel will run on many, but not all, 977 uniprocessor machines. On a uniprocessor machine, the kernel 978 will run faster if you say N here. 979 980 See also <file:Documentation/x86/i386/IO-APIC.rst>, 981 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 982 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 983 984 If you don't know what to do here, say N. 985 986config SMP_ON_UP 987 bool "Allow booting SMP kernel on uniprocessor systems" 988 depends on SMP && MMU 989 default y 990 help 991 SMP kernels contain instructions which fail on non-SMP processors. 992 Enabling this option allows the kernel to modify itself to make 993 these instructions safe. Disabling it allows about 1K of space 994 savings. 995 996 If you don't know what to do here, say Y. 997 998 999config CURRENT_POINTER_IN_TPIDRURO 1000 def_bool y 1001 depends on CPU_32v6K && !CPU_V6 1002 1003config IRQSTACKS 1004 def_bool y 1005 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1006 select HAVE_SOFTIRQ_ON_OWN_STACK 1007 1008config ARM_CPU_TOPOLOGY 1009 bool "Support cpu topology definition" 1010 depends on SMP && CPU_V7 1011 default y 1012 help 1013 Support ARM cpu topology definition. The MPIDR register defines 1014 affinity between processors which is then used to describe the cpu 1015 topology of an ARM System. 1016 1017config SCHED_MC 1018 bool "Multi-core scheduler support" 1019 depends on ARM_CPU_TOPOLOGY 1020 help 1021 Multi-core scheduler support improves the CPU scheduler's decision 1022 making when dealing with multi-core CPU chips at a cost of slightly 1023 increased overhead in some places. If unsure say N here. 1024 1025config SCHED_SMT 1026 bool "SMT scheduler support" 1027 depends on ARM_CPU_TOPOLOGY 1028 help 1029 Improves the CPU scheduler's decision making when dealing with 1030 MultiThreading at a cost of slightly increased overhead in some 1031 places. If unsure say N here. 1032 1033config HAVE_ARM_SCU 1034 bool 1035 help 1036 This option enables support for the ARM snoop control unit 1037 1038config HAVE_ARM_ARCH_TIMER 1039 bool "Architected timer support" 1040 depends on CPU_V7 1041 select ARM_ARCH_TIMER 1042 help 1043 This option enables support for the ARM architected timer 1044 1045config HAVE_ARM_TWD 1046 bool 1047 help 1048 This options enables support for the ARM timer and watchdog unit 1049 1050config MCPM 1051 bool "Multi-Cluster Power Management" 1052 depends on CPU_V7 && SMP 1053 help 1054 This option provides the common power management infrastructure 1055 for (multi-)cluster based systems, such as big.LITTLE based 1056 systems. 1057 1058config MCPM_QUAD_CLUSTER 1059 bool 1060 depends on MCPM 1061 help 1062 To avoid wasting resources unnecessarily, MCPM only supports up 1063 to 2 clusters by default. 1064 Platforms with 3 or 4 clusters that use MCPM must select this 1065 option to allow the additional clusters to be managed. 1066 1067config BIG_LITTLE 1068 bool "big.LITTLE support (Experimental)" 1069 depends on CPU_V7 && SMP 1070 select MCPM 1071 help 1072 This option enables support selections for the big.LITTLE 1073 system architecture. 1074 1075config BL_SWITCHER 1076 bool "big.LITTLE switcher support" 1077 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1078 select CPU_PM 1079 help 1080 The big.LITTLE "switcher" provides the core functionality to 1081 transparently handle transition between a cluster of A15's 1082 and a cluster of A7's in a big.LITTLE system. 1083 1084config BL_SWITCHER_DUMMY_IF 1085 tristate "Simple big.LITTLE switcher user interface" 1086 depends on BL_SWITCHER && DEBUG_KERNEL 1087 help 1088 This is a simple and dummy char dev interface to control 1089 the big.LITTLE switcher core code. It is meant for 1090 debugging purposes only. 1091 1092choice 1093 prompt "Memory split" 1094 depends on MMU 1095 default VMSPLIT_3G 1096 help 1097 Select the desired split between kernel and user memory. 1098 1099 If you are not absolutely sure what you are doing, leave this 1100 option alone! 1101 1102 config VMSPLIT_3G 1103 bool "3G/1G user/kernel split" 1104 config VMSPLIT_3G_OPT 1105 depends on !ARM_LPAE 1106 bool "3G/1G user/kernel split (for full 1G low memory)" 1107 config VMSPLIT_2G 1108 bool "2G/2G user/kernel split" 1109 config VMSPLIT_1G 1110 bool "1G/3G user/kernel split" 1111endchoice 1112 1113config PAGE_OFFSET 1114 hex 1115 default PHYS_OFFSET if !MMU 1116 default 0x40000000 if VMSPLIT_1G 1117 default 0x80000000 if VMSPLIT_2G 1118 default 0xB0000000 if VMSPLIT_3G_OPT 1119 default 0xC0000000 1120 1121config KASAN_SHADOW_OFFSET 1122 hex 1123 depends on KASAN 1124 default 0x1f000000 if PAGE_OFFSET=0x40000000 1125 default 0x5f000000 if PAGE_OFFSET=0x80000000 1126 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1127 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1128 default 0xffffffff 1129 1130config NR_CPUS 1131 int "Maximum number of CPUs (2-32)" 1132 range 2 16 if DEBUG_KMAP_LOCAL 1133 range 2 32 if !DEBUG_KMAP_LOCAL 1134 depends on SMP 1135 default "4" 1136 help 1137 The maximum number of CPUs that the kernel can support. 1138 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1139 debugging is enabled, which uses half of the per-CPU fixmap 1140 slots as guard regions. 1141 1142config HOTPLUG_CPU 1143 bool "Support for hot-pluggable CPUs" 1144 depends on SMP 1145 select GENERIC_IRQ_MIGRATION 1146 help 1147 Say Y here to experiment with turning CPUs off and on. CPUs 1148 can be controlled through /sys/devices/system/cpu. 1149 1150config ARM_PSCI 1151 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1152 depends on HAVE_ARM_SMCCC 1153 select ARM_PSCI_FW 1154 help 1155 Say Y here if you want Linux to communicate with system firmware 1156 implementing the PSCI specification for CPU-centric power 1157 management operations described in ARM document number ARM DEN 1158 0022A ("Power State Coordination Interface System Software on 1159 ARM processors"). 1160 1161# The GPIO number here must be sorted by descending number. In case of 1162# a multiplatform kernel, we just want the highest value required by the 1163# selected platforms. 1164config ARCH_NR_GPIO 1165 int 1166 default 2048 if ARCH_INTEL_SOCFPGA 1167 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1168 ARCH_ZYNQ || ARCH_ASPEED 1169 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1170 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1171 default 416 if ARCH_SUNXI 1172 default 392 if ARCH_U8500 1173 default 352 if ARCH_VT8500 1174 default 288 if ARCH_ROCKCHIP 1175 default 264 if MACH_H4700 1176 default 0 1177 help 1178 Maximum number of GPIOs in the system. 1179 1180 If unsure, leave the default value. 1181 1182config HZ_FIXED 1183 int 1184 default 128 if SOC_AT91RM9200 1185 default 0 1186 1187choice 1188 depends on HZ_FIXED = 0 1189 prompt "Timer frequency" 1190 1191config HZ_100 1192 bool "100 Hz" 1193 1194config HZ_200 1195 bool "200 Hz" 1196 1197config HZ_250 1198 bool "250 Hz" 1199 1200config HZ_300 1201 bool "300 Hz" 1202 1203config HZ_500 1204 bool "500 Hz" 1205 1206config HZ_1000 1207 bool "1000 Hz" 1208 1209endchoice 1210 1211config HZ 1212 int 1213 default HZ_FIXED if HZ_FIXED != 0 1214 default 100 if HZ_100 1215 default 200 if HZ_200 1216 default 250 if HZ_250 1217 default 300 if HZ_300 1218 default 500 if HZ_500 1219 default 1000 1220 1221config SCHED_HRTICK 1222 def_bool HIGH_RES_TIMERS 1223 1224config THUMB2_KERNEL 1225 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1226 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1227 default y if CPU_THUMBONLY 1228 select ARM_UNWIND 1229 help 1230 By enabling this option, the kernel will be compiled in 1231 Thumb-2 mode. 1232 1233 If unsure, say N. 1234 1235config ARM_PATCH_IDIV 1236 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1237 depends on CPU_32v7 1238 default y 1239 help 1240 The ARM compiler inserts calls to __aeabi_idiv() and 1241 __aeabi_uidiv() when it needs to perform division on signed 1242 and unsigned integers. Some v7 CPUs have support for the sdiv 1243 and udiv instructions that can be used to implement those 1244 functions. 1245 1246 Enabling this option allows the kernel to modify itself to 1247 replace the first two instructions of these library functions 1248 with the sdiv or udiv plus "bx lr" instructions when the CPU 1249 it is running on supports them. Typically this will be faster 1250 and less power intensive than running the original library 1251 code to do integer division. 1252 1253config AEABI 1254 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1255 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1256 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1257 help 1258 This option allows for the kernel to be compiled using the latest 1259 ARM ABI (aka EABI). This is only useful if you are using a user 1260 space environment that is also compiled with EABI. 1261 1262 Since there are major incompatibilities between the legacy ABI and 1263 EABI, especially with regard to structure member alignment, this 1264 option also changes the kernel syscall calling convention to 1265 disambiguate both ABIs and allow for backward compatibility support 1266 (selected with CONFIG_OABI_COMPAT). 1267 1268 To use this you need GCC version 4.0.0 or later. 1269 1270config OABI_COMPAT 1271 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1272 depends on AEABI && !THUMB2_KERNEL 1273 help 1274 This option preserves the old syscall interface along with the 1275 new (ARM EABI) one. It also provides a compatibility layer to 1276 intercept syscalls that have structure arguments which layout 1277 in memory differs between the legacy ABI and the new ARM EABI 1278 (only for non "thumb" binaries). This option adds a tiny 1279 overhead to all syscalls and produces a slightly larger kernel. 1280 1281 The seccomp filter system will not be available when this is 1282 selected, since there is no way yet to sensibly distinguish 1283 between calling conventions during filtering. 1284 1285 If you know you'll be using only pure EABI user space then you 1286 can say N here. If this option is not selected and you attempt 1287 to execute a legacy ABI binary then the result will be 1288 UNPREDICTABLE (in fact it can be predicted that it won't work 1289 at all). If in doubt say N. 1290 1291config ARCH_SELECT_MEMORY_MODEL 1292 def_bool y 1293 1294config ARCH_FLATMEM_ENABLE 1295 def_bool !(ARCH_RPC || ARCH_SA1100) 1296 1297config ARCH_SPARSEMEM_ENABLE 1298 def_bool !ARCH_FOOTBRIDGE 1299 select SPARSEMEM_STATIC if SPARSEMEM 1300 1301config HIGHMEM 1302 bool "High Memory Support" 1303 depends on MMU 1304 select KMAP_LOCAL 1305 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1306 help 1307 The address space of ARM processors is only 4 Gigabytes large 1308 and it has to accommodate user address space, kernel address 1309 space as well as some memory mapped IO. That means that, if you 1310 have a large amount of physical memory and/or IO, not all of the 1311 memory can be "permanently mapped" by the kernel. The physical 1312 memory that is not permanently mapped is called "high memory". 1313 1314 Depending on the selected kernel/user memory split, minimum 1315 vmalloc space and actual amount of RAM, you may not need this 1316 option which should result in a slightly faster kernel. 1317 1318 If unsure, say n. 1319 1320config HIGHPTE 1321 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1322 depends on HIGHMEM 1323 default y 1324 help 1325 The VM uses one page of physical memory for each page table. 1326 For systems with a lot of processes, this can use a lot of 1327 precious low memory, eventually leading to low memory being 1328 consumed by page tables. Setting this option will allow 1329 user-space 2nd level page tables to reside in high memory. 1330 1331config CPU_SW_DOMAIN_PAN 1332 bool "Enable use of CPU domains to implement privileged no-access" 1333 depends on MMU && !ARM_LPAE 1334 default y 1335 help 1336 Increase kernel security by ensuring that normal kernel accesses 1337 are unable to access userspace addresses. This can help prevent 1338 use-after-free bugs becoming an exploitable privilege escalation 1339 by ensuring that magic values (such as LIST_POISON) will always 1340 fault when dereferenced. 1341 1342 CPUs with low-vector mappings use a best-efforts implementation. 1343 Their lower 1MB needs to remain accessible for the vectors, but 1344 the remainder of userspace will become appropriately inaccessible. 1345 1346config HW_PERF_EVENTS 1347 def_bool y 1348 depends on ARM_PMU 1349 1350config ARM_MODULE_PLTS 1351 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1352 depends on MODULES 1353 select KASAN_VMALLOC if KASAN 1354 default y 1355 help 1356 Allocate PLTs when loading modules so that jumps and calls whose 1357 targets are too far away for their relative offsets to be encoded 1358 in the instructions themselves can be bounced via veneers in the 1359 module's PLT. This allows modules to be allocated in the generic 1360 vmalloc area after the dedicated module memory area has been 1361 exhausted. The modules will use slightly more memory, but after 1362 rounding up to page size, the actual memory footprint is usually 1363 the same. 1364 1365 Disabling this is usually safe for small single-platform 1366 configurations. If unsure, say y. 1367 1368config ARCH_FORCE_MAX_ORDER 1369 int "Maximum zone order" 1370 default "12" if SOC_AM33XX 1371 default "9" if SA1111 1372 default "11" 1373 help 1374 The kernel memory allocator divides physically contiguous memory 1375 blocks into "zones", where each zone is a power of two number of 1376 pages. This option selects the largest power of two that the kernel 1377 keeps in the memory allocator. If you need to allocate very large 1378 blocks of physically contiguous memory, then you may need to 1379 increase this value. 1380 1381 This config option is actually maximum order plus one. For example, 1382 a value of 11 means that the largest free memory block is 2^10 pages. 1383 1384config ALIGNMENT_TRAP 1385 def_bool CPU_CP15_MMU 1386 select HAVE_PROC_CPU if PROC_FS 1387 help 1388 ARM processors cannot fetch/store information which is not 1389 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1390 address divisible by 4. On 32-bit ARM processors, these non-aligned 1391 fetch/store instructions will be emulated in software if you say 1392 here, which has a severe performance impact. This is necessary for 1393 correct operation of some network protocols. With an IP-only 1394 configuration it is safe to say N, otherwise say Y. 1395 1396config UACCESS_WITH_MEMCPY 1397 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1398 depends on MMU 1399 default y if CPU_FEROCEON 1400 help 1401 Implement faster copy_to_user and clear_user methods for CPU 1402 cores where a 8-word STM instruction give significantly higher 1403 memory write throughput than a sequence of individual 32bit stores. 1404 1405 A possible side effect is a slight increase in scheduling latency 1406 between threads sharing the same address space if they invoke 1407 such copy operations with large buffers. 1408 1409 However, if the CPU data cache is using a write-allocate mode, 1410 this option is unlikely to provide any performance gain. 1411 1412config PARAVIRT 1413 bool "Enable paravirtualization code" 1414 help 1415 This changes the kernel so it can modify itself when it is run 1416 under a hypervisor, potentially improving performance significantly 1417 over full virtualization. 1418 1419config PARAVIRT_TIME_ACCOUNTING 1420 bool "Paravirtual steal time accounting" 1421 select PARAVIRT 1422 help 1423 Select this option to enable fine granularity task steal time 1424 accounting. Time spent executing other tasks in parallel with 1425 the current vCPU is discounted from the vCPU power. To account for 1426 that, there can be a small performance impact. 1427 1428 If in doubt, say N here. 1429 1430config XEN_DOM0 1431 def_bool y 1432 depends on XEN 1433 1434config XEN 1435 bool "Xen guest support on ARM" 1436 depends on ARM && AEABI && OF 1437 depends on CPU_V7 && !CPU_V6 1438 depends on !GENERIC_ATOMIC64 1439 depends on MMU 1440 select ARCH_DMA_ADDR_T_64BIT 1441 select ARM_PSCI 1442 select SWIOTLB 1443 select SWIOTLB_XEN 1444 select PARAVIRT 1445 help 1446 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1447 1448config CC_HAVE_STACKPROTECTOR_TLS 1449 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1450 1451config STACKPROTECTOR_PER_TASK 1452 bool "Use a unique stack canary value for each task" 1453 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1454 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1455 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1456 default y 1457 help 1458 Due to the fact that GCC uses an ordinary symbol reference from 1459 which to load the value of the stack canary, this value can only 1460 change at reboot time on SMP systems, and all tasks running in the 1461 kernel's address space are forced to use the same canary value for 1462 the entire duration that the system is up. 1463 1464 Enable this option to switch to a different method that uses a 1465 different canary value for each task. 1466 1467endmenu 1468 1469menu "Boot options" 1470 1471config USE_OF 1472 bool "Flattened Device Tree support" 1473 select IRQ_DOMAIN 1474 select OF 1475 help 1476 Include support for flattened device tree machine descriptions. 1477 1478config ATAGS 1479 bool "Support for the traditional ATAGS boot data passing" 1480 default y 1481 help 1482 This is the traditional way of passing data to the kernel at boot 1483 time. If you are solely relying on the flattened device tree (or 1484 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1485 to remove ATAGS support from your kernel binary. 1486 1487config UNUSED_BOARD_FILES 1488 bool "Board support for machines without known users" 1489 depends on ATAGS 1490 help 1491 Most ATAGS based board files are completely unused and are 1492 scheduled for removal in early 2023, and left out of kernels 1493 by default now. If you are using a board file that is marked 1494 as unused, turn on this option to build support into the kernel. 1495 1496 To keep support for your individual board from being removed, 1497 send a reply to the email discussion at 1498 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ 1499 1500config DEPRECATED_PARAM_STRUCT 1501 bool "Provide old way to pass kernel parameters" 1502 depends on ATAGS 1503 help 1504 This was deprecated in 2001 and announced to live on for 5 years. 1505 Some old boot loaders still use this way. 1506 1507# Compressed boot loader in ROM. Yes, we really want to ask about 1508# TEXT and BSS so we preserve their values in the config files. 1509config ZBOOT_ROM_TEXT 1510 hex "Compressed ROM boot loader base address" 1511 default 0x0 1512 help 1513 The physical address at which the ROM-able zImage is to be 1514 placed in the target. Platforms which normally make use of 1515 ROM-able zImage formats normally set this to a suitable 1516 value in their defconfig file. 1517 1518 If ZBOOT_ROM is not enabled, this has no effect. 1519 1520config ZBOOT_ROM_BSS 1521 hex "Compressed ROM boot loader BSS address" 1522 default 0x0 1523 help 1524 The base address of an area of read/write memory in the target 1525 for the ROM-able zImage which must be available while the 1526 decompressor is running. It must be large enough to hold the 1527 entire decompressed kernel plus an additional 128 KiB. 1528 Platforms which normally make use of ROM-able zImage formats 1529 normally set this to a suitable value in their defconfig file. 1530 1531 If ZBOOT_ROM is not enabled, this has no effect. 1532 1533config ZBOOT_ROM 1534 bool "Compressed boot loader in ROM/flash" 1535 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1536 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1537 help 1538 Say Y here if you intend to execute your compressed kernel image 1539 (zImage) directly from ROM or flash. If unsure, say N. 1540 1541config ARM_APPENDED_DTB 1542 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1543 depends on OF 1544 help 1545 With this option, the boot code will look for a device tree binary 1546 (DTB) appended to zImage 1547 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1548 1549 This is meant as a backward compatibility convenience for those 1550 systems with a bootloader that can't be upgraded to accommodate 1551 the documented boot protocol using a device tree. 1552 1553 Beware that there is very little in terms of protection against 1554 this option being confused by leftover garbage in memory that might 1555 look like a DTB header after a reboot if no actual DTB is appended 1556 to zImage. Do not leave this option active in a production kernel 1557 if you don't intend to always append a DTB. Proper passing of the 1558 location into r2 of a bootloader provided DTB is always preferable 1559 to this option. 1560 1561config ARM_ATAG_DTB_COMPAT 1562 bool "Supplement the appended DTB with traditional ATAG information" 1563 depends on ARM_APPENDED_DTB 1564 help 1565 Some old bootloaders can't be updated to a DTB capable one, yet 1566 they provide ATAGs with memory configuration, the ramdisk address, 1567 the kernel cmdline string, etc. Such information is dynamically 1568 provided by the bootloader and can't always be stored in a static 1569 DTB. To allow a device tree enabled kernel to be used with such 1570 bootloaders, this option allows zImage to extract the information 1571 from the ATAG list and store it at run time into the appended DTB. 1572 1573choice 1574 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1575 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1576 1577config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1578 bool "Use bootloader kernel arguments if available" 1579 help 1580 Uses the command-line options passed by the boot loader instead of 1581 the device tree bootargs property. If the boot loader doesn't provide 1582 any, the device tree bootargs property will be used. 1583 1584config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1585 bool "Extend with bootloader kernel arguments" 1586 help 1587 The command-line arguments provided by the boot loader will be 1588 appended to the the device tree bootargs property. 1589 1590endchoice 1591 1592config CMDLINE 1593 string "Default kernel command string" 1594 default "" 1595 help 1596 On some architectures (e.g. CATS), there is currently no way 1597 for the boot loader to pass arguments to the kernel. For these 1598 architectures, you should supply some command-line options at build 1599 time by entering them here. As a minimum, you should specify the 1600 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1601 1602choice 1603 prompt "Kernel command line type" if CMDLINE != "" 1604 default CMDLINE_FROM_BOOTLOADER 1605 1606config CMDLINE_FROM_BOOTLOADER 1607 bool "Use bootloader kernel arguments if available" 1608 help 1609 Uses the command-line options passed by the boot loader. If 1610 the boot loader doesn't provide any, the default kernel command 1611 string provided in CMDLINE will be used. 1612 1613config CMDLINE_EXTEND 1614 bool "Extend bootloader kernel arguments" 1615 help 1616 The command-line arguments provided by the boot loader will be 1617 appended to the default kernel command string. 1618 1619config CMDLINE_FORCE 1620 bool "Always use the default kernel command string" 1621 help 1622 Always use the default kernel command string, even if the boot 1623 loader passes other arguments to the kernel. 1624 This is useful if you cannot or don't want to change the 1625 command-line options your boot loader passes to the kernel. 1626endchoice 1627 1628config XIP_KERNEL 1629 bool "Kernel Execute-In-Place from ROM" 1630 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1631 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1632 help 1633 Execute-In-Place allows the kernel to run from non-volatile storage 1634 directly addressable by the CPU, such as NOR flash. This saves RAM 1635 space since the text section of the kernel is not loaded from flash 1636 to RAM. Read-write sections, such as the data section and stack, 1637 are still copied to RAM. The XIP kernel is not compressed since 1638 it has to run directly from flash, so it will take more space to 1639 store it. The flash address used to link the kernel object files, 1640 and for storing it, is configuration dependent. Therefore, if you 1641 say Y here, you must know the proper physical address where to 1642 store the kernel image depending on your own flash memory usage. 1643 1644 Also note that the make target becomes "make xipImage" rather than 1645 "make zImage" or "make Image". The final kernel binary to put in 1646 ROM memory will be arch/arm/boot/xipImage. 1647 1648 If unsure, say N. 1649 1650config XIP_PHYS_ADDR 1651 hex "XIP Kernel Physical Location" 1652 depends on XIP_KERNEL 1653 default "0x00080000" 1654 help 1655 This is the physical address in your flash memory the kernel will 1656 be linked for and stored to. This address is dependent on your 1657 own flash usage. 1658 1659config XIP_DEFLATED_DATA 1660 bool "Store kernel .data section compressed in ROM" 1661 depends on XIP_KERNEL 1662 select ZLIB_INFLATE 1663 help 1664 Before the kernel is actually executed, its .data section has to be 1665 copied to RAM from ROM. This option allows for storing that data 1666 in compressed form and decompressed to RAM rather than merely being 1667 copied, saving some precious ROM space. A possible drawback is a 1668 slightly longer boot delay. 1669 1670config KEXEC 1671 bool "Kexec system call (EXPERIMENTAL)" 1672 depends on (!SMP || PM_SLEEP_SMP) 1673 depends on MMU 1674 select KEXEC_CORE 1675 help 1676 kexec is a system call that implements the ability to shutdown your 1677 current kernel, and to start another kernel. It is like a reboot 1678 but it is independent of the system firmware. And like a reboot 1679 you can start any kernel with it, not just Linux. 1680 1681 It is an ongoing process to be certain the hardware in a machine 1682 is properly shutdown, so do not be surprised if this code does not 1683 initially work for you. 1684 1685config ATAGS_PROC 1686 bool "Export atags in procfs" 1687 depends on ATAGS && KEXEC 1688 default y 1689 help 1690 Should the atags used to boot the kernel be exported in an "atags" 1691 file in procfs. Useful with kexec. 1692 1693config CRASH_DUMP 1694 bool "Build kdump crash kernel (EXPERIMENTAL)" 1695 help 1696 Generate crash dump after being started by kexec. This should 1697 be normally only set in special crash dump kernels which are 1698 loaded in the main kernel with kexec-tools into a specially 1699 reserved region and then later executed after a crash by 1700 kdump/kexec. The crash dump kernel must be compiled to a 1701 memory address not used by the main kernel 1702 1703 For more details see Documentation/admin-guide/kdump/kdump.rst 1704 1705config AUTO_ZRELADDR 1706 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1707 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1708 help 1709 ZRELADDR is the physical address where the decompressed kernel 1710 image will be placed. If AUTO_ZRELADDR is selected, the address 1711 will be determined at run-time, either by masking the current IP 1712 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1713 This assumes the zImage being placed in the first 128MB from 1714 start of memory. 1715 1716config EFI_STUB 1717 bool 1718 1719config EFI 1720 bool "UEFI runtime support" 1721 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1722 select UCS2_STRING 1723 select EFI_PARAMS_FROM_FDT 1724 select EFI_STUB 1725 select EFI_GENERIC_STUB 1726 select EFI_RUNTIME_WRAPPERS 1727 help 1728 This option provides support for runtime services provided 1729 by UEFI firmware (such as non-volatile variables, realtime 1730 clock, and platform reset). A UEFI stub is also provided to 1731 allow the kernel to be booted as an EFI application. This 1732 is only useful for kernels that may run on systems that have 1733 UEFI firmware. 1734 1735config DMI 1736 bool "Enable support for SMBIOS (DMI) tables" 1737 depends on EFI 1738 default y 1739 help 1740 This enables SMBIOS/DMI feature for systems. 1741 1742 This option is only useful on systems that have UEFI firmware. 1743 However, even with this option, the resultant kernel should 1744 continue to boot on existing non-UEFI platforms. 1745 1746 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1747 i.e., the the practice of identifying the platform via DMI to 1748 decide whether certain workarounds for buggy hardware and/or 1749 firmware need to be enabled. This would require the DMI subsystem 1750 to be enabled much earlier than we do on ARM, which is non-trivial. 1751 1752endmenu 1753 1754menu "CPU Power Management" 1755 1756source "drivers/cpufreq/Kconfig" 1757 1758source "drivers/cpuidle/Kconfig" 1759 1760endmenu 1761 1762menu "Floating point emulation" 1763 1764comment "At least one emulation must be selected" 1765 1766config FPE_NWFPE 1767 bool "NWFPE math emulation" 1768 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1769 help 1770 Say Y to include the NWFPE floating point emulator in the kernel. 1771 This is necessary to run most binaries. Linux does not currently 1772 support floating point hardware so you need to say Y here even if 1773 your machine has an FPA or floating point co-processor podule. 1774 1775 You may say N here if you are going to load the Acorn FPEmulator 1776 early in the bootup. 1777 1778config FPE_NWFPE_XP 1779 bool "Support extended precision" 1780 depends on FPE_NWFPE 1781 help 1782 Say Y to include 80-bit support in the kernel floating-point 1783 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1784 Note that gcc does not generate 80-bit operations by default, 1785 so in most cases this option only enlarges the size of the 1786 floating point emulator without any good reason. 1787 1788 You almost surely want to say N here. 1789 1790config FPE_FASTFPE 1791 bool "FastFPE math emulation (EXPERIMENTAL)" 1792 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1793 help 1794 Say Y here to include the FAST floating point emulator in the kernel. 1795 This is an experimental much faster emulator which now also has full 1796 precision for the mantissa. It does not support any exceptions. 1797 It is very simple, and approximately 3-6 times faster than NWFPE. 1798 1799 It should be sufficient for most programs. It may be not suitable 1800 for scientific calculations, but you have to check this for yourself. 1801 If you do not feel you need a faster FP emulation you should better 1802 choose NWFPE. 1803 1804config VFP 1805 bool "VFP-format floating point maths" 1806 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1807 help 1808 Say Y to include VFP support code in the kernel. This is needed 1809 if your hardware includes a VFP unit. 1810 1811 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1812 release notes and additional status information. 1813 1814 Say N if your target does not have VFP hardware. 1815 1816config VFPv3 1817 bool 1818 depends on VFP 1819 default y if CPU_V7 1820 1821config NEON 1822 bool "Advanced SIMD (NEON) Extension support" 1823 depends on VFPv3 && CPU_V7 1824 help 1825 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1826 Extension. 1827 1828config KERNEL_MODE_NEON 1829 bool "Support for NEON in kernel mode" 1830 depends on NEON && AEABI 1831 help 1832 Say Y to include support for NEON in kernel mode. 1833 1834endmenu 1835 1836menu "Power management options" 1837 1838source "kernel/power/Kconfig" 1839 1840config ARCH_SUSPEND_POSSIBLE 1841 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1842 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1843 def_bool y 1844 1845config ARM_CPU_SUSPEND 1846 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1847 depends on ARCH_SUSPEND_POSSIBLE 1848 1849config ARCH_HIBERNATION_POSSIBLE 1850 bool 1851 depends on MMU 1852 default y if ARCH_SUSPEND_POSSIBLE 1853 1854endmenu 1855 1856source "arch/arm/Kconfig.assembler" 1857