1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CACHE_LINE_SIZE if OF 9 select ARCH_HAS_CPU_CACHE_ALIASING 10 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 11 select ARCH_HAS_CRC32 if KERNEL_MODE_NEON 12 select ARCH_HAS_CRC_T10DIF if KERNEL_MODE_NEON 13 select ARCH_HAS_CURRENT_STACK_POINTER 14 select ARCH_HAS_DEBUG_VIRTUAL if MMU 15 select ARCH_HAS_DMA_ALLOC if MMU 16 select ARCH_HAS_DMA_OPS 17 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 18 select ARCH_HAS_ELF_RANDOMIZE 19 select ARCH_HAS_FORTIFY_SOURCE 20 select ARCH_HAS_KEEPINITRD 21 select ARCH_HAS_KCOV 22 select ARCH_HAS_MEMBARRIER_SYNC_CORE 23 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 24 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 25 select ARCH_HAS_SETUP_DMA_OPS 26 select ARCH_HAS_SET_MEMORY 27 select ARCH_STACKWALK 28 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 29 select ARCH_HAS_STRICT_MODULE_RWX if MMU 30 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 31 select ARCH_HAS_SYNC_DMA_FOR_CPU 32 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 33 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 34 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 35 select ARCH_HAS_GCOV_PROFILE_ALL 36 select ARCH_KEEP_MEMBLOCK 37 select ARCH_HAS_UBSAN 38 select ARCH_MIGHT_HAVE_PC_PARPORT 39 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 40 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 41 select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 42 select ARCH_SUPPORTS_ATOMIC_RMW 43 select ARCH_SUPPORTS_CFI_CLANG 44 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 45 select ARCH_SUPPORTS_PER_VMA_LOCK 46 select ARCH_USE_BUILTIN_BSWAP 47 select ARCH_USE_CMPXCHG_LOCKREF 48 select ARCH_USE_MEMTEST 49 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 50 select ARCH_WANT_GENERAL_HUGETLB 51 select ARCH_WANT_IPC_PARSE_VERSION 52 select ARCH_WANT_LD_ORPHAN_WARN 53 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 54 select BUILDTIME_TABLE_SORT if MMU 55 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 56 select CLONE_BACKWARDS 57 select CPU_PM if SUSPEND || CPU_IDLE 58 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 59 select DMA_DECLARE_COHERENT 60 select DMA_GLOBAL_POOL if !MMU 61 select DMA_NONCOHERENT_MMAP if MMU 62 select EDAC_SUPPORT 63 select EDAC_ATOMIC_SCRUB 64 select GENERIC_ALLOCATOR 65 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 66 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 67 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 68 select GENERIC_IRQ_IPI if SMP 69 select GENERIC_CPU_AUTOPROBE 70 select GENERIC_CPU_DEVICES 71 select GENERIC_EARLY_IOREMAP 72 select GENERIC_IDLE_POLL_SETUP 73 select GENERIC_IRQ_MULTI_HANDLER 74 select GENERIC_IRQ_PROBE 75 select GENERIC_IRQ_SHOW 76 select GENERIC_IRQ_SHOW_LEVEL 77 select GENERIC_LIB_DEVMEM_IS_ALLOWED 78 select GENERIC_PCI_IOMAP 79 select GENERIC_SCHED_CLOCK 80 select GENERIC_SMP_IDLE_THREAD 81 select HARDIRQS_SW_RESEND 82 select HAS_IOPORT 83 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 84 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 85 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 86 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 87 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 88 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 89 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 90 select HAVE_ARCH_MMAP_RND_BITS if MMU 91 select HAVE_ARCH_PFN_VALID 92 select HAVE_ARCH_SECCOMP 93 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 94 select HAVE_ARCH_STACKLEAK 95 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 96 select HAVE_ARCH_TRACEHOOK 97 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 98 select HAVE_ARM_SMCCC if CPU_V7 99 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 100 select HAVE_CONTEXT_TRACKING_USER 101 select HAVE_C_RECORDMCOUNT 102 select HAVE_BUILDTIME_MCOUNT_SORT 103 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 104 select HAVE_DMA_CONTIGUOUS if MMU 105 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 106 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 107 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 108 select HAVE_EXIT_THREAD 109 select HAVE_GUP_FAST if ARM_LPAE 110 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 111 select HAVE_FUNCTION_ERROR_INJECTION 112 select HAVE_FUNCTION_GRAPH_TRACER 113 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 114 select HAVE_GCC_PLUGINS 115 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 116 select HAVE_IRQ_TIME_ACCOUNTING 117 select HAVE_KERNEL_GZIP 118 select HAVE_KERNEL_LZ4 119 select HAVE_KERNEL_LZMA 120 select HAVE_KERNEL_LZO 121 select HAVE_KERNEL_XZ 122 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 123 select HAVE_KRETPROBES if HAVE_KPROBES 124 select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_CAN_USE_KEEP_IN_OVERLAY) 125 select HAVE_MOD_ARCH_SPECIFIC 126 select HAVE_NMI 127 select HAVE_OPTPROBES if !THUMB2_KERNEL 128 select HAVE_PAGE_SIZE_4KB 129 select HAVE_PCI if MMU 130 select HAVE_PERF_EVENTS 131 select HAVE_PERF_REGS 132 select HAVE_PERF_USER_STACK_DUMP 133 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 134 select HAVE_REGS_AND_STACK_ACCESS_API 135 select HAVE_RSEQ 136 select HAVE_RUST if CPU_LITTLE_ENDIAN && CPU_32v7 137 select HAVE_STACKPROTECTOR 138 select HAVE_SYSCALL_TRACEPOINTS 139 select HAVE_UID16 140 select HAVE_VIRT_CPU_ACCOUNTING_GEN 141 select HOTPLUG_CORE_SYNC_DEAD if HOTPLUG_CPU 142 select IRQ_FORCED_THREADING 143 select LOCK_MM_AND_FIND_VMA 144 select MODULES_USE_ELF_REL 145 select NEED_DMA_MAP_STATE 146 select OF_EARLY_FLATTREE if OF 147 select OLD_SIGACTION 148 select OLD_SIGSUSPEND3 149 select PCI_DOMAINS_GENERIC if PCI 150 select PCI_SYSCALL if PCI 151 select PERF_USE_VMALLOC 152 select RTC_LIB 153 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 154 select SYS_SUPPORTS_APM_EMULATION 155 select THREAD_INFO_IN_TASK 156 select TIMER_OF if OF 157 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 158 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 159 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 160 # Above selects are sorted alphabetically; please add new ones 161 # according to that. Thanks. 162 help 163 The ARM series is a line of low-power-consumption RISC chip designs 164 licensed by ARM Ltd and targeted at embedded applications and 165 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 166 manufactured, but legacy ARM-based PC hardware remains popular in 167 Europe. There is an ARM Linux project with a web page at 168 <http://www.arm.linux.org.uk/>. 169 170config ARM_HAS_GROUP_RELOCS 171 def_bool y 172 depends on !LD_IS_LLD || LLD_VERSION >= 140000 173 depends on !COMPILE_TEST 174 help 175 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 176 relocations, which have been around for a long time, but were not 177 supported in LLD until version 14. The combined range is -/+ 256 MiB, 178 which is usually sufficient, but not for allyesconfig, so we disable 179 this feature when doing compile testing. 180 181config ARM_DMA_USE_IOMMU 182 bool 183 select NEED_SG_DMA_LENGTH 184 185if ARM_DMA_USE_IOMMU 186 187config ARM_DMA_IOMMU_ALIGNMENT 188 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 189 range 4 9 190 default 8 191 help 192 DMA mapping framework by default aligns all buffers to the smallest 193 PAGE_SIZE order which is greater than or equal to the requested buffer 194 size. This works well for buffers up to a few hundreds kilobytes, but 195 for larger buffers it just a waste of address space. Drivers which has 196 relatively small addressing window (like 64Mib) might run out of 197 virtual space with just a few allocations. 198 199 With this parameter you can specify the maximum PAGE_SIZE order for 200 DMA IOMMU buffers. Larger buffers will be aligned only to this 201 specified order. The order is expressed as a power of two multiplied 202 by the PAGE_SIZE. 203 204endif 205 206config SYS_SUPPORTS_APM_EMULATION 207 bool 208 209config HAVE_TCM 210 bool 211 select GENERIC_ALLOCATOR 212 213config HAVE_PROC_CPU 214 bool 215 216config NO_IOPORT_MAP 217 bool 218 219config SBUS 220 bool 221 222config STACKTRACE_SUPPORT 223 bool 224 default y 225 226config LOCKDEP_SUPPORT 227 bool 228 default y 229 230config ARCH_HAS_ILOG2_U32 231 bool 232 233config ARCH_HAS_ILOG2_U64 234 bool 235 236config ARCH_HAS_BANDGAP 237 bool 238 239config FIX_EARLYCON_MEM 240 def_bool y if MMU 241 242config GENERIC_HWEIGHT 243 bool 244 default y 245 246config GENERIC_CALIBRATE_DELAY 247 bool 248 default y 249 250config ARCH_MAY_HAVE_PC_FDC 251 bool 252 253config ARCH_SUPPORTS_UPROBES 254 def_bool y 255 256config GENERIC_ISA_DMA 257 bool 258 259config FIQ 260 bool 261 262config ARCH_MTD_XIP 263 bool 264 265config ARM_PATCH_PHYS_VIRT 266 bool "Patch physical to virtual translations at runtime" if !ARCH_MULTIPLATFORM 267 default y 268 depends on MMU 269 help 270 Patch phys-to-virt and virt-to-phys translation functions at 271 boot and module load time according to the position of the 272 kernel in system memory. 273 274 This can only be used with non-XIP MMU kernels where the base 275 of physical memory is at a 2 MiB boundary. 276 277 Only disable this option if you know that you do not require 278 this feature (eg, building a kernel for a single machine) and 279 you need to shrink the kernel to the minimal size. 280 281config NEED_MACH_IO_H 282 bool 283 help 284 Select this when mach/io.h is required to provide special 285 definitions for this platform. The need for mach/io.h should 286 be avoided when possible. 287 288config NEED_MACH_MEMORY_H 289 bool 290 help 291 Select this when mach/memory.h is required to provide special 292 definitions for this platform. The need for mach/memory.h should 293 be avoided when possible. 294 295config PHYS_OFFSET 296 hex "Physical address of main memory" if MMU 297 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 298 default DRAM_BASE if !MMU 299 default 0x00000000 if ARCH_FOOTBRIDGE 300 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 301 default 0xa0000000 if ARCH_PXA 302 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 303 default 0 304 help 305 Please provide the physical address corresponding to the 306 location of main memory in your system. 307 308config GENERIC_BUG 309 def_bool y 310 depends on BUG 311 312config PGTABLE_LEVELS 313 int 314 default 3 if ARM_LPAE 315 default 2 316 317menu "System Type" 318 319config MMU 320 bool "MMU-based Paged Memory Management Support" 321 default y 322 help 323 Select if you want MMU-based virtualised addressing space 324 support by paged memory management. If unsure, say 'Y'. 325 326config ARM_SINGLE_ARMV7M 327 def_bool !MMU 328 select ARM_NVIC 329 select CPU_V7M 330 select NO_IOPORT_MAP 331 332config ARCH_MMAP_RND_BITS_MIN 333 default 8 334 335config ARCH_MMAP_RND_BITS_MAX 336 default 14 if PAGE_OFFSET=0x40000000 337 default 15 if PAGE_OFFSET=0x80000000 338 default 16 339 340config ARCH_MULTIPLATFORM 341 bool "Require kernel to be portable to multiple machines" if EXPERT 342 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 343 default y 344 help 345 In general, all Arm machines can be supported in a single 346 kernel image, covering either Armv4/v5 or Armv6/v7. 347 348 However, some configuration options require hardcoding machine 349 specific physical addresses or enable errata workarounds that may 350 break other machines. 351 352 Selecting N here allows using those options, including 353 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 354 355source "arch/arm/Kconfig.platforms" 356 357# 358# This is sorted alphabetically by mach-* pathname. However, plat-* 359# Kconfigs may be included either alphabetically (according to the 360# plat- suffix) or along side the corresponding mach-* source. 361# 362source "arch/arm/mach-actions/Kconfig" 363 364source "arch/arm/mach-alpine/Kconfig" 365 366source "arch/arm/mach-artpec/Kconfig" 367 368source "arch/arm/mach-aspeed/Kconfig" 369 370source "arch/arm/mach-at91/Kconfig" 371 372source "arch/arm/mach-axxia/Kconfig" 373 374source "arch/arm/mach-bcm/Kconfig" 375 376source "arch/arm/mach-berlin/Kconfig" 377 378source "arch/arm/mach-clps711x/Kconfig" 379 380source "arch/arm/mach-davinci/Kconfig" 381 382source "arch/arm/mach-digicolor/Kconfig" 383 384source "arch/arm/mach-dove/Kconfig" 385 386source "arch/arm/mach-ep93xx/Kconfig" 387 388source "arch/arm/mach-exynos/Kconfig" 389 390source "arch/arm/mach-footbridge/Kconfig" 391 392source "arch/arm/mach-gemini/Kconfig" 393 394source "arch/arm/mach-highbank/Kconfig" 395 396source "arch/arm/mach-hisi/Kconfig" 397 398source "arch/arm/mach-hpe/Kconfig" 399 400source "arch/arm/mach-imx/Kconfig" 401 402source "arch/arm/mach-ixp4xx/Kconfig" 403 404source "arch/arm/mach-keystone/Kconfig" 405 406source "arch/arm/mach-lpc32xx/Kconfig" 407 408source "arch/arm/mach-mediatek/Kconfig" 409 410source "arch/arm/mach-meson/Kconfig" 411 412source "arch/arm/mach-milbeaut/Kconfig" 413 414source "arch/arm/mach-mmp/Kconfig" 415 416source "arch/arm/mach-mstar/Kconfig" 417 418source "arch/arm/mach-mv78xx0/Kconfig" 419 420source "arch/arm/mach-mvebu/Kconfig" 421 422source "arch/arm/mach-mxs/Kconfig" 423 424source "arch/arm/mach-nomadik/Kconfig" 425 426source "arch/arm/mach-npcm/Kconfig" 427 428source "arch/arm/mach-omap1/Kconfig" 429 430source "arch/arm/mach-omap2/Kconfig" 431 432source "arch/arm/mach-orion5x/Kconfig" 433 434source "arch/arm/mach-pxa/Kconfig" 435 436source "arch/arm/mach-qcom/Kconfig" 437 438source "arch/arm/mach-realtek/Kconfig" 439 440source "arch/arm/mach-rpc/Kconfig" 441 442source "arch/arm/mach-rockchip/Kconfig" 443 444source "arch/arm/mach-s3c/Kconfig" 445 446source "arch/arm/mach-s5pv210/Kconfig" 447 448source "arch/arm/mach-sa1100/Kconfig" 449 450source "arch/arm/mach-shmobile/Kconfig" 451 452source "arch/arm/mach-socfpga/Kconfig" 453 454source "arch/arm/mach-spear/Kconfig" 455 456source "arch/arm/mach-sti/Kconfig" 457 458source "arch/arm/mach-stm32/Kconfig" 459 460source "arch/arm/mach-sunxi/Kconfig" 461 462source "arch/arm/mach-tegra/Kconfig" 463 464source "arch/arm/mach-ux500/Kconfig" 465 466source "arch/arm/mach-versatile/Kconfig" 467 468source "arch/arm/mach-vt8500/Kconfig" 469 470source "arch/arm/mach-zynq/Kconfig" 471 472# ARMv7-M architecture 473config ARCH_LPC18XX 474 bool "NXP LPC18xx/LPC43xx" 475 depends on ARM_SINGLE_ARMV7M 476 select ARCH_HAS_RESET_CONTROLLER 477 select ARM_AMBA 478 select CLKSRC_LPC32XX 479 select PINCTRL 480 help 481 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 482 high performance microcontrollers. 483 484config ARCH_MPS2 485 bool "ARM MPS2 platform" 486 depends on ARM_SINGLE_ARMV7M 487 select ARM_AMBA 488 select CLKSRC_MPS2 489 help 490 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 491 with a range of available cores like Cortex-M3/M4/M7. 492 493 Please, note that depends which Application Note is used memory map 494 for the platform may vary, so adjustment of RAM base might be needed. 495 496# Definitions to make life easier 497config ARCH_ACORN 498 bool 499 500config PLAT_ORION 501 bool 502 select CLKSRC_MMIO 503 select GENERIC_IRQ_CHIP 504 select IRQ_DOMAIN 505 506config PLAT_ORION_LEGACY 507 bool 508 select PLAT_ORION 509 510config PLAT_VERSATILE 511 bool 512 513source "arch/arm/mm/Kconfig" 514 515config IWMMXT 516 bool "Enable iWMMXt support" 517 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK 518 default y if PXA27x || PXA3xx || ARCH_MMP 519 help 520 Enable support for iWMMXt context switching at run time if 521 running on a CPU that supports it. 522 523if !MMU 524source "arch/arm/Kconfig-nommu" 525endif 526 527config PJ4B_ERRATA_4742 528 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 529 depends on CPU_PJ4B && MACH_ARMADA_370 530 default y 531 help 532 When coming out of either a Wait for Interrupt (WFI) or a Wait for 533 Event (WFE) IDLE states, a specific timing sensitivity exists between 534 the retiring WFI/WFE instructions and the newly issued subsequent 535 instructions. This sensitivity can result in a CPU hang scenario. 536 Workaround: 537 The software must insert either a Data Synchronization Barrier (DSB) 538 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 539 instruction 540 541config ARM_ERRATA_326103 542 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 543 depends on CPU_V6 544 help 545 Executing a SWP instruction to read-only memory does not set bit 11 546 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 547 treat the access as a read, preventing a COW from occurring and 548 causing the faulting task to livelock. 549 550config ARM_ERRATA_411920 551 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 552 depends on CPU_V6 || CPU_V6K 553 help 554 Invalidation of the Instruction Cache operation can 555 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 556 It does not affect the MPCore. This option enables the ARM Ltd. 557 recommended workaround. 558 559config ARM_ERRATA_430973 560 bool "ARM errata: Stale prediction on replaced interworking branch" 561 depends on CPU_V7 562 help 563 This option enables the workaround for the 430973 Cortex-A8 564 r1p* erratum. If a code sequence containing an ARM/Thumb 565 interworking branch is replaced with another code sequence at the 566 same virtual address, whether due to self-modifying code or virtual 567 to physical address re-mapping, Cortex-A8 does not recover from the 568 stale interworking branch prediction. This results in Cortex-A8 569 executing the new code sequence in the incorrect ARM or Thumb state. 570 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 571 and also flushes the branch target cache at every context switch. 572 Note that setting specific bits in the ACTLR register may not be 573 available in non-secure mode. 574 575config ARM_ERRATA_458693 576 bool "ARM errata: Processor deadlock when a false hazard is created" 577 depends on CPU_V7 578 depends on !ARCH_MULTIPLATFORM 579 help 580 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 581 erratum. For very specific sequences of memory operations, it is 582 possible for a hazard condition intended for a cache line to instead 583 be incorrectly associated with a different cache line. This false 584 hazard might then cause a processor deadlock. The workaround enables 585 the L1 caching of the NEON accesses and disables the PLD instruction 586 in the ACTLR register. Note that setting specific bits in the ACTLR 587 register may not be available in non-secure mode and thus is not 588 available on a multiplatform kernel. This should be applied by the 589 bootloader instead. 590 591config ARM_ERRATA_460075 592 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 593 depends on CPU_V7 594 depends on !ARCH_MULTIPLATFORM 595 help 596 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 597 erratum. Any asynchronous access to the L2 cache may encounter a 598 situation in which recent store transactions to the L2 cache are lost 599 and overwritten with stale memory contents from external memory. The 600 workaround disables the write-allocate mode for the L2 cache via the 601 ACTLR register. Note that setting specific bits in the ACTLR register 602 may not be available in non-secure mode and thus is not available on 603 a multiplatform kernel. This should be applied by the bootloader 604 instead. 605 606config ARM_ERRATA_742230 607 bool "ARM errata: DMB operation may be faulty" 608 depends on CPU_V7 && SMP 609 depends on !ARCH_MULTIPLATFORM 610 help 611 This option enables the workaround for the 742230 Cortex-A9 612 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 613 between two write operations may not ensure the correct visibility 614 ordering of the two writes. This workaround sets a specific bit in 615 the diagnostic register of the Cortex-A9 which causes the DMB 616 instruction to behave as a DSB, ensuring the correct behaviour of 617 the two writes. Note that setting specific bits in the diagnostics 618 register may not be available in non-secure mode and thus is not 619 available on a multiplatform kernel. This should be applied by the 620 bootloader instead. 621 622config ARM_ERRATA_742231 623 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 624 depends on CPU_V7 && SMP 625 depends on !ARCH_MULTIPLATFORM 626 help 627 This option enables the workaround for the 742231 Cortex-A9 628 (r2p0..r2p2) erratum. Under certain conditions, specific to the 629 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 630 accessing some data located in the same cache line, may get corrupted 631 data due to bad handling of the address hazard when the line gets 632 replaced from one of the CPUs at the same time as another CPU is 633 accessing it. This workaround sets specific bits in the diagnostic 634 register of the Cortex-A9 which reduces the linefill issuing 635 capabilities of the processor. Note that setting specific bits in the 636 diagnostics register may not be available in non-secure mode and thus 637 is not available on a multiplatform kernel. This should be applied by 638 the bootloader instead. 639 640config ARM_ERRATA_643719 641 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 642 depends on CPU_V7 && SMP 643 default y 644 help 645 This option enables the workaround for the 643719 Cortex-A9 (prior to 646 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 647 register returns zero when it should return one. The workaround 648 corrects this value, ensuring cache maintenance operations which use 649 it behave as intended and avoiding data corruption. 650 651config ARM_ERRATA_720789 652 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 653 depends on CPU_V7 654 help 655 This option enables the workaround for the 720789 Cortex-A9 (prior to 656 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 657 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 658 As a consequence of this erratum, some TLB entries which should be 659 invalidated are not, resulting in an incoherency in the system page 660 tables. The workaround changes the TLB flushing routines to invalidate 661 entries regardless of the ASID. 662 663config ARM_ERRATA_743622 664 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 665 depends on CPU_V7 666 depends on !ARCH_MULTIPLATFORM 667 help 668 This option enables the workaround for the 743622 Cortex-A9 669 (r2p*) erratum. Under very rare conditions, a faulty 670 optimisation in the Cortex-A9 Store Buffer may lead to data 671 corruption. This workaround sets a specific bit in the diagnostic 672 register of the Cortex-A9 which disables the Store Buffer 673 optimisation, preventing the defect from occurring. This has no 674 visible impact on the overall performance or power consumption of the 675 processor. Note that setting specific bits in the diagnostics register 676 may not be available in non-secure mode and thus is not available on a 677 multiplatform kernel. This should be applied by the bootloader instead. 678 679config ARM_ERRATA_751472 680 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 681 depends on CPU_V7 682 depends on !ARCH_MULTIPLATFORM 683 help 684 This option enables the workaround for the 751472 Cortex-A9 (prior 685 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 686 completion of a following broadcasted operation if the second 687 operation is received by a CPU before the ICIALLUIS has completed, 688 potentially leading to corrupted entries in the cache or TLB. 689 Note that setting specific bits in the diagnostics register may 690 not be available in non-secure mode and thus is not available on 691 a multiplatform kernel. This should be applied by the bootloader 692 instead. 693 694config ARM_ERRATA_754322 695 bool "ARM errata: possible faulty MMU translations following an ASID switch" 696 depends on CPU_V7 697 help 698 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 699 r3p*) erratum. A speculative memory access may cause a page table walk 700 which starts prior to an ASID switch but completes afterwards. This 701 can populate the micro-TLB with a stale entry which may be hit with 702 the new ASID. This workaround places two dsb instructions in the mm 703 switching code so that no page table walks can cross the ASID switch. 704 705config ARM_ERRATA_754327 706 bool "ARM errata: no automatic Store Buffer drain" 707 depends on CPU_V7 && SMP 708 help 709 This option enables the workaround for the 754327 Cortex-A9 (prior to 710 r2p0) erratum. The Store Buffer does not have any automatic draining 711 mechanism and therefore a livelock may occur if an external agent 712 continuously polls a memory location waiting to observe an update. 713 This workaround defines cpu_relax() as smp_mb(), preventing correctly 714 written polling loops from denying visibility of updates to memory. 715 716config ARM_ERRATA_364296 717 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 718 depends on CPU_V6 719 help 720 This options enables the workaround for the 364296 ARM1136 721 r0p2 erratum (possible cache data corruption with 722 hit-under-miss enabled). It sets the undocumented bit 31 in 723 the auxiliary control register and the FI bit in the control 724 register, thus disabling hit-under-miss without putting the 725 processor into full low interrupt latency mode. ARM11MPCore 726 is not affected. 727 728config ARM_ERRATA_764369 729 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 730 depends on CPU_V7 && SMP 731 help 732 This option enables the workaround for erratum 764369 733 affecting Cortex-A9 MPCore with two or more processors (all 734 current revisions). Under certain timing circumstances, a data 735 cache line maintenance operation by MVA targeting an Inner 736 Shareable memory region may fail to proceed up to either the 737 Point of Coherency or to the Point of Unification of the 738 system. This workaround adds a DSB instruction before the 739 relevant cache maintenance functions and sets a specific bit 740 in the diagnostic control register of the SCU. 741 742config ARM_ERRATA_764319 743 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 744 depends on CPU_V7 745 help 746 This option enables the workaround for the 764319 Cortex-A9 erratum. 747 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 748 unexpected Undefined Instruction exception when the DBGSWENABLE 749 external pin is set to 0, even when the CP14 accesses are performed 750 from a privileged mode. This work around catches the exception in a 751 way the kernel does not stop execution. 752 753config ARM_ERRATA_775420 754 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 755 depends on CPU_V7 756 help 757 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 758 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 759 operation aborts with MMU exception, it might cause the processor 760 to deadlock. This workaround puts DSB before executing ISB if 761 an abort may occur on cache maintenance. 762 763config ARM_ERRATA_798181 764 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 765 depends on CPU_V7 && SMP 766 help 767 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 768 adequately shooting down all use of the old entries. This 769 option enables the Linux kernel workaround for this erratum 770 which sends an IPI to the CPUs that are running the same ASID 771 as the one being invalidated. 772 773config ARM_ERRATA_773022 774 bool "ARM errata: incorrect instructions may be executed from loop buffer" 775 depends on CPU_V7 776 help 777 This option enables the workaround for the 773022 Cortex-A15 778 (up to r0p4) erratum. In certain rare sequences of code, the 779 loop buffer may deliver incorrect instructions. This 780 workaround disables the loop buffer to avoid the erratum. 781 782config ARM_ERRATA_818325_852422 783 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 784 depends on CPU_V7 785 help 786 This option enables the workaround for: 787 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 788 instruction might deadlock. Fixed in r0p1. 789 - Cortex-A12 852422: Execution of a sequence of instructions might 790 lead to either a data corruption or a CPU deadlock. Not fixed in 791 any Cortex-A12 cores yet. 792 This workaround for all both errata involves setting bit[12] of the 793 Feature Register. This bit disables an optimisation applied to a 794 sequence of 2 instructions that use opposing condition codes. 795 796config ARM_ERRATA_821420 797 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 798 depends on CPU_V7 799 help 800 This option enables the workaround for the 821420 Cortex-A12 801 (all revs) erratum. In very rare timing conditions, a sequence 802 of VMOV to Core registers instructions, for which the second 803 one is in the shadow of a branch or abort, can lead to a 804 deadlock when the VMOV instructions are issued out-of-order. 805 806config ARM_ERRATA_825619 807 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 808 depends on CPU_V7 809 help 810 This option enables the workaround for the 825619 Cortex-A12 811 (all revs) erratum. Within rare timing constraints, executing a 812 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 813 and Device/Strongly-Ordered loads and stores might cause deadlock 814 815config ARM_ERRATA_857271 816 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 817 depends on CPU_V7 818 help 819 This option enables the workaround for the 857271 Cortex-A12 820 (all revs) erratum. Under very rare timing conditions, the CPU might 821 hang. The workaround is expected to have a < 1% performance impact. 822 823config ARM_ERRATA_852421 824 bool "ARM errata: A17: DMB ST might fail to create order between stores" 825 depends on CPU_V7 826 help 827 This option enables the workaround for the 852421 Cortex-A17 828 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 829 execution of a DMB ST instruction might fail to properly order 830 stores from GroupA and stores from GroupB. 831 832config ARM_ERRATA_852423 833 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 834 depends on CPU_V7 835 help 836 This option enables the workaround for: 837 - Cortex-A17 852423: Execution of a sequence of instructions might 838 lead to either a data corruption or a CPU deadlock. Not fixed in 839 any Cortex-A17 cores yet. 840 This is identical to Cortex-A12 erratum 852422. It is a separate 841 config option from the A12 erratum due to the way errata are checked 842 for and handled. 843 844config ARM_ERRATA_857272 845 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 846 depends on CPU_V7 847 help 848 This option enables the workaround for the 857272 Cortex-A17 erratum. 849 This erratum is not known to be fixed in any A17 revision. 850 This is identical to Cortex-A12 erratum 857271. It is a separate 851 config option from the A12 erratum due to the way errata are checked 852 for and handled. 853 854endmenu 855 856source "arch/arm/common/Kconfig" 857 858menu "Bus support" 859 860config ISA 861 bool 862 help 863 Find out whether you have ISA slots on your motherboard. ISA is the 864 name of a bus system, i.e. the way the CPU talks to the other stuff 865 inside your box. Other bus systems are PCI, EISA, MicroChannel 866 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 867 newer boards don't support it. If you have ISA, say Y, otherwise N. 868 869# Select ISA DMA interface 870config ISA_DMA_API 871 bool 872 873config ARM_ERRATA_814220 874 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 875 depends on CPU_V7 876 help 877 The v7 ARM states that all cache and branch predictor maintenance 878 operations that do not specify an address execute, relative to 879 each other, in program order. 880 However, because of this erratum, an L2 set/way cache maintenance 881 operation can overtake an L1 set/way cache maintenance operation. 882 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 883 r0p4, r0p5. 884 885endmenu 886 887menu "Kernel Features" 888 889config HAVE_SMP 890 bool 891 help 892 This option should be selected by machines which have an SMP- 893 capable CPU. 894 895 The only effect of this option is to make the SMP-related 896 options available to the user for configuration. 897 898config SMP 899 bool "Symmetric Multi-Processing" 900 depends on CPU_V6K || CPU_V7 901 depends on HAVE_SMP 902 depends on MMU || ARM_MPU 903 select IRQ_WORK 904 help 905 This enables support for systems with more than one CPU. If you have 906 a system with only one CPU, say N. If you have a system with more 907 than one CPU, say Y. 908 909 If you say N here, the kernel will run on uni- and multiprocessor 910 machines, but will use only one CPU of a multiprocessor machine. If 911 you say Y here, the kernel will run on many, but not all, 912 uniprocessor machines. On a uniprocessor machine, the kernel 913 will run faster if you say N here. 914 915 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 916 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 917 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 918 919 If you don't know what to do here, say N. 920 921config SMP_ON_UP 922 bool "Allow booting SMP kernel on uniprocessor systems" 923 depends on SMP && MMU 924 default y 925 help 926 SMP kernels contain instructions which fail on non-SMP processors. 927 Enabling this option allows the kernel to modify itself to make 928 these instructions safe. Disabling it allows about 1K of space 929 savings. 930 931 If you don't know what to do here, say Y. 932 933 934config CURRENT_POINTER_IN_TPIDRURO 935 def_bool y 936 depends on CPU_32v6K && !CPU_V6 937 938config IRQSTACKS 939 def_bool y 940 select HAVE_IRQ_EXIT_ON_IRQ_STACK 941 select HAVE_SOFTIRQ_ON_OWN_STACK 942 943config ARM_CPU_TOPOLOGY 944 bool "Support cpu topology definition" 945 depends on SMP && CPU_V7 946 default y 947 help 948 Support ARM cpu topology definition. The MPIDR register defines 949 affinity between processors which is then used to describe the cpu 950 topology of an ARM System. 951 952config SCHED_MC 953 bool "Multi-core scheduler support" 954 depends on ARM_CPU_TOPOLOGY 955 help 956 Multi-core scheduler support improves the CPU scheduler's decision 957 making when dealing with multi-core CPU chips at a cost of slightly 958 increased overhead in some places. If unsure say N here. 959 960config SCHED_SMT 961 bool "SMT scheduler support" 962 depends on ARM_CPU_TOPOLOGY 963 help 964 Improves the CPU scheduler's decision making when dealing with 965 MultiThreading at a cost of slightly increased overhead in some 966 places. If unsure say N here. 967 968config HAVE_ARM_SCU 969 bool 970 help 971 This option enables support for the ARM snoop control unit 972 973config HAVE_ARM_ARCH_TIMER 974 bool "Architected timer support" 975 depends on CPU_V7 976 select ARM_ARCH_TIMER 977 help 978 This option enables support for the ARM architected timer 979 980config HAVE_ARM_TWD 981 bool 982 help 983 This options enables support for the ARM timer and watchdog unit 984 985config MCPM 986 bool "Multi-Cluster Power Management" 987 depends on CPU_V7 && SMP 988 help 989 This option provides the common power management infrastructure 990 for (multi-)cluster based systems, such as big.LITTLE based 991 systems. 992 993config MCPM_QUAD_CLUSTER 994 bool 995 depends on MCPM 996 help 997 To avoid wasting resources unnecessarily, MCPM only supports up 998 to 2 clusters by default. 999 Platforms with 3 or 4 clusters that use MCPM must select this 1000 option to allow the additional clusters to be managed. 1001 1002config BIG_LITTLE 1003 bool "big.LITTLE support (Experimental)" 1004 depends on CPU_V7 && SMP 1005 select MCPM 1006 help 1007 This option enables support selections for the big.LITTLE 1008 system architecture. 1009 1010config BL_SWITCHER 1011 bool "big.LITTLE switcher support" 1012 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1013 select CPU_PM 1014 help 1015 The big.LITTLE "switcher" provides the core functionality to 1016 transparently handle transition between a cluster of A15's 1017 and a cluster of A7's in a big.LITTLE system. 1018 1019config BL_SWITCHER_DUMMY_IF 1020 tristate "Simple big.LITTLE switcher user interface" 1021 depends on BL_SWITCHER && DEBUG_KERNEL 1022 help 1023 This is a simple and dummy char dev interface to control 1024 the big.LITTLE switcher core code. It is meant for 1025 debugging purposes only. 1026 1027choice 1028 prompt "Memory split" 1029 depends on MMU 1030 default VMSPLIT_3G 1031 help 1032 Select the desired split between kernel and user memory. 1033 1034 If you are not absolutely sure what you are doing, leave this 1035 option alone! 1036 1037 config VMSPLIT_3G 1038 bool "3G/1G user/kernel split" 1039 config VMSPLIT_3G_OPT 1040 depends on !ARM_LPAE 1041 bool "3G/1G user/kernel split (for full 1G low memory)" 1042 config VMSPLIT_2G 1043 bool "2G/2G user/kernel split" 1044 config VMSPLIT_1G 1045 bool "1G/3G user/kernel split" 1046endchoice 1047 1048config PAGE_OFFSET 1049 hex 1050 default PHYS_OFFSET if !MMU 1051 default 0x40000000 if VMSPLIT_1G 1052 default 0x80000000 if VMSPLIT_2G 1053 default 0xB0000000 if VMSPLIT_3G_OPT 1054 default 0xC0000000 1055 1056config KASAN_SHADOW_OFFSET 1057 hex 1058 depends on KASAN 1059 default 0x1f000000 if PAGE_OFFSET=0x40000000 1060 default 0x5f000000 if PAGE_OFFSET=0x80000000 1061 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1062 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1063 default 0xffffffff 1064 1065config NR_CPUS 1066 int "Maximum number of CPUs (2-32)" 1067 range 2 16 if DEBUG_KMAP_LOCAL 1068 range 2 32 if !DEBUG_KMAP_LOCAL 1069 depends on SMP 1070 default "4" 1071 help 1072 The maximum number of CPUs that the kernel can support. 1073 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1074 debugging is enabled, which uses half of the per-CPU fixmap 1075 slots as guard regions. 1076 1077config HOTPLUG_CPU 1078 bool "Support for hot-pluggable CPUs" 1079 depends on SMP 1080 select GENERIC_IRQ_MIGRATION 1081 help 1082 Say Y here to experiment with turning CPUs off and on. CPUs 1083 can be controlled through /sys/devices/system/cpu. 1084 1085config ARM_PSCI 1086 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1087 depends on HAVE_ARM_SMCCC 1088 select ARM_PSCI_FW 1089 help 1090 Say Y here if you want Linux to communicate with system firmware 1091 implementing the PSCI specification for CPU-centric power 1092 management operations described in ARM document number ARM DEN 1093 0022A ("Power State Coordination Interface System Software on 1094 ARM processors"). 1095 1096config HZ_FIXED 1097 int 1098 default 128 if SOC_AT91RM9200 1099 default 0 1100 1101choice 1102 depends on HZ_FIXED = 0 1103 prompt "Timer frequency" 1104 1105config HZ_100 1106 bool "100 Hz" 1107 1108config HZ_200 1109 bool "200 Hz" 1110 1111config HZ_250 1112 bool "250 Hz" 1113 1114config HZ_300 1115 bool "300 Hz" 1116 1117config HZ_500 1118 bool "500 Hz" 1119 1120config HZ_1000 1121 bool "1000 Hz" 1122 1123endchoice 1124 1125config HZ 1126 int 1127 default HZ_FIXED if HZ_FIXED != 0 1128 default 100 if HZ_100 1129 default 200 if HZ_200 1130 default 250 if HZ_250 1131 default 300 if HZ_300 1132 default 500 if HZ_500 1133 default 1000 1134 1135config SCHED_HRTICK 1136 def_bool HIGH_RES_TIMERS 1137 1138config THUMB2_KERNEL 1139 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1140 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1141 default y if CPU_THUMBONLY 1142 select ARM_UNWIND 1143 help 1144 By enabling this option, the kernel will be compiled in 1145 Thumb-2 mode. 1146 1147 If unsure, say N. 1148 1149config ARM_PATCH_IDIV 1150 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1151 depends on CPU_32v7 1152 default y 1153 help 1154 The ARM compiler inserts calls to __aeabi_idiv() and 1155 __aeabi_uidiv() when it needs to perform division on signed 1156 and unsigned integers. Some v7 CPUs have support for the sdiv 1157 and udiv instructions that can be used to implement those 1158 functions. 1159 1160 Enabling this option allows the kernel to modify itself to 1161 replace the first two instructions of these library functions 1162 with the sdiv or udiv plus "bx lr" instructions when the CPU 1163 it is running on supports them. Typically this will be faster 1164 and less power intensive than running the original library 1165 code to do integer division. 1166 1167config AEABI 1168 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1169 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1170 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1171 help 1172 This option allows for the kernel to be compiled using the latest 1173 ARM ABI (aka EABI). This is only useful if you are using a user 1174 space environment that is also compiled with EABI. 1175 1176 Since there are major incompatibilities between the legacy ABI and 1177 EABI, especially with regard to structure member alignment, this 1178 option also changes the kernel syscall calling convention to 1179 disambiguate both ABIs and allow for backward compatibility support 1180 (selected with CONFIG_OABI_COMPAT). 1181 1182 To use this you need GCC version 4.0.0 or later. 1183 1184config OABI_COMPAT 1185 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1186 depends on AEABI && !THUMB2_KERNEL 1187 help 1188 This option preserves the old syscall interface along with the 1189 new (ARM EABI) one. It also provides a compatibility layer to 1190 intercept syscalls that have structure arguments which layout 1191 in memory differs between the legacy ABI and the new ARM EABI 1192 (only for non "thumb" binaries). This option adds a tiny 1193 overhead to all syscalls and produces a slightly larger kernel. 1194 1195 The seccomp filter system will not be available when this is 1196 selected, since there is no way yet to sensibly distinguish 1197 between calling conventions during filtering. 1198 1199 If you know you'll be using only pure EABI user space then you 1200 can say N here. If this option is not selected and you attempt 1201 to execute a legacy ABI binary then the result will be 1202 UNPREDICTABLE (in fact it can be predicted that it won't work 1203 at all). If in doubt say N. 1204 1205config ARCH_SELECT_MEMORY_MODEL 1206 def_bool y 1207 1208config ARCH_FLATMEM_ENABLE 1209 def_bool !(ARCH_RPC || ARCH_SA1100) 1210 1211config ARCH_SPARSEMEM_ENABLE 1212 def_bool !ARCH_FOOTBRIDGE 1213 select SPARSEMEM_STATIC if SPARSEMEM 1214 1215config HIGHMEM 1216 bool "High Memory Support" 1217 depends on MMU 1218 select KMAP_LOCAL 1219 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1220 help 1221 The address space of ARM processors is only 4 Gigabytes large 1222 and it has to accommodate user address space, kernel address 1223 space as well as some memory mapped IO. That means that, if you 1224 have a large amount of physical memory and/or IO, not all of the 1225 memory can be "permanently mapped" by the kernel. The physical 1226 memory that is not permanently mapped is called "high memory". 1227 1228 Depending on the selected kernel/user memory split, minimum 1229 vmalloc space and actual amount of RAM, you may not need this 1230 option which should result in a slightly faster kernel. 1231 1232 If unsure, say n. 1233 1234config HIGHPTE 1235 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1236 depends on HIGHMEM 1237 default y 1238 help 1239 The VM uses one page of physical memory for each page table. 1240 For systems with a lot of processes, this can use a lot of 1241 precious low memory, eventually leading to low memory being 1242 consumed by page tables. Setting this option will allow 1243 user-space 2nd level page tables to reside in high memory. 1244 1245config ARM_PAN 1246 bool "Enable privileged no-access" 1247 depends on MMU 1248 default y 1249 help 1250 Increase kernel security by ensuring that normal kernel accesses 1251 are unable to access userspace addresses. This can help prevent 1252 use-after-free bugs becoming an exploitable privilege escalation 1253 by ensuring that magic values (such as LIST_POISON) will always 1254 fault when dereferenced. 1255 1256 The implementation uses CPU domains when !CONFIG_ARM_LPAE and 1257 disabling of TTBR0 page table walks with CONFIG_ARM_LPAE. 1258 1259config CPU_SW_DOMAIN_PAN 1260 def_bool y 1261 depends on ARM_PAN && !ARM_LPAE 1262 help 1263 Enable use of CPU domains to implement privileged no-access. 1264 1265 CPUs with low-vector mappings use a best-efforts implementation. 1266 Their lower 1MB needs to remain accessible for the vectors, but 1267 the remainder of userspace will become appropriately inaccessible. 1268 1269config CPU_TTBR0_PAN 1270 def_bool y 1271 depends on ARM_PAN && ARM_LPAE 1272 help 1273 Enable privileged no-access by disabling TTBR0 page table walks when 1274 running in kernel mode. 1275 1276config HW_PERF_EVENTS 1277 def_bool y 1278 depends on ARM_PMU 1279 1280config ARM_MODULE_PLTS 1281 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1282 depends on MODULES 1283 select KASAN_VMALLOC if KASAN 1284 default y 1285 help 1286 Allocate PLTs when loading modules so that jumps and calls whose 1287 targets are too far away for their relative offsets to be encoded 1288 in the instructions themselves can be bounced via veneers in the 1289 module's PLT. This allows modules to be allocated in the generic 1290 vmalloc area after the dedicated module memory area has been 1291 exhausted. The modules will use slightly more memory, but after 1292 rounding up to page size, the actual memory footprint is usually 1293 the same. 1294 1295 Disabling this is usually safe for small single-platform 1296 configurations. If unsure, say y. 1297 1298config ARCH_FORCE_MAX_ORDER 1299 int "Order of maximal physically contiguous allocations" 1300 default "11" if SOC_AM33XX 1301 default "8" if SA1111 1302 default "10" 1303 help 1304 The kernel page allocator limits the size of maximal physically 1305 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 1306 defines the maximal power of two of number of pages that can be 1307 allocated as a single contiguous block. This option allows 1308 overriding the default setting when ability to allocate very 1309 large blocks of physically contiguous memory is required. 1310 1311 Don't change if unsure. 1312 1313config ALIGNMENT_TRAP 1314 def_bool CPU_CP15_MMU 1315 select HAVE_PROC_CPU if PROC_FS 1316 help 1317 ARM processors cannot fetch/store information which is not 1318 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1319 address divisible by 4. On 32-bit ARM processors, these non-aligned 1320 fetch/store instructions will be emulated in software if you say 1321 here, which has a severe performance impact. This is necessary for 1322 correct operation of some network protocols. With an IP-only 1323 configuration it is safe to say N, otherwise say Y. 1324 1325config UACCESS_WITH_MEMCPY 1326 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1327 depends on MMU 1328 default y if CPU_FEROCEON 1329 help 1330 Implement faster copy_to_user and clear_user methods for CPU 1331 cores where a 8-word STM instruction give significantly higher 1332 memory write throughput than a sequence of individual 32bit stores. 1333 1334 A possible side effect is a slight increase in scheduling latency 1335 between threads sharing the same address space if they invoke 1336 such copy operations with large buffers. 1337 1338 However, if the CPU data cache is using a write-allocate mode, 1339 this option is unlikely to provide any performance gain. 1340 1341config PARAVIRT 1342 bool "Enable paravirtualization code" 1343 help 1344 This changes the kernel so it can modify itself when it is run 1345 under a hypervisor, potentially improving performance significantly 1346 over full virtualization. 1347 1348config PARAVIRT_TIME_ACCOUNTING 1349 bool "Paravirtual steal time accounting" 1350 select PARAVIRT 1351 help 1352 Select this option to enable fine granularity task steal time 1353 accounting. Time spent executing other tasks in parallel with 1354 the current vCPU is discounted from the vCPU power. To account for 1355 that, there can be a small performance impact. 1356 1357 If in doubt, say N here. 1358 1359config XEN_DOM0 1360 def_bool y 1361 depends on XEN 1362 1363config XEN 1364 bool "Xen guest support on ARM" 1365 depends on ARM && AEABI && OF 1366 depends on CPU_V7 && !CPU_V6 1367 depends on !GENERIC_ATOMIC64 1368 depends on MMU 1369 select ARCH_DMA_ADDR_T_64BIT 1370 select ARM_PSCI 1371 select SWIOTLB 1372 select SWIOTLB_XEN 1373 select PARAVIRT 1374 help 1375 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1376 1377config CC_HAVE_STACKPROTECTOR_TLS 1378 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1379 1380config STACKPROTECTOR_PER_TASK 1381 bool "Use a unique stack canary value for each task" 1382 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1383 depends on CC_HAVE_STACKPROTECTOR_TLS 1384 default y 1385 help 1386 Due to the fact that GCC uses an ordinary symbol reference from 1387 which to load the value of the stack canary, this value can only 1388 change at reboot time on SMP systems, and all tasks running in the 1389 kernel's address space are forced to use the same canary value for 1390 the entire duration that the system is up. 1391 1392 Enable this option to switch to a different method that uses a 1393 different canary value for each task. 1394 1395endmenu 1396 1397menu "Boot options" 1398 1399config USE_OF 1400 bool "Flattened Device Tree support" 1401 select IRQ_DOMAIN 1402 select OF 1403 help 1404 Include support for flattened device tree machine descriptions. 1405 1406config ARCH_WANT_FLAT_DTB_INSTALL 1407 def_bool y 1408 1409config ATAGS 1410 bool "Support for the traditional ATAGS boot data passing" 1411 default y 1412 help 1413 This is the traditional way of passing data to the kernel at boot 1414 time. If you are solely relying on the flattened device tree (or 1415 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1416 to remove ATAGS support from your kernel binary. 1417 1418config DEPRECATED_PARAM_STRUCT 1419 bool "Provide old way to pass kernel parameters" 1420 depends on ATAGS 1421 help 1422 This was deprecated in 2001 and announced to live on for 5 years. 1423 Some old boot loaders still use this way. 1424 1425# Compressed boot loader in ROM. Yes, we really want to ask about 1426# TEXT and BSS so we preserve their values in the config files. 1427config ZBOOT_ROM_TEXT 1428 hex "Compressed ROM boot loader base address" 1429 default 0x0 1430 help 1431 The physical address at which the ROM-able zImage is to be 1432 placed in the target. Platforms which normally make use of 1433 ROM-able zImage formats normally set this to a suitable 1434 value in their defconfig file. 1435 1436 If ZBOOT_ROM is not enabled, this has no effect. 1437 1438config ZBOOT_ROM_BSS 1439 hex "Compressed ROM boot loader BSS address" 1440 default 0x0 1441 help 1442 The base address of an area of read/write memory in the target 1443 for the ROM-able zImage which must be available while the 1444 decompressor is running. It must be large enough to hold the 1445 entire decompressed kernel plus an additional 128 KiB. 1446 Platforms which normally make use of ROM-able zImage formats 1447 normally set this to a suitable value in their defconfig file. 1448 1449 If ZBOOT_ROM is not enabled, this has no effect. 1450 1451config ZBOOT_ROM 1452 bool "Compressed boot loader in ROM/flash" 1453 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1454 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1455 help 1456 Say Y here if you intend to execute your compressed kernel image 1457 (zImage) directly from ROM or flash. If unsure, say N. 1458 1459config ARM_APPENDED_DTB 1460 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1461 depends on OF 1462 help 1463 With this option, the boot code will look for a device tree binary 1464 (DTB) appended to zImage 1465 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1466 1467 This is meant as a backward compatibility convenience for those 1468 systems with a bootloader that can't be upgraded to accommodate 1469 the documented boot protocol using a device tree. 1470 1471 Beware that there is very little in terms of protection against 1472 this option being confused by leftover garbage in memory that might 1473 look like a DTB header after a reboot if no actual DTB is appended 1474 to zImage. Do not leave this option active in a production kernel 1475 if you don't intend to always append a DTB. Proper passing of the 1476 location into r2 of a bootloader provided DTB is always preferable 1477 to this option. 1478 1479config ARM_ATAG_DTB_COMPAT 1480 bool "Supplement the appended DTB with traditional ATAG information" 1481 depends on ARM_APPENDED_DTB 1482 help 1483 Some old bootloaders can't be updated to a DTB capable one, yet 1484 they provide ATAGs with memory configuration, the ramdisk address, 1485 the kernel cmdline string, etc. Such information is dynamically 1486 provided by the bootloader and can't always be stored in a static 1487 DTB. To allow a device tree enabled kernel to be used with such 1488 bootloaders, this option allows zImage to extract the information 1489 from the ATAG list and store it at run time into the appended DTB. 1490 1491choice 1492 prompt "Kernel command line type" 1493 depends on ARM_ATAG_DTB_COMPAT 1494 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1495 1496config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1497 bool "Use bootloader kernel arguments if available" 1498 help 1499 Uses the command-line options passed by the boot loader instead of 1500 the device tree bootargs property. If the boot loader doesn't provide 1501 any, the device tree bootargs property will be used. 1502 1503config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1504 bool "Extend with bootloader kernel arguments" 1505 help 1506 The command-line arguments provided by the boot loader will be 1507 appended to the the device tree bootargs property. 1508 1509endchoice 1510 1511config CMDLINE 1512 string "Default kernel command string" 1513 default "" 1514 help 1515 On some architectures (e.g. CATS), there is currently no way 1516 for the boot loader to pass arguments to the kernel. For these 1517 architectures, you should supply some command-line options at build 1518 time by entering them here. As a minimum, you should specify the 1519 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1520 1521choice 1522 prompt "Kernel command line type" 1523 depends on CMDLINE != "" 1524 default CMDLINE_FROM_BOOTLOADER 1525 1526config CMDLINE_FROM_BOOTLOADER 1527 bool "Use bootloader kernel arguments if available" 1528 help 1529 Uses the command-line options passed by the boot loader. If 1530 the boot loader doesn't provide any, the default kernel command 1531 string provided in CMDLINE will be used. 1532 1533config CMDLINE_EXTEND 1534 bool "Extend bootloader kernel arguments" 1535 help 1536 The command-line arguments provided by the boot loader will be 1537 appended to the default kernel command string. 1538 1539config CMDLINE_FORCE 1540 bool "Always use the default kernel command string" 1541 help 1542 Always use the default kernel command string, even if the boot 1543 loader passes other arguments to the kernel. 1544 This is useful if you cannot or don't want to change the 1545 command-line options your boot loader passes to the kernel. 1546endchoice 1547 1548config XIP_KERNEL 1549 bool "Kernel Execute-In-Place from ROM" 1550 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1551 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1552 help 1553 Execute-In-Place allows the kernel to run from non-volatile storage 1554 directly addressable by the CPU, such as NOR flash. This saves RAM 1555 space since the text section of the kernel is not loaded from flash 1556 to RAM. Read-write sections, such as the data section and stack, 1557 are still copied to RAM. The XIP kernel is not compressed since 1558 it has to run directly from flash, so it will take more space to 1559 store it. The flash address used to link the kernel object files, 1560 and for storing it, is configuration dependent. Therefore, if you 1561 say Y here, you must know the proper physical address where to 1562 store the kernel image depending on your own flash memory usage. 1563 1564 Also note that the make target becomes "make xipImage" rather than 1565 "make zImage" or "make Image". The final kernel binary to put in 1566 ROM memory will be arch/arm/boot/xipImage. 1567 1568 If unsure, say N. 1569 1570config XIP_PHYS_ADDR 1571 hex "XIP Kernel Physical Location" 1572 depends on XIP_KERNEL 1573 default "0x00080000" 1574 help 1575 This is the physical address in your flash memory the kernel will 1576 be linked for and stored to. This address is dependent on your 1577 own flash usage. 1578 1579config XIP_DEFLATED_DATA 1580 bool "Store kernel .data section compressed in ROM" 1581 depends on XIP_KERNEL 1582 select ZLIB_INFLATE 1583 help 1584 Before the kernel is actually executed, its .data section has to be 1585 copied to RAM from ROM. This option allows for storing that data 1586 in compressed form and decompressed to RAM rather than merely being 1587 copied, saving some precious ROM space. A possible drawback is a 1588 slightly longer boot delay. 1589 1590config ARCH_SUPPORTS_KEXEC 1591 def_bool (!SMP || PM_SLEEP_SMP) && MMU 1592 1593config ATAGS_PROC 1594 bool "Export atags in procfs" 1595 depends on ATAGS && KEXEC 1596 default y 1597 help 1598 Should the atags used to boot the kernel be exported in an "atags" 1599 file in procfs. Useful with kexec. 1600 1601config ARCH_SUPPORTS_CRASH_DUMP 1602 def_bool y 1603 1604config ARCH_DEFAULT_CRASH_DUMP 1605 def_bool y 1606 1607config AUTO_ZRELADDR 1608 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1609 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1610 help 1611 ZRELADDR is the physical address where the decompressed kernel 1612 image will be placed. If AUTO_ZRELADDR is selected, the address 1613 will be determined at run-time, either by masking the current IP 1614 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1615 This assumes the zImage being placed in the first 128MB from 1616 start of memory. 1617 1618config EFI_STUB 1619 bool 1620 1621config EFI 1622 bool "UEFI runtime support" 1623 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1624 select UCS2_STRING 1625 select EFI_PARAMS_FROM_FDT 1626 select EFI_STUB 1627 select EFI_GENERIC_STUB 1628 select EFI_RUNTIME_WRAPPERS 1629 help 1630 This option provides support for runtime services provided 1631 by UEFI firmware (such as non-volatile variables, realtime 1632 clock, and platform reset). A UEFI stub is also provided to 1633 allow the kernel to be booted as an EFI application. This 1634 is only useful for kernels that may run on systems that have 1635 UEFI firmware. 1636 1637config DMI 1638 bool "Enable support for SMBIOS (DMI) tables" 1639 depends on EFI 1640 default y 1641 help 1642 This enables SMBIOS/DMI feature for systems. 1643 1644 This option is only useful on systems that have UEFI firmware. 1645 However, even with this option, the resultant kernel should 1646 continue to boot on existing non-UEFI platforms. 1647 1648 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1649 i.e., the the practice of identifying the platform via DMI to 1650 decide whether certain workarounds for buggy hardware and/or 1651 firmware need to be enabled. This would require the DMI subsystem 1652 to be enabled much earlier than we do on ARM, which is non-trivial. 1653 1654endmenu 1655 1656menu "CPU Power Management" 1657 1658source "drivers/cpufreq/Kconfig" 1659 1660source "drivers/cpuidle/Kconfig" 1661 1662endmenu 1663 1664menu "Floating point emulation" 1665 1666comment "At least one emulation must be selected" 1667 1668config FPE_NWFPE 1669 bool "NWFPE math emulation" 1670 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1671 help 1672 Say Y to include the NWFPE floating point emulator in the kernel. 1673 This is necessary to run most binaries. Linux does not currently 1674 support floating point hardware so you need to say Y here even if 1675 your machine has an FPA or floating point co-processor podule. 1676 1677 You may say N here if you are going to load the Acorn FPEmulator 1678 early in the bootup. 1679 1680config FPE_NWFPE_XP 1681 bool "Support extended precision" 1682 depends on FPE_NWFPE 1683 help 1684 Say Y to include 80-bit support in the kernel floating-point 1685 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1686 Note that gcc does not generate 80-bit operations by default, 1687 so in most cases this option only enlarges the size of the 1688 floating point emulator without any good reason. 1689 1690 You almost surely want to say N here. 1691 1692config FPE_FASTFPE 1693 bool "FastFPE math emulation (EXPERIMENTAL)" 1694 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1695 help 1696 Say Y here to include the FAST floating point emulator in the kernel. 1697 This is an experimental much faster emulator which now also has full 1698 precision for the mantissa. It does not support any exceptions. 1699 It is very simple, and approximately 3-6 times faster than NWFPE. 1700 1701 It should be sufficient for most programs. It may be not suitable 1702 for scientific calculations, but you have to check this for yourself. 1703 If you do not feel you need a faster FP emulation you should better 1704 choose NWFPE. 1705 1706config VFP 1707 bool "VFP-format floating point maths" 1708 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1709 help 1710 Say Y to include VFP support code in the kernel. This is needed 1711 if your hardware includes a VFP unit. 1712 1713 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for 1714 release notes and additional status information. 1715 1716 Say N if your target does not have VFP hardware. 1717 1718config VFPv3 1719 bool 1720 depends on VFP 1721 default y if CPU_V7 1722 1723config NEON 1724 bool "Advanced SIMD (NEON) Extension support" 1725 depends on VFPv3 && CPU_V7 1726 help 1727 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1728 Extension. 1729 1730config KERNEL_MODE_NEON 1731 bool "Support for NEON in kernel mode" 1732 depends on NEON && AEABI 1733 help 1734 Say Y to include support for NEON in kernel mode. 1735 1736endmenu 1737 1738menu "Power management options" 1739 1740source "kernel/power/Kconfig" 1741 1742config ARCH_SUSPEND_POSSIBLE 1743 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1744 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1745 def_bool y 1746 1747config ARM_CPU_SUSPEND 1748 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1749 depends on ARCH_SUSPEND_POSSIBLE 1750 1751config ARCH_HIBERNATION_POSSIBLE 1752 bool 1753 depends on MMU 1754 default y if ARCH_SUSPEND_POSSIBLE 1755 1756endmenu 1757