1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_USE_MEMTEST 38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 39 select ARCH_WANT_IPC_PARSE_VERSION 40 select ARCH_WANT_LD_ORPHAN_WARN 41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 42 select BUILDTIME_TABLE_SORT if MMU 43 select CLONE_BACKWARDS 44 select CPU_PM if SUSPEND || CPU_IDLE 45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 46 select DMA_DECLARE_COHERENT 47 select DMA_OPS 48 select DMA_REMAP if MMU 49 select EDAC_SUPPORT 50 select EDAC_ATOMIC_SCRUB 51 select GENERIC_ALLOCATOR 52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 55 select GENERIC_IRQ_IPI if SMP 56 select GENERIC_CPU_AUTOPROBE 57 select GENERIC_EARLY_IOREMAP 58 select GENERIC_IDLE_POLL_SETUP 59 select GENERIC_IRQ_PROBE 60 select GENERIC_IRQ_SHOW 61 select GENERIC_IRQ_SHOW_LEVEL 62 select GENERIC_LIB_DEVMEM_IS_ALLOWED 63 select GENERIC_PCI_IOMAP 64 select GENERIC_SCHED_CLOCK 65 select GENERIC_SMP_IDLE_THREAD 66 select GENERIC_STRNCPY_FROM_USER 67 select GENERIC_STRNLEN_USER 68 select HANDLE_DOMAIN_IRQ 69 select HARDIRQS_SW_RESEND 70 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 71 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 72 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 73 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 74 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 75 select HAVE_ARCH_MMAP_RND_BITS if MMU 76 select HAVE_ARCH_PFN_VALID 77 select HAVE_ARCH_SECCOMP 78 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 79 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 80 select HAVE_ARCH_TRACEHOOK 81 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 82 select HAVE_ARM_SMCCC if CPU_V7 83 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 84 select HAVE_CONTEXT_TRACKING 85 select HAVE_C_RECORDMCOUNT 86 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 87 select HAVE_DMA_CONTIGUOUS if MMU 88 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 89 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 90 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 91 select HAVE_EXIT_THREAD 92 select HAVE_FAST_GUP if ARM_LPAE 93 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 94 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 95 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 96 select HAVE_GCC_PLUGINS 97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 98 select HAVE_IDE if PCI || ISA || PCMCIA 99 select HAVE_IRQ_TIME_ACCOUNTING 100 select HAVE_KERNEL_GZIP 101 select HAVE_KERNEL_LZ4 102 select HAVE_KERNEL_LZMA 103 select HAVE_KERNEL_LZO 104 select HAVE_KERNEL_XZ 105 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 106 select HAVE_KRETPROBES if HAVE_KPROBES 107 select HAVE_MOD_ARCH_SPECIFIC 108 select HAVE_NMI 109 select HAVE_OPTPROBES if !THUMB2_KERNEL 110 select HAVE_PERF_EVENTS 111 select HAVE_PERF_REGS 112 select HAVE_PERF_USER_STACK_DUMP 113 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 114 select HAVE_REGS_AND_STACK_ACCESS_API 115 select HAVE_RSEQ 116 select HAVE_STACKPROTECTOR 117 select HAVE_SYSCALL_TRACEPOINTS 118 select HAVE_UID16 119 select HAVE_VIRT_CPU_ACCOUNTING_GEN 120 select IRQ_FORCED_THREADING 121 select MODULES_USE_ELF_REL 122 select NEED_DMA_MAP_STATE 123 select OF_EARLY_FLATTREE if OF 124 select OLD_SIGACTION 125 select OLD_SIGSUSPEND3 126 select PCI_SYSCALL if PCI 127 select PERF_USE_VMALLOC 128 select RTC_LIB 129 select SET_FS 130 select SYS_SUPPORTS_APM_EMULATION 131 # Above selects are sorted alphabetically; please add new ones 132 # according to that. Thanks. 133 help 134 The ARM series is a line of low-power-consumption RISC chip designs 135 licensed by ARM Ltd and targeted at embedded applications and 136 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 137 manufactured, but legacy ARM-based PC hardware remains popular in 138 Europe. There is an ARM Linux project with a web page at 139 <http://www.arm.linux.org.uk/>. 140 141config ARM_HAS_SG_CHAIN 142 bool 143 144config ARM_DMA_USE_IOMMU 145 bool 146 select ARM_HAS_SG_CHAIN 147 select NEED_SG_DMA_LENGTH 148 149if ARM_DMA_USE_IOMMU 150 151config ARM_DMA_IOMMU_ALIGNMENT 152 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 153 range 4 9 154 default 8 155 help 156 DMA mapping framework by default aligns all buffers to the smallest 157 PAGE_SIZE order which is greater than or equal to the requested buffer 158 size. This works well for buffers up to a few hundreds kilobytes, but 159 for larger buffers it just a waste of address space. Drivers which has 160 relatively small addressing window (like 64Mib) might run out of 161 virtual space with just a few allocations. 162 163 With this parameter you can specify the maximum PAGE_SIZE order for 164 DMA IOMMU buffers. Larger buffers will be aligned only to this 165 specified order. The order is expressed as a power of two multiplied 166 by the PAGE_SIZE. 167 168endif 169 170config SYS_SUPPORTS_APM_EMULATION 171 bool 172 173config HAVE_TCM 174 bool 175 select GENERIC_ALLOCATOR 176 177config HAVE_PROC_CPU 178 bool 179 180config NO_IOPORT_MAP 181 bool 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config TRACE_IRQFLAGS_SUPPORT 195 bool 196 default !CPU_V7M 197 198config ARCH_HAS_ILOG2_U32 199 bool 200 201config ARCH_HAS_ILOG2_U64 202 bool 203 204config ARCH_HAS_BANDGAP 205 bool 206 207config FIX_EARLYCON_MEM 208 def_bool y if MMU 209 210config GENERIC_HWEIGHT 211 bool 212 default y 213 214config GENERIC_CALIBRATE_DELAY 215 bool 216 default y 217 218config ARCH_MAY_HAVE_PC_FDC 219 bool 220 221config ZONE_DMA 222 bool 223 224config ARCH_SUPPORTS_UPROBES 225 def_bool y 226 227config ARCH_HAS_DMA_SET_COHERENT_MASK 228 bool 229 230config GENERIC_ISA_DMA 231 bool 232 233config FIQ 234 bool 235 236config NEED_RET_TO_USER 237 bool 238 239config ARCH_MTD_XIP 240 bool 241 242config ARM_PATCH_PHYS_VIRT 243 bool "Patch physical to virtual translations at runtime" if EMBEDDED 244 default y 245 depends on !XIP_KERNEL && MMU 246 help 247 Patch phys-to-virt and virt-to-phys translation functions at 248 boot and module load time according to the position of the 249 kernel in system memory. 250 251 This can only be used with non-XIP MMU kernels where the base 252 of physical memory is at a 2 MiB boundary. 253 254 Only disable this option if you know that you do not require 255 this feature (eg, building a kernel for a single machine) and 256 you need to shrink the kernel to the minimal size. 257 258config NEED_MACH_IO_H 259 bool 260 help 261 Select this when mach/io.h is required to provide special 262 definitions for this platform. The need for mach/io.h should 263 be avoided when possible. 264 265config NEED_MACH_MEMORY_H 266 bool 267 help 268 Select this when mach/memory.h is required to provide special 269 definitions for this platform. The need for mach/memory.h should 270 be avoided when possible. 271 272config PHYS_OFFSET 273 hex "Physical address of main memory" if MMU 274 depends on !ARM_PATCH_PHYS_VIRT 275 default DRAM_BASE if !MMU 276 default 0x00000000 if ARCH_FOOTBRIDGE 277 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 278 default 0x20000000 if ARCH_S5PV210 279 default 0xc0000000 if ARCH_SA1100 280 help 281 Please provide the physical address corresponding to the 282 location of main memory in your system. 283 284config GENERIC_BUG 285 def_bool y 286 depends on BUG 287 288config PGTABLE_LEVELS 289 int 290 default 3 if ARM_LPAE 291 default 2 292 293menu "System Type" 294 295config MMU 296 bool "MMU-based Paged Memory Management Support" 297 default y 298 help 299 Select if you want MMU-based virtualised addressing space 300 support by paged memory management. If unsure, say 'Y'. 301 302config ARCH_MMAP_RND_BITS_MIN 303 default 8 304 305config ARCH_MMAP_RND_BITS_MAX 306 default 14 if PAGE_OFFSET=0x40000000 307 default 15 if PAGE_OFFSET=0x80000000 308 default 16 309 310# 311# The "ARM system type" choice list is ordered alphabetically by option 312# text. Please add new entries in the option alphabetic order. 313# 314choice 315 prompt "ARM system type" 316 default ARM_SINGLE_ARMV7M if !MMU 317 default ARCH_MULTIPLATFORM if MMU 318 319config ARCH_MULTIPLATFORM 320 bool "Allow multiple platforms to be selected" 321 depends on MMU 322 select ARCH_FLATMEM_ENABLE 323 select ARCH_SPARSEMEM_ENABLE 324 select ARCH_SELECT_MEMORY_MODEL 325 select ARM_HAS_SG_CHAIN 326 select ARM_PATCH_PHYS_VIRT 327 select AUTO_ZRELADDR 328 select TIMER_OF 329 select COMMON_CLK 330 select GENERIC_IRQ_MULTI_HANDLER 331 select HAVE_PCI 332 select PCI_DOMAINS_GENERIC if PCI 333 select SPARSE_IRQ 334 select USE_OF 335 336config ARM_SINGLE_ARMV7M 337 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 338 depends on !MMU 339 select ARM_NVIC 340 select AUTO_ZRELADDR 341 select TIMER_OF 342 select COMMON_CLK 343 select CPU_V7M 344 select NO_IOPORT_MAP 345 select SPARSE_IRQ 346 select USE_OF 347 348config ARCH_EP93XX 349 bool "EP93xx-based" 350 select ARCH_SPARSEMEM_ENABLE 351 select ARM_AMBA 352 imply ARM_PATCH_PHYS_VIRT 353 select ARM_VIC 354 select GENERIC_IRQ_MULTI_HANDLER 355 select AUTO_ZRELADDR 356 select CLKDEV_LOOKUP 357 select CLKSRC_MMIO 358 select CPU_ARM920T 359 select GPIOLIB 360 select HAVE_LEGACY_CLK 361 help 362 This enables support for the Cirrus EP93xx series of CPUs. 363 364config ARCH_FOOTBRIDGE 365 bool "FootBridge" 366 select CPU_SA110 367 select FOOTBRIDGE 368 select HAVE_IDE 369 select NEED_MACH_IO_H if !MMU 370 select NEED_MACH_MEMORY_H 371 help 372 Support for systems based on the DC21285 companion chip 373 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 374 375config ARCH_IOP32X 376 bool "IOP32x-based" 377 depends on MMU 378 select CPU_XSCALE 379 select GPIO_IOP 380 select GPIOLIB 381 select NEED_RET_TO_USER 382 select FORCE_PCI 383 select PLAT_IOP 384 help 385 Support for Intel's 80219 and IOP32X (XScale) family of 386 processors. 387 388config ARCH_IXP4XX 389 bool "IXP4xx-based" 390 depends on MMU 391 select ARCH_HAS_DMA_SET_COHERENT_MASK 392 select ARCH_SUPPORTS_BIG_ENDIAN 393 select CPU_XSCALE 394 select DMABOUNCE if PCI 395 select GENERIC_IRQ_MULTI_HANDLER 396 select GPIO_IXP4XX 397 select GPIOLIB 398 select HAVE_PCI 399 select IXP4XX_IRQ 400 select IXP4XX_TIMER 401 select NEED_MACH_IO_H 402 select USB_EHCI_BIG_ENDIAN_DESC 403 select USB_EHCI_BIG_ENDIAN_MMIO 404 help 405 Support for Intel's IXP4XX (XScale) family of processors. 406 407config ARCH_DOVE 408 bool "Marvell Dove" 409 select CPU_PJ4 410 select GENERIC_IRQ_MULTI_HANDLER 411 select GPIOLIB 412 select HAVE_PCI 413 select MVEBU_MBUS 414 select PINCTRL 415 select PINCTRL_DOVE 416 select PLAT_ORION_LEGACY 417 select SPARSE_IRQ 418 select PM_GENERIC_DOMAINS if PM 419 help 420 Support for the Marvell Dove SoC 88AP510 421 422config ARCH_PXA 423 bool "PXA2xx/PXA3xx-based" 424 depends on MMU 425 select ARCH_MTD_XIP 426 select ARM_CPU_SUSPEND if PM 427 select AUTO_ZRELADDR 428 select COMMON_CLK 429 select CLKSRC_PXA 430 select CLKSRC_MMIO 431 select TIMER_OF 432 select CPU_XSCALE if !CPU_XSC3 433 select GENERIC_IRQ_MULTI_HANDLER 434 select GPIO_PXA 435 select GPIOLIB 436 select HAVE_IDE 437 select IRQ_DOMAIN 438 select PLAT_PXA 439 select SPARSE_IRQ 440 help 441 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 442 443config ARCH_RPC 444 bool "RiscPC" 445 depends on MMU 446 select ARCH_ACORN 447 select ARCH_MAY_HAVE_PC_FDC 448 select ARCH_SPARSEMEM_ENABLE 449 select ARM_HAS_SG_CHAIN 450 select CPU_SA110 451 select FIQ 452 select HAVE_IDE 453 select HAVE_PATA_PLATFORM 454 select ISA_DMA_API 455 select LEGACY_TIMER_TICK 456 select NEED_MACH_IO_H 457 select NEED_MACH_MEMORY_H 458 select NO_IOPORT_MAP 459 help 460 On the Acorn Risc-PC, Linux can support the internal IDE disk and 461 CD-ROM interface, serial and parallel port, and the floppy drive. 462 463config ARCH_SA1100 464 bool "SA1100-based" 465 select ARCH_MTD_XIP 466 select ARCH_SPARSEMEM_ENABLE 467 select CLKSRC_MMIO 468 select CLKSRC_PXA 469 select TIMER_OF if OF 470 select COMMON_CLK 471 select CPU_FREQ 472 select CPU_SA1100 473 select GENERIC_IRQ_MULTI_HANDLER 474 select GPIOLIB 475 select HAVE_IDE 476 select IRQ_DOMAIN 477 select ISA 478 select NEED_MACH_MEMORY_H 479 select SPARSE_IRQ 480 help 481 Support for StrongARM 11x0 based boards. 482 483config ARCH_S3C24XX 484 bool "Samsung S3C24XX SoCs" 485 select ATAGS 486 select CLKSRC_SAMSUNG_PWM 487 select GPIO_SAMSUNG 488 select GPIOLIB 489 select GENERIC_IRQ_MULTI_HANDLER 490 select HAVE_S3C2410_I2C if I2C 491 select HAVE_S3C_RTC if RTC_CLASS 492 select NEED_MACH_IO_H 493 select S3C2410_WATCHDOG 494 select SAMSUNG_ATAGS 495 select USE_OF 496 select WATCHDOG 497 help 498 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 499 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 500 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 501 Samsung SMDK2410 development board (and derivatives). 502 503config ARCH_OMAP1 504 bool "TI OMAP1" 505 depends on MMU 506 select ARCH_OMAP 507 select CLKDEV_LOOKUP 508 select CLKSRC_MMIO 509 select GENERIC_IRQ_CHIP 510 select GENERIC_IRQ_MULTI_HANDLER 511 select GPIOLIB 512 select HAVE_IDE 513 select HAVE_LEGACY_CLK 514 select IRQ_DOMAIN 515 select NEED_MACH_IO_H if PCCARD 516 select NEED_MACH_MEMORY_H 517 select SPARSE_IRQ 518 help 519 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 520 521endchoice 522 523menu "Multiple platform selection" 524 depends on ARCH_MULTIPLATFORM 525 526comment "CPU Core family selection" 527 528config ARCH_MULTI_V4 529 bool "ARMv4 based platforms (FA526)" 530 depends on !ARCH_MULTI_V6_V7 531 select ARCH_MULTI_V4_V5 532 select CPU_FA526 533 534config ARCH_MULTI_V4T 535 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 536 depends on !ARCH_MULTI_V6_V7 537 select ARCH_MULTI_V4_V5 538 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 539 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 540 CPU_ARM925T || CPU_ARM940T) 541 542config ARCH_MULTI_V5 543 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 544 depends on !ARCH_MULTI_V6_V7 545 select ARCH_MULTI_V4_V5 546 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 547 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 548 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 549 550config ARCH_MULTI_V4_V5 551 bool 552 553config ARCH_MULTI_V6 554 bool "ARMv6 based platforms (ARM11)" 555 select ARCH_MULTI_V6_V7 556 select CPU_V6K 557 558config ARCH_MULTI_V7 559 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 560 default y 561 select ARCH_MULTI_V6_V7 562 select CPU_V7 563 select HAVE_SMP 564 565config ARCH_MULTI_V6_V7 566 bool 567 select MIGHT_HAVE_CACHE_L2X0 568 569config ARCH_MULTI_CPU_AUTO 570 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 571 select ARCH_MULTI_V5 572 573endmenu 574 575config ARCH_VIRT 576 bool "Dummy Virtual Machine" 577 depends on ARCH_MULTI_V7 578 select ARM_AMBA 579 select ARM_GIC 580 select ARM_GIC_V2M if PCI 581 select ARM_GIC_V3 582 select ARM_GIC_V3_ITS if PCI 583 select ARM_PSCI 584 select HAVE_ARM_ARCH_TIMER 585 select ARCH_SUPPORTS_BIG_ENDIAN 586 587# 588# This is sorted alphabetically by mach-* pathname. However, plat-* 589# Kconfigs may be included either alphabetically (according to the 590# plat- suffix) or along side the corresponding mach-* source. 591# 592source "arch/arm/mach-actions/Kconfig" 593 594source "arch/arm/mach-alpine/Kconfig" 595 596source "arch/arm/mach-artpec/Kconfig" 597 598source "arch/arm/mach-asm9260/Kconfig" 599 600source "arch/arm/mach-aspeed/Kconfig" 601 602source "arch/arm/mach-at91/Kconfig" 603 604source "arch/arm/mach-axxia/Kconfig" 605 606source "arch/arm/mach-bcm/Kconfig" 607 608source "arch/arm/mach-berlin/Kconfig" 609 610source "arch/arm/mach-clps711x/Kconfig" 611 612source "arch/arm/mach-cns3xxx/Kconfig" 613 614source "arch/arm/mach-davinci/Kconfig" 615 616source "arch/arm/mach-digicolor/Kconfig" 617 618source "arch/arm/mach-dove/Kconfig" 619 620source "arch/arm/mach-ep93xx/Kconfig" 621 622source "arch/arm/mach-exynos/Kconfig" 623 624source "arch/arm/mach-footbridge/Kconfig" 625 626source "arch/arm/mach-gemini/Kconfig" 627 628source "arch/arm/mach-highbank/Kconfig" 629 630source "arch/arm/mach-hisi/Kconfig" 631 632source "arch/arm/mach-imx/Kconfig" 633 634source "arch/arm/mach-integrator/Kconfig" 635 636source "arch/arm/mach-iop32x/Kconfig" 637 638source "arch/arm/mach-ixp4xx/Kconfig" 639 640source "arch/arm/mach-keystone/Kconfig" 641 642source "arch/arm/mach-lpc32xx/Kconfig" 643 644source "arch/arm/mach-mediatek/Kconfig" 645 646source "arch/arm/mach-meson/Kconfig" 647 648source "arch/arm/mach-milbeaut/Kconfig" 649 650source "arch/arm/mach-mmp/Kconfig" 651 652source "arch/arm/mach-moxart/Kconfig" 653 654source "arch/arm/mach-mstar/Kconfig" 655 656source "arch/arm/mach-mv78xx0/Kconfig" 657 658source "arch/arm/mach-mvebu/Kconfig" 659 660source "arch/arm/mach-mxs/Kconfig" 661 662source "arch/arm/mach-nomadik/Kconfig" 663 664source "arch/arm/mach-npcm/Kconfig" 665 666source "arch/arm/mach-nspire/Kconfig" 667 668source "arch/arm/plat-omap/Kconfig" 669 670source "arch/arm/mach-omap1/Kconfig" 671 672source "arch/arm/mach-omap2/Kconfig" 673 674source "arch/arm/mach-orion5x/Kconfig" 675 676source "arch/arm/mach-oxnas/Kconfig" 677 678source "arch/arm/mach-pxa/Kconfig" 679source "arch/arm/plat-pxa/Kconfig" 680 681source "arch/arm/mach-qcom/Kconfig" 682 683source "arch/arm/mach-rda/Kconfig" 684 685source "arch/arm/mach-realtek/Kconfig" 686 687source "arch/arm/mach-realview/Kconfig" 688 689source "arch/arm/mach-rockchip/Kconfig" 690 691source "arch/arm/mach-s3c/Kconfig" 692 693source "arch/arm/mach-s5pv210/Kconfig" 694 695source "arch/arm/mach-sa1100/Kconfig" 696 697source "arch/arm/mach-shmobile/Kconfig" 698 699source "arch/arm/mach-socfpga/Kconfig" 700 701source "arch/arm/mach-spear/Kconfig" 702 703source "arch/arm/mach-sti/Kconfig" 704 705source "arch/arm/mach-stm32/Kconfig" 706 707source "arch/arm/mach-sunxi/Kconfig" 708 709source "arch/arm/mach-tegra/Kconfig" 710 711source "arch/arm/mach-uniphier/Kconfig" 712 713source "arch/arm/mach-ux500/Kconfig" 714 715source "arch/arm/mach-versatile/Kconfig" 716 717source "arch/arm/mach-vexpress/Kconfig" 718 719source "arch/arm/mach-vt8500/Kconfig" 720 721source "arch/arm/mach-zynq/Kconfig" 722 723# ARMv7-M architecture 724config ARCH_LPC18XX 725 bool "NXP LPC18xx/LPC43xx" 726 depends on ARM_SINGLE_ARMV7M 727 select ARCH_HAS_RESET_CONTROLLER 728 select ARM_AMBA 729 select CLKSRC_LPC32XX 730 select PINCTRL 731 help 732 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 733 high performance microcontrollers. 734 735config ARCH_MPS2 736 bool "ARM MPS2 platform" 737 depends on ARM_SINGLE_ARMV7M 738 select ARM_AMBA 739 select CLKSRC_MPS2 740 help 741 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 742 with a range of available cores like Cortex-M3/M4/M7. 743 744 Please, note that depends which Application Note is used memory map 745 for the platform may vary, so adjustment of RAM base might be needed. 746 747# Definitions to make life easier 748config ARCH_ACORN 749 bool 750 751config PLAT_IOP 752 bool 753 754config PLAT_ORION 755 bool 756 select CLKSRC_MMIO 757 select COMMON_CLK 758 select GENERIC_IRQ_CHIP 759 select IRQ_DOMAIN 760 761config PLAT_ORION_LEGACY 762 bool 763 select PLAT_ORION 764 765config PLAT_PXA 766 bool 767 768config PLAT_VERSATILE 769 bool 770 771source "arch/arm/mm/Kconfig" 772 773config IWMMXT 774 bool "Enable iWMMXt support" 775 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 776 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 777 help 778 Enable support for iWMMXt context switching at run time if 779 running on a CPU that supports it. 780 781if !MMU 782source "arch/arm/Kconfig-nommu" 783endif 784 785config PJ4B_ERRATA_4742 786 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 787 depends on CPU_PJ4B && MACH_ARMADA_370 788 default y 789 help 790 When coming out of either a Wait for Interrupt (WFI) or a Wait for 791 Event (WFE) IDLE states, a specific timing sensitivity exists between 792 the retiring WFI/WFE instructions and the newly issued subsequent 793 instructions. This sensitivity can result in a CPU hang scenario. 794 Workaround: 795 The software must insert either a Data Synchronization Barrier (DSB) 796 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 797 instruction 798 799config ARM_ERRATA_326103 800 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 801 depends on CPU_V6 802 help 803 Executing a SWP instruction to read-only memory does not set bit 11 804 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 805 treat the access as a read, preventing a COW from occurring and 806 causing the faulting task to livelock. 807 808config ARM_ERRATA_411920 809 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 810 depends on CPU_V6 || CPU_V6K 811 help 812 Invalidation of the Instruction Cache operation can 813 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 814 It does not affect the MPCore. This option enables the ARM Ltd. 815 recommended workaround. 816 817config ARM_ERRATA_430973 818 bool "ARM errata: Stale prediction on replaced interworking branch" 819 depends on CPU_V7 820 help 821 This option enables the workaround for the 430973 Cortex-A8 822 r1p* erratum. If a code sequence containing an ARM/Thumb 823 interworking branch is replaced with another code sequence at the 824 same virtual address, whether due to self-modifying code or virtual 825 to physical address re-mapping, Cortex-A8 does not recover from the 826 stale interworking branch prediction. This results in Cortex-A8 827 executing the new code sequence in the incorrect ARM or Thumb state. 828 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 829 and also flushes the branch target cache at every context switch. 830 Note that setting specific bits in the ACTLR register may not be 831 available in non-secure mode. 832 833config ARM_ERRATA_458693 834 bool "ARM errata: Processor deadlock when a false hazard is created" 835 depends on CPU_V7 836 depends on !ARCH_MULTIPLATFORM 837 help 838 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 839 erratum. For very specific sequences of memory operations, it is 840 possible for a hazard condition intended for a cache line to instead 841 be incorrectly associated with a different cache line. This false 842 hazard might then cause a processor deadlock. The workaround enables 843 the L1 caching of the NEON accesses and disables the PLD instruction 844 in the ACTLR register. Note that setting specific bits in the ACTLR 845 register may not be available in non-secure mode. 846 847config ARM_ERRATA_460075 848 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 849 depends on CPU_V7 850 depends on !ARCH_MULTIPLATFORM 851 help 852 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 853 erratum. Any asynchronous access to the L2 cache may encounter a 854 situation in which recent store transactions to the L2 cache are lost 855 and overwritten with stale memory contents from external memory. The 856 workaround disables the write-allocate mode for the L2 cache via the 857 ACTLR register. Note that setting specific bits in the ACTLR register 858 may not be available in non-secure mode. 859 860config ARM_ERRATA_742230 861 bool "ARM errata: DMB operation may be faulty" 862 depends on CPU_V7 && SMP 863 depends on !ARCH_MULTIPLATFORM 864 help 865 This option enables the workaround for the 742230 Cortex-A9 866 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 867 between two write operations may not ensure the correct visibility 868 ordering of the two writes. This workaround sets a specific bit in 869 the diagnostic register of the Cortex-A9 which causes the DMB 870 instruction to behave as a DSB, ensuring the correct behaviour of 871 the two writes. 872 873config ARM_ERRATA_742231 874 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 875 depends on CPU_V7 && SMP 876 depends on !ARCH_MULTIPLATFORM 877 help 878 This option enables the workaround for the 742231 Cortex-A9 879 (r2p0..r2p2) erratum. Under certain conditions, specific to the 880 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 881 accessing some data located in the same cache line, may get corrupted 882 data due to bad handling of the address hazard when the line gets 883 replaced from one of the CPUs at the same time as another CPU is 884 accessing it. This workaround sets specific bits in the diagnostic 885 register of the Cortex-A9 which reduces the linefill issuing 886 capabilities of the processor. 887 888config ARM_ERRATA_643719 889 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 890 depends on CPU_V7 && SMP 891 default y 892 help 893 This option enables the workaround for the 643719 Cortex-A9 (prior to 894 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 895 register returns zero when it should return one. The workaround 896 corrects this value, ensuring cache maintenance operations which use 897 it behave as intended and avoiding data corruption. 898 899config ARM_ERRATA_720789 900 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 901 depends on CPU_V7 902 help 903 This option enables the workaround for the 720789 Cortex-A9 (prior to 904 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 905 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 906 As a consequence of this erratum, some TLB entries which should be 907 invalidated are not, resulting in an incoherency in the system page 908 tables. The workaround changes the TLB flushing routines to invalidate 909 entries regardless of the ASID. 910 911config ARM_ERRATA_743622 912 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 913 depends on CPU_V7 914 depends on !ARCH_MULTIPLATFORM 915 help 916 This option enables the workaround for the 743622 Cortex-A9 917 (r2p*) erratum. Under very rare conditions, a faulty 918 optimisation in the Cortex-A9 Store Buffer may lead to data 919 corruption. This workaround sets a specific bit in the diagnostic 920 register of the Cortex-A9 which disables the Store Buffer 921 optimisation, preventing the defect from occurring. This has no 922 visible impact on the overall performance or power consumption of the 923 processor. 924 925config ARM_ERRATA_751472 926 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 927 depends on CPU_V7 928 depends on !ARCH_MULTIPLATFORM 929 help 930 This option enables the workaround for the 751472 Cortex-A9 (prior 931 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 932 completion of a following broadcasted operation if the second 933 operation is received by a CPU before the ICIALLUIS has completed, 934 potentially leading to corrupted entries in the cache or TLB. 935 936config ARM_ERRATA_754322 937 bool "ARM errata: possible faulty MMU translations following an ASID switch" 938 depends on CPU_V7 939 help 940 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 941 r3p*) erratum. A speculative memory access may cause a page table walk 942 which starts prior to an ASID switch but completes afterwards. This 943 can populate the micro-TLB with a stale entry which may be hit with 944 the new ASID. This workaround places two dsb instructions in the mm 945 switching code so that no page table walks can cross the ASID switch. 946 947config ARM_ERRATA_754327 948 bool "ARM errata: no automatic Store Buffer drain" 949 depends on CPU_V7 && SMP 950 help 951 This option enables the workaround for the 754327 Cortex-A9 (prior to 952 r2p0) erratum. The Store Buffer does not have any automatic draining 953 mechanism and therefore a livelock may occur if an external agent 954 continuously polls a memory location waiting to observe an update. 955 This workaround defines cpu_relax() as smp_mb(), preventing correctly 956 written polling loops from denying visibility of updates to memory. 957 958config ARM_ERRATA_364296 959 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 960 depends on CPU_V6 961 help 962 This options enables the workaround for the 364296 ARM1136 963 r0p2 erratum (possible cache data corruption with 964 hit-under-miss enabled). It sets the undocumented bit 31 in 965 the auxiliary control register and the FI bit in the control 966 register, thus disabling hit-under-miss without putting the 967 processor into full low interrupt latency mode. ARM11MPCore 968 is not affected. 969 970config ARM_ERRATA_764369 971 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 972 depends on CPU_V7 && SMP 973 help 974 This option enables the workaround for erratum 764369 975 affecting Cortex-A9 MPCore with two or more processors (all 976 current revisions). Under certain timing circumstances, a data 977 cache line maintenance operation by MVA targeting an Inner 978 Shareable memory region may fail to proceed up to either the 979 Point of Coherency or to the Point of Unification of the 980 system. This workaround adds a DSB instruction before the 981 relevant cache maintenance functions and sets a specific bit 982 in the diagnostic control register of the SCU. 983 984config ARM_ERRATA_775420 985 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 986 depends on CPU_V7 987 help 988 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 989 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 990 operation aborts with MMU exception, it might cause the processor 991 to deadlock. This workaround puts DSB before executing ISB if 992 an abort may occur on cache maintenance. 993 994config ARM_ERRATA_798181 995 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 996 depends on CPU_V7 && SMP 997 help 998 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 999 adequately shooting down all use of the old entries. This 1000 option enables the Linux kernel workaround for this erratum 1001 which sends an IPI to the CPUs that are running the same ASID 1002 as the one being invalidated. 1003 1004config ARM_ERRATA_773022 1005 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1006 depends on CPU_V7 1007 help 1008 This option enables the workaround for the 773022 Cortex-A15 1009 (up to r0p4) erratum. In certain rare sequences of code, the 1010 loop buffer may deliver incorrect instructions. This 1011 workaround disables the loop buffer to avoid the erratum. 1012 1013config ARM_ERRATA_818325_852422 1014 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1015 depends on CPU_V7 1016 help 1017 This option enables the workaround for: 1018 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1019 instruction might deadlock. Fixed in r0p1. 1020 - Cortex-A12 852422: Execution of a sequence of instructions might 1021 lead to either a data corruption or a CPU deadlock. Not fixed in 1022 any Cortex-A12 cores yet. 1023 This workaround for all both errata involves setting bit[12] of the 1024 Feature Register. This bit disables an optimisation applied to a 1025 sequence of 2 instructions that use opposing condition codes. 1026 1027config ARM_ERRATA_821420 1028 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1029 depends on CPU_V7 1030 help 1031 This option enables the workaround for the 821420 Cortex-A12 1032 (all revs) erratum. In very rare timing conditions, a sequence 1033 of VMOV to Core registers instructions, for which the second 1034 one is in the shadow of a branch or abort, can lead to a 1035 deadlock when the VMOV instructions are issued out-of-order. 1036 1037config ARM_ERRATA_825619 1038 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1039 depends on CPU_V7 1040 help 1041 This option enables the workaround for the 825619 Cortex-A12 1042 (all revs) erratum. Within rare timing constraints, executing a 1043 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1044 and Device/Strongly-Ordered loads and stores might cause deadlock 1045 1046config ARM_ERRATA_857271 1047 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1048 depends on CPU_V7 1049 help 1050 This option enables the workaround for the 857271 Cortex-A12 1051 (all revs) erratum. Under very rare timing conditions, the CPU might 1052 hang. The workaround is expected to have a < 1% performance impact. 1053 1054config ARM_ERRATA_852421 1055 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1056 depends on CPU_V7 1057 help 1058 This option enables the workaround for the 852421 Cortex-A17 1059 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1060 execution of a DMB ST instruction might fail to properly order 1061 stores from GroupA and stores from GroupB. 1062 1063config ARM_ERRATA_852423 1064 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1065 depends on CPU_V7 1066 help 1067 This option enables the workaround for: 1068 - Cortex-A17 852423: Execution of a sequence of instructions might 1069 lead to either a data corruption or a CPU deadlock. Not fixed in 1070 any Cortex-A17 cores yet. 1071 This is identical to Cortex-A12 erratum 852422. It is a separate 1072 config option from the A12 erratum due to the way errata are checked 1073 for and handled. 1074 1075config ARM_ERRATA_857272 1076 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1077 depends on CPU_V7 1078 help 1079 This option enables the workaround for the 857272 Cortex-A17 erratum. 1080 This erratum is not known to be fixed in any A17 revision. 1081 This is identical to Cortex-A12 erratum 857271. It is a separate 1082 config option from the A12 erratum due to the way errata are checked 1083 for and handled. 1084 1085endmenu 1086 1087source "arch/arm/common/Kconfig" 1088 1089menu "Bus support" 1090 1091config ISA 1092 bool 1093 help 1094 Find out whether you have ISA slots on your motherboard. ISA is the 1095 name of a bus system, i.e. the way the CPU talks to the other stuff 1096 inside your box. Other bus systems are PCI, EISA, MicroChannel 1097 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1098 newer boards don't support it. If you have ISA, say Y, otherwise N. 1099 1100# Select ISA DMA controller support 1101config ISA_DMA 1102 bool 1103 select ISA_DMA_API 1104 1105# Select ISA DMA interface 1106config ISA_DMA_API 1107 bool 1108 1109config PCI_NANOENGINE 1110 bool "BSE nanoEngine PCI support" 1111 depends on SA1100_NANOENGINE 1112 help 1113 Enable PCI on the BSE nanoEngine board. 1114 1115config ARM_ERRATA_814220 1116 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1117 depends on CPU_V7 1118 help 1119 The v7 ARM states that all cache and branch predictor maintenance 1120 operations that do not specify an address execute, relative to 1121 each other, in program order. 1122 However, because of this erratum, an L2 set/way cache maintenance 1123 operation can overtake an L1 set/way cache maintenance operation. 1124 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1125 r0p4, r0p5. 1126 1127endmenu 1128 1129menu "Kernel Features" 1130 1131config HAVE_SMP 1132 bool 1133 help 1134 This option should be selected by machines which have an SMP- 1135 capable CPU. 1136 1137 The only effect of this option is to make the SMP-related 1138 options available to the user for configuration. 1139 1140config SMP 1141 bool "Symmetric Multi-Processing" 1142 depends on CPU_V6K || CPU_V7 1143 depends on HAVE_SMP 1144 depends on MMU || ARM_MPU 1145 select IRQ_WORK 1146 help 1147 This enables support for systems with more than one CPU. If you have 1148 a system with only one CPU, say N. If you have a system with more 1149 than one CPU, say Y. 1150 1151 If you say N here, the kernel will run on uni- and multiprocessor 1152 machines, but will use only one CPU of a multiprocessor machine. If 1153 you say Y here, the kernel will run on many, but not all, 1154 uniprocessor machines. On a uniprocessor machine, the kernel 1155 will run faster if you say N here. 1156 1157 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1158 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1159 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1160 1161 If you don't know what to do here, say N. 1162 1163config SMP_ON_UP 1164 bool "Allow booting SMP kernel on uniprocessor systems" 1165 depends on SMP && !XIP_KERNEL && MMU 1166 default y 1167 help 1168 SMP kernels contain instructions which fail on non-SMP processors. 1169 Enabling this option allows the kernel to modify itself to make 1170 these instructions safe. Disabling it allows about 1K of space 1171 savings. 1172 1173 If you don't know what to do here, say Y. 1174 1175config ARM_CPU_TOPOLOGY 1176 bool "Support cpu topology definition" 1177 depends on SMP && CPU_V7 1178 default y 1179 help 1180 Support ARM cpu topology definition. The MPIDR register defines 1181 affinity between processors which is then used to describe the cpu 1182 topology of an ARM System. 1183 1184config SCHED_MC 1185 bool "Multi-core scheduler support" 1186 depends on ARM_CPU_TOPOLOGY 1187 help 1188 Multi-core scheduler support improves the CPU scheduler's decision 1189 making when dealing with multi-core CPU chips at a cost of slightly 1190 increased overhead in some places. If unsure say N here. 1191 1192config SCHED_SMT 1193 bool "SMT scheduler support" 1194 depends on ARM_CPU_TOPOLOGY 1195 help 1196 Improves the CPU scheduler's decision making when dealing with 1197 MultiThreading at a cost of slightly increased overhead in some 1198 places. If unsure say N here. 1199 1200config HAVE_ARM_SCU 1201 bool 1202 help 1203 This option enables support for the ARM snoop control unit 1204 1205config HAVE_ARM_ARCH_TIMER 1206 bool "Architected timer support" 1207 depends on CPU_V7 1208 select ARM_ARCH_TIMER 1209 help 1210 This option enables support for the ARM architected timer 1211 1212config HAVE_ARM_TWD 1213 bool 1214 help 1215 This options enables support for the ARM timer and watchdog unit 1216 1217config MCPM 1218 bool "Multi-Cluster Power Management" 1219 depends on CPU_V7 && SMP 1220 help 1221 This option provides the common power management infrastructure 1222 for (multi-)cluster based systems, such as big.LITTLE based 1223 systems. 1224 1225config MCPM_QUAD_CLUSTER 1226 bool 1227 depends on MCPM 1228 help 1229 To avoid wasting resources unnecessarily, MCPM only supports up 1230 to 2 clusters by default. 1231 Platforms with 3 or 4 clusters that use MCPM must select this 1232 option to allow the additional clusters to be managed. 1233 1234config BIG_LITTLE 1235 bool "big.LITTLE support (Experimental)" 1236 depends on CPU_V7 && SMP 1237 select MCPM 1238 help 1239 This option enables support selections for the big.LITTLE 1240 system architecture. 1241 1242config BL_SWITCHER 1243 bool "big.LITTLE switcher support" 1244 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1245 select CPU_PM 1246 help 1247 The big.LITTLE "switcher" provides the core functionality to 1248 transparently handle transition between a cluster of A15's 1249 and a cluster of A7's in a big.LITTLE system. 1250 1251config BL_SWITCHER_DUMMY_IF 1252 tristate "Simple big.LITTLE switcher user interface" 1253 depends on BL_SWITCHER && DEBUG_KERNEL 1254 help 1255 This is a simple and dummy char dev interface to control 1256 the big.LITTLE switcher core code. It is meant for 1257 debugging purposes only. 1258 1259choice 1260 prompt "Memory split" 1261 depends on MMU 1262 default VMSPLIT_3G 1263 help 1264 Select the desired split between kernel and user memory. 1265 1266 If you are not absolutely sure what you are doing, leave this 1267 option alone! 1268 1269 config VMSPLIT_3G 1270 bool "3G/1G user/kernel split" 1271 config VMSPLIT_3G_OPT 1272 depends on !ARM_LPAE 1273 bool "3G/1G user/kernel split (for full 1G low memory)" 1274 config VMSPLIT_2G 1275 bool "2G/2G user/kernel split" 1276 config VMSPLIT_1G 1277 bool "1G/3G user/kernel split" 1278endchoice 1279 1280config PAGE_OFFSET 1281 hex 1282 default PHYS_OFFSET if !MMU 1283 default 0x40000000 if VMSPLIT_1G 1284 default 0x80000000 if VMSPLIT_2G 1285 default 0xB0000000 if VMSPLIT_3G_OPT 1286 default 0xC0000000 1287 1288config KASAN_SHADOW_OFFSET 1289 hex 1290 depends on KASAN 1291 default 0x1f000000 if PAGE_OFFSET=0x40000000 1292 default 0x5f000000 if PAGE_OFFSET=0x80000000 1293 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1294 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1295 default 0xffffffff 1296 1297config NR_CPUS 1298 int "Maximum number of CPUs (2-32)" 1299 range 2 16 if DEBUG_KMAP_LOCAL 1300 range 2 32 if !DEBUG_KMAP_LOCAL 1301 depends on SMP 1302 default "4" 1303 help 1304 The maximum number of CPUs that the kernel can support. 1305 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1306 debugging is enabled, which uses half of the per-CPU fixmap 1307 slots as guard regions. 1308 1309config HOTPLUG_CPU 1310 bool "Support for hot-pluggable CPUs" 1311 depends on SMP 1312 select GENERIC_IRQ_MIGRATION 1313 help 1314 Say Y here to experiment with turning CPUs off and on. CPUs 1315 can be controlled through /sys/devices/system/cpu. 1316 1317config ARM_PSCI 1318 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1319 depends on HAVE_ARM_SMCCC 1320 select ARM_PSCI_FW 1321 help 1322 Say Y here if you want Linux to communicate with system firmware 1323 implementing the PSCI specification for CPU-centric power 1324 management operations described in ARM document number ARM DEN 1325 0022A ("Power State Coordination Interface System Software on 1326 ARM processors"). 1327 1328# The GPIO number here must be sorted by descending number. In case of 1329# a multiplatform kernel, we just want the highest value required by the 1330# selected platforms. 1331config ARCH_NR_GPIO 1332 int 1333 default 2048 if ARCH_INTEL_SOCFPGA 1334 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1335 ARCH_ZYNQ || ARCH_ASPEED 1336 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1337 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1338 default 416 if ARCH_SUNXI 1339 default 392 if ARCH_U8500 1340 default 352 if ARCH_VT8500 1341 default 288 if ARCH_ROCKCHIP 1342 default 264 if MACH_H4700 1343 default 0 1344 help 1345 Maximum number of GPIOs in the system. 1346 1347 If unsure, leave the default value. 1348 1349config HZ_FIXED 1350 int 1351 default 128 if SOC_AT91RM9200 1352 default 0 1353 1354choice 1355 depends on HZ_FIXED = 0 1356 prompt "Timer frequency" 1357 1358config HZ_100 1359 bool "100 Hz" 1360 1361config HZ_200 1362 bool "200 Hz" 1363 1364config HZ_250 1365 bool "250 Hz" 1366 1367config HZ_300 1368 bool "300 Hz" 1369 1370config HZ_500 1371 bool "500 Hz" 1372 1373config HZ_1000 1374 bool "1000 Hz" 1375 1376endchoice 1377 1378config HZ 1379 int 1380 default HZ_FIXED if HZ_FIXED != 0 1381 default 100 if HZ_100 1382 default 200 if HZ_200 1383 default 250 if HZ_250 1384 default 300 if HZ_300 1385 default 500 if HZ_500 1386 default 1000 1387 1388config SCHED_HRTICK 1389 def_bool HIGH_RES_TIMERS 1390 1391config THUMB2_KERNEL 1392 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1393 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1394 default y if CPU_THUMBONLY 1395 select ARM_UNWIND 1396 help 1397 By enabling this option, the kernel will be compiled in 1398 Thumb-2 mode. 1399 1400 If unsure, say N. 1401 1402config ARM_PATCH_IDIV 1403 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1404 depends on CPU_32v7 && !XIP_KERNEL 1405 default y 1406 help 1407 The ARM compiler inserts calls to __aeabi_idiv() and 1408 __aeabi_uidiv() when it needs to perform division on signed 1409 and unsigned integers. Some v7 CPUs have support for the sdiv 1410 and udiv instructions that can be used to implement those 1411 functions. 1412 1413 Enabling this option allows the kernel to modify itself to 1414 replace the first two instructions of these library functions 1415 with the sdiv or udiv plus "bx lr" instructions when the CPU 1416 it is running on supports them. Typically this will be faster 1417 and less power intensive than running the original library 1418 code to do integer division. 1419 1420config AEABI 1421 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1422 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1423 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1424 help 1425 This option allows for the kernel to be compiled using the latest 1426 ARM ABI (aka EABI). This is only useful if you are using a user 1427 space environment that is also compiled with EABI. 1428 1429 Since there are major incompatibilities between the legacy ABI and 1430 EABI, especially with regard to structure member alignment, this 1431 option also changes the kernel syscall calling convention to 1432 disambiguate both ABIs and allow for backward compatibility support 1433 (selected with CONFIG_OABI_COMPAT). 1434 1435 To use this you need GCC version 4.0.0 or later. 1436 1437config OABI_COMPAT 1438 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1439 depends on AEABI && !THUMB2_KERNEL 1440 help 1441 This option preserves the old syscall interface along with the 1442 new (ARM EABI) one. It also provides a compatibility layer to 1443 intercept syscalls that have structure arguments which layout 1444 in memory differs between the legacy ABI and the new ARM EABI 1445 (only for non "thumb" binaries). This option adds a tiny 1446 overhead to all syscalls and produces a slightly larger kernel. 1447 1448 The seccomp filter system will not be available when this is 1449 selected, since there is no way yet to sensibly distinguish 1450 between calling conventions during filtering. 1451 1452 If you know you'll be using only pure EABI user space then you 1453 can say N here. If this option is not selected and you attempt 1454 to execute a legacy ABI binary then the result will be 1455 UNPREDICTABLE (in fact it can be predicted that it won't work 1456 at all). If in doubt say N. 1457 1458config ARCH_SELECT_MEMORY_MODEL 1459 bool 1460 1461config ARCH_FLATMEM_ENABLE 1462 bool 1463 1464config ARCH_SPARSEMEM_ENABLE 1465 bool 1466 select SPARSEMEM_STATIC if SPARSEMEM 1467 1468config HIGHMEM 1469 bool "High Memory Support" 1470 depends on MMU 1471 select KMAP_LOCAL 1472 help 1473 The address space of ARM processors is only 4 Gigabytes large 1474 and it has to accommodate user address space, kernel address 1475 space as well as some memory mapped IO. That means that, if you 1476 have a large amount of physical memory and/or IO, not all of the 1477 memory can be "permanently mapped" by the kernel. The physical 1478 memory that is not permanently mapped is called "high memory". 1479 1480 Depending on the selected kernel/user memory split, minimum 1481 vmalloc space and actual amount of RAM, you may not need this 1482 option which should result in a slightly faster kernel. 1483 1484 If unsure, say n. 1485 1486config HIGHPTE 1487 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1488 depends on HIGHMEM 1489 default y 1490 help 1491 The VM uses one page of physical memory for each page table. 1492 For systems with a lot of processes, this can use a lot of 1493 precious low memory, eventually leading to low memory being 1494 consumed by page tables. Setting this option will allow 1495 user-space 2nd level page tables to reside in high memory. 1496 1497config CPU_SW_DOMAIN_PAN 1498 bool "Enable use of CPU domains to implement privileged no-access" 1499 depends on MMU && !ARM_LPAE 1500 default y 1501 help 1502 Increase kernel security by ensuring that normal kernel accesses 1503 are unable to access userspace addresses. This can help prevent 1504 use-after-free bugs becoming an exploitable privilege escalation 1505 by ensuring that magic values (such as LIST_POISON) will always 1506 fault when dereferenced. 1507 1508 CPUs with low-vector mappings use a best-efforts implementation. 1509 Their lower 1MB needs to remain accessible for the vectors, but 1510 the remainder of userspace will become appropriately inaccessible. 1511 1512config HW_PERF_EVENTS 1513 def_bool y 1514 depends on ARM_PMU 1515 1516config ARCH_WANT_GENERAL_HUGETLB 1517 def_bool y 1518 1519config ARM_MODULE_PLTS 1520 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1521 depends on MODULES 1522 default y 1523 help 1524 Allocate PLTs when loading modules so that jumps and calls whose 1525 targets are too far away for their relative offsets to be encoded 1526 in the instructions themselves can be bounced via veneers in the 1527 module's PLT. This allows modules to be allocated in the generic 1528 vmalloc area after the dedicated module memory area has been 1529 exhausted. The modules will use slightly more memory, but after 1530 rounding up to page size, the actual memory footprint is usually 1531 the same. 1532 1533 Disabling this is usually safe for small single-platform 1534 configurations. If unsure, say y. 1535 1536config FORCE_MAX_ZONEORDER 1537 int "Maximum zone order" 1538 default "12" if SOC_AM33XX 1539 default "9" if SA1111 1540 default "11" 1541 help 1542 The kernel memory allocator divides physically contiguous memory 1543 blocks into "zones", where each zone is a power of two number of 1544 pages. This option selects the largest power of two that the kernel 1545 keeps in the memory allocator. If you need to allocate very large 1546 blocks of physically contiguous memory, then you may need to 1547 increase this value. 1548 1549 This config option is actually maximum order plus one. For example, 1550 a value of 11 means that the largest free memory block is 2^10 pages. 1551 1552config ALIGNMENT_TRAP 1553 def_bool CPU_CP15_MMU 1554 select HAVE_PROC_CPU if PROC_FS 1555 help 1556 ARM processors cannot fetch/store information which is not 1557 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1558 address divisible by 4. On 32-bit ARM processors, these non-aligned 1559 fetch/store instructions will be emulated in software if you say 1560 here, which has a severe performance impact. This is necessary for 1561 correct operation of some network protocols. With an IP-only 1562 configuration it is safe to say N, otherwise say Y. 1563 1564config UACCESS_WITH_MEMCPY 1565 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1566 depends on MMU 1567 default y if CPU_FEROCEON 1568 help 1569 Implement faster copy_to_user and clear_user methods for CPU 1570 cores where a 8-word STM instruction give significantly higher 1571 memory write throughput than a sequence of individual 32bit stores. 1572 1573 A possible side effect is a slight increase in scheduling latency 1574 between threads sharing the same address space if they invoke 1575 such copy operations with large buffers. 1576 1577 However, if the CPU data cache is using a write-allocate mode, 1578 this option is unlikely to provide any performance gain. 1579 1580config PARAVIRT 1581 bool "Enable paravirtualization code" 1582 help 1583 This changes the kernel so it can modify itself when it is run 1584 under a hypervisor, potentially improving performance significantly 1585 over full virtualization. 1586 1587config PARAVIRT_TIME_ACCOUNTING 1588 bool "Paravirtual steal time accounting" 1589 select PARAVIRT 1590 help 1591 Select this option to enable fine granularity task steal time 1592 accounting. Time spent executing other tasks in parallel with 1593 the current vCPU is discounted from the vCPU power. To account for 1594 that, there can be a small performance impact. 1595 1596 If in doubt, say N here. 1597 1598config XEN_DOM0 1599 def_bool y 1600 depends on XEN 1601 1602config XEN 1603 bool "Xen guest support on ARM" 1604 depends on ARM && AEABI && OF 1605 depends on CPU_V7 && !CPU_V6 1606 depends on !GENERIC_ATOMIC64 1607 depends on MMU 1608 select ARCH_DMA_ADDR_T_64BIT 1609 select ARM_PSCI 1610 select SWIOTLB 1611 select SWIOTLB_XEN 1612 select PARAVIRT 1613 help 1614 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1615 1616config STACKPROTECTOR_PER_TASK 1617 bool "Use a unique stack canary value for each task" 1618 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1619 select GCC_PLUGIN_ARM_SSP_PER_TASK 1620 default y 1621 help 1622 Due to the fact that GCC uses an ordinary symbol reference from 1623 which to load the value of the stack canary, this value can only 1624 change at reboot time on SMP systems, and all tasks running in the 1625 kernel's address space are forced to use the same canary value for 1626 the entire duration that the system is up. 1627 1628 Enable this option to switch to a different method that uses a 1629 different canary value for each task. 1630 1631endmenu 1632 1633menu "Boot options" 1634 1635config USE_OF 1636 bool "Flattened Device Tree support" 1637 select IRQ_DOMAIN 1638 select OF 1639 help 1640 Include support for flattened device tree machine descriptions. 1641 1642config ATAGS 1643 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1644 default y 1645 help 1646 This is the traditional way of passing data to the kernel at boot 1647 time. If you are solely relying on the flattened device tree (or 1648 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1649 to remove ATAGS support from your kernel binary. If unsure, 1650 leave this to y. 1651 1652config DEPRECATED_PARAM_STRUCT 1653 bool "Provide old way to pass kernel parameters" 1654 depends on ATAGS 1655 help 1656 This was deprecated in 2001 and announced to live on for 5 years. 1657 Some old boot loaders still use this way. 1658 1659# Compressed boot loader in ROM. Yes, we really want to ask about 1660# TEXT and BSS so we preserve their values in the config files. 1661config ZBOOT_ROM_TEXT 1662 hex "Compressed ROM boot loader base address" 1663 default 0x0 1664 help 1665 The physical address at which the ROM-able zImage is to be 1666 placed in the target. Platforms which normally make use of 1667 ROM-able zImage formats normally set this to a suitable 1668 value in their defconfig file. 1669 1670 If ZBOOT_ROM is not enabled, this has no effect. 1671 1672config ZBOOT_ROM_BSS 1673 hex "Compressed ROM boot loader BSS address" 1674 default 0x0 1675 help 1676 The base address of an area of read/write memory in the target 1677 for the ROM-able zImage which must be available while the 1678 decompressor is running. It must be large enough to hold the 1679 entire decompressed kernel plus an additional 128 KiB. 1680 Platforms which normally make use of ROM-able zImage formats 1681 normally set this to a suitable value in their defconfig file. 1682 1683 If ZBOOT_ROM is not enabled, this has no effect. 1684 1685config ZBOOT_ROM 1686 bool "Compressed boot loader in ROM/flash" 1687 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1688 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1689 help 1690 Say Y here if you intend to execute your compressed kernel image 1691 (zImage) directly from ROM or flash. If unsure, say N. 1692 1693config ARM_APPENDED_DTB 1694 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1695 depends on OF 1696 help 1697 With this option, the boot code will look for a device tree binary 1698 (DTB) appended to zImage 1699 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1700 1701 This is meant as a backward compatibility convenience for those 1702 systems with a bootloader that can't be upgraded to accommodate 1703 the documented boot protocol using a device tree. 1704 1705 Beware that there is very little in terms of protection against 1706 this option being confused by leftover garbage in memory that might 1707 look like a DTB header after a reboot if no actual DTB is appended 1708 to zImage. Do not leave this option active in a production kernel 1709 if you don't intend to always append a DTB. Proper passing of the 1710 location into r2 of a bootloader provided DTB is always preferable 1711 to this option. 1712 1713config ARM_ATAG_DTB_COMPAT 1714 bool "Supplement the appended DTB with traditional ATAG information" 1715 depends on ARM_APPENDED_DTB 1716 help 1717 Some old bootloaders can't be updated to a DTB capable one, yet 1718 they provide ATAGs with memory configuration, the ramdisk address, 1719 the kernel cmdline string, etc. Such information is dynamically 1720 provided by the bootloader and can't always be stored in a static 1721 DTB. To allow a device tree enabled kernel to be used with such 1722 bootloaders, this option allows zImage to extract the information 1723 from the ATAG list and store it at run time into the appended DTB. 1724 1725choice 1726 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1727 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1728 1729config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1730 bool "Use bootloader kernel arguments if available" 1731 help 1732 Uses the command-line options passed by the boot loader instead of 1733 the device tree bootargs property. If the boot loader doesn't provide 1734 any, the device tree bootargs property will be used. 1735 1736config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1737 bool "Extend with bootloader kernel arguments" 1738 help 1739 The command-line arguments provided by the boot loader will be 1740 appended to the the device tree bootargs property. 1741 1742endchoice 1743 1744config CMDLINE 1745 string "Default kernel command string" 1746 default "" 1747 help 1748 On some architectures (e.g. CATS), there is currently no way 1749 for the boot loader to pass arguments to the kernel. For these 1750 architectures, you should supply some command-line options at build 1751 time by entering them here. As a minimum, you should specify the 1752 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1753 1754choice 1755 prompt "Kernel command line type" if CMDLINE != "" 1756 default CMDLINE_FROM_BOOTLOADER 1757 depends on ATAGS 1758 1759config CMDLINE_FROM_BOOTLOADER 1760 bool "Use bootloader kernel arguments if available" 1761 help 1762 Uses the command-line options passed by the boot loader. If 1763 the boot loader doesn't provide any, the default kernel command 1764 string provided in CMDLINE will be used. 1765 1766config CMDLINE_EXTEND 1767 bool "Extend bootloader kernel arguments" 1768 help 1769 The command-line arguments provided by the boot loader will be 1770 appended to the default kernel command string. 1771 1772config CMDLINE_FORCE 1773 bool "Always use the default kernel command string" 1774 help 1775 Always use the default kernel command string, even if the boot 1776 loader passes other arguments to the kernel. 1777 This is useful if you cannot or don't want to change the 1778 command-line options your boot loader passes to the kernel. 1779endchoice 1780 1781config XIP_KERNEL 1782 bool "Kernel Execute-In-Place from ROM" 1783 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1784 help 1785 Execute-In-Place allows the kernel to run from non-volatile storage 1786 directly addressable by the CPU, such as NOR flash. This saves RAM 1787 space since the text section of the kernel is not loaded from flash 1788 to RAM. Read-write sections, such as the data section and stack, 1789 are still copied to RAM. The XIP kernel is not compressed since 1790 it has to run directly from flash, so it will take more space to 1791 store it. The flash address used to link the kernel object files, 1792 and for storing it, is configuration dependent. Therefore, if you 1793 say Y here, you must know the proper physical address where to 1794 store the kernel image depending on your own flash memory usage. 1795 1796 Also note that the make target becomes "make xipImage" rather than 1797 "make zImage" or "make Image". The final kernel binary to put in 1798 ROM memory will be arch/arm/boot/xipImage. 1799 1800 If unsure, say N. 1801 1802config XIP_PHYS_ADDR 1803 hex "XIP Kernel Physical Location" 1804 depends on XIP_KERNEL 1805 default "0x00080000" 1806 help 1807 This is the physical address in your flash memory the kernel will 1808 be linked for and stored to. This address is dependent on your 1809 own flash usage. 1810 1811config XIP_DEFLATED_DATA 1812 bool "Store kernel .data section compressed in ROM" 1813 depends on XIP_KERNEL 1814 select ZLIB_INFLATE 1815 help 1816 Before the kernel is actually executed, its .data section has to be 1817 copied to RAM from ROM. This option allows for storing that data 1818 in compressed form and decompressed to RAM rather than merely being 1819 copied, saving some precious ROM space. A possible drawback is a 1820 slightly longer boot delay. 1821 1822config KEXEC 1823 bool "Kexec system call (EXPERIMENTAL)" 1824 depends on (!SMP || PM_SLEEP_SMP) 1825 depends on MMU 1826 select KEXEC_CORE 1827 help 1828 kexec is a system call that implements the ability to shutdown your 1829 current kernel, and to start another kernel. It is like a reboot 1830 but it is independent of the system firmware. And like a reboot 1831 you can start any kernel with it, not just Linux. 1832 1833 It is an ongoing process to be certain the hardware in a machine 1834 is properly shutdown, so do not be surprised if this code does not 1835 initially work for you. 1836 1837config ATAGS_PROC 1838 bool "Export atags in procfs" 1839 depends on ATAGS && KEXEC 1840 default y 1841 help 1842 Should the atags used to boot the kernel be exported in an "atags" 1843 file in procfs. Useful with kexec. 1844 1845config CRASH_DUMP 1846 bool "Build kdump crash kernel (EXPERIMENTAL)" 1847 help 1848 Generate crash dump after being started by kexec. This should 1849 be normally only set in special crash dump kernels which are 1850 loaded in the main kernel with kexec-tools into a specially 1851 reserved region and then later executed after a crash by 1852 kdump/kexec. The crash dump kernel must be compiled to a 1853 memory address not used by the main kernel 1854 1855 For more details see Documentation/admin-guide/kdump/kdump.rst 1856 1857config AUTO_ZRELADDR 1858 bool "Auto calculation of the decompressed kernel image address" 1859 help 1860 ZRELADDR is the physical address where the decompressed kernel 1861 image will be placed. If AUTO_ZRELADDR is selected, the address 1862 will be determined at run-time, either by masking the current IP 1863 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1864 This assumes the zImage being placed in the first 128MB from 1865 start of memory. 1866 1867config EFI_STUB 1868 bool 1869 1870config EFI 1871 bool "UEFI runtime support" 1872 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1873 select UCS2_STRING 1874 select EFI_PARAMS_FROM_FDT 1875 select EFI_STUB 1876 select EFI_GENERIC_STUB 1877 select EFI_RUNTIME_WRAPPERS 1878 help 1879 This option provides support for runtime services provided 1880 by UEFI firmware (such as non-volatile variables, realtime 1881 clock, and platform reset). A UEFI stub is also provided to 1882 allow the kernel to be booted as an EFI application. This 1883 is only useful for kernels that may run on systems that have 1884 UEFI firmware. 1885 1886config DMI 1887 bool "Enable support for SMBIOS (DMI) tables" 1888 depends on EFI 1889 default y 1890 help 1891 This enables SMBIOS/DMI feature for systems. 1892 1893 This option is only useful on systems that have UEFI firmware. 1894 However, even with this option, the resultant kernel should 1895 continue to boot on existing non-UEFI platforms. 1896 1897 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1898 i.e., the the practice of identifying the platform via DMI to 1899 decide whether certain workarounds for buggy hardware and/or 1900 firmware need to be enabled. This would require the DMI subsystem 1901 to be enabled much earlier than we do on ARM, which is non-trivial. 1902 1903endmenu 1904 1905menu "CPU Power Management" 1906 1907source "drivers/cpufreq/Kconfig" 1908 1909source "drivers/cpuidle/Kconfig" 1910 1911endmenu 1912 1913menu "Floating point emulation" 1914 1915comment "At least one emulation must be selected" 1916 1917config FPE_NWFPE 1918 bool "NWFPE math emulation" 1919 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1920 help 1921 Say Y to include the NWFPE floating point emulator in the kernel. 1922 This is necessary to run most binaries. Linux does not currently 1923 support floating point hardware so you need to say Y here even if 1924 your machine has an FPA or floating point co-processor podule. 1925 1926 You may say N here if you are going to load the Acorn FPEmulator 1927 early in the bootup. 1928 1929config FPE_NWFPE_XP 1930 bool "Support extended precision" 1931 depends on FPE_NWFPE 1932 help 1933 Say Y to include 80-bit support in the kernel floating-point 1934 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1935 Note that gcc does not generate 80-bit operations by default, 1936 so in most cases this option only enlarges the size of the 1937 floating point emulator without any good reason. 1938 1939 You almost surely want to say N here. 1940 1941config FPE_FASTFPE 1942 bool "FastFPE math emulation (EXPERIMENTAL)" 1943 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1944 help 1945 Say Y here to include the FAST floating point emulator in the kernel. 1946 This is an experimental much faster emulator which now also has full 1947 precision for the mantissa. It does not support any exceptions. 1948 It is very simple, and approximately 3-6 times faster than NWFPE. 1949 1950 It should be sufficient for most programs. It may be not suitable 1951 for scientific calculations, but you have to check this for yourself. 1952 If you do not feel you need a faster FP emulation you should better 1953 choose NWFPE. 1954 1955config VFP 1956 bool "VFP-format floating point maths" 1957 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1958 help 1959 Say Y to include VFP support code in the kernel. This is needed 1960 if your hardware includes a VFP unit. 1961 1962 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1963 release notes and additional status information. 1964 1965 Say N if your target does not have VFP hardware. 1966 1967config VFPv3 1968 bool 1969 depends on VFP 1970 default y if CPU_V7 1971 1972config NEON 1973 bool "Advanced SIMD (NEON) Extension support" 1974 depends on VFPv3 && CPU_V7 1975 help 1976 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1977 Extension. 1978 1979config KERNEL_MODE_NEON 1980 bool "Support for NEON in kernel mode" 1981 depends on NEON && AEABI 1982 help 1983 Say Y to include support for NEON in kernel mode. 1984 1985endmenu 1986 1987menu "Power management options" 1988 1989source "kernel/power/Kconfig" 1990 1991config ARCH_SUSPEND_POSSIBLE 1992 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1993 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1994 def_bool y 1995 1996config ARM_CPU_SUSPEND 1997 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1998 depends on ARCH_SUSPEND_POSSIBLE 1999 2000config ARCH_HIBERNATION_POSSIBLE 2001 bool 2002 depends on MMU 2003 default y if ARCH_SUSPEND_POSSIBLE 2004 2005endmenu 2006 2007source "drivers/firmware/Kconfig" 2008 2009if CRYPTO 2010source "arch/arm/crypto/Kconfig" 2011endif 2012 2013source "arch/arm/Kconfig.assembler" 2014